[alsa-devel] [PATCH 1/3] ASoC: rt5677: Modify the behavior that updates the PLL parameter.
The patch modified the behavior that updates the PLL parameter. It set the update bit before the PLL power up.
Signed-off-by: Oder Chiou oder_chiou@realtek.com --- sound/soc/codecs/rt5677.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index 8900221..d27630a 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -2174,10 +2174,14 @@ static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
switch (event) { - case SND_SOC_DAPM_POST_PMU: + case SND_SOC_DAPM_PRE_PMU: regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); + break; + + case SND_SOC_DAPM_POST_PMU: regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); break; + default: return 0; } @@ -2192,10 +2196,14 @@ static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
switch (event) { - case SND_SOC_DAPM_POST_PMU: + case SND_SOC_DAPM_PRE_PMU: regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); + break; + + case SND_SOC_DAPM_POST_PMU: regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); break; + default: return 0; } @@ -2303,9 +2311,11 @@ static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, - 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU), + 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, - 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU), + 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU),
/* ASRC */ SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
The patch adds the MICBIAS VDD setting in the platform data. It can be set to 1V8 or 3V3 in the MICBIAS VDD.
Signed-off-by: Oder Chiou oder_chiou@realtek.com --- include/sound/rt5677.h | 3 +++ sound/soc/codecs/rt5677.c | 5 +++++ 2 files changed, 8 insertions(+)
diff --git a/include/sound/rt5677.h b/include/sound/rt5677.h index d9eb7d8..a620704 100644 --- a/include/sound/rt5677.h +++ b/include/sound/rt5677.h @@ -37,6 +37,9 @@ struct rt5677_platform_data { OFF, GPIO4, GPIO5 and GPIO6 respectively */ unsigned int jd2_gpio; unsigned int jd3_gpio; + + /* Set MICBIAS1 VDD 1v8 or 3v3 */ + bool micbias1_vdd_3v3; };
#endif diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index d27630a..32c368c 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -4923,6 +4923,11 @@ static int rt5677_i2c_probe(struct i2c_client *i2c, RT5677_GPIO5_DIR_OUT); }
+ if (rt5677->pdata.micbias1_vdd_3v3) + regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, + RT5677_MICBIAS1_CTRL_VDD_MASK, + RT5677_MICBIAS1_CTRL_VDD_3_3V); + rt5677_init_gpio(i2c); rt5677_init_irq(i2c);
On Thu, Jan 08, 2015 at 10:31:06AM +0800, Oder Chiou wrote:
The patch adds the MICBIAS VDD setting in the platform data. It can be set to 1V8 or 3V3 in the MICBIAS VDD.
Applied, thanks.
The patch adds the specific TDM setting for Intel platform in the platform data. It enables the TDM1's capbility that can receive the 100FS data.
Signed-off-by: Oder Chiou oder_chiou@realtek.com --- include/sound/rt5677.h | 3 +++ sound/soc/codecs/rt5677.c | 6 +++++- 2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/sound/rt5677.h b/include/sound/rt5677.h index a620704..1137183 100644 --- a/include/sound/rt5677.h +++ b/include/sound/rt5677.h @@ -40,6 +40,9 @@ struct rt5677_platform_data {
/* Set MICBIAS1 VDD 1v8 or 3v3 */ bool micbias1_vdd_3v3; + + /* Set TDM mode for Intel */ + bool tdm_for_intel; };
#endif diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index 32c368c..b1c17b0 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -4427,7 +4427,7 @@ static int rt5677_probe(struct snd_soc_codec *codec)
rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
- regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020); + regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0020, 0x0020); regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
for (i = 0; i < RT5677_GPIO_NUM; i++) @@ -4928,6 +4928,10 @@ static int rt5677_i2c_probe(struct i2c_client *i2c, RT5677_MICBIAS1_CTRL_VDD_MASK, RT5677_MICBIAS1_CTRL_VDD_3_3V);
+ if (rt5677->pdata.tdm_for_intel) + regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, + 0x8000); + rt5677_init_gpio(i2c); rt5677_init_irq(i2c);
On Thu, Jan 08, 2015 at 10:31:07AM +0800, Oder Chiou wrote:
The patch adds the specific TDM setting for Intel platform in the platform data. It enables the TDM1's capbility that can receive the 100FS data.
So, this is total magic number stuff... can you be more specific as to what this 100fs mode is? We do have an interface for setting up TDM but given that this is just flipping one bit I'd expect the hardware isn't actually generic enough to use that so I'd like to better understand what the configuration actually does.
On Thu, Jan 08, 2015 at 10:31:05AM +0800, Oder Chiou wrote:
The patch modified the behavior that updates the PLL parameter. It set the update bit before the PLL power up.
This looks like it's a bug fix?
-----Original Message----- From: Mark Brown [mailto:broonie@kernel.org] Sent: Friday, January 09, 2015 2:36 AM To: Oder Chiou Cc: lgirdwood@gmail.com; alsa-devel@alsa-project.org; Bard Liao; Flove; John Lin; yang.a.fang@intel.com Subject: Re: [PATCH 1/3] ASoC: rt5677: Modify the behavior that updates the PLL parameter.
On Thu, Jan 08, 2015 at 10:31:05AM +0800, Oder Chiou wrote:
The patch modified the behavior that updates the PLL parameter. It set the update bit before the PLL power up.
This looks like it's a bug fix?
Actually, the previous version had be verified, but our HW engineer recommended to this kind of sequence, thanks.
On Fri, Jan 09, 2015 at 02:20:37AM +0000, Oder Chiou wrote:
This looks like it's a bug fix?
Actually, the previous version had be verified, but our HW engineer recommended to this kind of sequence, thanks.
That does sound like a hardware correctness fix then - something that will fail in some use cases or based on factors like timing.
On Thu, Jan 08, 2015 at 10:31:05AM +0800, Oder Chiou wrote:
The patch modified the behavior that updates the PLL parameter. It set the update bit before the PLL power up.
Applied, thanks.
participants (2)
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Mark Brown -
Oder Chiou