[alsa-devel] [PATCH v3 00/11] Add Samus Hotwording for RT5677
This patch series adds the hotwording implementation used in the Pixelbook on the RT5677 driver.
Known Issues: There is a known issue where the system will fail to detect a hotword if suspended while the stream is open. This is due to the fact that the haswell-dsp suspends its I2S MCLK before the RT5677 suspends which causes the writes and reads to become corrupted as a result. Any recommendations to correct this behaviour would be appreciated.
Changes since v1: * Addressed Mark's and Kuninori's comments * Adjusted DAI Links * Squashed related patches * Removed all kcontrol writes * Addressed race condition with dapm * Added firmware boot check * Moved all clocking to driver API * Moved DAPM routes that spanned drivers to machine driver
Changes since v2: * Updated and removed necessary dapm forced power on * Addressed Cexzary's comments
Cc: Dylan Reid dgreid@chromium.org Cc: Ben Zhang benzh@chromium.org
Ben Zhang (7): ASoC: rt5677: Load firmware via SPI using delayed work ASoC: bdw-rt5677: Add a DAI link for rt5677 SPI PCM device ASoC: rt5677: Enable jack detect while DSP is running ASoC: rt5677: Add DAPM audio path for hotword stream ASoC: rt5677: Mark reg RT5677_PWR_ANLG2 as volatile ASoC: rt5677: Stop and restart DSP over suspend/resume ASoC: rt5677: Disable irq at suspend
Curtis Malainey (4): ASoC: rt5677: Allow VAD to be shut on/off at all times ASoC: bdw-rt5677: Turn on MCLK1 for DSP via DAPM ASoC: rt5677: Set ADC clock to use PLL and enable ASRC ASoC: rt5677: Wait for DSP to boot before loading firmware
sound/soc/codecs/rt5677-spi.c | 13 + sound/soc/codecs/rt5677.c | 445 +++++++++++++++++++++++----- sound/soc/codecs/rt5677.h | 11 +- sound/soc/intel/boards/bdw-rt5677.c | 51 ++++ 4 files changed, 447 insertions(+), 73 deletions(-)
From: Ben Zhang benzh@chromium.org
The firmware rt5677_elf_vad is an ELF binary obtained from request_firmware(). Sections of the ELF are loaded to the DSP via SPI. A model (e.g. en_us.mmap) can optionally be loaded to the DSP at RT5677_MODEL_ADDR to overwrite the baked-in model in rt5677_elf_vad.
Then we switch to DSP mode, load firmware, and let DSP run. When a hotword is detected, an interrupt is fired and rt5677_irq() is called. When 'DSP VAD Switch' is turned off, the codec is set back to normal mode.
The kcontrol 'DSP VAD Switch' is automatically enabled/disabled when the hotwording PCM stream is opened/closed.
Change-Id: I9db4a2d125e83c13a969e31fec904fd52ff500c2 Signed-off-by: Ben Zhang benzh@chromium.org Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/codecs/rt5677-spi.c | 13 ++ sound/soc/codecs/rt5677.c | 301 ++++++++++++++++++++++++++-------- sound/soc/codecs/rt5677.h | 6 +- 3 files changed, 253 insertions(+), 67 deletions(-)
diff --git a/sound/soc/codecs/rt5677-spi.c b/sound/soc/codecs/rt5677-spi.c index 3aa3ea7c2768..25e28be3722e 100644 --- a/sound/soc/codecs/rt5677-spi.c +++ b/sound/soc/codecs/rt5677-spi.c @@ -26,6 +26,7 @@
#include <sound/soc.h>
+#include "rt5677.h" #include "rt5677-spi.h"
#define DRV_NAME "rt5677spi" @@ -111,10 +112,16 @@ static int rt5677_spi_pcm_close( struct snd_soc_component *component, struct snd_pcm_substream *substream) { + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_component *codec_component = + snd_soc_rtdcom_lookup(rtd, "rt5677"); + struct rt5677_priv *rt5677 = + snd_soc_component_get_drvdata(codec_component); struct rt5677_dsp *rt5677_dsp = snd_soc_component_get_drvdata(component);
cancel_delayed_work_sync(&rt5677_dsp->copy_work); + rt5677->set_dsp_vad(codec_component, false); return 0; }
@@ -154,9 +161,15 @@ static int rt5677_spi_prepare( struct snd_soc_component *component, struct snd_pcm_substream *substream) { + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_component *rt5677_component = + snd_soc_rtdcom_lookup(rtd, "rt5677"); + struct rt5677_priv *rt5677 = + snd_soc_component_get_drvdata(rt5677_component); struct rt5677_dsp *rt5677_dsp = snd_soc_component_get_drvdata(component);
+ rt5677->set_dsp_vad(rt5677_component, true); rt5677_dsp->dma_offset = 0; rt5677_dsp->avail_bytes = 0; return 0; diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index 315a3d39bc09..13f21bf4e04e 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -38,6 +38,10 @@
#define RT5677_DEVICE_ID 0x6327
+/* Register controlling boot vector */ +#define RT5677_DSP_BOOT_VECTOR 0x1801f090 +#define RT5677_MODEL_ADDR 0x5FFC9800 + #define RT5677_PR_RANGE_BASE (0xff + 1) #define RT5677_PR_SPACING 0x100
@@ -686,10 +690,8 @@ static int rt5677_dsp_mode_i2c_read( return ret; }
-static void rt5677_set_dsp_mode(struct snd_soc_component *component, bool on) +static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on) { - struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); - if (on) { regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, RT5677_PWR_DSP, RT5677_PWR_DSP); @@ -701,86 +703,234 @@ static void rt5677_set_dsp_mode(struct snd_soc_component *component, bool on) } }
+static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677) +{ + /* DMIC1 power = enabled + * DMIC CLK = 256 * fs / 12 + */ + regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, + RT5677_DMIC_CLK_MASK, 5 << RT5677_DMIC_CLK_SFT); + + /* I2S pre divide 2 = /6 (clk_sys2) */ + regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, + RT5677_I2S_PD2_MASK, RT5677_I2S_PD2_6); + + /* DSP Clock = MCLK1 (bypassed PLL2) */ + regmap_write(rt5677->regmap, RT5677_GLB_CLK2, + RT5677_DSP_CLK_SRC_BYPASS); + + /* SAD Threshold1 */ + regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f); + /* SAD Threshold2 */ + regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5); + /* SAD Sample Rate Converter = Up 6 (8K to 48K) + * SAD Output Sample Rate = Same as I2S + * SAD Threshold3 + */ + regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4, + RT5677_VAD_OUT_SRC_RATE_MASK | RT5677_VAD_OUT_SRC_MASK | + RT5677_VAD_LV_DIFF_MASK, 0x7f << RT5677_VAD_LV_DIFF_SFT); + /* Minimum frame level within a pre-determined duration = 32 frames + * Bypass ADPCM Encoder/Decoder = Bypass ADPCM + * Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable + * SAD Buffer Over-Writing = enable + * SAD Buffer Pop Mode Control = disable + * SAD Buffer Push Mode Control = enable + * SAD Detector Control = enable + * SAD Function Control = enable + * SAD Function Reset = normal + */ + regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, + RT5677_VAD_FUNC_RESET | RT5677_VAD_FUNC_ENABLE | + RT5677_VAD_DET_ENABLE | RT5677_VAD_BUF_PUSH | + RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC | + RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT); + + /* IRQ Source of VAD Jack Detection = enable */ + regmap_write(rt5677->regmap, RT5677_IRQ_CTRL2, 0x4000); + + /* Private register, no doc */ + regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4, + 0x0f00, 0x0100); + + /* LDO2 output = 1.2V + * LDO1 output = 1.2V (LDO_IN = 1.8V) + */ + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, + RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, + 5 << RT5677_LDO1_SEL_SFT | 5 << RT5677_LDO2_SEL_SFT); + + /* Codec core power = power on + * LDO1 power = power on + */ + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, + RT5677_PWR_CORE | RT5677_PWR_LDO1, + RT5677_PWR_CORE | RT5677_PWR_LDO1); + + /* Isolation for DCVDD4 = normal (set during probe) + * Isolation for DCVDD2 = normal (set during probe) + * Isolation for DSP = normal + * Isolation for Band 0~7 = disable + * Isolation for InBound 4~10 and OutBound 4~10 = disable + */ + regmap_write(rt5677->regmap, RT5677_PWR_DSP2, + RT5677_PWR_CORE_ISO | RT5677_PWR_DSP_ISO | + RT5677_PWR_SR7_ISO | RT5677_PWR_SR6_ISO | + RT5677_PWR_SR5_ISO | RT5677_PWR_SR4_ISO | + RT5677_PWR_SR3_ISO | RT5677_PWR_SR2_ISO | + RT5677_PWR_SR1_ISO | RT5677_PWR_SR0_ISO | + RT5677_PWR_MLT_ISO); + + /* System Band 0~7 = power on + * InBound 4~10 and OutBound 4~10 = power on + * DSP = power on + * DSP CPU = stop (will be set to "run" after firmware loaded) + */ + regmap_write(rt5677->regmap, RT5677_PWR_DSP1, + RT5677_PWR_SR7 | RT5677_PWR_SR6 | + RT5677_PWR_SR5 | RT5677_PWR_SR4 | + RT5677_PWR_SR3 | RT5677_PWR_SR2 | + RT5677_PWR_SR1 | RT5677_PWR_SR0 | + RT5677_PWR_MLT | RT5677_PWR_DSP | + RT5677_PWR_DSP_CPU); + + return 0; +} + +static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf, + unsigned int len) +{ + struct snd_soc_component *component = rt5677->component; + Elf32_Ehdr *elf_hdr; + Elf32_Phdr *pr_hdr; + Elf32_Half i; + int ret = 0; + + if (!buf || (len < sizeof(Elf32_Ehdr))) + return -ENOMEM; + + elf_hdr = (Elf32_Ehdr *)buf; +#ifndef EM_XTENSA +#define EM_XTENSA 94 +#endif + if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1)) + dev_err(component->dev, "Wrong ELF header prefix\n"); + if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr)) + dev_err(component->dev, "Wrong Elf header size\n"); + if (elf_hdr->e_machine != EM_XTENSA) + dev_err(component->dev, "Wrong DSP code file\n"); + + if (len < elf_hdr->e_phoff) + return -ENOMEM; + pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff); + for (i = 0; i < elf_hdr->e_phnum; i++) { + /* TODO: handle p_memsz != p_filesz */ + if (pr_hdr->p_paddr && pr_hdr->p_filesz) { + dev_info(component->dev, "Load 0x%x bytes to 0x%x\n", + pr_hdr->p_filesz, pr_hdr->p_paddr); + + ret = rt5677_spi_write(pr_hdr->p_paddr, + buf + pr_hdr->p_offset, + pr_hdr->p_filesz); + if (ret) + dev_err(component->dev, "Load firmware failed %d\n", + ret); + } + pr_hdr++; + } + return ret; +} + +static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677) +{ + const struct firmware *fwp; + struct device *dev = rt5677->component->dev; + int ret = 0; + + /* Load dsp firmware from rt5677_elf_vad file */ + ret = request_firmware(&fwp, "rt5677_elf_vad", dev); + if (ret) { + dev_err(dev, "Request rt5677_elf_vad failed %d\n", ret); + return ret; + } + dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size); + + ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size); + release_firmware(fwp); + return ret; +} + static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on) { struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); - static bool activity; - int ret; + rt5677->dsp_vad_en = on;
if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI)) return -ENXIO;
- if (on && !activity) { - activity = true; + schedule_delayed_work(&rt5677->dsp_work, 0); + return 0; +}
- regcache_cache_only(rt5677->regmap, false); - regcache_cache_bypass(rt5677->regmap, true); +static void rt5677_dsp_work(struct work_struct *work) +{ + struct rt5677_priv *rt5677 = + container_of(work, struct rt5677_priv, dsp_work.work); + static bool activity; + bool enable = rt5677->dsp_vad_en;
- regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1); - regmap_update_bits(rt5677->regmap, - RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00); - regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, - RT5677_LDO1_SEL_MASK, 0x0); - regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, - RT5677_PWR_LDO1, RT5677_PWR_LDO1); - switch (rt5677->type) { - case RT5677: - regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, - RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC); - regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, - RT5677_PLL2_PR_SRC_MASK | - RT5677_DSP_CLK_SRC_MASK, - RT5677_PLL2_PR_SRC_MCLK2 | - RT5677_DSP_CLK_SRC_BYPASS); - break; - case RT5676: - regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, - RT5677_DSP_CLK_SRC_MASK, - RT5677_DSP_CLK_SRC_BYPASS); - break; - default: - break; - } - regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff); - regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd); - rt5677_set_dsp_mode(component, true); - - ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1, - component->dev); - if (ret == 0) { - rt5677_spi_write_firmware(0x50000000, rt5677->fw1); - release_firmware(rt5677->fw1); - }
- ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2, - component->dev); - if (ret == 0) { - rt5677_spi_write_firmware(0x60000000, rt5677->fw2); - release_firmware(rt5677->fw2); - } + dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n", + enable, activity);
- regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0); + if (enable && !activity) { + activity = true;
- regcache_cache_bypass(rt5677->regmap, false); - regcache_cache_only(rt5677->regmap, true); - } else if (!on && activity) { + /* Set GPIO1 as an output pin driving a 0. Firmware will + * raise GPIO1 upon hotword detect. + */ + regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, + RT5677_GPIO1_DIR_MASK | RT5677_GPIO1_OUT_MASK | + RT5677_GPIO1_P_MASK, RT5677_GPIO1_DIR_OUT | + RT5677_GPIO1_OUT_LO | RT5677_GPIO1_P_NOR); + regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, + RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_GPIO1); + + rt5677_set_vad_source(rt5677); + rt5677_set_dsp_mode(rt5677, true); + + /* Boot the firmware from IRAM instead of SRAM0. */ + rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, + 0x0009, 0x0003); + rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, + 0x0019, 0x0003); + rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, + 0x0009, 0x0003); + + rt5677_load_dsp_from_file(rt5677); + + /* Set DSP CPU to Run */ + regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, + RT5677_PWR_DSP_CPU, 0x0); + } else if (!enable && activity) { activity = false;
- regcache_cache_only(rt5677->regmap, false); - regcache_cache_bypass(rt5677->regmap, true); + /* Set DSP CPU to Stop */ + regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, + RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU);
- regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1); - rt5677_set_dsp_mode(component, false); - regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001); + rt5677_set_dsp_mode(rt5677, false);
- regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); + /* Disable and clear VAD interrupt */ + regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184); + regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL2, + 0xF000, 0x0000);
- regcache_cache_bypass(rt5677->regmap, false); - regcache_mark_dirty(rt5677->regmap); - regcache_sync(rt5677->regmap); - } + /* Set GPIO1 pin back to be IRQ output for jack detect */ + regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, + RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
- return 0; + } }
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); @@ -819,7 +969,8 @@ static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) - rt5677_set_dsp_vad(component, rt5677->dsp_vad_en); + rt5677_set_dsp_vad(component, + !!ucontrol->value.integer.value[0]);
return 0; } @@ -4740,6 +4891,8 @@ static void rt5677_remove(struct snd_soc_component *component) { struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
+ cancel_delayed_work_sync(&rt5677->dsp_work); + regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); gpiod_set_value_cansleep(rt5677->reset_pin, 1); @@ -4938,6 +5091,17 @@ static struct snd_soc_dai_driver rt5677_dai[] = { }, .ops = &rt5677_aif_dai_ops, }, + { + .name = "rt5677-dspbuffer", + .id = RT5677_DSPBUFF, + .capture = { + .stream_name = "DSP Buffer", + .channels_min = 1, + .channels_max = 1, + .rates = SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + }, };
static const struct snd_soc_component_driver soc_component_dev_rt5677 = { @@ -5081,6 +5245,9 @@ static irqreturn_t rt5677_irq(int unused, void *data)
mutex_lock(&rt5677->irq_lock);
+ if (rt5677->dsp_vad_en) + rt5677_spi_hotword_detected(); + /* * Loop to handle interrupts until the last i2c read shows no pending * irqs. The interrupt line is shared by multiple interrupt sources. @@ -5271,6 +5438,8 @@ static int rt5677_i2c_probe(struct i2c_client *i2c) return -ENOMEM;
rt5677->dev = &i2c->dev; + rt5677->set_dsp_vad = rt5677_set_dsp_vad; + INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work); i2c_set_clientdata(i2c, rt5677);
if (i2c->dev.of_node) { diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h index 213f4b8ca269..d18b41da1176 100644 --- a/sound/soc/codecs/rt5677.h +++ b/sound/soc/codecs/rt5677.h @@ -1730,6 +1730,7 @@ enum { RT5677_AIF4, RT5677_AIF5, RT5677_AIFS, + RT5677_DSPBUFF, };
enum { @@ -1845,14 +1846,17 @@ struct rt5677_priv { #ifdef CONFIG_GPIOLIB struct gpio_chip gpio_chip; #endif - bool dsp_vad_en; + bool dsp_vad_en; /* DSP VAD enable/disable request */ bool is_dsp_mode; bool is_vref_slow; + struct delayed_work dsp_work;
/* Interrupt handling */ struct irq_domain *domain; struct mutex irq_lock; unsigned int irq_en; + + int (*set_dsp_vad)(struct snd_soc_component *component, bool on); };
int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
On Tue, Nov 5, 2019 at 5:13 PM Curtis Malainey cujomalainey@chromium.org wrote:
the codec is set back to normal mode.
The kcontrol 'DSP VAD Switch' is automatically enabled/disabled when the hotwording PCM stream is opened/closed.
Change-Id: I9db4a2d125e83c13a969e31fec904fd52ff500c2
Gah, that commit hook always gets me. If everything is good Mark will you remove that change-id for me or would you want me to resend the series? Sorry for that.
Signed-off-by: Ben Zhang benzh@chromium.org Signed-off-by: Curtis Malainey cujomalainey@chromium.org
From: Ben Zhang benzh@chromium.org
This link is needed for the RT5677 DSP to do hotwording
Signed-off-by: Ben Zhang benzh@chromium.org Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/intel/boards/bdw-rt5677.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/sound/soc/intel/boards/bdw-rt5677.c b/sound/soc/intel/boards/bdw-rt5677.c index 4a4d3353e26d..eeb9a11e4e14 100644 --- a/sound/soc/intel/boards/bdw-rt5677.c +++ b/sound/soc/intel/boards/bdw-rt5677.c @@ -74,6 +74,7 @@ static const struct snd_soc_dapm_route bdw_rt5677_map[] = { /* CODEC BE connections */ {"SSP0 CODEC IN", NULL, "AIF1 Capture"}, {"AIF1 Playback", NULL, "SSP0 CODEC OUT"}, + {"DSP Capture", NULL, "DSP Buffer"}, };
static const struct snd_kcontrol_new bdw_rt5677_controls[] = { @@ -258,6 +259,12 @@ SND_SOC_DAILINK_DEF(platform, SND_SOC_DAILINK_DEF(be, DAILINK_COMP_ARRAY(COMP_CODEC("i2c-RT5677CE:00", "rt5677-aif1")));
+/* Wake on voice interface */ +SND_SOC_DAILINK_DEFS(dsp, + DAILINK_COMP_ARRAY(COMP_CPU("spi-RT5677AA:00")), + DAILINK_COMP_ARRAY(COMP_CODEC("i2c-RT5677CE:00", "rt5677-dspbuffer")), + DAILINK_COMP_ARRAY(COMP_PLATFORM("spi-RT5677AA:00"))); + static struct snd_soc_dai_link bdw_rt5677_dais[] = { /* Front End DAI links */ { @@ -276,6 +283,13 @@ static struct snd_soc_dai_link bdw_rt5677_dais[] = { SND_SOC_DAILINK_REG(fe, dummy, platform), },
+ /* Non-DPCM links */ + { + .name = "Codec DSP", + .stream_name = "Wake on Voice", + SND_SOC_DAILINK_REG(dsp), + }, + /* Back End DAI links */ { /* SSP0 - Codec */
From: Ben Zhang benzh@chromium.org
Before a hotword is detected, GPIO1 pin is configured as IRQ output so that jack detect works. When a hotword is detected, the DSP firmware configures the GPIO1 pin as GPIO1 and drives a 1. rt5677_irq() is called after a rising edge on the GPIO1 pin, due to either jack detect event or hotword event, or both. All possible events are checked and handled in rt5677_irq() where GPIO1 pin is configured back to IRQ output if a hotword is detected.
Signed-off-by: Ben Zhang benzh@chromium.org Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/codecs/rt5677.c | 64 +++++++++++++++++++++++++++++---------- 1 file changed, 48 insertions(+), 16 deletions(-)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index 13f21bf4e04e..48955b22262f 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -312,6 +312,8 @@ static bool rt5677_volatile_register(struct device *dev, unsigned int reg) case RT5677_IRQ_CTRL1: case RT5677_IRQ_CTRL2: case RT5677_GPIO_ST: + case RT5677_GPIO_CTRL1: /* Modified by DSP firmware */ + case RT5677_GPIO_CTRL2: /* Modified by DSP firmware */ case RT5677_DSP_INB1_SRC_CTRL4: case RT5677_DSP_INB2_SRC_CTRL4: case RT5677_DSP_INB3_SRC_CTRL4: @@ -746,8 +748,11 @@ static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677) RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC | RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT);
- /* IRQ Source of VAD Jack Detection = enable */ - regmap_write(rt5677->regmap, RT5677_IRQ_CTRL2, 0x4000); + /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it + * is routed to DSP_IRQ_0, so DSP firmware may use it to sleep and save + * power. See ALC5677 datasheet section 9.17 "GPIO, Interrupt and Jack + * Detection" for more info. + */
/* Private register, no doc */ regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4, @@ -886,15 +891,15 @@ static void rt5677_dsp_work(struct work_struct *work) if (enable && !activity) { activity = true;
- /* Set GPIO1 as an output pin driving a 0. Firmware will - * raise GPIO1 upon hotword detect. + /* Before a hotword is detected, GPIO1 pin is configured as IRQ + * output so that jack detect works. When a hotword is detected, + * the DSP firmware configures the GPIO1 pin as GPIO1 and + * drives a 1. rt5677_irq() is called after a rising edge on + * the GPIO1 pin, due to either jack detect event or hotword + * event, or both. All possible events are checked and handled + * in rt5677_irq() where GPIO1 pin is configured back to IRQ + * output if a hotword is detected. */ - regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, - RT5677_GPIO1_DIR_MASK | RT5677_GPIO1_OUT_MASK | - RT5677_GPIO1_P_MASK, RT5677_GPIO1_DIR_OUT | - RT5677_GPIO1_OUT_LO | RT5677_GPIO1_P_NOR); - regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, - RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_GPIO1);
rt5677_set_vad_source(rt5677); rt5677_set_dsp_mode(rt5677, true); @@ -915,6 +920,8 @@ static void rt5677_dsp_work(struct work_struct *work) } else if (!enable && activity) { activity = false;
+ /* Don't turn off the DSP while handling irqs */ + mutex_lock(&rt5677->irq_lock); /* Set DSP CPU to Stop */ regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU); @@ -923,13 +930,12 @@ static void rt5677_dsp_work(struct work_struct *work)
/* Disable and clear VAD interrupt */ regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184); - regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL2, - 0xF000, 0x0000);
/* Set GPIO1 pin back to be IRQ output for jack detect */ regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
+ mutex_unlock(&rt5677->irq_lock); } }
@@ -5237,6 +5243,28 @@ static const struct rt5677_irq_desc rt5677_irq_descs[] = { }, };
+bool rt5677_check_hotword(struct rt5677_priv *rt5677) +{ + int reg_gpio; + + if (!rt5677->is_dsp_mode) + return false; + + if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio)) + return false; + + /* Firmware sets GPIO1 pin to be GPIO1 after hotword is detected */ + if ((reg_gpio & RT5677_GPIO1_PIN_MASK) == RT5677_GPIO1_PIN_IRQ) + return false; + + /* Set GPIO1 pin back to be IRQ output for jack detect */ + regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, + RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); + + rt5677_spi_hotword_detected(); + return true; +} + static irqreturn_t rt5677_irq(int unused, void *data) { struct rt5677_priv *rt5677 = data; @@ -5245,9 +5273,6 @@ static irqreturn_t rt5677_irq(int unused, void *data)
mutex_lock(&rt5677->irq_lock);
- if (rt5677->dsp_vad_en) - rt5677_spi_hotword_detected(); - /* * Loop to handle interrupts until the last i2c read shows no pending * irqs. The interrupt line is shared by multiple interrupt sources. @@ -5285,7 +5310,13 @@ static irqreturn_t rt5677_irq(int unused, void *data) reg_irq ^= rt5677_irq_descs[i].polarity_mask; } } - if (!irq_fired) + + /* Exit the loop only when we know for sure that GPIO1 pin + * was low at some point since irq_lock was acquired. Any event + * after that point creates a rising edge that triggers another + * call to rt5677_irq(). + */ + if (!irq_fired && !rt5677_check_hotword(rt5677)) goto exit;
ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq); @@ -5296,6 +5327,7 @@ static irqreturn_t rt5677_irq(int unused, void *data) } } exit: + WARN_ON_ONCE(loop == 20); mutex_unlock(&rt5677->irq_lock); if (irq_fired) return IRQ_HANDLED;
From: Ben Zhang benzh@chromium.org
Add a DAPM audio path from "DMIC L1" to "DSP Buffer" so that when hotwording is enabled, DAPM does not power off the codec with SND_SOC_BIAS_OFF.
Signed-off-by: Ben Zhang benzh@chromium.org Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/codecs/rt5677.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index 48955b22262f..ea235f3874ca 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -707,6 +707,13 @@ static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on)
static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677) { + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(rt5677->component); + /* Force dapm to sync before we enable the + * DSP to prevent write corruption + */ + snd_soc_dapm_sync(dapm); + /* DMIC1 power = enabled * DMIC CLK = 256 * fs / 12 */ @@ -3167,6 +3174,7 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("DSPTX", "DSP Buffer", 0, SND_SOC_NOPM, 0, 0),
/* Sidetone Mux */ SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, @@ -3701,11 +3709,24 @@ static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { { "SLBTX", NULL, "SLB ADC3 Mux" }, { "SLBTX", NULL, "SLB ADC4 Mux" },
+ { "DSPTX", NULL, "IB01 Bypass Mux" }, + { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, - { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" }, + /* The IB01 Mux controls the source for InBound0 and InBound1. + * When the mux option "VAD ADC/DAC1 FS" is selected, "VAD ADC" goes to + * InBound0 and "DAC1 FS" goes to InBound1. "VAD ADC" is used for + * hotwording. "DAC1 FS" is not used currently. + * + * Creating a common widget node for "VAD ADC" + "DAC1 FS" and + * connecting the common widget to IB01 Mux causes the issue where + * there is an active path going from system playback -> "DAC1 FS" -> + * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses + * DAPM. Therefore "DAC1 FS" is ignored for now. + */ + { "IB01 Mux", "VAD ADC/DAC1 FS", "VAD ADC Mux" },
{ "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
From: Ben Zhang benzh@chromium.org
The codec dies when RT5677_PWR_ANLG2(MX-64h) is set to 0xACE1 while it's streaming audio over SPI. The DSP firmware turns on PLL2 (MX-64 bit 8) when SPI streaming starts. However regmap does not believe that register can change by itself. When BST1 (bit 15) is turned on with regmap_update_bits(), it doesn't read the register first before write, so PLL2 power bit is cleared by accident.
Marking MX-64h as volatile in regmap solved the issue.
Signed-off-by: Ben Zhang benzh@chromium.org Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/codecs/rt5677.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index ea235f3874ca..e5db9dc60378 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -302,6 +302,7 @@ static bool rt5677_volatile_register(struct device *dev, unsigned int reg) case RT5677_I2C_MASTER_CTRL7: case RT5677_I2C_MASTER_CTRL8: case RT5677_HAP_GENE_CTRL2: + case RT5677_PWR_ANLG2: /* Modified by DSP firmware */ case RT5677_PWR_DSP_ST: case RT5677_PRIV_DATA: case RT5677_ASRC_22:
From: Ben Zhang benzh@chromium.org
MCLK1 gets disabled at suspend and re-enabled at resume. Before MCLK1 is re-enabled, if the DSP is already on (either the DSP was left on during suspend, or the DSP is turned on early at resume), i2c register read returns garbage and corrupts the regmap cache.
This patch stops the DSP before suspend and restarts it after resume with a dalay to ensure MCLK is on while loading firmware.
Signed-off-by: Ben Zhang benzh@chromium.org Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/codecs/rt5677.c | 24 +++++++++++++++++++++--- sound/soc/codecs/rt5677.h | 3 ++- 2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index e5db9dc60378..eb55d6b9d0c1 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -876,6 +876,7 @@ static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677) static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on) { struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); + rt5677->dsp_vad_en_request = on; rt5677->dsp_vad_en = on;
if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI)) @@ -969,7 +970,7 @@ static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
- ucontrol->value.integer.value[0] = rt5677->dsp_vad_en; + ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request;
return 0; } @@ -4636,14 +4637,15 @@ static int rt5677_set_bias_level(struct snd_soc_component *component, enum snd_soc_bias_level level) { struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); + enum snd_soc_bias_level prev_bias = + snd_soc_component_get_bias_level(component);
switch (level) { case SND_SOC_BIAS_ON: break;
case SND_SOC_BIAS_PREPARE: - if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) { - rt5677_set_dsp_vad(component, false); + if (prev_bias == SND_SOC_BIAS_STANDBY) {
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, @@ -4667,9 +4669,25 @@ static int rt5677_set_bias_level(struct snd_soc_component *component, break;
case SND_SOC_BIAS_STANDBY: + if (prev_bias == SND_SOC_BIAS_OFF && + rt5677->dsp_vad_en_request) { + /* Re-enable the DSP if it was turned off at suspend */ + rt5677->dsp_vad_en = true; + /* The delay is to wait for MCLK */ + schedule_delayed_work(&rt5677->dsp_work, + msecs_to_jiffies(1000)); + } break;
case SND_SOC_BIAS_OFF: + flush_delayed_work(&rt5677->dsp_work); + if (rt5677->is_dsp_mode) { + /* Turn off the DSP before suspend */ + rt5677->dsp_vad_en = false; + schedule_delayed_work(&rt5677->dsp_work, 0); + flush_delayed_work(&rt5677->dsp_work); + } + regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h index d18b41da1176..046ed2ee8e31 100644 --- a/sound/soc/codecs/rt5677.h +++ b/sound/soc/codecs/rt5677.h @@ -1846,7 +1846,8 @@ struct rt5677_priv { #ifdef CONFIG_GPIOLIB struct gpio_chip gpio_chip; #endif - bool dsp_vad_en; /* DSP VAD enable/disable request */ + bool dsp_vad_en_request; /* DSP VAD enable/disable request */ + bool dsp_vad_en; /* dsp_work parameter */ bool is_dsp_mode; bool is_vref_slow; struct delayed_work dsp_work;
From: Ben Zhang benzh@chromium.org
The irq is disabled at suspend to avoid running the threaded irq handler after the codec has been powered off. At resume, codec irq is re-enabled and the interrupt status register is checked to see if headphone has been pluggnd/unplugged while the device is suspended.
There is still a chance that the headphone gets enabled or disabled after the codec is suspended. disable_irq syncs the threaded irq handler, but soc-jack's threaded irq handler schedules a delayed work to poll gpios (for debounce). This is still OK. The codec won't be powered back on again because all audio paths have been suspended, and there are no force enabled supply widgets (MICBIAS1 is disabled). The gpio status read after codec power off could be wrong, so the gpio values are checked again after resume.
Signed-off-by: Ben Zhang benzh@chromium.org Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/codecs/rt5677.c | 46 +++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/rt5677.h | 2 ++ 2 files changed, 48 insertions(+)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index eb55d6b9d0c1..14f04db8e5e7 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -4949,6 +4949,11 @@ static int rt5677_suspend(struct snd_soc_component *component) { struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
+ if (rt5677->irq) { + cancel_delayed_work_sync(&rt5677->resume_irq_check); + disable_irq(rt5677->irq); + } + if (!rt5677->dsp_vad_en) { regcache_cache_only(rt5677->regmap, true); regcache_mark_dirty(rt5677->regmap); @@ -4977,6 +4982,11 @@ static int rt5677_resume(struct snd_soc_component *component) regcache_sync(rt5677->regmap); }
+ if (rt5677->irq) { + enable_irq(rt5677->irq); + schedule_delayed_work(&rt5677->resume_irq_check, 0); + } + return 0; } #else @@ -5375,6 +5385,39 @@ static irqreturn_t rt5677_irq(int unused, void *data) return IRQ_NONE; }
+static void rt5677_resume_irq_check(struct work_struct *work) +{ + int i, virq; + struct rt5677_priv *rt5677 = + container_of(work, struct rt5677_priv, resume_irq_check.work); + + /* This is needed to check and clear the interrupt status register + * at resume. If the headset is plugged/unplugged when the device is + * fully suspended, there won't be a rising edge at resume to trigger + * the interrupt. Without this, we miss the next unplug/plug event. + */ + rt5677_irq(0, rt5677); + + /* Call all enabled jack detect irq handlers again. This is needed in + * addition to the above check for a corner case caused by jack gpio + * debounce. After codec irq is disabled at suspend, the delayed work + * scheduled by soc-jack may run and read wrong jack gpio values, since + * the regmap is in cache only mode. At resume, there is no irq because + * rt5677_irq has already ran and cleared the irq status at suspend. + * Without this explicit check, unplug the headset right after suspend + * starts, then after resume the headset is still shown as plugged in. + */ + mutex_lock(&rt5677->irq_lock); + for (i = 0; i < RT5677_IRQ_NUM; i++) { + if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) { + virq = irq_find_mapping(rt5677->domain, i); + if (virq) + handle_nested_irq(virq); + } + } + mutex_unlock(&rt5677->irq_lock); +} + static void rt5677_irq_bus_lock(struct irq_data *data) { struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); @@ -5450,6 +5493,7 @@ static int rt5677_init_irq(struct i2c_client *i2c) }
mutex_init(&rt5677->irq_lock); + INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check);
/* * Select RC as the debounce clock so that GPIO works even when @@ -5495,6 +5539,8 @@ static int rt5677_init_irq(struct i2c_client *i2c) if (ret) dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
+ rt5677->irq = i2c->irq; + return ret; }
diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h index 046ed2ee8e31..f8ada967fdbc 100644 --- a/sound/soc/codecs/rt5677.h +++ b/sound/soc/codecs/rt5677.h @@ -1856,6 +1856,8 @@ struct rt5677_priv { struct irq_domain *domain; struct mutex irq_lock; unsigned int irq_en; + struct delayed_work resume_irq_check; + int irq;
int (*set_dsp_vad)(struct snd_soc_component *component, bool on); };
Due to limitations of the clocking configuration, we have no way of scheduling our hibernation before the bdw dsp hibernates. This causes issues when the system suspends with an open stream. We need userspace to toggle the kcontrol before we are suspended so that any writes on suspend are not lost and we don't corrupt the regmap.
Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/codecs/rt5677.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index 14f04db8e5e7..a65d1554366d 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -979,13 +979,8 @@ static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); - struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); - - rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
- if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) - rt5677_set_dsp_vad(component, - !!ucontrol->value.integer.value[0]); + rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]);
return 0; }
The RT5677 DSP needs the I2S MCLK1 to run its DSP. Add a dapm route to SSP0 CODEC IN so the clock is turned on automatically when the DSP is turned on.
Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/intel/boards/bdw-rt5677.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/sound/soc/intel/boards/bdw-rt5677.c b/sound/soc/intel/boards/bdw-rt5677.c index eeb9a11e4e14..b2475e3eff7b 100644 --- a/sound/soc/intel/boards/bdw-rt5677.c +++ b/sound/soc/intel/boards/bdw-rt5677.c @@ -75,6 +75,10 @@ static const struct snd_soc_dapm_route bdw_rt5677_map[] = { {"SSP0 CODEC IN", NULL, "AIF1 Capture"}, {"AIF1 Playback", NULL, "SSP0 CODEC OUT"}, {"DSP Capture", NULL, "DSP Buffer"}, + + /* DSP Clock Connections */ + { "DSP Buffer", NULL, "SSP0 CODEC IN" }, + { "SSP0 CODEC IN", NULL, "DSPTX" }, };
static const struct snd_kcontrol_new bdw_rt5677_controls[] = {
Use the PLL to kept the correct 24M clock rate so frequency shift does not occur when using the DSP VAD.
Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/codecs/rt5677.c | 6 ++++++ sound/soc/codecs/rt5677.h | 2 ++ sound/soc/intel/boards/bdw-rt5677.c | 33 +++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index a65d1554366d..0e7773584145 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -5046,6 +5046,11 @@ static const struct snd_soc_dai_ops rt5677_aif_dai_ops = { .set_tdm_slot = rt5677_set_tdm_slot, };
+static const struct snd_soc_dai_ops rt5677_dsp_dai_ops = { + .set_sysclk = rt5677_set_dai_sysclk, + .set_pll = rt5677_set_dai_pll, +}; + static struct snd_soc_dai_driver rt5677_dai[] = { { .name = "rt5677-aif1", @@ -5152,6 +5157,7 @@ static struct snd_soc_dai_driver rt5677_dai[] = { .rates = SNDRV_PCM_RATE_16000, .formats = SNDRV_PCM_FMTBIT_S16_LE, }, + .ops = &rt5677_dsp_dai_ops, }, };
diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h index f8ada967fdbc..944ae02aafc2 100644 --- a/sound/soc/codecs/rt5677.h +++ b/sound/soc/codecs/rt5677.h @@ -1336,6 +1336,8 @@ #define RT5677_PLL_M_SFT 12 #define RT5677_PLL_M_BP (0x1 << 11) #define RT5677_PLL_M_BP_SFT 11 +#define RT5677_PLL_UPDATE_PLL1 (0x1 << 1) +#define RT5677_PLL_UPDATE_PLL1_SFT 1
/* Global Clock Control 1 (0x80) */ #define RT5677_SCLK_SRC_MASK (0x3 << 14) diff --git a/sound/soc/intel/boards/bdw-rt5677.c b/sound/soc/intel/boards/bdw-rt5677.c index b2475e3eff7b..2af8e5a62da8 100644 --- a/sound/soc/intel/boards/bdw-rt5677.c +++ b/sound/soc/intel/boards/bdw-rt5677.c @@ -170,10 +170,37 @@ static int bdw_rt5677_hw_params(struct snd_pcm_substream *substream, return ret; }
+static int bdw_rt5677_dsp_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + int ret; + + ret = snd_soc_dai_set_sysclk(codec_dai, RT5677_SCLK_S_PLL1, 24576000, + SND_SOC_CLOCK_IN); + if (ret < 0) { + dev_err(rtd->dev, "can't set codec sysclk configuration\n"); + return ret; + } + ret = snd_soc_dai_set_pll(codec_dai, 0, RT5677_PLL1_S_MCLK, + 24000000, 24576000); + if (ret < 0) { + dev_err(rtd->dev, "can't set codec pll configuration\n"); + return ret; + } + + return 0; +} + static const struct snd_soc_ops bdw_rt5677_ops = { .hw_params = bdw_rt5677_hw_params, };
+static const struct snd_soc_ops bdw_rt5677_dsp_ops = { + .hw_params = bdw_rt5677_dsp_hw_params, +}; + #if !IS_ENABLED(CONFIG_SND_SOC_SOF_BROADWELL) static int bdw_rt5677_rtd_init(struct snd_soc_pcm_runtime *rtd) { @@ -213,6 +240,11 @@ static int bdw_rt5677_init(struct snd_soc_pcm_runtime *rtd) rt5677_sel_asrc_clk_src(component, RT5677_DA_STEREO_FILTER | RT5677_AD_STEREO1_FILTER | RT5677_I2S1_SOURCE, RT5677_CLK_SEL_I2S1_ASRC); + /* Enable codec ASRC function for Mono ADC L. + * The ASRC clock source is clk_sys2_asrc. + */ + rt5677_sel_asrc_clk_src(component, RT5677_AD_MONO_L_FILTER, + RT5677_CLK_SEL_SYS2);
/* Request rt5677 GPIO for headphone amp control */ bdw_rt5677->gpio_hp_en = devm_gpiod_get(component->dev, "headphone-enable", @@ -291,6 +323,7 @@ static struct snd_soc_dai_link bdw_rt5677_dais[] = { { .name = "Codec DSP", .stream_name = "Wake on Voice", + .ops = &bdw_rt5677_dsp_ops, SND_SOC_DAILINK_REG(dsp), },
Wait for hardware to startup. If we load before hardware is ready we could end up corrupting the firmware.
Signed-off-by: Curtis Malainey cujomalainey@chromium.org --- sound/soc/codecs/rt5677.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index 0e7773584145..f2f763b4c399 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -892,6 +892,7 @@ static void rt5677_dsp_work(struct work_struct *work) container_of(work, struct rt5677_priv, dsp_work.work); static bool activity; bool enable = rt5677->dsp_vad_en; + int i, val;
dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n", @@ -913,6 +914,18 @@ static void rt5677_dsp_work(struct work_struct *work) rt5677_set_vad_source(rt5677); rt5677_set_dsp_mode(rt5677, true);
+#define RT5677_BOOT_RETRY 20 + for (i = 0; i < RT5677_BOOT_RETRY; i++) { + regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val); + if (val == 0x3ff) + break; + udelay(500); + } + if (i == RT5677_BOOT_RETRY && val != 0x3ff) { + dev_err(rt5677->component->dev, "DSP Boot Timed Out!"); + return; + } + /* Boot the firmware from IRAM instead of SRAM0. */ rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 0x0009, 0x0003);
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Curtis Malainey