[alsa-devel] [PATCH 0/4] ARM: sun8i: a83t: Add support for I2S and I2C
Hi everyone,
This series adds support for I2S and I2C on the Allwinner A83T SoC. The I2S controllers are similar to the ones found on the A31. However the TX FIFO and interrupt status registers were swapped around. This seems to be a recurring theme for the audio related hardware blocks.
Patch 1 adds support for the A83T variant with a compatible string and associated quirks structure.
Patch 2 adds device nodes and default pinmux settings for the I2S controllers.
Patch 3 adds device nodes and default pinmux settings for the I2C controllers.
Patch 4 is an example of a PCM5122 codec tied to I2C2 and I2S1 over the GPIO header of the Banana Pi M3. This patch should not be merged.
Please have a look.
Regards ChenYu
Chen-Yu Tsai (4): ASoC: sun4i-i2s: Add support for A83T ARM: dts: sun8i: a83t: Add I2S controller device nodes ARM: dts: sun8i: a83t: Add I2C device nodes and pinmux settings [DO NOT MERGE] ARM: dts: sun8i: a83t: bpi-m3: Enable PCM5122 codec with I2S1
.../devicetree/bindings/sound/sun4i-i2s.txt | 2 + arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 33 ++++++++ arch/arm/boot/dts/sun8i-a83t.dtsi | 99 ++++++++++++++++++++++ sound/soc/sunxi/sun4i-i2s.c | 21 +++++ 4 files changed, 155 insertions(+)
The I2S controller in the A83T is mostly compatible with the one found in earlier SoCs such as the A20 and A31. While the documents publicly available for the A83T do not cover this hardware, the officially released BSP kernel does have register definitions for it. These were matched against the A20 user manual. The only difference is the TX FIFO and interrupt status registers have been swapped around, like what we have seen with the SPDIF controller.
This patch adds support for this hardware.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- .../devicetree/bindings/sound/sun4i-i2s.txt | 2 ++ sound/soc/sunxi/sun4i-i2s.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt index 05d7135a8d2f..b9d50d6cdef3 100644 --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt @@ -8,6 +8,7 @@ Required properties: - compatible: should be one of the following: - "allwinner,sun4i-a10-i2s" - "allwinner,sun6i-a31-i2s" + - "allwinner,sun8i-a83t-i2s" - "allwinner,sun8i-h3-i2s" - reg: physical base address of the controller and length of memory mapped region. @@ -23,6 +24,7 @@ Required properties:
Required properties for the following compatibles: - "allwinner,sun6i-a31-i2s" + - "allwinner,sun8i-a83t-i2s" - "allwinner,sun8i-h3-i2s" - resets: phandle to the reset line for this codec
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index bc147e2dcff5..dca1143c1150 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -921,6 +921,23 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), };
+static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { + .has_reset = true, + .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, + .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), + .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), + .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), + .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), + .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), + .has_slave_select_bit = true, + .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), + .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), +}; + static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .has_reset = true, .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, @@ -1144,6 +1161,10 @@ static const struct of_device_id sun4i_i2s_match[] = { .compatible = "allwinner,sun6i-a31-i2s", .data = &sun6i_a31_i2s_quirks, }, + { + .compatible = "allwinner,sun8i-a83t-i2s", + .data = &sun8i_a83t_i2s_quirks, + }, { .compatible = "allwinner,sun8i-h3-i2s", .data = &sun8i_h3_i2s_quirks,
On Tue, Dec 12, 2017 at 04:11:45PM +0800, Chen-Yu Tsai wrote:
The I2S controller in the A83T is mostly compatible with the one found in earlier SoCs such as the A20 and A31. While the documents publicly available for the A83T do not cover this hardware, the officially released BSP kernel does have register definitions for it. These were matched against the A20 user manual. The only difference is the TX FIFO and interrupt status registers have been swapped around, like what we have seen with the SPDIF controller.
This patch adds support for this hardware.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
Maxime
The patch
ASoC: sun4i-i2s: Add support for A83T
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From 21faaea1343f2f8dc6539302c92231afc6d999a5 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai wens@csie.org Date: Tue, 12 Dec 2017 16:11:45 +0800 Subject: [PATCH] ASoC: sun4i-i2s: Add support for A83T
The I2S controller in the A83T is mostly compatible with the one found in earlier SoCs such as the A20 and A31. While the documents publicly available for the A83T do not cover this hardware, the officially released BSP kernel does have register definitions for it. These were matched against the A20 user manual. The only difference is the TX FIFO and interrupt status registers have been swapped around, like what we have seen with the SPDIF controller.
This patch adds support for this hardware.
Signed-off-by: Chen-Yu Tsai wens@csie.org Acked-by: Maxime Ripard maxime.ripard@free-electrons.com Signed-off-by: Mark Brown broonie@kernel.org --- .../devicetree/bindings/sound/sun4i-i2s.txt | 2 ++ sound/soc/sunxi/sun4i-i2s.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt index 05d7135a8d2f..b9d50d6cdef3 100644 --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt @@ -8,6 +8,7 @@ Required properties: - compatible: should be one of the following: - "allwinner,sun4i-a10-i2s" - "allwinner,sun6i-a31-i2s" + - "allwinner,sun8i-a83t-i2s" - "allwinner,sun8i-h3-i2s" - reg: physical base address of the controller and length of memory mapped region. @@ -23,6 +24,7 @@ Required properties:
Required properties for the following compatibles: - "allwinner,sun6i-a31-i2s" + - "allwinner,sun8i-a83t-i2s" - "allwinner,sun8i-h3-i2s" - resets: phandle to the reset line for this codec
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 04f92583a969..13d7ecabe1b6 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -897,6 +897,23 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), };
+static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { + .has_reset = true, + .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, + .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), + .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), + .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), + .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), + .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), + .has_slave_select_bit = true, + .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), + .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), +}; + static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .has_reset = true, .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, @@ -1120,6 +1137,10 @@ static const struct of_device_id sun4i_i2s_match[] = { .compatible = "allwinner,sun6i-a31-i2s", .data = &sun6i_a31_i2s_quirks, }, + { + .compatible = "allwinner,sun8i-a83t-i2s", + .data = &sun8i_a83t_i2s_quirks, + }, { .compatible = "allwinner,sun8i-h3-i2s", .data = &sun8i_h3_i2s_quirks,
The A83T has 3 I2S controllers. The first is multiplexed with the TDM controller. The pins are generally connected to the codec side of the AXP81x PMIC/codec/RTC chip. The second is free for other uses. The third only supports output, and is connected internally to the HDMI controller for HDMI audio output.
This patch adds device nodes for the controllers, and a default pinmux setting for the second controller.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/boot/dts/sun8i-a83t.dtsi | 47 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index a384b766f3dc..354cb4b48f47 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -348,6 +348,12 @@ drive-strength = <40>; };
+ i2s1_pins: i2s1-pins { + /* I2S1 does not have external MCLK pin */ + pins = "PG10", "PG11", "PG12", "PG13"; + function = "i2s1"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -430,6 +436,47 @@ status = "disabled"; };
+ i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + resets = <&ccu RST_BUS_I2S0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_pins>; + status = "disabled"; + }; + + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22800 0x400>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + dmas = <&dma 27>; + resets = <&ccu RST_BUS_I2S2>; + dma-names = "tx"; + status = "disabled"; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>;
Hi,
On Tue, Dec 12, 2017 at 04:11:46PM +0800, Chen-Yu Tsai wrote:
The A83T has 3 I2S controllers. The first is multiplexed with the TDM controller. The pins are generally connected to the codec side of the AXP81x PMIC/codec/RTC chip. The second is free for other uses. The third only supports output, and is connected internally to the HDMI controller for HDMI audio output.
This patch adds device nodes for the controllers, and a default pinmux setting for the second controller.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
The A83T has 3 I2C controllers under the standard bus. There is one more in the R_ block section. The pin functions for the 3 controllers are on PH 0~6. I2C2 can also be used on pins PE14 and PE15, but these pins can also mux the CSI (camera sensor interface) controller's embedded I2C controller. The latter seems to be preferred in the reference designs for I2C camera sensor access, freeing I2C2 for other uses.
This patch adds device nodes for the three standard I2C controllers, as well as pinmux settings for the PH pins. For I2C0 and I2C1, since they only have one possible setting, just set them by default.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/boot/dts/sun8i-a83t.dtsi | 52 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 354cb4b48f47..b8c5f0a2c463 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -348,6 +348,21 @@ drive-strength = <40>; };
+ i2c0_pins: i2c0-pins { + pins = "PH0", "PH1"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PH2", "PH3"; + function = "i2c1"; + }; + + i2c2_ph_pins: i2c2-ph-pins { + pins = "PH4", "PH5"; + function = "i2c2"; + }; + i2s1_pins: i2s1-pins { /* I2S1 does not have external MCLK pin */ pins = "PG10", "PG11", "PG12", "PG13"; @@ -499,6 +514,43 @@ status = "disabled"; };
+ i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@1c30000 { compatible = "allwinner,sun8i-a83t-emac"; syscon = <&syscon>;
Hi,
On Tue, Dec 12, 2017 at 04:11:47PM +0800, Chen-Yu Tsai wrote:
i2c0: i2c@1c2ac00 {compatible = "allwinner,sun6i-a31-i2c";
Same remark than for Mylene's patch here, you should have a per-SoC compatible first.
Once fixed, Acked-by: Maxime Ripard maxime.ripard@free-electrons.com
Maxime
This patch enables a PiFi DAC+ V2.0, which is a PCM5122-based audio output DAC add-on board for the Raspberry Pi B+ and later, connected to the GPIO header of the Bananapi M3 via jumper cables. The power, ground, and I2C pins are in the same position, but the I2S ones are not.
The I2C controller used is I2C2, while the I2S controller is I2S1.
Signed-off-by: Chen-Yu Tsai wens@csie.org ---
I'm sure I've asked this before, and IIRC the answer was yes: The I2C controllers available on the GPIO header all have proper, always-on, external pull-ups. Does that mean we can enable them by default, seeing as they are likely intended to be used this way (as I2C pins)?
I think we have a few boards where either I2C or UARTs on the GPIO header are enabled by default.
--- arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 6550bf0e594b..a9a208ebda12 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -70,6 +70,23 @@ gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ };
+ sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "PiFi DAC+ v2.0"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <512>; + simple-audio-card,frame-master = <&link_cpu>; + simple-audio-card,bitclock-master = <&link_cpu>; + + link_cpu: simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + + simple-audio-card,codec { + sound-dai = <&pcm5122>; + }; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; @@ -100,6 +117,22 @@ status = "okay"; };
+&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_ph_pins>; + status = "okay"; + + pcm5122: pcm5122@4d { + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; + }; +}; + +&i2s1 { + status = "okay"; +}; + &mdio { rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22";
Hi,
On Tue, Dec 12, 2017 at 04:11:48PM +0800, Chen-Yu Tsai wrote:
This patch enables a PiFi DAC+ V2.0, which is a PCM5122-based audio output DAC add-on board for the Raspberry Pi B+ and later, connected to the GPIO header of the Bananapi M3 via jumper cables. The power, ground, and I2C pins are in the same position, but the I2S ones are not.
The I2C controller used is I2C2, while the I2S controller is I2S1.
Signed-off-by: Chen-Yu Tsai wens@csie.org
I'm sure I've asked this before, and IIRC the answer was yes: The I2C controllers available on the GPIO header all have proper, always-on, external pull-ups. Does that mean we can enable them by default, seeing as they are likely intended to be used this way (as I2C pins)?
I think we have a few boards where either I2C or UARTs on the GPIO header are enabled by default.
The consensus we reached that we would fill the nodes, but leave them disabled.
In this particular case, I guess it would help for the i2c controller, but not for the i2s one.
Maxime
participants (3)
-
Chen-Yu Tsai -
Mark Brown -
Maxime Ripard