[alsa-devel] [PATCH 0/2] ASoC: Mediatek: MT8183: fix compile error
This patch fixed the compile error which patches for support S32_LE and S24_LE. The patch is based on broonie "for-5.3" branch.
Jiaxin Yu (2): ASoC: Mediatek: MT8183: fix compile error ASoC: Mediatek: MT8183: fix compile error
sound/soc/mediatek/common/mtk-afe-fe-dai.c | 3 +-- sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 18 +++++++++--------- 2 files changed, 10 insertions(+), 11 deletions(-)
mtk_regmap_update_bits() has been changed from four parameters to five parameters.
Fixes: 1628fc3f4771 ("ASoC: Mediatek: MT8183: add memory interface data align")
Signed-off-by: Jiaxin Yu jiaxin.yu@mediatek.com --- Hi, This patch is based on for-5.3 branch. And tested pass on kukui board locally. --- sound/soc/mediatek/common/mtk-afe-fe-dai.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/mediatek/common/mtk-afe-fe-dai.c b/sound/soc/mediatek/common/mtk-afe-fe-dai.c index 19048c3..d165634 100644 --- a/sound/soc/mediatek/common/mtk-afe-fe-dai.c +++ b/sound/soc/mediatek/common/mtk-afe-fe-dai.c @@ -266,8 +266,7 @@ int mtk_afe_fe_prepare(struct snd_pcm_substream *substream, 1, hd_audio, memif->data->hd_shift);
mtk_regmap_update_bits(afe->regmap, memif->data->hd_align_reg, - memif->data->hd_align_mshift, - hd_align ? memif->data->hd_align_mshift : 0); + 1, hd_align, memif->data->hd_align_mshift);
return 0; }
The patch
ASoC: Mediatek: MT8183: fix compile error
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.3
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From e355d3de196fe08e4de99bc0521c25a36c903b1b Mon Sep 17 00:00:00 2001
From: Jiaxin Yu jiaxin.yu@mediatek.com Date: Tue, 21 May 2019 17:29:37 +0800 Subject: [PATCH] ASoC: Mediatek: MT8183: fix compile error
mtk_regmap_update_bits() has been changed from four parameters to five parameters.
Fixes: 1628fc3f4771 ("ASoC: Mediatek: MT8183: add memory interface data align")
Signed-off-by: Jiaxin Yu jiaxin.yu@mediatek.com Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/mediatek/common/mtk-afe-fe-dai.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/mediatek/common/mtk-afe-fe-dai.c b/sound/soc/mediatek/common/mtk-afe-fe-dai.c index 19048c3dc324..d16563408465 100644 --- a/sound/soc/mediatek/common/mtk-afe-fe-dai.c +++ b/sound/soc/mediatek/common/mtk-afe-fe-dai.c @@ -266,8 +266,7 @@ int mtk_afe_fe_prepare(struct snd_pcm_substream *substream, 1, hd_audio, memif->data->hd_shift);
mtk_regmap_update_bits(afe->regmap, memif->data->hd_align_reg, - memif->data->hd_align_mshift, - hd_align ? memif->data->hd_align_mshift : 0); + 1, hd_align, memif->data->hd_align_mshift);
return 0; }
mtk_regmap_update_bits() has been changed to take a shift and warn when reg >= 0 but shift < 0.So the hd_align_mshift must not have shift. Change it from XXX_HD_ALIGN_MASK_SFT to XXX_HD_ALIGN_MASK.
Fixes: cf61f5b01531 ("ASoC: Mediatek: MT8183: set data align")
Signed-off-by: Jiaxin Yu jiaxin.yu@mediatek.com --- Hi, This patch is base on for-5.3 branch. And tested pass on kukui board locally. --- sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c index ab2bce1..56c3732 100644 --- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c +++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c @@ -439,7 +439,7 @@ static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = DL1_HD_SFT, - .hd_align_mshift = DL1_HD_ALIGN_MASK_SFT, + .hd_align_mshift = DL1_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -460,7 +460,7 @@ static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = DL2_HD_SFT, - .hd_align_mshift = DL2_HD_ALIGN_MASK_SFT, + .hd_align_mshift = DL2_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -481,7 +481,7 @@ static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = DL3_HD_SFT, - .hd_align_mshift = DL3_HD_ALIGN_MASK_SFT, + .hd_align_mshift = DL3_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -502,7 +502,7 @@ static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = VUL2_HD_SFT, - .hd_align_mshift = VUL2_HD_ALIGN_MASK_SFT, + .hd_align_mshift = VUL2_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -523,7 +523,7 @@ static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = AWB_HD_SFT, - .hd_align_mshift = AWB_HD_ALIGN_MASK_SFT, + .hd_align_mshift = AWB_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -544,7 +544,7 @@ static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = AWB2_HD_SFT, - .hd_align_mshift = AWB2_ALIGN_MASK_SFT, + .hd_align_mshift = AWB2_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -565,7 +565,7 @@ static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = VUL12_HD_SFT, - .hd_align_mshift = VUL12_HD_ALIGN_MASK_SFT, + .hd_align_mshift = VUL12_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -586,7 +586,7 @@ static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = MOD_DAI_HD_SFT, - .hd_align_mshift = MOD_DAI_HD_ALIGN_MASK_SFT, + .hd_align_mshift = MOD_DAI_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -607,7 +607,7 @@ static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = HDMI_HD_SFT, - .hd_align_mshift = HDMI_HD_ALIGN_MASK_SFT, + .hd_align_mshift = HDMI_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1,
The patch
ASoC: Mediatek: MT8183: fix compile error
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.3
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From 383d30e72e682021fdaf0371ade1c58ad2c434a4 Mon Sep 17 00:00:00 2001
From: Jiaxin Yu jiaxin.yu@mediatek.com Date: Tue, 21 May 2019 17:29:38 +0800 Subject: [PATCH] ASoC: Mediatek: MT8183: fix compile error
mtk_regmap_update_bits() has been changed to take a shift and warn when reg >= 0 but shift < 0.So the hd_align_mshift must not have shift. Change it from XXX_HD_ALIGN_MASK_SFT to XXX_HD_ALIGN_MASK.
Fixes: cf61f5b01531 ("ASoC: Mediatek: MT8183: set data align")
Signed-off-by: Jiaxin Yu jiaxin.yu@mediatek.com Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c index ab2bce1d9b3d..56c37323bc13 100644 --- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c +++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c @@ -439,7 +439,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = DL1_HD_SFT, - .hd_align_mshift = DL1_HD_ALIGN_MASK_SFT, + .hd_align_mshift = DL1_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -460,7 +460,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = DL2_HD_SFT, - .hd_align_mshift = DL2_HD_ALIGN_MASK_SFT, + .hd_align_mshift = DL2_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -481,7 +481,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = DL3_HD_SFT, - .hd_align_mshift = DL3_HD_ALIGN_MASK_SFT, + .hd_align_mshift = DL3_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -502,7 +502,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = VUL2_HD_SFT, - .hd_align_mshift = VUL2_HD_ALIGN_MASK_SFT, + .hd_align_mshift = VUL2_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -523,7 +523,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = AWB_HD_SFT, - .hd_align_mshift = AWB_HD_ALIGN_MASK_SFT, + .hd_align_mshift = AWB_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -544,7 +544,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = AWB2_HD_SFT, - .hd_align_mshift = AWB2_ALIGN_MASK_SFT, + .hd_align_mshift = AWB2_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -565,7 +565,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = VUL12_HD_SFT, - .hd_align_mshift = VUL12_HD_ALIGN_MASK_SFT, + .hd_align_mshift = VUL12_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -586,7 +586,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = MOD_DAI_HD_SFT, - .hd_align_mshift = MOD_DAI_HD_ALIGN_MASK_SFT, + .hd_align_mshift = MOD_DAI_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1, @@ -607,7 +607,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = { .hd_reg = AFE_MEMIF_HD_MODE, .hd_align_reg = AFE_MEMIF_HDALIGN, .hd_shift = HDMI_HD_SFT, - .hd_align_mshift = HDMI_HD_ALIGN_MASK_SFT, + .hd_align_mshift = HDMI_HD_ALIGN_SFT, .agent_disable_reg = -1, .agent_disable_shift = -1, .msb_reg = -1,
participants (2)
-
Jiaxin Yu -
Mark Brown