[alsa-devel] [PATCH 0/4] clk: Samsung: audss: Add support for Exynos5420
This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420 audio subsystem has a gate bit for ADMA controller and the some of parent clks for mout_i2s are also different from Exynos5250. So this patch adds provision for supporting both the platforms by passing the parent clk names through device tree.
Andrew Bresticker (3): clk: exynos-audss: add support for Exynos 5420 clk: exynos-audss: allow input clocks to be specified in device tree ARM: dts: exynos5420: add audio clock controller
Padmavathi Venna (1): ARM: dts: Correct the /include entry on exynos5420 dtsi file
.../devicetree/bindings/clock/clk-exynos-audss.txt | 38 +++++++++++++++++-- arch/arm/boot/dts/exynos5420.dtsi | 13 ++++++- drivers/clk/samsung/clk-exynos-audss.c | 36 ++++++++++++++++-- include/dt-bindings/clk/exynos-audss-clk.h | 3 +- 4 files changed, 80 insertions(+), 10 deletions(-)
From: Andrew Bresticker abrestic@chromium.org
The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock.
Signed-off-by: Andrew Bresticker abrestic@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/57711 Reviewed-by: Simon Glass sjg@chromium.org --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 7 +++++-- drivers/clk/samsung/clk-exynos-audss.c | 8 ++++++++ include/dt-bindings/clk/exynos-audss-clk.h | 3 ++- 3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index a120180..3115930 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -8,8 +8,10 @@ Required Properties:
- compatible: should be one of the following: - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. - - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs. - + - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 + SoCs. + - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 + SoCs. - reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1. @@ -34,6 +36,7 @@ i2s_bus 6 sclk_i2s 7 pcm_bus 8 sclk_pcm 9 +adma 10 Exynos5420
Example 1: An example of a clock controller node is listed below.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 9b1bbd5..86d2606 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -121,6 +121,12 @@ void __init exynos_audss_clk_init(struct device_node *np) "div_pcm0", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock);
+ if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) { + clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", + "dout_srp", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 9, 0, &lock); + } + #ifdef CONFIG_PM_SLEEP register_syscore_ops(&exynos_audss_clk_syscore_ops); #endif @@ -131,3 +137,5 @@ CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock", exynos_audss_clk_init); CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock", exynos_audss_clk_init); +CLK_OF_DECLARE(exynos5420_audss_clk, "samsung,exynos5420-audss-clock", + exynos_audss_clk_init); diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h index 8279f42..0ae6f5a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -19,7 +19,8 @@ #define EXYNOS_SCLK_I2S 7 #define EXYNOS_PCM_BUS 8 #define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10
-#define EXYNOS_AUDSS_MAX_CLKS 10 +#define EXYNOS_AUDSS_MAX_CLKS 11
#endif
From: Andrew Bresticker abrestic@chromium.org
This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. This will be useful when adding support for the Exynos5420 where the audio bus clock is called "sclk_maudio0" instead of "sclk_audio0".
Signed-off-by: Andrew Bresticker abrestic@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/57833 Reviewed-by: Simon Glass sjg@chromium.org --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 31 ++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c | 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 3115930..66d4662 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -16,6 +16,21 @@ Required Properties:
- #clock-cells: should be 1.
+Optional Properties: + +- clocks: + - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" + is used if not specified. + - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" + is used if not specified. + - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not + specified. + - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if + not specified. + +- clock-names: Aliases for the above clocks. They should be "pll_ref", + "pll_in", "cdclk", and "sclk_audio", respectively. + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. Some of the clocks are available only on a particular @@ -38,15 +53,27 @@ pcm_bus 8 sclk_pcm 9 adma 10 Exynos5420
-Example 1: An example of a clock controller node is listed below. +Example 1: An example of a clock controller node using the default input + clock names is listed below. + +clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; +}; + +Example 2: An example of a clock controller node with audio bus input clock + specified is listed below.
clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock 148>; + clock-names = "sclk_audio"; };
-Example 2: I2S controller node that consumes the clock generated by the clock +Example 3: I2S controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 86d2606..39d3383 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -32,10 +32,6 @@ static unsigned long reg_save[][2] = { {ASS_CLK_GATE, 0}, };
-/* list of all parent clock list */ -static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; -static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; - #ifdef CONFIG_PM_SLEEP static int exynos_audss_clk_suspend(void) { @@ -64,6 +60,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = { /* register exynos_audss clocks */ void __init exynos_audss_clk_init(struct device_node *np) { + const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; + const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; + struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio; + reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: failed to map audss registers\n", __func__); @@ -81,10 +81,30 @@ void __init exynos_audss_clk_init(struct device_node *np) clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+ pll_ref = of_clk_get_by_name(np, "pll_ref"); + pll_in = of_clk_get_by_name(np, "pll_in"); + if (!IS_ERR(pll_ref)) { + mout_audss_p[0] = __clk_get_name(pll_ref); + clk_put(pll_ref); + } + if (!IS_ERR(pll_in)) { + mout_audss_p[1] = __clk_get_name(pll_in); + clk_put(pll_in); + } clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), 0, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
+ cdclk = of_clk_get_by_name(np, "cdclk"); + sclk_audio = of_clk_get_by_name(np, "sclk_audio"); + if (!IS_ERR(cdclk)) { + mout_i2s_p[1] = __clk_get_name(cdclk); + clk_put(cdclk); + } + if (!IS_ERR(sclk_audio)) { + mout_i2s_p[2] = __clk_get_name(sclk_audio); + clk_put(sclk_audio); + } clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0, reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
Hi Padmavathi, Andrew,
On Wednesday 10 of July 2013 17:41:51 Padmavathi Venna wrote:
From: Andrew Bresticker abrestic@chromium.org
This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. This will be useful when adding support for the Exynos5420 where the audio bus clock is called "sclk_maudio0" instead of "sclk_audio0".
Signed-off-by: Andrew Bresticker abrestic@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/57833 Reviewed-by: Simon Glass sjg@chromium.org
.../devicetree/bindings/clock/clk-exynos-audss.txt | 31 ++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c | 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 deletions(-)
Well, this is basically how it should be done, but in current state of clock core I can see a problem: can we really rely on the order of clock initialization? I mean, we can't defer initialization of particular clock controller until all external clocks it needs are available, because there is no probing involved here.
Best regards, Tomasz
Quoting Tomasz Figa (2013-07-22 09:28:47)
Hi Padmavathi, Andrew,
On Wednesday 10 of July 2013 17:41:51 Padmavathi Venna wrote:
From: Andrew Bresticker abrestic@chromium.org
This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. This will be useful when adding support for the Exynos5420 where the audio bus clock is called "sclk_maudio0" instead of "sclk_audio0".
Signed-off-by: Andrew Bresticker abrestic@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/57833 Reviewed-by: Simon Glass sjg@chromium.org
.../devicetree/bindings/clock/clk-exynos-audss.txt | 31 ++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c | 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 deletions(-)
Well, this is basically how it should be done, but in current state of clock core I can see a problem: can we really rely on the order of clock initialization? I mean, we can't defer initialization of particular clock controller until all external clocks it needs are available, because there is no probing involved here.
The clock core allows registering clocks even if their parents are not yet registered. I test this path with some dummy clocks every so often to make sure the re-parenting operation are completed successfully after the parents eventually are registered.
This feature was not used in practice until recently with the advent of multiple clock controllers getting registered and DT description of clocks / clock controllers that may be "out of order". If you find any bugs please let me know ;-)
Regards, Mike
Best regards, Tomasz
On Monday 22 of July 2013 11:15:30 Mike Turquette wrote:
Quoting Tomasz Figa (2013-07-22 09:28:47)
Hi Padmavathi, Andrew,
On Wednesday 10 of July 2013 17:41:51 Padmavathi Venna wrote:
From: Andrew Bresticker abrestic@chromium.org
This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. This will be useful when adding support for the Exynos5420 where the audio bus clock is called "sclk_maudio0" instead of "sclk_audio0".
Signed-off-by: Andrew Bresticker abrestic@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/57833 Reviewed-by: Simon Glass sjg@chromium.org
.../devicetree/bindings/clock/clk-exynos-audss.txt | 31
++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c |> > 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 deletions(-)
Well, this is basically how it should be done, but in current state of clock core I can see a problem: can we really rely on the order of clock initialization? I mean, we can't defer initialization of particular clock controller until all external clocks it needs are available, because there is no probing involved here.
The clock core allows registering clocks even if their parents are not yet registered. I test this path with some dummy clocks every so often to make sure the re-parenting operation are completed successfully after the parents eventually are registered.
Sure it does, but this patch is about something different. It adds device tree based lookup (of_clk_get_by_name()) of external clocks (as opposed to existing lookup by name), which will fail if provider pointed by phandle is not registered yet.
This feature was not used in practice until recently with the advent of multiple clock controllers getting registered and DT description of clocks / clock controllers that may be "out of order". If you find any bugs please let me know ;-)
I will send you a bunch of patches sorting out issues I found in clk_set_rate() path, but give me some time to prepare them :).
As for multiple clock controllers, this is going to be funny. I have discussed this a bit with Sylwester and we managed to find some design issues that I think must be solved:
a) What about multiple controllers with identical clock names? Imagine two PMICs that can also generate 32 KHz clocks, both having them named "clk32k". Am I right saying that this won't work with current code?
b) What are the rules of using clock-output-names property (and what should be used in non-DT case)? I can imagine using it to assign platform- specific names of clock outputs of extra clock controllers (this would help in the above case of "clk32k"), but currently it seems like it is optional to use it in clock drivers and the meaning is provider-specific.
Best regards, Tomasz
Hi Tomasz,
On Tue, Jul 23, 2013 at 1:12 AM, Tomasz Figa tomasz.figa@gmail.com wrote:
On Monday 22 of July 2013 11:15:30 Mike Turquette wrote:
Quoting Tomasz Figa (2013-07-22 09:28:47)
Hi Padmavathi, Andrew,
On Wednesday 10 of July 2013 17:41:51 Padmavathi Venna wrote:
From: Andrew Bresticker abrestic@chromium.org
This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. This will be useful when adding support for the Exynos5420 where the audio bus clock is called "sclk_maudio0" instead of "sclk_audio0".
Signed-off-by: Andrew Bresticker abrestic@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/57833 Reviewed-by: Simon Glass sjg@chromium.org
.../devicetree/bindings/clock/clk-exynos-audss.txt | 31
++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c |> > 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 deletions(-)
Well, this is basically how it should be done, but in current state of clock core I can see a problem: can we really rely on the order of clock initialization? I mean, we can't defer initialization of particular clock controller until all external clocks it needs are available, because there is no probing involved here.
your point is valid. In this case audio clk controller registration happening only after CMU clk controller from which audss needs clks. So this patch can't be taken in?
Thanks Padma
The clock core allows registering clocks even if their parents are not yet registered. I test this path with some dummy clocks every so often to make sure the re-parenting operation are completed successfully after the parents eventually are registered.
Sure it does, but this patch is about something different. It adds device tree based lookup (of_clk_get_by_name()) of external clocks (as opposed to existing lookup by name), which will fail if provider pointed by phandle is not registered yet.
This feature was not used in practice until recently with the advent of multiple clock controllers getting registered and DT description of clocks / clock controllers that may be "out of order". If you find any bugs please let me know ;-)
I will send you a bunch of patches sorting out issues I found in clk_set_rate() path, but give me some time to prepare them :).
As for multiple clock controllers, this is going to be funny. I have discussed this a bit with Sylwester and we managed to find some design issues that I think must be solved:
a) What about multiple controllers with identical clock names? Imagine two PMICs that can also generate 32 KHz clocks, both having them named "clk32k". Am I right saying that this won't work with current code?
b) What are the rules of using clock-output-names property (and what should be used in non-DT case)? I can imagine using it to assign platform- specific names of clock outputs of extra clock controllers (this would help in the above case of "clk32k"), but currently it seems like it is optional to use it in clock drivers and the meaning is provider-specific.
Best regards, Tomasz
This patch corrects the /include to #include on exynos5420
Signed-off-by: Padmavathi Venna padma.v@samsung.com --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8c54c4b..da55160 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -14,7 +14,7 @@ */
#include "exynos5.dtsi" -/include/ "exynos5420-pinctrl.dtsi" +#include "exynos5420-pinctrl.dtsi" / { compatible = "samsung,exynos5420";
On 07/10/13 21:11, Padmavathi Venna wrote:
This patch corrects the /include to #include on exynos5420
Signed-off-by: Padmavathi Vennapadma.v@samsung.com
arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8c54c4b..da55160 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -14,7 +14,7 @@ */
#include "exynos5.dtsi" -/include/ "exynos5420-pinctrl.dtsi" +#include "exynos5420-pinctrl.dtsi" / { compatible = "samsung,exynos5420";
Applied, thanks.
- Kukjin
From: Andrew Bresticker abrestic@chromium.org
This adds device-tree bindings for the audio subsystem clock controller on Exynos 5420.
Signed-off-by: Andrew Bresticker abrestic@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/57712 Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Padmavathi Venna padma.v@samsung.com --- arch/arm/boot/dts/exynos5420.dtsi | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index da55160..a84f5f1 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -15,6 +15,9 @@
#include "exynos5.dtsi" #include "exynos5420-pinctrl.dtsi" + +#include <dt-bindings/clk/exynos-audss-clk.h> + / { compatible = "samsung,exynos5420";
@@ -65,6 +68,14 @@ #clock-cells = <1>; };
+ clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5420-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + clocks = <&clock 148>; + clock-names = "sclk_audio"; + }; + mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>;
On 07/10/13 21:11, Padmavathi Venna wrote:
From: Andrew Brestickerabrestic@chromium.org
This adds device-tree bindings for the audio subsystem clock controller on Exynos 5420.
Signed-off-by: Andrew Brestickerabrestic@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/57712 Reviewed-by: Simon Glasssjg@chromium.org Signed-off-by: Padmavathi Vennapadma.v@samsung.com
arch/arm/boot/dts/exynos5420.dtsi | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index da55160..a84f5f1 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -15,6 +15,9 @@
#include "exynos5.dtsi" #include "exynos5420-pinctrl.dtsi"
+#include<dt-bindings/clk/exynos-audss-clk.h>
- / { compatible = "samsung,exynos5420";
@@ -65,6 +68,14 @@ #clock-cells =<1>; };
- clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5420-audss-clock";reg =<0x03810000 0x0C>;#clock-cells =<1>;clocks =<&clock 148>;clock-names = "sclk_audio";- };
- mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg =<0x101C0000 0x800>;
Applied, thanks.
- Kukjin
Hi Kukjin,
Any comments on this patch set?
Thanks Padma
On Wed, Jul 10, 2013 at 5:41 PM, Padmavathi Venna padma.v@samsung.com wrote:
This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420 audio subsystem has a gate bit for ADMA controller and the some of parent clks for mout_i2s are also different from Exynos5250. So this patch adds provision for supporting both the platforms by passing the parent clk names through device tree.
Andrew Bresticker (3): clk: exynos-audss: add support for Exynos 5420 clk: exynos-audss: allow input clocks to be specified in device tree ARM: dts: exynos5420: add audio clock controller
Padmavathi Venna (1): ARM: dts: Correct the /include entry on exynos5420 dtsi file
.../devicetree/bindings/clock/clk-exynos-audss.txt | 38 +++++++++++++++++-- arch/arm/boot/dts/exynos5420.dtsi | 13 ++++++- drivers/clk/samsung/clk-exynos-audss.c | 36 ++++++++++++++++-- include/dt-bindings/clk/exynos-audss-clk.h | 3 +- 4 files changed, 80 insertions(+), 10 deletions(-)
-- 1.7.4.4
participants (6)
-
Kukjin Kim -
Mike Turquette -
Padma Venkat -
Padmavathi Venna -
Tomasz Figa -
Tomasz Figa