[PATCH v2 0/5] Add I2S support for the StarFive JH7110 SoC
This patch series adds I2S support for the StarFive JH7110 RISC-V SoC based on Designware I2S controller. There has three I2S channels (RX/TX0/TX1) on the JH7110 SoC, one of which is for record(RX) and two for playback(TX).
The first patch adds support for the StarFive JH7110 SoC in the Designware I2S bindings. The second patch adds the ops to get data from platform bus in the I2S driver. The third patch adds support for the StarFive JH7110 SoC in the Designware I2S driver. The fourth patch fixes the name of I2STX1 pinmux. The last patch adds device node of I2S RX/TX0/TX1 in JH7110 dts.
This patch series is based on Linux-next(20230818) which is merge clock, syscon and dma nodes for the StarFive JH7110 SoC.
The series has been tested and works normally on the VisionFive 2 board by plugging an audio expansion board.
Changes since v1: - Added the maxItems of clocks, clock-names and resets on each I2S controllers in the binding. - Dropped the useless settings about dma bus width in the I2S driver. - Used the 'i2s@' instead of 'i2stx@' or 'i2srx@' in the JH7110 dts.
v1: https://lore.kernel.org/all/20230802084301.134122-1-xingyu.wu@starfivetech.c...
Xingyu Wu (5): ASoC: dt-bindings: snps,designware-i2s: Add StarFive JH7110 SoC support ASoC: dwc: Use ops to get platform data ASoC: dwc: i2s: Add StarFive JH7110 SoC support riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1 riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1
.../bindings/sound/snps,designware-i2s.yaml | 108 ++++++- arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 4 +- .../jh7110-starfive-visionfive-2.dtsi | 58 ++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 65 ++++ include/sound/designware_i2s.h | 3 + sound/soc/dwc/dwc-i2s.c | 306 ++++++++++++++++-- sound/soc/dwc/local.h | 1 + 7 files changed, 518 insertions(+), 27 deletions(-)
Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the StarFive JH7110 SoC.
Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com --- .../jh7110-starfive-visionfive-2.dtsi | 58 +++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 65 +++++++++++++++++++ 2 files changed, 123 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index d79f94432b27..7179f1a31cf2 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -203,6 +203,24 @@ &i2c6 { status = "okay"; };
+&i2srx { + pinctrl-names = "default"; + pinctrl-0 = <&i2srx_pins>; + status = "okay"; +}; + +&i2stx0 { + pinctrl-names = "default"; + pinctrl-0 = <&mclk_ext_pins>; + status = "okay"; +}; + +&i2stx1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2stx1_pins>; + status = "okay"; +}; + &mmc0 { max-frequency = <100000000>; bus-width = <8>; @@ -337,6 +355,46 @@ GPOEN_SYS_I2C6_DATA, }; };
+ i2srx_pins: i2srx-0 { + clk-sd-pins { + pinmux = <GPIOMUX(38, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2SRX_BCLK)>, + <GPIOMUX(63, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2SRX_LRCK)>, + <GPIOMUX(38, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2STX1_BCLK)>, + <GPIOMUX(63, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2STX1_LRCK)>, + <GPIOMUX(61, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_I2SRX_SDIN0)>; + input-enable; + }; + }; + + i2stx1_pins: i2stx1-0 { + sd-pins { + pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + input-disable; + }; + }; + + mclk_ext_pins: mclk-ext-0 { + mclk-ext-pins { + pinmux = <GPIOMUX(4, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_MCLK_EXT)>; + input-enable; + }; + }; + mmc0_pins: mmc0-0 { rst-pins { pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index e85464c328d0..621b68c02ea8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -512,6 +512,30 @@ tdm: tdm@10090000 { status = "disabled"; };
+ i2srx: i2s@100e0000 { + compatible = "starfive,jh7110-i2srx"; + reg = <0x0 0x100e0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2SRX_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>, + <&syscrg JH7110_SYSCLK_I2SRX_BCLK>, + <&syscrg JH7110_SYSCLK_I2SRX_LRCK>, + <&i2srx_bclk_ext>, + <&i2srx_lrck_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner", "mclk_ext", "bclk", + "lrck", "bclk_ext", "lrck_ext"; + resets = <&syscrg JH7110_SYSRST_I2SRX_APB>, + <&syscrg JH7110_SYSRST_I2SRX_BCLK>; + dmas = <0>, <&dma 24>; + dma-names = "tx", "rx"; + starfive,syscon = <&sys_syscon 0x18 0x2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + usb0: usb@10100000 { compatible = "starfive,jh7110-usb"; ranges = <0x0 0x0 0x10100000 0x100000>; @@ -736,6 +760,47 @@ spi6: spi@120a0000 { status = "disabled"; };
+ i2stx0: i2s@120b0000 { + compatible = "starfive,jh7110-i2stx0"; + reg = <0x0 0x120b0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2STX0_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner","mclk_ext"; + resets = <&syscrg JH7110_SYSRST_I2STX0_APB>, + <&syscrg JH7110_SYSRST_I2STX0_BCLK>; + dmas = <&dma 47>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2stx1: i2s@120c0000 { + compatible = "starfive,jh7110-i2stx1"; + reg = <0x0 0x120c0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2STX1_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>, + <&syscrg JH7110_SYSCLK_I2STX1_BCLK>, + <&syscrg JH7110_SYSCLK_I2STX1_LRCK>, + <&i2stx_bclk_ext>, + <&i2stx_lrck_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner", "mclk_ext", "bclk", + "lrck", "bclk_ext", "lrck_ext"; + resets = <&syscrg JH7110_SYSRST_I2STX1_APB>, + <&syscrg JH7110_SYSRST_I2STX1_BCLK>; + dmas = <&dma 48>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sfctemp: temperature-sensor@120e0000 { compatible = "starfive,jh7110-temp"; reg = <0x0 0x120e0000 0x0 0x10000>;
On 2023/8/21 22:41, Xingyu Wu wrote:
Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the StarFive JH7110 SoC.
Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com
.../jh7110-starfive-visionfive-2.dtsi | 58 +++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 65 +++++++++++++++++++ 2 files changed, 123 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index d79f94432b27..7179f1a31cf2 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -203,6 +203,24 @@ &i2c6 { status = "okay"; };
+&i2srx {
- pinctrl-names = "default";
- pinctrl-0 = <&i2srx_pins>;
- status = "okay";
+};
+&i2stx0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mclk_ext_pins>;
- status = "okay";
+};
+&i2stx1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2stx1_pins>;
- status = "okay";
+};
&mmc0 { max-frequency = <100000000>; bus-width = <8>; @@ -337,6 +355,46 @@ GPOEN_SYS_I2C6_DATA, }; };
- i2srx_pins: i2srx-0 {
clk-sd-pins {pinmux = <GPIOMUX(38, GPOUT_LOW,GPOEN_DISABLE,GPI_SYS_I2SRX_BCLK)>,<GPIOMUX(63, GPOUT_LOW,GPOEN_DISABLE,GPI_SYS_I2SRX_LRCK)>,<GPIOMUX(38, GPOUT_LOW,GPOEN_DISABLE,GPI_SYS_I2STX1_BCLK)>,<GPIOMUX(63, GPOUT_LOW,GPOEN_DISABLE,GPI_SYS_I2STX1_LRCK)>,<GPIOMUX(61, GPOUT_LOW,GPOEN_DISABLE,GPI_SYS_I2SRX_SDIN0)>;input-enable;};- };
- i2stx1_pins: i2stx1-0 {
sd-pins {pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0,GPOEN_ENABLE,GPI_NONE)>;bias-disable;input-disable;};- };
- mclk_ext_pins: mclk-ext-0 {
mclk-ext-pins {pinmux = <GPIOMUX(4, GPOUT_LOW,GPOEN_DISABLE,GPI_SYS_MCLK_EXT)>;input-enable;};- };
- mmc0_pins: mmc0-0 { rst-pins { pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index e85464c328d0..621b68c02ea8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -512,6 +512,30 @@ tdm: tdm@10090000 { status = "disabled"; };
i2srx: i2s@100e0000 {compatible = "starfive,jh7110-i2srx";reg = <0x0 0x100e0000 0x0 0x1000>;clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,<&syscrg JH7110_SYSCLK_I2SRX_APB>,<&syscrg JH7110_SYSCLK_MCLK>,<&syscrg JH7110_SYSCLK_MCLK_INNER>,<&mclk_ext>,<&syscrg JH7110_SYSCLK_I2SRX_BCLK>,<&syscrg JH7110_SYSCLK_I2SRX_LRCK>,<&i2srx_bclk_ext>,<&i2srx_lrck_ext>;clock-names = "i2sclk", "apb", "mclk","mclk_inner", "mclk_ext", "bclk","lrck", "bclk_ext", "lrck_ext";resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,<&syscrg JH7110_SYSRST_I2SRX_BCLK>;dmas = <0>, <&dma 24>;dma-names = "tx", "rx";starfive,syscon = <&sys_syscon 0x18 0x2>;#sound-dai-cells = <0>;status = "disabled";};- usb0: usb@10100000 { compatible = "starfive,jh7110-usb"; ranges = <0x0 0x0 0x10100000 0x100000>;
@@ -736,6 +760,47 @@ spi6: spi@120a0000 { status = "disabled"; };
i2stx0: i2s@120b0000 {compatible = "starfive,jh7110-i2stx0";reg = <0x0 0x120b0000 0x0 0x1000>;clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,<&syscrg JH7110_SYSCLK_I2STX0_APB>,<&syscrg JH7110_SYSCLK_MCLK>,<&syscrg JH7110_SYSCLK_MCLK_INNER>,<&mclk_ext>;clock-names = "i2sclk", "apb", "mclk","mclk_inner","mclk_ext";resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,<&syscrg JH7110_SYSRST_I2STX0_BCLK>;dmas = <&dma 47>;dma-names = "tx";#sound-dai-cells = <0>;status = "disabled";};i2stx1: i2s@120c0000 {compatible = "starfive,jh7110-i2stx1";reg = <0x0 0x120c0000 0x0 0x1000>;clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,<&syscrg JH7110_SYSCLK_I2STX1_APB>,<&syscrg JH7110_SYSCLK_MCLK>,<&syscrg JH7110_SYSCLK_MCLK_INNER>,<&mclk_ext>,<&syscrg JH7110_SYSCLK_I2STX1_BCLK>,<&syscrg JH7110_SYSCLK_I2STX1_LRCK>,<&i2stx_bclk_ext>,<&i2stx_lrck_ext>;clock-names = "i2sclk", "apb", "mclk","mclk_inner", "mclk_ext", "bclk","lrck", "bclk_ext", "lrck_ext";resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,<&syscrg JH7110_SYSRST_I2STX1_BCLK>;dmas = <&dma 48>;dma-names = "tx";#sound-dai-cells = <0>;status = "disabled";};- sfctemp: temperature-sensor@120e0000 { compatible = "starfive,jh7110-temp"; reg = <0x0 0x120e0000 0x0 0x10000>;
Reviewed-by: Walker Chen walker.chen@starfivetech.com Thanks!
These pins are actually I2STX1 clock input, not I2STX0, so their names should be changed.
Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com --- arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h index fb0139b56723..256de17f5261 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h +++ b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h @@ -240,8 +240,8 @@ #define GPI_SYS_MCLK_EXT 30 #define GPI_SYS_I2SRX_BCLK 31 #define GPI_SYS_I2SRX_LRCK 32 -#define GPI_SYS_I2STX0_BCLK 33 -#define GPI_SYS_I2STX0_LRCK 34 +#define GPI_SYS_I2STX1_BCLK 33 +#define GPI_SYS_I2STX1_LRCK 34 #define GPI_SYS_TDM_CLK 35 #define GPI_SYS_TDM_RXD 36 #define GPI_SYS_TDM_SYNC 37
On 2023/8/21 22:41, Xingyu Wu wrote:
These pins are actually I2STX1 clock input, not I2STX0, so their names should be changed.
Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com
arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h index fb0139b56723..256de17f5261 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h +++ b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h @@ -240,8 +240,8 @@ #define GPI_SYS_MCLK_EXT 30 #define GPI_SYS_I2SRX_BCLK 31 #define GPI_SYS_I2SRX_LRCK 32 -#define GPI_SYS_I2STX0_BCLK 33 -#define GPI_SYS_I2STX0_LRCK 34 +#define GPI_SYS_I2STX1_BCLK 33 +#define GPI_SYS_I2STX1_LRCK 34 #define GPI_SYS_TDM_CLK 35 #define GPI_SYS_TDM_RXD 36 #define GPI_SYS_TDM_SYNC 37
Reviewed-by: Walker Chen walker.chen@starfivetech.com Thanks!
On Mon, 21 Aug 2023 22:41:50 +0800, Xingyu Wu wrote:
These pins are actually I2STX1 clock input, not I2STX0, so their names should be changed.
Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com
arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Rob Herring robh@kernel.org
Use of_device_get_match_data() to get platform data.
Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com --- sound/soc/dwc/dwc-i2s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c index 0a4698008d64..e70d41d57dfd 100644 --- a/sound/soc/dwc/dwc-i2s.c +++ b/sound/soc/dwc/dwc-i2s.c @@ -691,7 +691,7 @@ static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
static int dw_i2s_probe(struct platform_device *pdev) { - const struct i2s_platform_data *pdata = pdev->dev.platform_data; + const struct i2s_platform_data *pdata = of_device_get_match_data(&pdev->dev); struct dw_i2s_dev *dev; struct resource *res; int ret, irq;
Add StarFive JH7110(TX0/TX1/RX channels) SoC support in the designware I2S driver and a flag to check if it is on the JH7110 SoC.
These channels need to enable clocks, resets and syscon register on the JH7110 SoC. So add init ops in platform data for the JH7110 SoC to do this.
Their resets should be deassert before changing the parent of clocks so these are done in the init ops of platform data.
The I2S controllers use DMA controller by platform data on the JH7110 and their settings about snd_dmaengine_dai_dma_data() should be added in the dw_configure_dai_by_pd(). And use dmaengine PCM registration if these do not have IRQ on the JH7110 SoC.
Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com --- include/sound/designware_i2s.h | 3 + sound/soc/dwc/dwc-i2s.c | 304 ++++++++++++++++++++++++++++++--- sound/soc/dwc/local.h | 1 + 3 files changed, 287 insertions(+), 21 deletions(-)
diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h index 80d275b9ae0d..f6803205a9fb 100644 --- a/include/sound/designware_i2s.h +++ b/include/sound/designware_i2s.h @@ -21,6 +21,8 @@ struct i2s_clk_config_data { u32 sample_rate; };
+struct dw_i2s_dev; + struct i2s_platform_data { #define DWC_I2S_PLAY (1 << 0) #define DWC_I2S_RECORD (1 << 1) @@ -42,6 +44,7 @@ struct i2s_platform_data { void *capture_dma_data; bool (*filter)(struct dma_chan *chan, void *slave); int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); + int (*i2s_pd_init)(struct dw_i2s_dev *dev); };
struct i2s_dma_data { diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c index e70d41d57dfd..5ab1b3eb2d28 100644 --- a/sound/soc/dwc/dwc-i2s.c +++ b/sound/soc/dwc/dwc-i2s.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/interrupt.h> +#include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/reset.h> #include <linux/slab.h> @@ -198,7 +199,8 @@ static void i2s_start(struct dw_i2s_dev *dev, else i2s_write_reg(dev->i2s_base, IRER, 1);
- if (dev->use_pio) + /* I2S needs to enable IRQ to make a handshake with DMAC on the JH7110 SoC */ + if (dev->use_pio || dev->is_jh7110) i2s_enable_irqs(dev, substream->stream, config->chan_nr); else i2s_enable_dma(dev, substream->stream); @@ -216,7 +218,7 @@ static void i2s_stop(struct dw_i2s_dev *dev, else i2s_write_reg(dev->i2s_base, IRER, 0);
- if (dev->use_pio) + if (dev->use_pio || dev->is_jh7110) i2s_disable_irqs(dev, substream->stream, 8); else i2s_disable_dma(dev, substream->stream); @@ -227,6 +229,21 @@ static void i2s_stop(struct dw_i2s_dev *dev, } }
+static int dw_i2s_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); + + if (dev->is_jh7110) { + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); + struct snd_soc_dai_link *dai_link = rtd->dai_link; + + dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC; + } + + return 0; +} + static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) { u32 ch_reg; @@ -453,6 +470,7 @@ static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
static const struct snd_soc_dai_ops dw_i2s_dai_ops = { .probe = dw_i2s_dai_probe, + .startup = dw_i2s_startup, .hw_params = dw_i2s_hw_params, .prepare = dw_i2s_prepare, .trigger = dw_i2s_trigger, @@ -637,17 +655,39 @@ static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) idx = 1; - /* Set DMA slaves info */ - dev->play_dma_data.pd.data = pdata->play_dma_data; - dev->capture_dma_data.pd.data = pdata->capture_dma_data; - dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; - dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; - dev->play_dma_data.pd.max_burst = 16; - dev->capture_dma_data.pd.max_burst = 16; - dev->play_dma_data.pd.addr_width = bus_widths[idx]; - dev->capture_dma_data.pd.addr_width = bus_widths[idx]; - dev->play_dma_data.pd.filter = pdata->filter; - dev->capture_dma_data.pd.filter = pdata->filter; + + if (dev->is_jh7110) { + /* Use platform data and snd_dmaengine_dai_dma_data struct at the same time */ + u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); + u32 idx2; + + if (COMP1_TX_ENABLED(comp1)) { + idx2 = COMP1_TX_WORDSIZE_0(comp1); + dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; + dev->play_dma_data.dt.fifo_size = dev->fifo_th * 2 * + (fifo_width[idx2]) >> 8; + dev->play_dma_data.dt.maxburst = 16; + } + if (COMP1_RX_ENABLED(comp1)) { + idx2 = COMP2_RX_WORDSIZE_0(comp2); + dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; + dev->capture_dma_data.dt.fifo_size = dev->fifo_th * 2 * + (fifo_width[idx2] >> 8); + dev->capture_dma_data.dt.maxburst = 16; + } + } else { + /* Set DMA slaves info */ + dev->play_dma_data.pd.data = pdata->play_dma_data; + dev->capture_dma_data.pd.data = pdata->capture_dma_data; + dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; + dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; + dev->play_dma_data.pd.max_burst = 16; + dev->capture_dma_data.pd.max_burst = 16; + dev->play_dma_data.pd.addr_width = bus_widths[idx]; + dev->capture_dma_data.pd.addr_width = bus_widths[idx]; + dev->play_dma_data.pd.filter = pdata->filter; + dev->capture_dma_data.pd.filter = pdata->filter; + }
return 0; } @@ -689,6 +729,190 @@ static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
}
+/* clocks initialization with master mode on JH7110 SoC */ +static int jh7110_i2s_crg_master_init(struct dw_i2s_dev *dev) +{ + static struct clk_bulk_data clks[] = { + { .id = "mclk" }, + { .id = "mclk_ext" }, + { .id = "mclk_inner" }, + { .id = "apb" }, + { .id = "i2sclk" }, + }; + struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); + int ret; + struct clk *pclk; + struct clk *bclk_mst; + struct clk *mclk; + struct clk *mclk_ext; + struct clk *mclk_inner; + + if (IS_ERR(resets)) + return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); + + ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); + if (ret) + return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); + + mclk = clks[0].clk; + mclk_ext = clks[1].clk; + mclk_inner = clks[2].clk; + pclk = clks[3].clk; + bclk_mst = clks[4].clk; + + ret = clk_prepare_enable(pclk); + if (ret) + goto exit; + + /* Use inner mclk first and avoid uninitialized gpio for external mclk */ + ret = clk_set_parent(mclk, mclk_inner); + if (ret) + goto err_dis_pclk; + + ret = clk_prepare_enable(bclk_mst); + if (ret) + goto err_dis_pclk; + + /* deassert resets before set clock parent */ + ret = reset_control_deassert(resets); + if (ret) + goto err_dis_all; + + /* external clock (12.288MHz) for Audio */ + ret = clk_set_parent(mclk, mclk_ext); + if (ret) + goto err_dis_all; + + /* i2sclk will be got and enabled repeatedly later and should be disabled now. */ + clk_disable_unprepare(bclk_mst); + clk_bulk_put(ARRAY_SIZE(clks), clks); + dev->is_jh7110 = true; + + return 0; + +err_dis_all: + clk_disable_unprepare(bclk_mst); +err_dis_pclk: + clk_disable_unprepare(pclk); +exit: + clk_bulk_put(ARRAY_SIZE(clks), clks); + return ret; +} + +/* clocks initialization with slave mode on JH7110 SoC */ +static int jh7110_i2s_crg_slave_init(struct dw_i2s_dev *dev) +{ + static struct clk_bulk_data clks[] = { + { .id = "mclk" }, + { .id = "mclk_ext" }, + { .id = "apb" }, + { .id = "bclk_ext" }, + { .id = "lrck_ext" }, + { .id = "bclk" }, + { .id = "lrck" }, + { .id = "mclk_inner" }, + { .id = "i2sclk" }, + }; + struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); + int ret; + struct clk *pclk; + struct clk *bclk_mst; + struct clk *bclk_ext; + struct clk *lrck_ext; + struct clk *bclk; + struct clk *lrck; + struct clk *mclk; + struct clk *mclk_ext; + struct clk *mclk_inner; + + if (IS_ERR(resets)) + return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); + + ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); + if (ret) + return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); + + mclk = clks[0].clk; + mclk_ext = clks[1].clk; + pclk = clks[2].clk; + bclk_ext = clks[3].clk; + lrck_ext = clks[4].clk; + bclk = clks[5].clk; + lrck = clks[6].clk; + mclk_inner = clks[7].clk; + bclk_mst = clks[8].clk; + + ret = clk_prepare_enable(pclk); + if (ret) + goto exit; + + ret = clk_set_parent(mclk, mclk_inner); + if (ret) + goto err_dis_pclk; + + ret = clk_prepare_enable(bclk_mst); + if (ret) + goto err_dis_pclk; + + ret = reset_control_deassert(resets); + if (ret) + goto err_dis_all; + + /* The sources of BCLK and LRCK are the external codec. */ + ret = clk_set_parent(bclk, bclk_ext); + if (ret) + goto err_dis_all; + + ret = clk_set_parent(lrck, lrck_ext); + if (ret) + goto err_dis_all; + + ret = clk_set_parent(mclk, mclk_ext); + if (ret) + goto err_dis_all; + + /* The i2sclk will be got and enabled repeatedly later and should be disabled now. */ + clk_disable_unprepare(bclk_mst); + clk_bulk_put(ARRAY_SIZE(clks), clks); + dev->is_jh7110 = true; + + return 0; + +err_dis_all: + clk_disable_unprepare(bclk_mst); +err_dis_pclk: + clk_disable_unprepare(pclk); +exit: + clk_bulk_put(ARRAY_SIZE(clks), clks); + return ret; +} + +/* Special syscon initialization about RX channel with slave mode on JH7110 SoC */ +static int jh7110_i2srx_crg_init(struct dw_i2s_dev *dev) +{ + struct regmap *regmap; + unsigned int args[2]; + + regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node, + "starfive,syscon", + 2, args); + if (IS_ERR(regmap)) + return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n"); + + /* Enable I2Srx with syscon register, args[0]: offset, args[1]: mask */ + regmap_update_bits(regmap, args[0], args[1], args[1]); + + return jh7110_i2s_crg_slave_init(dev); +} + +static int jh7110_i2stx0_clk_cfg(struct i2s_clk_config_data *config) +{ + struct dw_i2s_dev *dev = container_of(config, struct dw_i2s_dev, config); + u32 bclk_rate = config->sample_rate * 64; + + return clk_set_rate(dev->clk, bclk_rate); +} + static int dw_i2s_probe(struct platform_device *pdev) { const struct i2s_platform_data *pdata = of_device_get_match_data(&pdev->dev); @@ -712,15 +936,25 @@ static int dw_i2s_probe(struct platform_device *pdev) if (IS_ERR(dev->i2s_base)) return PTR_ERR(dev->i2s_base);
- dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev); - if (IS_ERR(dev->reset)) - return PTR_ERR(dev->reset); + dev->dev = &pdev->dev; + dev->is_jh7110 = false; + if (pdata) { + if (pdata->i2s_pd_init) { + ret = pdata->i2s_pd_init(dev); + if (ret) + return ret; + } + }
- ret = reset_control_deassert(dev->reset); - if (ret) - return ret; + if (!dev->is_jh7110) { + dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev); + if (IS_ERR(dev->reset)) + return PTR_ERR(dev->reset);
- dev->dev = &pdev->dev; + ret = reset_control_deassert(dev->reset); + if (ret) + return ret; + }
irq = platform_get_irq_optional(pdev, 0); if (irq >= 0) { @@ -779,7 +1013,7 @@ static int dw_i2s_probe(struct platform_device *pdev) goto err_clk_disable; }
- if (!pdata) { + if (!pdata || dev->is_jh7110) { if (irq >= 0) { ret = dw_pcm_register(pdev); dev->use_pio = true; @@ -821,8 +1055,36 @@ static void dw_i2s_remove(struct platform_device *pdev) }
#ifdef CONFIG_OF +static const struct i2s_platform_data jh7110_i2stx0_data = { + .cap = DWC_I2S_PLAY | DW_I2S_MASTER, + .channel = TWO_CHANNEL_SUPPORT, + .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, + .snd_rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000, + .i2s_clk_cfg = jh7110_i2stx0_clk_cfg, + .i2s_pd_init = jh7110_i2s_crg_master_init, +}; + +static const struct i2s_platform_data jh7110_i2stx1_data = { + .cap = DWC_I2S_PLAY | DW_I2S_SLAVE, + .channel = TWO_CHANNEL_SUPPORT, + .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, + .snd_rates = SNDRV_PCM_RATE_8000_192000, + .i2s_pd_init = jh7110_i2s_crg_slave_init, +}; + +static const struct i2s_platform_data jh7110_i2srx_data = { + .cap = DWC_I2S_RECORD | DW_I2S_SLAVE, + .channel = TWO_CHANNEL_SUPPORT, + .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, + .snd_rates = SNDRV_PCM_RATE_8000_192000, + .i2s_pd_init = jh7110_i2srx_crg_init, +}; + static const struct of_device_id dw_i2s_of_match[] = { { .compatible = "snps,designware-i2s", }, + { .compatible = "starfive,jh7110-i2stx0", .data = &jh7110_i2stx0_data, }, + { .compatible = "starfive,jh7110-i2stx1", .data = &jh7110_i2stx1_data,}, + { .compatible = "starfive,jh7110-i2srx", .data = &jh7110_i2srx_data,}, {}, };
diff --git a/sound/soc/dwc/local.h b/sound/soc/dwc/local.h index 4ce96bac2f39..dce88c9ad5f3 100644 --- a/sound/soc/dwc/local.h +++ b/sound/soc/dwc/local.h @@ -123,6 +123,7 @@ struct dw_i2s_dev { u32 fifo_th; u32 l_reg; u32 r_reg; + bool is_jh7110; /* Flag for StarFive JH7110 SoC */
/* data related to DMA transfers b/w i2s and DMAC */ union dw_i2s_snd_dma_data play_dma_data;
Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings of Designware I2S controller. The I2S controller needs two reset items to work properly on the JH7110 SoC. And TX0 channel as master mode needs 5 clock items and TX1/RX channels as slave mode need 9 clock items on the JH7110 SoC. The RX channel needs System Register Controller property to enable it and other platforms do not need it.
Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com --- .../bindings/sound/snps,designware-i2s.yaml | 108 +++++++++++++++++- 1 file changed, 105 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml index a970fd264b21..a48d040b0a4f 100644 --- a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml @@ -17,6 +17,9 @@ properties: - const: snps,designware-i2s - enum: - snps,designware-i2s + - starfive,jh7110-i2stx0 + - starfive,jh7110-i2stx1 + - starfive,jh7110-i2srx
reg: maxItems: 1 @@ -29,15 +32,36 @@ properties: maxItems: 1
clocks: - description: Sampling rate reference clock - maxItems: 1 + items: + - description: Sampling rate reference clock + - description: APB clock + - description: Audio master clock + - description: Inner audio master clock source + - description: External audio master clock source + - description: Bit clock + - description: Left/right channel clock + - description: External bit clock + - description: External left/right channel clock + minItems: 1
clock-names: - const: i2sclk + items: + - const: i2sclk + - const: apb + - const: mclk + - const: mclk_inner + - const: mclk_ext + - const: bclk + - const: lrck + - const: bclk_ext + - const: lrck_ext + minItems: 1
resets: items: - description: Optional controller resets + - description: controller reset of Sampling rate + minItems: 1
dmas: items: @@ -51,6 +75,17 @@ properties: - const: rx minItems: 1
+ starfive,syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller sys_syscon node. + - description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register. + - description: I2S-rx enabled control mask + description: + The phandle to System Register Controller syscon node and the I2S-rx(ADC) + enabled control offset and mask of SYS_SYSCONSAIF__SYSCFG register. + allOf: - $ref: dai-common.yaml# - if: @@ -66,6 +101,73 @@ allOf: properties: "#sound-dai-cells": const: 0 + - if: + properties: + compatible: + contains: + const: snps,designware-i2s + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + resets: + maxItems: 1 + else: + properties: + resets: + minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + const: starfive,jh7110-i2stx0 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + minItems: 5 + maxItems: 5 + required: + - resets + - if: + properties: + compatible: + contains: + const: starfive,jh7110-i2stx1 + then: + properties: + clocks: + minItems: 9 + maxItems: 9 + clock-names: + minItems: 9 + maxItems: 9 + required: + - resets + - if: + properties: + compatible: + contains: + const: starfive,jh7110-i2srx + then: + properties: + clocks: + minItems: 9 + maxItems: 9 + clock-names: + minItems: 9 + maxItems: 9 + required: + - resets + - starfive,syscon + else: + properties: + starfive,syscon: false
required: - compatible
On 21/08/2023 16:41, Xingyu Wu wrote:
Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings of Designware I2S controller. The I2S controller needs two reset items to work properly on the JH7110 SoC. And TX0 channel as master mode needs 5 clock items and TX1/RX channels as slave mode need 9 clock items on the JH7110 SoC. The RX channel needs System Register Controller property to enable it and other platforms do not need it.
Signed-off-by: Xingyu Wu xingyu.wu@starfivetech.com
Reviewed-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Best regards, Krzysztof
On Mon, 21 Aug 2023 22:41:46 +0800, Xingyu Wu wrote:
This patch series adds I2S support for the StarFive JH7110 RISC-V SoC based on Designware I2S controller. There has three I2S channels (RX/TX0/TX1) on the JH7110 SoC, one of which is for record(RX) and two for playback(TX).
The first patch adds support for the StarFive JH7110 SoC in the Designware I2S bindings. The second patch adds the ops to get data from platform bus in the I2S driver. The third patch adds support for the StarFive JH7110 SoC in the Designware I2S driver. The fourth patch fixes the name of I2STX1 pinmux. The last patch adds device node of I2S RX/TX0/TX1 in JH7110 dts.
[...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/5] ASoC: dt-bindings: snps,designware-i2s: Add StarFive JH7110 SoC support commit: 206110c74c4af6772916acacae5f28993085bf18 [2/5] ASoC: dwc: Use ops to get platform data commit: d6d6c513f5d2d14651336fb4e30f097822b46f29 [3/5] ASoC: dwc: i2s: Add StarFive JH7110 SoC support commit: 52ea7c0543f8a39da8a6fc17a5ab36b7b58d5431
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From: Conor Dooley conor.dooley@microchip.com
On Mon, 21 Aug 2023 22:41:46 +0800, Xingyu Wu wrote:
This patch series adds I2S support for the StarFive JH7110 RISC-V SoC based on Designware I2S controller. There has three I2S channels (RX/TX0/TX1) on the JH7110 SoC, one of which is for record(RX) and two for playback(TX).
The first patch adds support for the StarFive JH7110 SoC in the Designware I2S bindings. The second patch adds the ops to get data from platform bus in the I2S driver. The third patch adds support for the StarFive JH7110 SoC in the Designware I2S driver. The fourth patch fixes the name of I2STX1 pinmux. The last patch adds device node of I2S RX/TX0/TX1 in JH7110 dts.
[...]
Applied to riscv-dt-for-next, thanks!
[4/5] riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1 https://git.kernel.org/conor/c/4e1abae5688a [5/5] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 https://git.kernel.org/conor/c/92cfc35838b2
Thanks, Conor.
participants (6)
-
Conor Dooley -
Krzysztof Kozlowski -
Mark Brown -
Rob Herring -
Walker Chen -
Xingyu Wu