[alsa-devel] [PATCH v2] ASoC: tlv320aic3x: add missing registers and bits
Second version of patch keeping formatting. Adds missing register default values to cache. Adds register and bits definitions in header file. Changes are for TLV320AIC310x based on data sheet.
Signed-off-by: Jiri Prchal jiri.prchal@aksignal.cz
--- /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c.orig +++ /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c.new @@ -122,7 +122,9 @@ 0x00, 0x00, 0x00, 0x00, /* 88 */ 0x00, 0x00, 0x00, 0x00, /* 92 */ 0x00, 0x00, 0x00, 0x00, /* 96 */ - 0x00, 0x00, 0x02, /* 100 */ + 0x00, 0x00, 0x02, 0x00, /* 100 */ + 0x00, 0x00, 0x00, 0x00, /* 104 */ + 0x00, 0x00, /* 108 */ };
--- /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.h +++ /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.h.new @@ -13,7 +13,7 @@ #define _AIC3X_H
/* AIC3X register space */ -#define AIC3X_CACHEREGNUM 103 +#define AIC3X_CACHEREGNUM 110
/* Page select register */ #define AIC3X_PAGE_SELECT 0 @@ -74,6 +74,8 @@ #define HPLCOM_CFG 37 /* Right High Power Output control registers */ #define HPRCOM_CFG 38 +/* High Power Output Stage Control Register */ +#define HPOUT_SC 40 /* DAC Output Switching control registers */ #define DAC_LINE_MUX 41 /* High Power Output Driver Pop Reduction registers */ @@ -148,6 +150,17 @@ #define AIC3X_GPIOB_REG 101 /* Clock generation control register */ #define AIC3X_CLKGEN_CTRL_REG 102 +/* New AGC registers */ +#define LAGCN_ATTACK 103 +#define LAGCN_DECAY 104 +#define RAGCN_ATTACK 105 +#define RAGCN_DECAY 106 +/* New Programmable ADC Digital Path and I2C Bus Condition Register */ +#define NEW_ADC_DIGITALPATH 107 +/* Passive Analog Signal Bypass Selection During Powerdown Register */ +#define PASSIVE_BYPASS 108 +/* DAC Quiescent Current Adjustment Register */ +#define DAC_ICC_ADJ 109
/* Page select register bits */ #define PAGE0_SELECT 0 @@ -163,6 +176,10 @@ #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) #define LDAC2LCH (0x1 << 3) #define RDAC2RCH (0x1 << 1) +#define LDAC2RCH (0x2 << 3) +#define RDAC2LCH (0x2 << 1) +#define LDAC2MONOMIX (0x3 << 3) +#define RDAC2MONOMIX (0x3 << 1)
/* PLL registers bitfields */ #define PLLP_SHIFT 0
On Wed, Jun 27, 2012 at 08:06:59AM +0200, Prchal Jiří wrote:
Second version of patch keeping formatting. Adds missing register default values to cache. Adds register and bits definitions in header file.
Changes are for TLV320AIC310x based on data sheet.
I tried to apply it but it doesn't apply, git am says:
error: home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c.new: does not exist in index
which is because:
--- /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c.orig +++ /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c.new
Please format the patch as covered in SubmittingPatches, it should be something that can be applied patch -p1. Also...
@@ -122,7 +122,9 @@ 0x00, 0x00, 0x00, 0x00, /* 88 */ 0x00, 0x00, 0x00, 0x00, /* 92 */ 0x00, 0x00, 0x00, 0x00, /* 96 */
- 0x00, 0x00, 0x02, /* 100 */
- 0x00, 0x00, 0x02, 0x00, /* 100 */
- 0x00, 0x00, 0x00, 0x00, /* 104 */
- 0x00, 0x00, /* 108 */
};
This is a lot clearer, your changelog (and the previous submission) suggested that there may be some errors in the register default values since you were talking about missing bits but really all you're doing is adding new registers which is a bit different to correcting mistakes.
The "missing bits" here are instead just:
@@ -74,6 +74,8 @@ #define HPLCOM_CFG 37 /* Right High Power Output control registers */ #define HPRCOM_CFG 38 +/* High Power Output Stage Control Register */ +#define HPOUT_SC 40 /* DAC Output Switching control registers */ #define DAC_LINE_MUX 41 /* High Power Output Driver Pop Reduction registers */
these new defines in the header.
Adds missing register default values to cache. Adds register and bit shift definitions in header file. Changes are for TLV320AIC310x based on data sheet.
v2: keep formatting of cache v3: fix wrong diff format (sorry for that, I start learning git)
Signed-off-by: Jiri Prchal jiri.prchal@aksignal.cz --- sound/soc/codecs/tlv320aic3x.c | 4 +++- sound/soc/codecs/tlv320aic3x.h | 19 ++++++++++++++++++- 2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index 64d2a4f..50a7112 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -118,7 +118,9 @@ static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 0x00, 0x00, 0x00, 0x00, /* 88 */ 0x00, 0x00, 0x00, 0x00, /* 92 */ 0x00, 0x00, 0x00, 0x00, /* 96 */ - 0x00, 0x00, 0x02, /* 100 */ + 0x00, 0x00, 0x02, 0x00, /* 100 */ + 0x00, 0x00, 0x00, 0x00, /* 104 */ + 0x00, 0x00, /* 108 */ };
#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h index 6f097fb..5da5eb3 100644 --- a/sound/soc/codecs/tlv320aic3x.h +++ b/sound/soc/codecs/tlv320aic3x.h @@ -13,7 +13,7 @@ #define _AIC3X_H
/* AIC3X register space */ -#define AIC3X_CACHEREGNUM 103 +#define AIC3X_CACHEREGNUM 110
/* Page select register */ #define AIC3X_PAGE_SELECT 0 @@ -74,6 +74,8 @@ #define HPLCOM_CFG 37 /* Right High Power Output control registers */ #define HPRCOM_CFG 38 +/* High Power Output Stage Control Register */ +#define HPOUT_SC 40 /* DAC Output Switching control registers */ #define DAC_LINE_MUX 41 /* High Power Output Driver Pop Reduction registers */ @@ -148,6 +150,17 @@ #define AIC3X_GPIOB_REG 101 /* Clock generation control register */ #define AIC3X_CLKGEN_CTRL_REG 102 +/* New AGC registers */ +#define LAGCN_ATTACK 103 +#define LAGCN_DECAY 104 +#define RAGCN_ATTACK 105 +#define RAGCN_DECAY 106 +/* New Programmable ADC Digital Path and I2C Bus Condition Register */ +#define NEW_ADC_DIGITALPATH 107 +/* Passive Analog Signal Bypass Selection During Powerdown Register */ +#define PASSIVE_BYPASS 108 +/* DAC Quiescent Current Adjustment Register */ +#define DAC_ICC_ADJ 109
/* Page select register bits */ #define PAGE0_SELECT 0 @@ -163,6 +176,10 @@ #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) #define LDAC2LCH (0x1 << 3) #define RDAC2RCH (0x1 << 1) +#define LDAC2RCH (0x2 << 3) +#define RDAC2LCH (0x2 << 1) +#define LDAC2MONOMIX (0x3 << 3) +#define RDAC2MONOMIX (0x3 << 1)
/* PLL registers bitfields */ #define PLLP_SHIFT 0
On Wed, Jun 27, 2012 at 03:01:29PM +0200, Prchal Jiří wrote:
Adds missing register default values to cache. Adds register and bit shift definitions in header file. Changes are for TLV320AIC310x based on data sheet.
This doesn't apply against current ASoC, please regenerate it against my current tree.
v2: keep formatting of cache v3: fix wrong diff format (sorry for that, I start learning git)
Don't put noise like this in the changelog, if you want to include it put it after the --- like SubmittingPatches says.
Adds missing register default values to cache. Adds register and bit shift definitions in header file. Changes are for TLV320AIC310x based on data sheet.
Signed-off-by: Jiri Prchal jiri.prchal@aksignal.cz --- sound/soc/codecs/tlv320aic3x.c | 4 +++- sound/soc/codecs/tlv320aic3x.h | 19 ++++++++++++++++++- 2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index 7a49390..bd03f4d 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -119,7 +119,9 @@ static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 0x00, 0x00, 0x00, 0x00, /* 88 */ 0x00, 0x00, 0x00, 0x00, /* 92 */ 0x00, 0x00, 0x00, 0x00, /* 96 */ - 0x00, 0x00, 0x02, /* 100 */ + 0x00, 0x00, 0x02, 0x00, /* 100 */ + 0x00, 0x00, 0x00, 0x00, /* 104 */ + 0x00, 0x00, /* 108 */ };
/* diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h index 06a1978..586c5d5 100644 --- a/sound/soc/codecs/tlv320aic3x.h +++ b/sound/soc/codecs/tlv320aic3x.h @@ -13,7 +13,7 @@ #define _AIC3X_H
/* AIC3X register space */ -#define AIC3X_CACHEREGNUM 103 +#define AIC3X_CACHEREGNUM 110
/* Page select register */ #define AIC3X_PAGE_SELECT 0 @@ -74,6 +74,8 @@ #define HPLCOM_CFG 37 /* Right High Power Output control registers */ #define HPRCOM_CFG 38 +/* High Power Output Stage Control Register */ +#define HPOUT_SC 40 /* DAC Output Switching control registers */ #define DAC_LINE_MUX 41 /* High Power Output Driver Pop Reduction registers */ @@ -148,6 +150,17 @@ #define AIC3X_GPIOB_REG 101 /* Clock generation control register */ #define AIC3X_CLKGEN_CTRL_REG 102 +/* New AGC registers */ +#define LAGCN_ATTACK 103 +#define LAGCN_DECAY 104 +#define RAGCN_ATTACK 105 +#define RAGCN_DECAY 106 +/* New Programmable ADC Digital Path and I2C Bus Condition Register */ +#define NEW_ADC_DIGITALPATH 107 +/* Passive Analog Signal Bypass Selection During Powerdown Register */ +#define PASSIVE_BYPASS 108 +/* DAC Quiescent Current Adjustment Register */ +#define DAC_ICC_ADJ 109
/* Page select register bits */ #define PAGE0_SELECT 0 @@ -163,6 +176,10 @@ #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) #define LDAC2LCH (0x1 << 3) #define RDAC2RCH (0x1 << 1) +#define LDAC2RCH (0x2 << 3) +#define RDAC2LCH (0x2 << 1) +#define LDAC2MONOMIX (0x3 << 3) +#define RDAC2MONOMIX (0x3 << 1)
/* PLL registers bitfields */ #define PLLP_SHIFT 0
On Tue, Jul 03, 2012 at 11:41:43AM +0200, Prchal Jiří wrote:
Adds missing register default values to cache. Adds register and bit shift definitions in header file. Changes are for TLV320AIC310x based on data sheet.
This still doesn't apply, please regnerate against current ASoC and check that your mail client isn't mangling the patch when you send it.
It should also be being split into two, one to add the new register defines and one for extending the cache.
participants (2)
-
Mark Brown -
Prchal Jiří