Hi,

This is a follow-up to a previous series that was printing a warning when a mux has a set_parent implementation but is missing determine_rate().

The rationale is that set_parent() is very likely to be useful when changing the rate, but it's determine_rate() that takes the parenting decision. If we're missing it, then the current parent is always going to be used, and thus set_parent() will not be used. The only exception being a direct call to clk_set_parent(), but those are fairly rare compared to clk_set_rate().

Stephen then asked to promote the warning to an error, and to fix up all the muxes that are in that situation first. So here it is :)

It was build-tested on x86, arm and arm64.

Affected drivers have been tracked down by the following coccinelle script:

virtual report

@ clk_ops @ identifier ops; position p; @@

struct clk_ops ops@p = { ... };

@ has_set_parent @ identifier clk_ops.ops; identifier set_parent_f; @@

struct clk_ops ops = { .set_parent = set_parent_f, };

@ has_determine_rate @ identifier clk_ops.ops; identifier determine_rate_f; @@

struct clk_ops ops = { .determine_rate = determine_rate_f, };

@ script:python depends on report && has_set_parent && !has_determine_rate @ ops << clk_ops.ops; set_parent_f << has_set_parent.set_parent_f; p << clk_ops.p; @@

coccilib.report.print_report(p[0], "ERROR: %s has set_parent (%s)" % (ops, set_parent_f))

Berlin is the only user still matching after this series has been applied, but it's because it uses a composite clock which throws the script off. The driver has been converted and shouldn't be a problem.

Let me know what you think, Maxime

Signed-off-by: Maxime Ripard maxime@cerno.tech --- Changes in v3: - Rebased on top of next-20230404 - Link to v2: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v2-0-f6736dec138e@...

Changes in v2: - Drop all the patches already applied - Promote the clk registration warning to an error - Make all muxes use determine_rate - Link to v1: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v1-0-f3ef80518140@...

--- Maxime Ripard (65): clk: Export clk_hw_forward_rate_request() clk: lan966x: Remove unused round_rate hook clk: nodrv: Add a determine_rate hook clk: test: Add a determine_rate hook clk: actions: composite: Add a determine_rate hook for pass clk clk: at91: main: Add a determine_rate hook clk: at91: sckc: Add a determine_rate hook clk: berlin: div: Add a determine_rate hook clk: cdce706: Add a determine_rate hook clk: k210: pll: Add a determine_rate hook clk: k210: aclk: Add a determine_rate hook clk: k210: mux: Add a determine_rate hook clk: lmk04832: clkout: Add a determine_rate hook clk: lochnagar: Add a determine_rate hook clk: qoriq: Add a determine_rate hook clk: si5341: Add a determine_rate hook clk: stm32f4: mux: Add a determine_rate hook clk: vc5: mux: Add a determine_rate hook clk: vc5: clkout: Add a determine_rate hook clk: wm831x: clkout: Add a determine_rate hook clk: davinci: da8xx-cfgchip: Add a determine_rate hook clk: davinci: da8xx-cfgchip: Add a determine_rate hook clk: imx: busy: Add a determine_rate hook clk: imx: fixup-mux: Add a determine_rate hook clk: imx: scu: Add a determine_rate hook clk: mediatek: cpumux: Add a determine_rate hook clk: pxa: Add a determine_rate hook clk: renesas: r9a06g032: Add a determine_rate hook clk: socfpga: gate: Add a determine_rate hook clk: stm32: core: Add a determine_rate hook clk: tegra: bpmp: Add a determine_rate hook clk: tegra: super: Add a determine_rate hook clk: tegra: periph: Add a determine_rate hook clk: ux500: prcmu: Add a determine_rate hook clk: ux500: sysctrl: Add a determine_rate hook clk: versatile: sp810: Add a determine_rate hook drm/tegra: sor: Add a determine_rate hook phy: cadence: sierra: Add a determine_rate hook phy: cadence: torrent: Add a determine_rate hook phy: ti: am654-serdes: Add a determine_rate hook phy: ti: j721e-wiz: Add a determine_rate hook rtc: sun6i: Add a determine_rate hook ASoC: tlv320aic32x4: Add a determine_rate hook clk: actions: composite: div: Switch to determine_rate clk: actions: composite: fact: Switch to determine_rate clk: at91: smd: Switch to determine_rate clk: axi-clkgen: Switch to determine_rate clk: cdce706: divider: Switch to determine_rate clk: cdce706: clkout: Switch to determine_rate clk: si5341: Switch to determine_rate clk: si5351: pll: Switch to determine_rate clk: si5351: msynth: Switch to determine_rate clk: si5351: clkout: Switch to determine_rate clk: da8xx: clk48: Switch to determine_rate clk: imx: scu: Switch to determine_rate clk: ingenic: cgu: Switch to determine_rate clk: ingenic: tcu: Switch to determine_rate clk: sprd: composite: Switch to determine_rate clk: st: flexgen: Switch to determine_rate clk: stm32: composite: Switch to determine_rate clk: tegra: periph: Switch to determine_rate clk: tegra: super: Switch to determine_rate ASoC: tlv320aic32x4: pll: Switch to determine_rate ASoC: tlv320aic32x4: div: Switch to determine_rate clk: Forbid to register a mux without determine_rate

drivers/clk/actions/owl-composite.c | 35 +++++++++++----- drivers/clk/actions/owl-composite.h | 2 +- drivers/clk/at91/clk-main.c | 3 +- drivers/clk/at91/clk-smd.c | 29 +++++++------ drivers/clk/at91/sckc.c | 3 +- drivers/clk/berlin/berlin2-div.c | 3 +- drivers/clk/clk-axi-clkgen.c | 14 ++++--- drivers/clk/clk-cdce706.c | 31 ++++++++------ drivers/clk/clk-k210.c | 17 +++++--- drivers/clk/clk-lan966x.c | 17 -------- drivers/clk/clk-lmk04832.c | 1 + drivers/clk/clk-lochnagar.c | 2 + drivers/clk/clk-qoriq.c | 10 +++-- drivers/clk/clk-si5341.c | 21 +++++----- drivers/clk/clk-si5351.c | 67 +++++++++++++++++-------------- drivers/clk/clk-stm32f4.c | 3 +- drivers/clk/clk-versaclock5.c | 8 ++-- drivers/clk/clk-wm831x.c | 3 +- drivers/clk/clk.c | 15 +++++++ drivers/clk/clk_test.c | 1 + drivers/clk/davinci/da8xx-cfgchip.c | 15 ++++--- drivers/clk/imx/clk-busy.c | 3 +- drivers/clk/imx/clk-fixup-mux.c | 3 +- drivers/clk/imx/clk-scu.c | 27 +++++++++++-- drivers/clk/ingenic/cgu.c | 15 +++---- drivers/clk/ingenic/tcu.c | 19 +++++---- drivers/clk/mediatek/clk-cpumux.c | 3 +- drivers/clk/pxa/clk-pxa.c | 3 +- drivers/clk/renesas/r9a06g032-clocks.c | 3 +- drivers/clk/socfpga/clk-gate.c | 3 +- drivers/clk/sprd/composite.c | 16 +++++--- drivers/clk/st/clk-flexgen.c | 15 +++---- drivers/clk/stm32/clk-stm32-core.c | 33 ++++++++++----- drivers/clk/tegra/clk-bpmp.c | 7 +++- drivers/clk/tegra/clk-periph.c | 19 ++++++--- drivers/clk/tegra/clk-super.c | 18 ++++++--- drivers/clk/ux500/clk-prcmu.c | 3 +- drivers/clk/ux500/clk-sysctrl.c | 4 +- drivers/clk/versatile/clk-sp810.c | 3 +- drivers/gpu/drm/tegra/sor.c | 3 +- drivers/phy/cadence/phy-cadence-sierra.c | 1 + drivers/phy/cadence/phy-cadence-torrent.c | 1 + drivers/phy/ti/phy-am654-serdes.c | 1 + drivers/phy/ti/phy-j721e-wiz.c | 1 + drivers/rtc/rtc-sun6i.c | 2 + sound/soc/codecs/tlv320aic32x4-clk.c | 37 ++++++++++------- 46 files changed, 343 insertions(+), 200 deletions(-) --- base-commit: 6a53bda3aaf3de5edeea27d0b1d8781d067640b6 change-id: 20221018-clk-range-checks-fixes-2039f3523240

Best regards,