The sun8i codec is effectively an on-die variant of the X-Powers AC100 codec. The AC100 can derive its clocks from either of two I2S master clocks or an internal PLL. For the on-die variant, Allwinner replaced the codec's own PLL with a connection to SoC's existing PLL_AUDIO, and they connected both I2S MCLK inputs to the same source -- which happens to be an integer divider from the same PLL_AUDIO.

So there's actually no clocking flexibility. To run SYSCLK at the required rate, it must be run straight from the PLL. The only choice is whether it goes through AIF1CLK or AIF2CLK. Since both run at the same rate, the only effect of that choice is which field in SYS_SR_CTRL (AIF1_FS or AIF2_FS) controls the system sample rate.

Since AIFnCLK is required to bring up the corresponding DAI, and AIF1 (connected to the CPU) is used most often, let's use AIF1CLK as the SYSCLK parent. That means we no longer need to set AIF2_FS.

Since this clock tree never changes, we can program it from the component probe function, instead of using DAPM widgets. The DAPM widgets unnecessarily change clock parents when the codec goes in/out of idle and the supply widgets are powered up/down.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 54 +++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 19 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 178f6fb31fd4..407f0fedc4ed 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -19,20 +19,23 @@ #include <linux/log2.h>

#include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/soc-dapm.h>

#define SUN8I_SYSCLK_CTL 0x00c #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 -#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL 9 -#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC 8 +#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL (0x2 << 8) +#define SUN8I_SYSCLK_CTL_AIF2CLK_ENA 7 +#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL (0x2 << 4) #define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0 +#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK (0x0 << 0) +#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF2CLK (0x1 << 0) #define SUN8I_MOD_CLK_ENA 0x010 #define SUN8I_MOD_CLK_ENA_AIF1 15 #define SUN8I_MOD_CLK_ENA_ADC 3 #define SUN8I_MOD_CLK_ENA_DAC 2 #define SUN8I_MOD_RST_CTL 0x014 #define SUN8I_MOD_RST_CTL_AIF1 15 #define SUN8I_MOD_RST_CTL_ADC 3 #define SUN8I_MOD_RST_CTL_DAC 2 @@ -74,16 +77,18 @@ #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8

+#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) +#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4) #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)

struct sun8i_codec_quirks { @@ -318,19 +323,16 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,

sample_rate = sun8i_codec_get_hw_rate(params); if (sample_rate < 0) return sample_rate;

regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); - regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF2_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS);

return 0; }

static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, @@ -361,18 +363,26 @@ static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = { SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), };

static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { + /* System Clocks */ SND_SOC_DAPM_CLOCK_SUPPLY("mod"),

+ SND_SOC_DAPM_SUPPLY("AIF1CLK", + SUN8I_SYSCLK_CTL, + SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("SYSCLK", + SUN8I_SYSCLK_CTL, + SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), + /* Digital parts of the DACs and ADC */ SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0),

/* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, @@ -410,44 +420,33 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {

/* Clocks */ SND_SOC_DAPM_SUPPLY("MODCLK AIF1", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), - - SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0), - /* Inversion as 0=AIF1, 1=AIF2 */ - SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),

/* Module reset */ SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), };

static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { /* Clock Routes */ - { "AIF1", NULL, "mod" }, + { "AIF1CLK", NULL, "mod" },

- { "AIF1", NULL, "SYSCLK AIF1" }, - { "AIF1 PLL", NULL, "AIF1" }, - { "SYSCLK", NULL, "AIF1 PLL" }, + { "SYSCLK", NULL, "AIF1CLK" },

+ { "RST AIF1", NULL, "AIF1CLK" }, { "RST AIF1", NULL, "SYSCLK" }, { "MODCLK AIF1", NULL, "RST AIF1" }, { "AIF1 AD0L", NULL, "MODCLK AIF1" }, { "AIF1 AD0R", NULL, "MODCLK AIF1" }, { "AIF1 DA0L", NULL, "MODCLK AIF1" }, { "AIF1 DA0R", NULL, "MODCLK AIF1" },

{ "RST DAC", NULL, "SYSCLK" }, @@ -519,16 +518,33 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) return ret;

ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_legacy_routes, ARRAY_SIZE(sun8i_codec_legacy_routes)); if (ret) return ret; }

+ /* + * AIF1CLK and AIF2CLK share a pair of clock parents: PLL_AUDIO ("mod") + * and MCLK (from the CPU DAI connected to AIF1). MCLK's parent is also + * PLL_AUDIO, so using it adds no additional flexibility. Use PLL_AUDIO + * directly to simplify the clock tree. + */ + regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, + SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK | + SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK, + SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL | + SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL); + + /* Use AIF1CLK as the SYSCLK parent since AIF1 is used most often. */ + regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, + BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC), + SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK); + return 0; }

static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { .hw_params = sun8i_codec_hw_params, .set_fmt = sun8i_set_fmt, };

This matches the module power-up/down sequence from the vendor's driver.

While updating these widgets/routes, reorder them to match the register and bit layout of the hardware. This puts them in the same place in the widget and route arrays (previously they were at opposite ends), and it makes it easier to track which parts of which registers are implemented.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 72 +++++++++++++++++++---------------- 1 file changed, 39 insertions(+), 33 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 407f0fedc4ed..6887a2e897f4 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -373,16 +373,38 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {

SND_SOC_DAPM_SUPPLY("AIF1CLK", SUN8I_SYSCLK_CTL, SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL, SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),

+ /* Module Clocks */ + SND_SOC_DAPM_SUPPLY("CLK AIF1", + SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLK ADC", + SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLK DAC", + SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), + + /* Module Resets */ + SND_SOC_DAPM_SUPPLY("RST AIF1", + SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RST ADC", + SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RST DAC", + SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), + /* Digital parts of the DACs and ADC */ SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0),

/* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, @@ -412,60 +434,44 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0, sun8i_input_mixer_controls), SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0, sun8i_input_mixer_controls), - - /* Clocks */ - SND_SOC_DAPM_SUPPLY("MODCLK AIF1", SUN8I_MOD_CLK_ENA, - SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, - SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA, - SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), - - /* Module reset */ - SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL, - SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, - SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, - SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), };

static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { /* Clock Routes */ { "AIF1CLK", NULL, "mod" },

{ "SYSCLK", NULL, "AIF1CLK" },

- { "RST AIF1", NULL, "AIF1CLK" }, - { "RST AIF1", NULL, "SYSCLK" }, - { "MODCLK AIF1", NULL, "RST AIF1" }, - { "AIF1 AD0L", NULL, "MODCLK AIF1" }, - { "AIF1 AD0R", NULL, "MODCLK AIF1" }, - { "AIF1 DA0L", NULL, "MODCLK AIF1" }, - { "AIF1 DA0R", NULL, "MODCLK AIF1" }, - - { "RST DAC", NULL, "SYSCLK" }, - { "MODCLK DAC", NULL, "RST DAC" }, - { "DAC", NULL, "MODCLK DAC" }, - { "DACL", NULL, "DAC" }, - { "DACR", NULL, "DAC" }, - - { "RST ADC", NULL, "SYSCLK" }, - { "MODCLK ADC", NULL, "RST ADC" }, - { "ADC", NULL, "MODCLK ADC" }, + { "CLK AIF1", NULL, "AIF1CLK" }, + { "CLK AIF1", NULL, "SYSCLK" }, + { "RST AIF1", NULL, "CLK AIF1" }, + { "AIF1 AD0L", NULL, "RST AIF1" }, + { "AIF1 AD0R", NULL, "RST AIF1" }, + { "AIF1 DA0L", NULL, "RST AIF1" }, + { "AIF1 DA0R", NULL, "RST AIF1" }, + + { "CLK ADC", NULL, "SYSCLK" }, + { "RST ADC", NULL, "CLK ADC" }, + { "ADC", NULL, "RST ADC" }, { "ADCL", NULL, "ADC" }, { "ADCR", NULL, "ADC" },

+ { "CLK DAC", NULL, "SYSCLK" }, + { "RST DAC", NULL, "CLK DAC" }, + { "DAC", NULL, "RST DAC" }, + { "DACL", NULL, "DAC" }, + { "DACR", NULL, "DAC" }, + /* DAC Routes */ { "DACL", NULL, "Left Digital DAC Mixer" }, { "DACR", NULL, "Right Digital DAC Mixer" },

/* DAC Mixer Routes */ { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L" }, { "Left Digital DAC Mixer", "ADC Digital DAC Playback Switch", "ADCL" },

Sort the remaining pieces of the DAPM driver so that they are all in the same order among controls/widgets/routes, and so they roughly match the register word and bit order of the hardware. This nicely separates the AIF-related widgets from the ADC/DAC widgets, which allows the AIF widgets to stay in a logical order as more AIFs are added to the driver.

No widgets are renamed, to ease verification that this commit makes no functional change.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 101 ++++++++++++++++++---------------- 1 file changed, 53 insertions(+), 48 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 6887a2e897f4..d14243c434f9 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -327,16 +327,35 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,

regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);

return 0; }

+static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { + SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", + SUN8I_AIF1_MXR_SRC, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, + SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), + SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", + SUN8I_AIF1_MXR_SRC, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, + SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), + SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", + SUN8I_AIF1_MXR_SRC, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, + SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), + SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", + SUN8I_AIF1_MXR_SRC, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, + SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), +}; + static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, @@ -344,34 +363,16 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), };

-static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = { - SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", - SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, - SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), - SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, - SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), - SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", - SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, - SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), - SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", - SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, - SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), -}; - static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* System Clocks */ SND_SOC_DAPM_CLOCK_SUPPLY("mod"),

SND_SOC_DAPM_SUPPLY("AIF1CLK", SUN8I_SYSCLK_CTL, SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("SYSCLK", @@ -395,55 +396,59 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),

- /* Digital parts of the DACs and ADC */ - SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, - 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, - 0, NULL, 0), - - /* AIF "DAC" Inputs */ - SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, - SUN8I_AIF1_DACDAT_CTRL, - SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 0, - SUN8I_AIF1_DACDAT_CTRL, - SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), + /* Module Supplies */ + SND_SOC_DAPM_SUPPLY("ADC", + SUN8I_ADC_DIG_CTRL, + SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC", + SUN8I_DAC_DIG_CTRL, + SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0),

/* AIF "ADC" Outputs */ SND_SOC_DAPM_AIF_IN("AIF1 AD0L", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), SND_SOC_DAPM_AIF_IN("AIF1 AD0R", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),

+ /* AIF "ADC" Mixers */ + SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0, + sun8i_aif1_ad0_mixer_controls), + SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0, + sun8i_aif1_ad0_mixer_controls), + + /* AIF "DAC" Inputs */ + SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), + SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 0, + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), + /* ADC Inputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),

/* DAC Outputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),

- /* DAC and ADC Mixers */ + /* DAC Mixers */ SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), - SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0, - sun8i_input_mixer_controls), - SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0, - sun8i_input_mixer_controls), };

static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { /* Clock Routes */ { "AIF1CLK", NULL, "mod" },

{ "SYSCLK", NULL, "AIF1CLK" },

@@ -462,37 +467,37 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "ADCR", NULL, "ADC" },

{ "CLK DAC", NULL, "SYSCLK" }, { "RST DAC", NULL, "CLK DAC" }, { "DAC", NULL, "RST DAC" }, { "DACL", NULL, "DAC" }, { "DACR", NULL, "DAC" },

- /* DAC Routes */ + /* AIF "ADC" Output Routes */ + { "AIF1 AD0L", NULL, "Left Digital ADC Mixer" }, + { "AIF1 AD0R", NULL, "Right Digital ADC Mixer" }, + + /* AIF "ADC" Mixer Routes */ + { "Left Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L" }, + { "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" }, + + { "Right Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R" }, + { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" }, + + /* DAC Output Routes */ { "DACL", NULL, "Left Digital DAC Mixer" }, { "DACR", NULL, "Right Digital DAC Mixer" },

/* DAC Mixer Routes */ { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L" }, { "Left Digital DAC Mixer", "ADC Digital DAC Playback Switch", "ADCL" },

{ "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R" }, { "Right Digital DAC Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, - - /* ADC Routes */ - { "AIF1 AD0L", NULL, "Left Digital ADC Mixer" }, - { "AIF1 AD0R", NULL, "Right Digital ADC Mixer" }, - - /* ADC Mixer Routes */ - { "Left Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L" }, - { "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" }, - - { "Right Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R" }, - { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" }, };

static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = { /* Legacy ADC Inputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_ADC("AIF1 Slot 0 Left ADC", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("AIF1 Slot 0 Right ADC", NULL, SND_SOC_NOPM, 0, 0),

/* Legacy DAC Outputs (connected to analog codec DAPM context) */

This cleans up the mixer widget names. The AIF1 AD0 Mixer names were previously wrong -- they do not control the digital side of the ADC. The DAC mixer widgets were not wrong, but they were verbose and did not match the naming scheme of the other widgets.

The mixer controls are not renamed because they are exposed to userspace.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index d14243c434f9..30fe27648254 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -413,19 +413,19 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_AIF_IN("AIF1 AD0L", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), SND_SOC_DAPM_AIF_IN("AIF1 AD0R", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),

/* AIF "ADC" Mixers */ - SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0, + SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls), - SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0, + SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls),

/* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 0, SUN8I_AIF1_DACDAT_CTRL, @@ -435,19 +435,19 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),

/* DAC Outputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),

/* DAC Mixers */ - SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, + SOC_MIXER_ARRAY("DACL Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), - SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0, + SOC_MIXER_ARRAY("DACR Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), };

static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { /* Clock Routes */ { "AIF1CLK", NULL, "mod" },

{ "SYSCLK", NULL, "AIF1CLK" }, @@ -468,36 +468,36 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {

{ "CLK DAC", NULL, "SYSCLK" }, { "RST DAC", NULL, "CLK DAC" }, { "DAC", NULL, "RST DAC" }, { "DACL", NULL, "DAC" }, { "DACR", NULL, "DAC" },

/* AIF "ADC" Output Routes */ - { "AIF1 AD0L", NULL, "Left Digital ADC Mixer" }, - { "AIF1 AD0R", NULL, "Right Digital ADC Mixer" }, + { "AIF1 AD0L", NULL, "AIF1 AD0L Mixer" }, + { "AIF1 AD0R", NULL, "AIF1 AD0R Mixer" },

/* AIF "ADC" Mixer Routes */ - { "Left Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L" }, - { "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" }, + { "AIF1 AD0L Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L" }, + { "AIF1 AD0L Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" },

- { "Right Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R" }, - { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" }, + { "AIF1 AD0R Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R" }, + { "AIF1 AD0R Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" },

/* DAC Output Routes */ - { "DACL", NULL, "Left Digital DAC Mixer" }, - { "DACR", NULL, "Right Digital DAC Mixer" }, + { "DACL", NULL, "DACL Mixer" }, + { "DACR", NULL, "DACR Mixer" },

/* DAC Mixer Routes */ - { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L" }, - { "Left Digital DAC Mixer", "ADC Digital DAC Playback Switch", "ADCL" }, + { "DACL Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L" }, + { "DACL Mixer", "ADC Digital DAC Playback Switch", "ADCL" },

- { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R" }, - { "Right Digital DAC Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, + { "DACR Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R" }, + { "DACR Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, };

static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = { /* Legacy ADC Inputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_ADC("AIF1 Slot 0 Left ADC", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("AIF1 Slot 0 Right ADC", NULL, SND_SOC_NOPM, 0, 0),

/* Legacy DAC Outputs (connected to analog codec DAPM context) */

Whie the aif_in and aif_out widget types are handled exactly the same in the core DAPM code, a future widget event hook will need the correct widget type to derive the associated substream. Clean up the widget type for that reason, and so these widgets will match newly-added widgets for the other AIFs.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 30fe27648254..d0028883950c 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -405,22 +405,22 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0),

/* AIF "ADC" Outputs */ - SND_SOC_DAPM_AIF_IN("AIF1 AD0L", "Capture", 0, - SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 AD0R", "Capture", 0, - SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), + SND_SOC_DAPM_AIF_OUT("AIF1 AD0L", "Capture", 0, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), + SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "Capture", 0, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),

/* AIF "ADC" Mixers */ SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls), SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls),

/* AIF "DAC" Inputs */

Both the left and right side widgets referenced channel 0. This would unnecessarily power on the right side widget (and its associated path) when a mono stream was active.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index d0028883950c..2c89974243e1 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -408,31 +408,31 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0),

/* AIF "ADC" Outputs */ SND_SOC_DAPM_AIF_OUT("AIF1 AD0L", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), - SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "Capture", 0, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "Capture", 1, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),

/* AIF "ADC" Mixers */ SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls), SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls),

/* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 0, + SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 1, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),

/* ADC Inputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),

/* DAC Outputs (connected to analog codec DAPM context) */

Each left/right pair of AIF input/output channels can be swapped or combined. This is useful for sending a mono audio source to both sides of a stereo sink, or for creating complex mixing scenarios.

Add the support to control this feature from userspace.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 82 ++++++++++++++++++++++++++++++++--- 1 file changed, 76 insertions(+), 6 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 2c89974243e1..578c0c0e6330 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -49,19 +49,23 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8 #define SUN8I_AIF1_DACDAT_CTRL 0x048 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 +#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10 +#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8 #define SUN8I_AIF1_MXR_SRC 0x04c #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL 13 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR 12 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 @@ -327,16 +331,30 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,

regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);

return 0; }

+static const char *const sun8i_aif_stereo_mux_enum_values[] = { + "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" +}; + +static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC, + sun8i_aif_stereo_mux_enum_values); + +static const struct snd_kcontrol_new sun8i_aif1_ad0_stereo_mux_control = + SOC_DAPM_ENUM("AIF1 AD0 Stereo Capture Route", + sun8i_aif1_ad0_stereo_mux_enum); + static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, @@ -346,16 +364,26 @@ static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), };

+static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_da0_stereo_mux_enum, + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC, + sun8i_aif_stereo_mux_enum_values); + +static const struct snd_kcontrol_new sun8i_aif1_da0_stereo_mux_control = + SOC_DAPM_ENUM("AIF1 DA0 Stereo Playback Route", + sun8i_aif1_da0_stereo_mux_enum); + static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, @@ -412,22 +440,34 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* AIF "ADC" Outputs */ SND_SOC_DAPM_AIF_OUT("AIF1 AD0L", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "Capture", 1, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),

+ /* AIF "ADC" Mono/Stereo Muxes */ + SND_SOC_DAPM_MUX("AIF1 AD0L Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_ad0_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF1 AD0R Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_ad0_stereo_mux_control), + /* AIF "ADC" Mixers */ SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls), SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls),

+ /* AIF "DAC" Mono/Stereo Muxes */ + SND_SOC_DAPM_MUX("AIF1 DA0L Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_da0_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF1 DA0R Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_da0_stereo_mux_control), + /* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 1, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),

@@ -468,35 +508,65 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {

{ "CLK DAC", NULL, "SYSCLK" }, { "RST DAC", NULL, "CLK DAC" }, { "DAC", NULL, "RST DAC" }, { "DACL", NULL, "DAC" }, { "DACR", NULL, "DAC" },

/* AIF "ADC" Output Routes */ - { "AIF1 AD0L", NULL, "AIF1 AD0L Mixer" }, - { "AIF1 AD0R", NULL, "AIF1 AD0R Mixer" }, + { "AIF1 AD0L", NULL, "AIF1 AD0L Stereo Mux" }, + { "AIF1 AD0R", NULL, "AIF1 AD0R Stereo Mux" }, + + /* AIF "ADC" Mono/Stereo Mux Routes */ + { "AIF1 AD0L Stereo Mux", "Stereo", "AIF1 AD0L Mixer" }, + { "AIF1 AD0L Stereo Mux", "Reverse Stereo", "AIF1 AD0R Mixer" }, + { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, + { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, + { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, + { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" }, + + { "AIF1 AD0R Stereo Mux", "Stereo", "AIF1 AD0R Mixer" }, + { "AIF1 AD0R Stereo Mux", "Reverse Stereo", "AIF1 AD0L Mixer" }, + { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, + { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, + { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, + { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" },

/* AIF "ADC" Mixer Routes */ - { "AIF1 AD0L Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L" }, + { "AIF1 AD0L Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L Stereo Mux" }, { "AIF1 AD0L Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" },

- { "AIF1 AD0R Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R" }, + { "AIF1 AD0R Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R Stereo Mux" }, { "AIF1 AD0R Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" },

+ /* AIF "DAC" Mono/Stereo Mux Routes */ + { "AIF1 DA0L Stereo Mux", "Stereo", "AIF1 DA0L" }, + { "AIF1 DA0L Stereo Mux", "Reverse Stereo", "AIF1 DA0R" }, + { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0L" }, + { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0R" }, + { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0L" }, + { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0R" }, + + { "AIF1 DA0R Stereo Mux", "Stereo", "AIF1 DA0R" }, + { "AIF1 DA0R Stereo Mux", "Reverse Stereo", "AIF1 DA0L" }, + { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0L" }, + { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0R" }, + { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0L" }, + { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0R" }, + /* DAC Output Routes */ { "DACL", NULL, "DACL Mixer" }, { "DACR", NULL, "DACR Mixer" },

/* DAC Mixer Routes */ - { "DACL Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L" }, + { "DACL Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L Stereo Mux" }, { "DACL Mixer", "ADC Digital DAC Playback Switch", "ADCL" },

- { "DACR Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R" }, + { "DACR Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R Stereo Mux" }, { "DACR Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, };

static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = { /* Legacy ADC Inputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_ADC("AIF1 Slot 0 Left ADC", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("AIF1 Slot 0 Right ADC", NULL, SND_SOC_NOPM, 0, 0),

Remove a level of indirection by getting the device directly from the passed-in struct snd_soc_dai, instead of going through its component.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 578c0c0e6330..7590c4b04d14 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -162,17 +162,17 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) return 0xa; default: return -EINVAL; } }

static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { - struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); u32 value;

/* clock masters */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ value = 0x1; break; case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */ @@ -294,17 +294,17 @@ static int sun8i_codec_get_lrck_div(unsigned int channels,

return ilog2(div) - 4; }

static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { - struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); int sample_rate, lrck_div; u8 bclk_div;

/* * The CPU DAI handles only a sample of 16 bits. Configure the * codec to handle this type of sample resolution. */ regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,

In preparation for adding additional DAIs to this component, convert the DAI driver definition to an array. Since this changes all of the lines in the definition anyway, let's move it closer to the ops function definitions, instead of on the far side of the DAPM arrays. And while moving the DAI driver ops, rename the set_fmt hook to match the usual naming scheme.

Give the existing DAI an explicit ID and more meaningful stream names, so it will remain unique as more DAIs are added. The AIF widget streams must be updated to match.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 76 +++++++++++++++++++---------------- 1 file changed, 42 insertions(+), 34 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 7590c4b04d14..346f699c2e86 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -90,16 +90,21 @@ #define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4) #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)

+enum { + AIF1, + NAIFS +}; + struct sun8i_codec_quirks { bool legacy_widgets : 1; bool lrck_inversion : 1; };

struct sun8i_codec { struct regmap *regmap; struct clk *clk_module; @@ -160,17 +165,17 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) return 0x9; case 192000: return 0xa; default: return -EINVAL; } }

-static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); u32 value;

/* clock masters */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ value = 0x1; @@ -331,16 +336,46 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,

regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);

return 0; }

+static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { + .set_fmt = sun8i_codec_set_fmt, + .hw_params = sun8i_codec_hw_params, +}; + +static struct snd_soc_dai_driver sun8i_codec_dais[] = { + { + .name = "sun8i-codec-aif1", + .id = AIF1, + .ops = &sun8i_codec_dai_ops, + /* capture capabilities */ + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .sig_bits = 24, + }, + /* playback capabilities */ + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + }, +}; + static const char *const sun8i_aif_stereo_mux_enum_values[] = { "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" };

static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC, @@ -433,20 +468,20 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0),

/* AIF "ADC" Outputs */ - SND_SOC_DAPM_AIF_OUT("AIF1 AD0L", "Capture", 0, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0L", "AIF1 Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), - SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "Capture", 1, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "AIF1 Capture", 1, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),

/* AIF "ADC" Mono/Stereo Muxes */ SND_SOC_DAPM_MUX("AIF1 AD0L Stereo Mux", SND_SOC_NOPM, 0, 0, &sun8i_aif1_ad0_stereo_mux_control), SND_SOC_DAPM_MUX("AIF1 AD0R Stereo Mux", SND_SOC_NOPM, 0, 0, &sun8i_aif1_ad0_stereo_mux_control), @@ -459,20 +494,20 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {

/* AIF "DAC" Mono/Stereo Muxes */ SND_SOC_DAPM_MUX("AIF1 DA0L Stereo Mux", SND_SOC_NOPM, 0, 0, &sun8i_aif1_da0_stereo_mux_control), SND_SOC_DAPM_MUX("AIF1 DA0R Stereo Mux", SND_SOC_NOPM, 0, 0, &sun8i_aif1_da0_stereo_mux_control),

/* AIF "DAC" Inputs */ - SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, + SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 1, + SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "AIF1 Playback", 1, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),

/* ADC Inputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),

/* DAC Outputs (connected to analog codec DAPM context) */ @@ -619,44 +654,16 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) /* Use AIF1CLK as the SYSCLK parent since AIF1 is used most often. */ regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC), SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK);

return 0; }

-static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { - .hw_params = sun8i_codec_hw_params, - .set_fmt = sun8i_set_fmt, -}; - -static struct snd_soc_dai_driver sun8i_codec_dai = { - .name = "sun8i", - /* playback capabilities */ - .playback = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - /* capture capabilities */ - .capture = { - .stream_name = "Capture", - .channels_min = 1, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - .sig_bits = 24, - }, - /* pcm operations */ - .ops = &sun8i_codec_dai_ops, -}; - static const struct snd_soc_component_driver sun8i_soc_component = { .dapm_widgets = sun8i_codec_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), .dapm_routes = sun8i_codec_dapm_routes, .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes), .probe = sun8i_codec_component_probe, .idle_bias_on = 1, .use_pmdown_time = 1, @@ -709,17 +716,18 @@ static int sun8i_codec_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); if (!pm_runtime_enabled(&pdev->dev)) { ret = sun8i_codec_runtime_resume(&pdev->dev); if (ret) goto err_pm_disable; }

ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component, - &sun8i_codec_dai, 1); + sun8i_codec_dais, + ARRAY_SIZE(sun8i_codec_dais)); if (ret) { dev_err(&pdev->dev, "Failed to register codec\n"); goto err_suspend; }

return ret;

err_suspend:

The LRCK inversion bit has a different meaning in DSP mode: it selects between DSP A and DSP B formats. To support this, we need to know if the selected format is a DSP format. One easy way to do this is to set the format field before the inversion fields.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 46 +++++++++++++++++------------------ 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 346f699c2e86..0b713b2a2028 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -168,33 +168,55 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) default: return -EINVAL; } }

static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); - u32 value; + u32 format, value;

/* clock masters */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ value = 0x1; break; case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */ value = 0x0; break; default: return -EINVAL; } regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD), value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);

+ /* DAI format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + format = 0x0; + break; + case SND_SOC_DAIFMT_LEFT_J: + format = 0x1; + break; + case SND_SOC_DAIFMT_RIGHT_J: + format = 0x2; + break; + case SND_SOC_DAIFMT_DSP_A: + case SND_SOC_DAIFMT_DSP_B: + format = 0x3; + break; + default: + return -EINVAL; + } + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, + SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, + format << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT); + /* clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_NB_NF: /* Normal */ value = 0x0; break; case SND_SOC_DAIFMT_IB_IF: /* Inversion */ value = 0x1; break; @@ -215,38 +237,16 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) * that the codec probably gets it backward, and we have to * invert the value here. */ value ^= scodec->quirks->lrck_inversion; regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV), value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);

- /* DAI format */ - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_I2S: - value = 0x0; - break; - case SND_SOC_DAIFMT_LEFT_J: - value = 0x1; - break; - case SND_SOC_DAIFMT_RIGHT_J: - value = 0x2; - break; - case SND_SOC_DAIFMT_DSP_A: - case SND_SOC_DAIFMT_DSP_B: - value = 0x3; - break; - default: - return -EINVAL; - } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT); - return 0; }

struct sun8i_codec_clk_div { u8 div; u8 val; };

When using the I2S, LEFT_J, or RIGHT_J format, the hardware supports independent BCLK and LRCK inversion control. When using DSP_A or DSP_B, LRCK inversion is not supported. The register bit is repurposed to select between DSP_A and DSP_B. Extend the driver to support this.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 57 +++++++++++++++++++++++------------ 1 file changed, 37 insertions(+), 20 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 0b713b2a2028..506420fb355c 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -39,18 +39,17 @@ #define SUN8I_MOD_RST_CTL_AIF1 15 #define SUN8I_MOD_RST_CTL_ADC 3 #define SUN8I_MOD_RST_CTL_DAC 2 #define SUN8I_SYS_SR_CTRL 0x018 #define SUN8I_SYS_SR_CTRL_AIF1_FS 12 #define SUN8I_SYS_SR_CTRL_AIF2_FS 8 #define SUN8I_AIF1CLK_CTRL 0x040 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14 -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13 +#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 @@ -85,16 +84,17 @@ #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8

#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) #define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4) #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) +#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)

enum { AIF1, NAIFS @@ -168,17 +168,17 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) default: return -EINVAL; } }

static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); - u32 format, value; + u32 format, invert, value;

/* clock masters */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ value = 0x1; break; case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */ value = 0x0; @@ -197,55 +197,72 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) break; case SND_SOC_DAIFMT_LEFT_J: format = 0x1; break; case SND_SOC_DAIFMT_RIGHT_J: format = 0x2; break; case SND_SOC_DAIFMT_DSP_A: + format = 0x3; + invert = 0x0; /* Set LRCK_INV to 0 */ + break; case SND_SOC_DAIFMT_DSP_B: format = 0x3; + invert = 0x1; /* Set LRCK_INV to 1 */ break; default: return -EINVAL; } regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, format << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);

/* clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_NB_NF: /* Normal */ value = 0x0; break; - case SND_SOC_DAIFMT_IB_IF: /* Inversion */ + case SND_SOC_DAIFMT_NB_IF: /* Inverted LRCK */ value = 0x1; break; + case SND_SOC_DAIFMT_IB_NF: /* Inverted BCLK */ + value = 0x2; + break; + case SND_SOC_DAIFMT_IB_IF: /* Both inverted */ + value = 0x3; + break; default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV), - value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);

- /* - * It appears that the DAI and the codec in the A33 SoC don't - * share the same polarity for the LRCK signal when they mean - * 'normal' and 'inverted' in the datasheet. - * - * Since the DAI here is our regular i2s driver that have been - * tested with way more codecs than just this one, it means - * that the codec probably gets it backward, and we have to - * invert the value here. - */ - value ^= scodec->quirks->lrck_inversion; + if (format == 0x3) { + /* Inverted LRCK is not available in DSP mode. */ + if (value & BIT(0)) + return -EINVAL; + + /* Instead, the bit selects between DSP A/B formats. */ + value |= invert; + } else { + /* + * It appears that the DAI and the codec in the A33 SoC don't + * share the same polarity for the LRCK signal when they mean + * 'normal' and 'inverted' in the datasheet. + * + * Since the DAI here is our regular i2s driver that have been + * tested with way more codecs than just this one, it means + * that the codec probably gets it backward, and we have to + * invert the value here. + */ + value ^= scodec->quirks->lrck_inversion; + } + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV), - value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV); + SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK, + value << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV);

return 0; }

struct sun8i_codec_clk_div { u8 div; u8 val; };

The hardware supports 8 to 24-bit word sizes on all three of its DAIs, only one of which is connected to the CPU DAI. Program the word size based on the actual selected format, instead of relying on limitations in another driver (which, incedentally, has patches pending to remove that limitation).

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 506420fb355c..e7f01a4b4001 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -43,17 +43,16 @@ #define SUN8I_SYS_SR_CTRL_AIF1_FS 12 #define SUN8I_SYS_SR_CTRL_AIF2_FS 8 #define SUN8I_AIF1CLK_CTRL 0x040 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 #define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8 #define SUN8I_AIF1_DACDAT_CTRL 0x048 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 @@ -317,26 +316,40 @@ static int sun8i_codec_get_lrck_div(unsigned int channels, return ilog2(div) - 4; }

static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); - int sample_rate, lrck_div; + int lrck_div, sample_rate, word_size; u8 bclk_div;

- /* - * The CPU DAI handles only a sample of 16 bits. Configure the - * codec to handle this type of sample resolution. - */ + /* word size */ + switch (params_width(params)) { + case 8: + word_size = 0x0; + break; + case 16: + word_size = 0x1; + break; + case 20: + word_size = 0x2; + break; + case 24: + word_size = 0x3; + break; + default: + return -EINVAL; + } + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, - SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16); + word_size << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ);

bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16); regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);

lrck_div = sun8i_codec_get_lrck_div(params_channels(params), params_physical_width(params));

The codec supports only power-of-two BCLK/LRCK divisors. If either the slot width or the number of slots is not a power of two, the LRCK divisor must be rounded up to provide enough space. To do that, use order_base_2 (instead of ilog2, which rounds down).

Since the rounded divisor is also needed for setting the SYSCLK/BCLK divisor, return the order base 2 instead of fully calculating the hardware register encoding.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index e7f01a4b4001..779853d023fe 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -300,33 +300,35 @@ static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec, best_diff = diff; best_val = bdiv->val; } }

return best_val; }

-static int sun8i_codec_get_lrck_div(unsigned int channels, - unsigned int word_size) +static int sun8i_codec_get_lrck_div_order(unsigned int slots, + unsigned int slot_width) { - unsigned int div = word_size * channels; + unsigned int div = slots * slot_width;

if (div < 16 || div > 256) return -EINVAL;

- return ilog2(div) - 4; + return order_base_2(div); }

static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); - int lrck_div, sample_rate, word_size; + unsigned int slots = params_channels(params); + unsigned int slot_width = params_width(params); + int lrck_div_order, sample_rate, word_size; u8 bclk_div;

/* word size */ switch (params_width(params)) { case 8: word_size = 0x0; break; case 16: @@ -346,24 +348,24 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, word_size << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ);

bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16); regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);

- lrck_div = sun8i_codec_get_lrck_div(params_channels(params), - params_physical_width(params)); - if (lrck_div < 0) - return lrck_div; + /* LRCK divider (BCLK/LRCK ratio) */ + lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width); + if (lrck_div_order < 0) + return lrck_div_order;

regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, - lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV); + (lrck_div_order - 4) << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);

sample_rate = sun8i_codec_get_hw_rate(params); if (sample_rate < 0) return sample_rate;

regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);

Previously, the BCLK divisor calculation assumed a power-of-two slot width and exactly two slots. In order to support the TDM slot binding and 20/24-bit word sizes, those assumptions must be removed.

Due to hardware limitations, the BCLK/LRCK ratio is not as simple as "slot_width * slots". However, the correct value is already calculated elsewhere in this function, since it must also be programmed into the hardware. Reuse that value to calculate the correct SYSCLK/BCLK divisor.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 779853d023fe..78feed37aa42 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -279,21 +279,21 @@ static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = { { .div = 48, .val = 9 }, { .div = 64, .val = 10 }, { .div = 96, .val = 11 }, { .div = 128, .val = 12 }, { .div = 192, .val = 13 }, };

static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec, - unsigned int rate, - unsigned int word_size) + unsigned int lrck_div_order, + unsigned int sample_rate) { unsigned long clk_rate = clk_get_rate(scodec->clk_module); - unsigned int div = clk_rate / rate / word_size / 2; + unsigned int div = clk_rate / sample_rate >> lrck_div_order; unsigned int best_val = 0, best_diff = ~0; int i;

for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) { const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i]; unsigned int diff = abs(bdiv->div - div);

if (diff < best_diff) { @@ -343,30 +343,31 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, default: return -EINVAL; }

regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, word_size << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ);

- bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16); - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, - bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); - /* LRCK divider (BCLK/LRCK ratio) */ lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width); if (lrck_div_order < 0) return lrck_div_order;

regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, (lrck_div_order - 4) << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);

+ /* BCLK divider (SYSCLK/BCLK ratio) */ + bclk_div = sun8i_codec_get_bclk_div(scodec, lrck_div_order, params_rate(params)); + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, + SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, + bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); + sample_rate = sun8i_codec_get_hw_rate(params); if (sample_rate < 0) return sample_rate;

regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);

Now that BCLK and LRCK rate calculations can handle any hardware-supported slot width and number of slots, enable support for overriding these parameters from the device tree.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 78feed37aa42..0a53dc0c34d0 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -94,25 +94,31 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)

enum { AIF1, NAIFS };

+struct sun8i_codec_aif { + unsigned int slots; + unsigned int slot_width; +}; + struct sun8i_codec_quirks { bool legacy_widgets : 1; bool lrck_inversion : 1; };

struct sun8i_codec { struct regmap *regmap; struct clk *clk_module; const struct sun8i_codec_quirks *quirks; + struct sun8i_codec_aif aifs[NAIFS]; };

static int sun8i_codec_runtime_resume(struct device *dev) { struct sun8i_codec *scodec = dev_get_drvdata(dev); int ret;

regcache_cache_only(scodec->regmap, false); @@ -256,16 +262,32 @@ static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)

regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK, value << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV);

return 0; }

+static int sun8i_codec_set_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, + int slots, int slot_width) +{ + struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); + struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; + + if (slot_width && !is_power_of_2(slot_width)) + return -EINVAL; + + aif->slots = slots; + aif->slot_width = slot_width; + + return 0; +} + struct sun8i_codec_clk_div { u8 div; u8 val; };

static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = { { .div = 1, .val = 0 }, { .div = 2, .val = 1 }, @@ -316,18 +338,19 @@ static int sun8i_codec_get_lrck_div_order(unsigned int slots, return order_base_2(div); }

static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); - unsigned int slots = params_channels(params); - unsigned int slot_width = params_width(params); + struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; + unsigned int slots = aif->slots ?: params_channels(params); + unsigned int slot_width = aif->slot_width ?: params_width(params); int lrck_div_order, sample_rate, word_size; u8 bclk_div;

/* word size */ switch (params_width(params)) { case 8: word_size = 0x0; break; @@ -371,16 +394,17 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);

return 0; }

static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { .set_fmt = sun8i_codec_set_fmt, + .set_tdm_slot = sun8i_codec_set_tdm_slot, .hw_params = sun8i_codec_hw_params, };

static struct snd_soc_dai_driver sun8i_codec_dais[] = { { .name = "sun8i-codec-aif1", .id = AIF1, .ops = &sun8i_codec_dai_ops,

The AIFs have a single register controlling DAI parameters in both directions, including BCLK/LRCK divisor word size. The DAIs produce only noise or silence if any of these parameters is wrong. Therefore, we need to enforce symmetry for these parameters, so starting a new substream will not break an existing substream.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 0a53dc0c34d0..f21274530a0e 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -420,16 +420,19 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { /* playback capabilities */ .playback = { .stream_name = "AIF1 Playback", .channels_min = 1, .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE, }, + .symmetric_rates = true, + .symmetric_channels = true, + .symmetric_samplebits = true, }, };

static const char *const sun8i_aif_stereo_mux_enum_values[] = { "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" };

static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum,

The system sample rate programmed into the hardware is really a clock divider from SYSCLK to the ADC and DAC. Since we support two SYSCLK frequencies, we can use all sample rates corresponding to one of those frequencies divided by any available divisor.

This commit enables support for those sample rates. It also stops advertising support for a 64 kHz sample rate, which is not supported.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index f21274530a0e..f4b2a7cc9810 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -89,16 +89,23 @@ #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) #define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)

+#define SUN8I_CODEC_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ + SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_176400 |\ + SNDRV_PCM_RATE_192000 |\ + SNDRV_PCM_RATE_KNOT) + enum { AIF1, NAIFS };

struct sun8i_codec_aif { unsigned int slots; unsigned int slot_width; @@ -142,37 +149,41 @@ static int sun8i_codec_runtime_suspend(struct device *dev) return 0; }

static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) { unsigned int rate = params_rate(params);

switch (rate) { - case 8000: case 7350: + case 8000: return 0x0; case 11025: return 0x1; case 12000: return 0x2; + case 14700: case 16000: return 0x3; case 22050: return 0x4; case 24000: return 0x5; + case 29400: case 32000: return 0x6; case 44100: return 0x7; case 48000: return 0x8; + case 88200: case 96000: return 0x9; + case 176400: case 192000: return 0xa; default: return -EINVAL; } }

static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) @@ -408,26 +419,26 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { .name = "sun8i-codec-aif1", .id = AIF1, .ops = &sun8i_codec_dai_ops, /* capture capabilities */ .capture = { .stream_name = "AIF1 Capture", .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, + .rates = SUN8I_CODEC_PCM_RATES, .formats = SNDRV_PCM_FMTBIT_S16_LE, .sig_bits = 24, }, /* playback capabilities */ .playback = { .stream_name = "AIF1 Playback", .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, + .rates = SUN8I_CODEC_PCM_RATES, .formats = SNDRV_PCM_FMTBIT_S16_LE, }, .symmetric_rates = true, .symmetric_channels = true, .symmetric_samplebits = true, }, };

The sun8i codec has three clock/sample rate domains: - The AIF1 domain, with a sample rate equal to AIF1 LRCK - The AIF2 domain, with a sample rate equal to AIF2 LRCK - The SYSCLK domain, containing the ADC, DAC, and effects (AGC/DRC), with a sample rate given by a divisor from SYSCLK. The divisor is controlled by the AIF1_FS or AIF2_FS field in SYS_SR_CTRL, depending on if SYSCLK's source is AIF1CLK or AIF2CLK, respectively. The exact sample rate depends on if SYSCLK is running at 22.6 MHz or 24.6 MHz.

When an AIF (currently only AIF1) is active, the ADC and DAC should run at that sample rate to avoid artifacting. Sample rate conversion is only available when multiple AIFs are active and are routed to each other; this means the sample rate conversion hardware usually cannot be used.

Only attach the event hook to the channel 0 AIF widgets, since we only need one event when a DAI stream starts or stops. Channel 0 is always brought up with a DAI stream, regardless of the number of channels in the stream.

The ADC and DAC (along with their effects blocks) can be used even if no AIFs are in use. In that case, we should select an appropriate sample rate divisor, instead of keeping the last-used AIF sample rate. 44.1/48 kHz was chosen to balance audio quality and power consumption.

Since the sample rate is tied to active AIF paths, disabling pmdown_time allows switching to the optimal sample rate immediately, instead of after a 5 second delay.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 103 +++++++++++++++++++++++++++------- 1 file changed, 84 insertions(+), 19 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index f4b2a7cc9810..43b4319e3d84 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -89,31 +89,36 @@ #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) #define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)

+#define SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE 48000 + #define SUN8I_CODEC_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ SNDRV_PCM_RATE_88200 |\ SNDRV_PCM_RATE_96000 |\ SNDRV_PCM_RATE_176400 |\ SNDRV_PCM_RATE_192000 |\ SNDRV_PCM_RATE_KNOT)

enum { AIF1, NAIFS };

struct sun8i_codec_aif { + unsigned int sample_rate; unsigned int slots; unsigned int slot_width; + unsigned int active_streams : 2; + unsigned int open_streams : 2; };

struct sun8i_codec_quirks { bool legacy_widgets : 1; bool lrck_inversion : 1; };

struct sun8i_codec { @@ -144,21 +149,19 @@ static int sun8i_codec_runtime_suspend(struct device *dev) struct sun8i_codec *scodec = dev_get_drvdata(dev);

regcache_cache_only(scodec->regmap, true); regcache_mark_dirty(scodec->regmap);

return 0; }

-static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) +static int sun8i_codec_get_hw_rate(unsigned int sample_rate) { - unsigned int rate = params_rate(params); - - switch (rate) { + switch (sample_rate) { case 7350: case 8000: return 0x0; case 11025: return 0x1; case 12000: return 0x2; case 14700: @@ -181,16 +184,43 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) case 176400: case 192000: return 0xa; default: return -EINVAL; } }

+static int sun8i_codec_update_sample_rate(struct sun8i_codec *scodec) +{ + unsigned int max_rate = 0; + int hw_rate, i; + + for (i = AIF1; i < NAIFS; ++i) { + struct sun8i_codec_aif *aif = &scodec->aifs[i]; + + if (aif->active_streams) + max_rate = max(max_rate, aif->sample_rate); + } + + /* Set the sample rate for ADC->DAC passthrough when no AIF is active. */ + if (!max_rate) + max_rate = SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE; + + hw_rate = sun8i_codec_get_hw_rate(max_rate); + if (hw_rate < 0) + return hw_rate; + + regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, + SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, + hw_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); + + return 0; +} + static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); u32 format, invert, value;

/* clock masters */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ @@ -350,19 +380,20 @@ static int sun8i_codec_get_lrck_div_order(unsigned int slots, }

static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; + unsigned int sample_rate = params_rate(params); unsigned int slots = aif->slots ?: params_channels(params); unsigned int slot_width = aif->slot_width ?: params_width(params); - int lrck_div_order, sample_rate, word_size; + int lrck_div_order, word_size; u8 bclk_div;

/* word size */ switch (params_width(params)) { case 8: word_size = 0x0; break; case 16: @@ -387,36 +418,48 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, if (lrck_div_order < 0) return lrck_div_order;

regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, (lrck_div_order - 4) << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);

/* BCLK divider (SYSCLK/BCLK ratio) */ - bclk_div = sun8i_codec_get_bclk_div(scodec, lrck_div_order, params_rate(params)); + bclk_div = sun8i_codec_get_bclk_div(scodec, lrck_div_order, sample_rate); regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);

- sample_rate = sun8i_codec_get_hw_rate(params); - if (sample_rate < 0) - return sample_rate; + aif->sample_rate = sample_rate; + aif->open_streams |= BIT(substream->stream);

- regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); + return sun8i_codec_update_sample_rate(scodec); +} + +static int sun8i_codec_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); + struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; + + if (aif->open_streams != BIT(substream->stream)) + goto done;

+ aif->sample_rate = 0; + +done: + aif->open_streams &= ~BIT(substream->stream); return 0; }

static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { .set_fmt = sun8i_codec_set_fmt, .set_tdm_slot = sun8i_codec_set_tdm_slot, .hw_params = sun8i_codec_hw_params, + .hw_free = sun8i_codec_hw_free, };

static struct snd_soc_dai_driver sun8i_codec_dais[] = { { .name = "sun8i-codec-aif1", .id = AIF1, .ops = &sun8i_codec_dai_ops, /* capture capabilities */ @@ -437,16 +480,32 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { .formats = SNDRV_PCM_FMTBIT_S16_LE, }, .symmetric_rates = true, .symmetric_channels = true, .symmetric_samplebits = true, }, };

+static int sun8i_codec_aif_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); + struct sun8i_codec_aif *aif = &scodec->aifs[w->sname[3] - '1']; + int stream = w->id == snd_soc_dapm_aif_out; + + if (SND_SOC_DAPM_EVENT_ON(event)) + aif->active_streams |= BIT(stream); + else + aif->active_streams &= ~BIT(stream); + + return sun8i_codec_update_sample_rate(scodec); +} + static const char *const sun8i_aif_stereo_mux_enum_values[] = { "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" };

static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC, @@ -539,19 +598,21 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0),

/* AIF "ADC" Outputs */ - SND_SOC_DAPM_AIF_OUT("AIF1 AD0L", "AIF1 Capture", 0, - SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), + SND_SOC_DAPM_AIF_OUT_E("AIF1 AD0L", "AIF1 Capture", 0, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0, + sun8i_codec_aif_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "AIF1 Capture", 1, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),

/* AIF "ADC" Mono/Stereo Muxes */ SND_SOC_DAPM_MUX("AIF1 AD0L Stereo Mux", SND_SOC_NOPM, 0, 0, &sun8i_aif1_ad0_stereo_mux_control), SND_SOC_DAPM_MUX("AIF1 AD0R Stereo Mux", SND_SOC_NOPM, 0, 0, @@ -565,19 +626,21 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {

/* AIF "DAC" Mono/Stereo Muxes */ SND_SOC_DAPM_MUX("AIF1 DA0L Stereo Mux", SND_SOC_NOPM, 0, 0, &sun8i_aif1_da0_stereo_mux_control), SND_SOC_DAPM_MUX("AIF1 DA0R Stereo Mux", SND_SOC_NOPM, 0, 0, &sun8i_aif1_da0_stereo_mux_control),

/* AIF "DAC" Inputs */ - SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "AIF1 Playback", 0, - SUN8I_AIF1_DACDAT_CTRL, - SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), + SND_SOC_DAPM_AIF_IN_E("AIF1 DA0L", "AIF1 Playback", 0, + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0, + sun8i_codec_aif_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "AIF1 Playback", 1, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),

/* ADC Inputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),

@@ -722,27 +785,29 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL | SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL);

/* Use AIF1CLK as the SYSCLK parent since AIF1 is used most often. */ regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC), SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK);

+ /* Program the default sample rate. */ + sun8i_codec_update_sample_rate(scodec); + return 0; }

static const struct snd_soc_component_driver sun8i_soc_component = { .dapm_widgets = sun8i_codec_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), .dapm_routes = sun8i_codec_dapm_routes, .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes), .probe = sun8i_codec_component_probe, .idle_bias_on = 1, - .use_pmdown_time = 1, .endianness = 1, .non_legacy_dai_naming = 1, };

static const struct regmap_config sun8i_codec_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32,

While another stream is active, only allow userspace to use sample rates that are compatible with the current SYSCLK frequency. This ensures the actual sample rate will always match what is given in hw_params.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 59 ++++++++++++++++++++++++++++++++--- 1 file changed, 55 insertions(+), 4 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 43b4319e3d84..501af64d43a0 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -121,16 +121,18 @@ struct sun8i_codec_quirks { bool lrck_inversion : 1; };

struct sun8i_codec { struct regmap *regmap; struct clk *clk_module; const struct sun8i_codec_quirks *quirks; struct sun8i_codec_aif aifs[NAIFS]; + unsigned int sysclk_rate; + int sysclk_refcnt; };

static int sun8i_codec_runtime_resume(struct device *dev) { struct sun8i_codec *scodec = dev_get_drvdata(dev); int ret;

regcache_cache_only(scodec->regmap, false); @@ -319,16 +321,57 @@ static int sun8i_codec_set_tdm_slot(struct snd_soc_dai *dai, return -EINVAL;

aif->slots = slots; aif->slot_width = slot_width;

return 0; }

+static const unsigned int sun8i_codec_rates[] = { + 7350, 8000, 11025, 12000, 14700, 16000, 22050, 24000, + 29400, 32000, 44100, 48000, 88200, 96000, 176400, 192000, +}; + +static const struct snd_pcm_hw_constraint_list sun8i_codec_all_rates = { + .list = sun8i_codec_rates, + .count = ARRAY_SIZE(sun8i_codec_rates), +}; + +static const struct snd_pcm_hw_constraint_list sun8i_codec_22M_rates = { + .list = sun8i_codec_rates, + .count = ARRAY_SIZE(sun8i_codec_rates), + .mask = 0x5555, +}; + +static const struct snd_pcm_hw_constraint_list sun8i_codec_24M_rates = { + .list = sun8i_codec_rates, + .count = ARRAY_SIZE(sun8i_codec_rates), + .mask = 0xaaaa, +}; + +static int sun8i_codec_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); + const struct snd_pcm_hw_constraint_list *list; + + if (!scodec->sysclk_refcnt) + list = &sun8i_codec_all_rates; + else if (scodec->sysclk_rate == 22579200) + list = &sun8i_codec_22M_rates; + else if (scodec->sysclk_rate == 24576000) + list = &sun8i_codec_24M_rates; + else + return -EINVAL; + + return snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, list); +} + struct sun8i_codec_clk_div { u8 div; u8 val; };

static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = { { .div = 1, .val = 0 }, { .div = 2, .val = 1 }, @@ -341,22 +384,21 @@ static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = { { .div = 32, .val = 8 }, { .div = 48, .val = 9 }, { .div = 64, .val = 10 }, { .div = 96, .val = 11 }, { .div = 128, .val = 12 }, { .div = 192, .val = 13 }, };

-static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec, +static u8 sun8i_codec_get_bclk_div(unsigned int sysclk_rate, unsigned int lrck_div_order, unsigned int sample_rate) { - unsigned long clk_rate = clk_get_rate(scodec->clk_module); - unsigned int div = clk_rate / sample_rate >> lrck_div_order; + unsigned int div = sysclk_rate / sample_rate >> lrck_div_order; unsigned int best_val = 0, best_diff = ~0; int i;

for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) { const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i]; unsigned int diff = abs(bdiv->div - div);

if (diff < best_diff) { @@ -383,16 +425,17 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; unsigned int sample_rate = params_rate(params); unsigned int slots = aif->slots ?: params_channels(params); unsigned int slot_width = aif->slot_width ?: params_width(params); + unsigned int sysclk_rate = clk_get_rate(scodec->clk_module); int lrck_div_order, word_size; u8 bclk_div;

/* word size */ switch (params_width(params)) { case 8: word_size = 0x0; break; @@ -418,46 +461,54 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, if (lrck_div_order < 0) return lrck_div_order;

regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, (lrck_div_order - 4) << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);

/* BCLK divider (SYSCLK/BCLK ratio) */ - bclk_div = sun8i_codec_get_bclk_div(scodec, lrck_div_order, sample_rate); + bclk_div = sun8i_codec_get_bclk_div(sysclk_rate, lrck_div_order, sample_rate); regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);

+ if (!aif->open_streams) { + scodec->sysclk_rate = sysclk_rate; + scodec->sysclk_refcnt++; + } + aif->sample_rate = sample_rate; aif->open_streams |= BIT(substream->stream);

return sun8i_codec_update_sample_rate(scodec); }

static int sun8i_codec_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); struct sun8i_codec_aif *aif = &scodec->aifs[dai->id];

if (aif->open_streams != BIT(substream->stream)) goto done;

+ scodec->sysclk_refcnt--; + aif->sample_rate = 0;

done: aif->open_streams &= ~BIT(substream->stream); return 0; }

static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { .set_fmt = sun8i_codec_set_fmt, .set_tdm_slot = sun8i_codec_set_tdm_slot, + .startup = sun8i_codec_startup, .hw_params = sun8i_codec_hw_params, .hw_free = sun8i_codec_hw_free, };

static struct snd_soc_dai_driver sun8i_codec_dais[] = { { .name = "sun8i-codec-aif1", .id = AIF1,

The codec's clock input is shared among all AIFs, and shared with other audio-related hardware in the SoC, including I2S and SPDIF controllers. To ensure sample rates selected by userspace or by codec2codec DAI links are maintained, the clock rate must be protected while it is in use.

Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 501af64d43a0..86065bee7cd3 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -416,27 +416,32 @@ static int sun8i_codec_get_lrck_div_order(unsigned int slots, unsigned int div = slots * slot_width;

if (div < 16 || div > 256) return -EINVAL;

return order_base_2(div); }

+static unsigned int sun8i_codec_get_sysclk_rate(unsigned int sample_rate) +{ + return sample_rate % 4000 ? 22579200 : 24576000; +} + static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; unsigned int sample_rate = params_rate(params); unsigned int slots = aif->slots ?: params_channels(params); unsigned int slot_width = aif->slot_width ?: params_width(params); - unsigned int sysclk_rate = clk_get_rate(scodec->clk_module); - int lrck_div_order, word_size; + unsigned int sysclk_rate = sun8i_codec_get_sysclk_rate(sample_rate); + int lrck_div_order, ret, word_size; u8 bclk_div;

/* word size */ switch (params_width(params)) { case 8: word_size = 0x0; break; case 16: @@ -466,17 +471,30 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, (lrck_div_order - 4) << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);

/* BCLK divider (SYSCLK/BCLK ratio) */ bclk_div = sun8i_codec_get_bclk_div(sysclk_rate, lrck_div_order, sample_rate); regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);

- if (!aif->open_streams) { + /* SYSCLK rate */ + if (aif->open_streams) { + ret = clk_set_rate(scodec->clk_module, sysclk_rate); + if (ret < 0) + return ret; + } else { + ret = clk_set_rate_exclusive(scodec->clk_module, sysclk_rate); + if (ret == -EBUSY) + dev_err(dai->dev, "%s: clock is busy! Sample rate %u Hz " + "conflicts with other audio streams.\n", + dai->name, sample_rate); + if (ret < 0) + return ret; + scodec->sysclk_rate = sysclk_rate; scodec->sysclk_refcnt++; }

aif->sample_rate = sample_rate; aif->open_streams |= BIT(substream->stream);

return sun8i_codec_update_sample_rate(scodec); @@ -487,16 +505,17 @@ static int sun8i_codec_hw_free(struct snd_pcm_substream *substream, { struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); struct sun8i_codec_aif *aif = &scodec->aifs[dai->id];

if (aif->open_streams != BIT(substream->stream)) goto done;

scodec->sysclk_refcnt--; + clk_rate_exclusive_put(scodec->clk_module);

aif->sample_rate = 0;

done: aif->open_streams &= ~BIT(substream->stream); return 0; }