[alsa-devel] [RFC PATCH 00/34] sun8i-codec fixes and new features
Hello all,
The sun8i-codec driver, as used in the Allwinner A33 and A64, currently only exposes a small subset of the available hardware features. In order to use the A64 in a smartphone (the PinePhone), I've added the necessary functionality to the driver: * The full set of supported DAI format options * Support for AIF2 and AIF3 * Additional routing knobs * Additional volume controls
Unfortunately, due to preexisting issues with the driver, there are some breaking changes, as explained further in the commit messages: * The LRCK inversion issue means we need a new compatible for the A64. * Some controls are named inaccurately, so they are renamed. * Likewise, the DAPM widgets used in device trees were either named wrong, or the device trees were using the wrong widgets in the first place. (Specifically, the links between the analog codec and digital codec happen at the ADC and DAC, not AIF1.)
I tended to take the philosophy of "while I'm breaking things, I might as well do them right", so I've probably made a few more changes than absolutely necessary. I'm not sure about where all of the policy boundaries are, about how far I should go to maintain compatibility. For example, for the DT widget usage, I could: * Rename everything and update the DTS files (which is what I did) * Keep the old (misleading/wrong) name for the widgets, but repurpose them to work correctly (i.e. "ADC Left" would be named "AIF1 Slot 0 Left ADC", but it would work just like "ADC Left" does in this patchset) * Keep the old widgets around as a compatibility layer, but add new widgets and update the in-tree DTS files to use them (i.e. "ADC Left" would have a path from "AIF1 Slot 0 Left ADC", but "AIF1 Slot 0 Left ADC" would be a no-op widget) * Something else entirely
There are several trivial fixes in here, and there are several commits that just add new features without changing any existing behavior, but there is enough changing that I thought it would be best to send the whole thing as an RFC. I'm more than happy to reorganize this into one or several patchsets in future revisions. It doesn't have to all go in at once.
This has all been tested on the PinePhone. For example, I've successfully routed a voice call between the modem at AIF2 and a Bluetooth headset at AIF3, merged with an audio file played from AIF1. Unfortunately, the PinePhone does not have a DTS upstream yet (partially due to the audio driver situation), so I don't have an example DTS in this patchset.
Thanks for any feedback, Samuel
Samuel Holland (34): ASoC: dt-bindings: Add a separate compatible for the A64 codec ASoC: sun8i-codec: LRCK is not inverted on A64 arm64: dts: allwinner: a64: Fix the audio codec compatible ASoC: sun8i-codec: Remove unused dev from codec struct ASoC: sun8i-codec: Remove incorrect SND_SOC_DAIFMT_DSP_B ASoC: sun8i-codec: Fix setting DAI data format ASoC: sun8i-codec: Remove extraneous widgets ASoC: sun8i-codec: Fix direction of AIF1 outputs ASoC: sun8i-codec: Fix broken DAPM routing ASoC: sun8i-codec: Advertise only hardware-supported rates ASoC: sun8i-codec: Enforce parameter symmetry ASoC: sun8i-codec: Fix AIF1 MODCLK widget name ASoC: sun8i-codec: Fix AIF1_ADCDAT_CTRL field names ASoC: sun8i-codec: Fix AIF1_MXR_SRC field names ASoC: sun8i-codec: Fix ADC_DIG_CTRL field name ASoC: sun8i-codec: Fix field bit number indentation ASoC: sun8i-codec: Sort masks in a consistent order ASoC: sun8i-codec: Allow all clock inversion permutations ASoC: sun8i-codec: Support mono DAI configurations ASoC: sun8i-codec: Support 8/20/24-bit word sizes ASoC: sun8i-codec: Clean up module/clock hierarchy ASoC: sun8i-codec: Clean up AIF1 Slot 0 widgets ASoC: sun8i-codec: Clean up DAC widgets ASoC: sun8i-codec: Prepare to support multiple AIFs ASoC: sun8i-codec: Add support for AIF2 ASoC: sun8i-codec: Add support for AIF3 ASoC: sun8i-codec: Add AIF mono/stereo controls ASoC: sun8i-codec: Add AIF loopback controls ASoC: sun8i-codec: Add AIF, ADC, and DAC volume controls ASoC: dt-bindings: Bump sound-dai-cells on sun8i-codec ARM: dts: sun8i-a33: Allow using multiple codec DAIs arm64: dts: allwinner: a64: Allow using multiple codec DAIs arm64: dts: allwinner: a64: Allow multiple DAI links arm64: dts: allwinner: a64: Add pinmux for AIF2/AIF3
.../sound/allwinner,sun8i-a33-codec.yaml | 6 +- arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 6 +- arch/arm/boot/dts/sun8i-a33.dtsi | 10 +- .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 8 +- .../dts/allwinner/sun50i-a64-orangepi-win.dts | 8 +- .../boot/dts/allwinner/sun50i-a64-pine64.dts | 8 +- .../dts/allwinner/sun50i-a64-pinebook.dts | 8 +- .../boot/dts/allwinner/sun50i-a64-pinetab.dts | 14 +- .../allwinner/sun50i-a64-sopine-baseboard.dts | 8 +- .../boot/dts/allwinner/sun50i-a64-teres-i.dts | 8 +- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 47 +- sound/soc/sunxi/sun8i-codec.c | 1056 +++++++++++++---- 12 files changed, 890 insertions(+), 297 deletions(-)
The digital codec in the A64 is largely compatible with the one in the A33, with two changes: - It is missing some muxing options for AIF1/2/3 (not currently supported by the driver) - It does not have the LRCK inversion issue that A33 has
To fix the Left/Right channel inversion on the A64 caused by the A33 LRCK fix, we need to introduce a new compatible for the codec in the A64.
Cc: stable@kernel.org Fixes: ec4a95409d5c ("arm64: dts: allwinner: a64: add nodes necessary for analog sound support") Signed-off-by: Samuel Holland samuel@sholland.org --- .../devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml index 55d28268d2f4..7c66409f13ea 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml @@ -15,7 +15,9 @@ properties: const: 0
compatible: - const: allwinner,sun8i-a33-codec + enum: + - allwinner,sun8i-a33-codec + - allwinner,sun50i-a64-codec
reg: maxItems: 1
On Mon, Feb 17, 2020 at 2:42 PM Samuel Holland samuel@sholland.org wrote:
The digital codec in the A64 is largely compatible with the one in the A33, with two changes:
- It is missing some muxing options for AIF1/2/3 (not currently supported by the driver)
Is this at the pinctrl level or mixer level? If it's at the pinctrl level then it's out of the scope of this driver/binding. It could very well have those signals, just that they aren't routed outside the SoC.
ChenYu
- It does not have the LRCK inversion issue that A33 has
To fix the Left/Right channel inversion on the A64 caused by the A33 LRCK fix, we need to introduce a new compatible for the codec in the A64.
Cc: stable@kernel.org Fixes: ec4a95409d5c ("arm64: dts: allwinner: a64: add nodes necessary for analog sound support") Signed-off-by: Samuel Holland samuel@sholland.org
.../devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml index 55d28268d2f4..7c66409f13ea 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml @@ -15,7 +15,9 @@ properties: const: 0
compatible:
- const: allwinner,sun8i-a33-codec
enum:
- allwinner,sun8i-a33-codec- allwinner,sun50i-a64-codecreg: maxItems: 1
-- 2.24.1
On 2/17/20 3:49 AM, Chen-Yu Tsai wrote:
On Mon, Feb 17, 2020 at 2:42 PM Samuel Holland samuel@sholland.org wrote:
The digital codec in the A64 is largely compatible with the one in the A33, with two changes:
- It is missing some muxing options for AIF1/2/3 (not currently supported by the driver)
Is this at the pinctrl level or mixer level? If it's at the pinctrl level then it's out of the scope of this driver/binding. It could very well have those signals, just that they aren't routed outside the SoC.
This is in reference to the muxes shown at the top of the A33 diagram, above the I2S/PCM interfaces. These appear to map to bits 0-6 of AIF3_SGP_CTRL, which are marked as reserved on the A64 and the AC100.
Comparing the three datasheets in a bit more detail (but by no means exhaustively): - The A64 has a second DRC block, unlike the A33 and AC100. - The jack detection registers (0x310-0x318) are present on the A64 and AC100, but undocumented/missing on the A33.
So there are enough differences to warrant a new compatible, but since none of the unique functionality is used by the driver (even after this series), a fallback should work.
On Mon, 17 Feb 2020 00:42:17 -0600, Samuel Holland wrote:
The digital codec in the A64 is largely compatible with the one in the A33, with two changes:
- It is missing some muxing options for AIF1/2/3 (not currently supported by the driver)
- It does not have the LRCK inversion issue that A33 has
To fix the Left/Right channel inversion on the A64 caused by the A33 LRCK fix, we need to introduce a new compatible for the codec in the A64.
Cc: stable@kernel.org Fixes: ec4a95409d5c ("arm64: dts: allwinner: a64: add nodes necessary for analog sound support") Signed-off-by: Samuel Holland samuel@sholland.org
.../devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Acked-by: Rob Herring robh@kernel.org
On the A64 (tested with the Pinephone), the current code causes the left/right channels to be swapped during I2S playback from the CPU on AIF1, and breaks DSP_A communication with the modem on AIF2.
Trusting that the comment in the code is correct, the existing behavior is kept for the A33.
Cc: stable@kernel.org Fixes: ec4a95409d5c ("arm64: dts: allwinner: a64: add nodes necessary for analog sound support") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 55798bc8eae2..14cf31f5c535 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -13,6 +13,7 @@ #include <linux/delay.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/of_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/log2.h> @@ -89,6 +90,7 @@ struct sun8i_codec { struct regmap *regmap; struct clk *clk_module; struct clk *clk_bus; + bool inverted_lrck; };
static int sun8i_codec_runtime_resume(struct device *dev) @@ -209,18 +211,19 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
/* - * It appears that the DAI and the codec don't share the same - * polarity for the LRCK signal when they mean 'normal' and - * 'inverted' in the datasheet. + * It appears that the DAI and the codec in the A33 SoC don't + * share the same polarity for the LRCK signal when they mean + * 'normal' and 'inverted' in the datasheet. * * Since the DAI here is our regular i2s driver that have been * tested with way more codecs than just this one, it means * that the codec probably gets it backward, and we have to * invert the value here. */ + value ^= scodec->inverted_lrck; regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV), - !value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV); + value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
/* DAI format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -568,6 +571,8 @@ static int sun8i_codec_probe(struct platform_device *pdev) return PTR_ERR(scodec->regmap); }
+ scodec->inverted_lrck = (uintptr_t)of_device_get_match_data(&pdev->dev); + platform_set_drvdata(pdev, scodec);
pm_runtime_enable(&pdev->dev); @@ -606,7 +611,14 @@ static int sun8i_codec_remove(struct platform_device *pdev) }
static const struct of_device_id sun8i_codec_of_match[] = { - { .compatible = "allwinner,sun8i-a33-codec" }, + { + .compatible = "allwinner,sun8i-a33-codec", + .data = (void *)1, + }, + { + .compatible = "allwinner,sun50i-a64-codec", + .data = (void *)0, + }, {} }; MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
On Mon, Feb 17, 2020 at 2:42 PM Samuel Holland samuel@sholland.org wrote:
On the A64 (tested with the Pinephone), the current code causes the left/right channels to be swapped during I2S playback from the CPU on AIF1, and breaks DSP_A communication with the modem on AIF2.
Trusting that the comment in the code is correct, the existing behavior is kept for the A33.
Cc: stable@kernel.org Fixes: ec4a95409d5c ("arm64: dts: allwinner: a64: add nodes necessary for analog sound support") Signed-off-by: Samuel Holland samuel@sholland.org
sound/soc/sunxi/sun8i-codec.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 55798bc8eae2..14cf31f5c535 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -13,6 +13,7 @@ #include <linux/delay.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/of_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/log2.h> @@ -89,6 +90,7 @@ struct sun8i_codec { struct regmap *regmap; struct clk *clk_module; struct clk *clk_bus;
bool inverted_lrck;};
static int sun8i_codec_runtime_resume(struct device *dev) @@ -209,18 +211,19 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
/*
* It appears that the DAI and the codec don't share the same* polarity for the LRCK signal when they mean 'normal' and* 'inverted' in the datasheet.
* It appears that the DAI and the codec in the A33 SoC don't* share the same polarity for the LRCK signal when they mean* 'normal' and 'inverted' in the datasheet. * * Since the DAI here is our regular i2s driver that have been * tested with way more codecs than just this one, it means * that the codec probably gets it backward, and we have to * invert the value here. */value ^= scodec->inverted_lrck; regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
!value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV); /* DAI format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {@@ -568,6 +571,8 @@ static int sun8i_codec_probe(struct platform_device *pdev) return PTR_ERR(scodec->regmap); }
scodec->inverted_lrck = (uintptr_t)of_device_get_match_data(&pdev->dev);platform_set_drvdata(pdev, scodec); pm_runtime_enable(&pdev->dev);@@ -606,7 +611,14 @@ static int sun8i_codec_remove(struct platform_device *pdev) }
static const struct of_device_id sun8i_codec_of_match[] = {
{ .compatible = "allwinner,sun8i-a33-codec" },
{.compatible = "allwinner,sun8i-a33-codec",.data = (void *)1,
So depending on the answer to the previous patch, this might be enough, though somewhat an eyesore. Otherwise I suggest using a proper quirks structure.
ChenYu
},{.compatible = "allwinner,sun50i-a64-codec",.data = (void *)0,}, {}}; MODULE_DEVICE_TABLE(of, sun8i_codec_of_match); -- 2.24.1
On Mon, Feb 17, 2020 at 12:42:18AM -0600, Samuel Holland wrote:
- scodec->inverted_lrck = (uintptr_t)of_device_get_match_data(&pdev->dev);
This is going to break the moment someone finds another quirk for some variant of this device, it's not scalable.
Some differences were found between the A33 codec and the A64 codec, causing the left and right channels to be swapped. To fix this, a new compatible was added for the A64 variant of the codec. Update the A64 DTS to use the correct compatible.
Cc: stable@kernel.org Fixes: ec4a95409d5c ("arm64: dts: allwinner: a64: add nodes necessary for analog sound support") Signed-off-by: Samuel Holland samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 27e48234f1c2..6d7aa1736d21 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -802,7 +802,7 @@ dai: dai@1c22c00 {
codec: codec@1c22e00 { #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-a33-codec"; + compatible = "allwinner,sun50i-a64-codec"; reg = <0x01c22e00 0x600>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
On Mon, Feb 17, 2020 at 12:42:19AM -0600, Samuel Holland wrote:
Cc: stable@kernel.org Fixes: ec4a95409d5c ("arm64: dts: allwinner: a64: add nodes necessary for analog sound support") Signed-off-by: Samuel Holland samuel@sholland.org
codec: codec@1c22e00 { #sound-dai-cells = <0>;
compatible = "allwinner,sun8i-a33-codec";
compatible = "allwinner,sun50i-a64-codec";
This is an incompatible change in the ABI, it's going to break unless it's applied at exactly the same time as the matching kernel update adding the new compatible string. That's not suitable for stable, you need to keep the old compatible as a fallback.
This field is not used anywhere in the driver, so remove it.
Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 14cf31f5c535..33ffbc2be47c 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -86,7 +86,6 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
struct sun8i_codec { - struct device *dev; struct regmap *regmap; struct clk *clk_module; struct clk *clk_bus; @@ -544,8 +543,6 @@ static int sun8i_codec_probe(struct platform_device *pdev) if (!scodec) return -ENOMEM;
- scodec->dev = &pdev->dev; - scodec->clk_module = devm_clk_get(&pdev->dev, "mod"); if (IS_ERR(scodec->clk_module)) { dev_err(&pdev->dev, "Failed to get the module clock\n");
On Mon, Feb 17, 2020 at 2:42 PM Samuel Holland samuel@sholland.org wrote:
This field is not used anywhere in the driver, so remove it.
Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
On Mon, Feb 17, 2020 at 12:42:20AM -0600, Samuel Holland wrote:
This field is not used anywhere in the driver, so remove it.
Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec")
This is in no way a bug fix, it's a random cleanup. This means that the Fixes tag isn't really appropriate and it should be done after the subsequent changes in the series that fix real bugs. You should always put bug fixes first so that they don't have any unneeded depenencies on other things and can be merged without them.
The patch
ASoC: sun8i-codec: Remove unused dev from codec struct
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.7
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From 150cbf8e66ec86966c13fd7a0e3de8813bca03d8 Mon Sep 17 00:00:00 2001
From: Samuel Holland samuel@sholland.org Date: Mon, 17 Feb 2020 00:42:20 -0600 Subject: [PATCH] ASoC: sun8i-codec: Remove unused dev from codec struct
This field is not used anywhere in the driver, so remove it.
Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org Acked-by: Chen-Yu Tsai wens@csie.org Link: https://lore.kernel.org/r/20200217064250.15516-5-samuel@sholland.org Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/sunxi/sun8i-codec.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 55798bc8eae2..41471bd01042 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -85,7 +85,6 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
struct sun8i_codec { - struct device *dev; struct regmap *regmap; struct clk *clk_module; struct clk *clk_bus; @@ -541,8 +540,6 @@ static int sun8i_codec_probe(struct platform_device *pdev) if (!scodec) return -ENOMEM;
- scodec->dev = &pdev->dev; - scodec->clk_module = devm_clk_get(&pdev->dev, "mod"); if (IS_ERR(scodec->clk_module)) { dev_err(&pdev->dev, "Failed to get the module clock\n");
DSP_A and DSP_B are not interchangeable. The timing used by the codec in DSP mode is consistent with DSP_A. This is verified with an EG25-G modem connected to AIF2, as well as by comparing with the BSP driver.
Remove the DSP_B option, as it is not supported by the hardware.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 1 - 1 file changed, 1 deletion(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 33ffbc2be47c..32b7410540c6 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -236,7 +236,6 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) value = 0x2; break; case SND_SOC_DAIFMT_DSP_A: - case SND_SOC_DAIFMT_DSP_B: value = 0x3; break; default:
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
DSP_A and DSP_B are not interchangeable. The timing used by the codec in DSP mode is consistent with DSP_A. This is verified with an EG25-G modem connected to AIF2, as well as by comparing with the BSP driver.
Remove the DSP_B option, as it is not supported by the hardware.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
On Mon, Feb 17, 2020 at 12:42:21AM -0600, Samuel Holland wrote:
DSP_A and DSP_B are not interchangeable. The timing used by the codec in DSP mode is consistent with DSP_A. This is verified with an EG25-G modem connected to AIF2, as well as by comparing with the BSP driver.
Remove the DSP_B option, as it is not supported by the hardware.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec")
This can only break things for existing systems using stable, if they haven't noticed a problem with DSP B they'll certainly notice failing to set up the DAI at all without it.
On 2/17/20 9:02 AM, Mark Brown wrote:
On Mon, Feb 17, 2020 at 12:42:21AM -0600, Samuel Holland wrote:
DSP_A and DSP_B are not interchangeable. The timing used by the codec in DSP mode is consistent with DSP_A. This is verified with an EG25-G modem connected to AIF2, as well as by comparing with the BSP driver.
Remove the DSP_B option, as it is not supported by the hardware.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec")
This can only break things for existing systems using stable, if they haven't noticed a problem with DSP B they'll certainly notice failing to set up the DAI at all without it.
Are you suggesting that I drop this patch entirely, or only that I remove the CC to stable (and/or Fixes: tag)? Is this something that can't be removed once it's there, or is the concern about making user-visible changes on stable?
Thanks, Samuel
On Mon, Feb 17, 2020 at 07:35:08PM -0600, Samuel Holland wrote:
On 2/17/20 9:02 AM, Mark Brown wrote:
On Mon, Feb 17, 2020 at 12:42:21AM -0600, Samuel Holland wrote:
DSP_A and DSP_B are not interchangeable. The timing used by the codec in DSP mode is consistent with DSP_A. This is verified with an EG25-G modem connected to AIF2, as well as by comparing with the BSP driver.
This can only break things for existing systems using stable, if they haven't noticed a problem with DSP B they'll certainly notice failing to set up the DAI at all without it.
Are you suggesting that I drop this patch entirely, or only that I remove the CC to stable (and/or Fixes: tag)? Is this something that can't be removed once it's there, or is the concern about making user-visible changes on stable?
Remove the stable tag, if someone is relying on the DSP B support in stable this will break it.
Use the correct mask for this two-bit field. This fixes setting the DAI data format to RIGHT_J or DSP_A.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 32b7410540c6..cb3867644363 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -81,6 +81,7 @@
#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) +#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) @@ -242,7 +243,7 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; } regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT), + SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
return 0;
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
Use the correct mask for this two-bit field. This fixes setting the DAI data format to RIGHT_J or DSP_A.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
The patch
ASoC: sun8i-codec: Fix setting DAI data format
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From 96781fd941b39e1f78098009344ebcd7af861c67 Mon Sep 17 00:00:00 2001
From: Samuel Holland samuel@sholland.org Date: Mon, 17 Feb 2020 00:42:22 -0600 Subject: [PATCH] ASoC: sun8i-codec: Fix setting DAI data format
Use the correct mask for this two-bit field. This fixes setting the DAI data format to RIGHT_J or DSP_A.
Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org Acked-by: Chen-Yu Tsai wens@csie.org Cc: stable@kernel.org Link: https://lore.kernel.org/r/20200217064250.15516-7-samuel@sholland.org Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/sunxi/sun8i-codec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 55798bc8eae2..686561df8e13 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -80,6 +80,7 @@
#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) +#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) @@ -241,7 +242,7 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; } regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT), + SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
return 0;
This driver is for the digital part of the codec, which has no microphone input. These widgets look like they were copied from sun4i-codec. Since they do not belong here, remove them.
Cc: stable@kernel.org Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index cb3867644363..0eca75d22f13 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -441,10 +441,6 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), - - SND_SOC_DAPM_MIC("Headset Mic", NULL), - SND_SOC_DAPM_MIC("Mic", NULL), - };
static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
This driver is for the digital part of the codec, which has no microphone input. These widgets look like they were copied from sun4i-codec. Since they do not belong here, remove them.
Cc: stable@kernel.org Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org
Reviewed-by: Chen-Yu Tsai wens@csie.org
On Mon, Feb 17, 2020 at 12:42:23AM -0600, Samuel Holland wrote:
This driver is for the digital part of the codec, which has no microphone input. These widgets look like they were copied from sun4i-codec. Since they do not belong here, remove them.
Cc: stable@kernel.org Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33")
This is a cleanup, why send it to stable?
The naming convention for AIFs in this codec is to call the "DAC" the path from the AIF into the codec, and the ADC the path from the codec back to the AIF, regardless of if there is any analog path involved.
The output from AIF 1 used for capture should be declared as such.
Cc: stable@kernel.org Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 0eca75d22f13..83c812742cc1 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -399,12 +399,12 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
/* Analog ADC AIF */ - SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left ADC", "Capture", 0, - SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right ADC", "Capture", 0, - SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0), + SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Left ADC", "Capture", 0, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0), + SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Right ADC", "Capture", 0, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0),
/* DAC and ADC Mixers */ SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
The naming convention for AIFs in this codec is to call the "DAC" the path from the AIF into the codec, and the ADC the path from the codec back to the AIF, regardless of if there is any analog path involved.
The output from AIF 1 used for capture should be declared as such.
Cc: stable@kernel.org Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
On Mon, Feb 17, 2020 at 12:42:24AM -0600, Samuel Holland wrote:
The naming convention for AIFs in this codec is to call the "DAC" the path from the AIF into the codec, and the ADC the path from the codec back to the AIF, regardless of if there is any analog path involved.
This renames widgets but does not update any DAPM routes from those widgets which will break things if this patch is applied.
Cc: stable@kernel.org
Why is this suitable for stable? It's a random textual cleanup.
On 2/17/20 9:09 AM, Mark Brown wrote:
On Mon, Feb 17, 2020 at 12:42:24AM -0600, Samuel Holland wrote:
The naming convention for AIFs in this codec is to call the "DAC" the path from the AIF into the codec, and the ADC the path from the codec back to the AIF, regardless of if there is any analog path involved.
This renames widgets but does not update any DAPM routes from those widgets which will break things if this patch is applied.
This commit doesn't change the widget name, only the widget type. My commit message did not make that clear.
Cc: stable@kernel.org
Why is this suitable for stable? It's a random textual cleanup.
This was one of the first patches I wrote. Now that I understand DAPM better, I realize that it has no functional impact, and this shouldn't go to stable. (snd_soc_dapm_aif_in and snd_soc_dapm_aif_out are handled exactly the same, so fixing the widget type is, as you say, just a textual cleanup.)
The A33/A64 digital codec has 4 physical inputs and 4 physical outputs: 3 AIFs (DAIs) and one ADC/DAC pair. Every input and output has a volume control for each channel in that connection. Furthermore, every input and output has a mono/stereo mux of some sort. Internal routing is accomplished by a 4-channel mixer connected to each output.
This commit provides the minimal necessary changes to the driver's device tree ABI, so that the driver can begin to describe the full hardware topology.
Currently the driver works mostly by accident. The DAPM routes currently in the various device trees specify the AIF1 widgets, not the ADC or DAC widgets they should have.
For Playback, the correct topology is:
(CPU) -> AIF1 DA0 -> DAC Mixer -> DAC (digital) -> DAC (analog)
but the driver and device trees currently describe:
(CPU) -> AIF1 DA0 -> DAC (analog) --> DAC Mixer -> ???
For Capture, the situation is worse, because the Mixer route is backward. The topology should be:
ADC (analog) -> ADC (digital) -> AIF1 AD0 Mixer -> AIF1 AD0 -> (CPU)
but the driver and device trees currently describe:
ADC (analog) -> AIF1 AD0 -> (CPU) --> ADC Mixer -> ???
The reason that DAPM powers on the ADC/DAC at all is the supply routes that make AIF1 AD0 depend on the ADC running, and AIF1 DA0 depend on the DAC running. However, neither of these supplies are correct based on the hardware topology: there is a route directly from the ADC to the DAC, controlled by the "ADC Digital DAC Playback Switch". It doesn't work (and wouldn't work if a route was added in the device tree), because AIF1 isn't used in the route:
ADC (analog) -> ADC (dig) -> DAC Mixer -> DAC (dig) -> DAC (analog)
so neither the ADC nor the DAC are powered up. Similarly, there are routes between AIF2/3 and the ADC/DAC (and each other) that should work without involving AIF1.
DAPM needs to represent the real hardware topology so the driver can be extended to support AIF2 and AIF3 and the other codec features. To do this, new ADC and DAC widgets are added. Only the minimal necessary routes for AIF1 -> DAC playback and ADC -> AIF1 capture are included, to keep this commit easier to backport.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Fixes: 9ee325d029c4 ("ASoC: sun8i-codec: add missing route for ADC") Signed-off-by: Samuel Holland samuel@sholland.org --- arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 6 ++-- arch/arm/boot/dts/sun8i-a33.dtsi | 6 ++-- .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 8 ++--- .../dts/allwinner/sun50i-a64-orangepi-win.dts | 8 ++--- .../boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++--- .../dts/allwinner/sun50i-a64-pinebook.dts | 8 ++--- .../boot/dts/allwinner/sun50i-a64-pinetab.dts | 14 ++++---- .../allwinner/sun50i-a64-sopine-baseboard.dts | 8 ++--- .../boot/dts/allwinner/sun50i-a64-teres-i.dts | 8 ++--- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++--- sound/soc/sunxi/sun8i-codec.c | 34 +++++++++++++++---- 11 files changed, 71 insertions(+), 45 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts index 3d78169cdeed..306f141772ff 100644 --- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts @@ -194,10 +194,12 @@ &sound { "Headphone", "Headphone Jack"; /* Board level routing. First 2 routes copied from SoC level */ simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", "HP", "HPCOM", "Headphone Jack", "HP", + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC", "MIC1", "Microphone Jack", "Microphone Jack", "MBIAS"; status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 1532a0e59af4..40b903fa73da 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -189,8 +189,10 @@ sound: sound { simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right"; + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC"; status = "disabled";
simple-audio-card,cpu { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 208373efee49..8645b1d2facb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -353,11 +353,11 @@ &sound { "Microphone", "Microphone Jack", "Microphone", "Onboard Microphone"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", "Headphone Jack", "HP", + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC", "MIC2", "Microphone Jack", "Onboard Microphone", "MBIAS", "MIC1", "Onboard Microphone"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index f54a415f2e3b..027aa55625af 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -352,11 +352,11 @@ &sound { "Microphone", "Microphone Jack", "Microphone", "Onboard Microphone"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", "Headphone Jack", "HP", + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC", "MIC2", "Microphone Jack", "Onboard Microphone", "MBIAS", "MIC1", "Onboard Microphone"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 409523cb0950..749c864b88ae 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -283,11 +283,11 @@ &sound { simple-audio-card,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC", "MIC2", "Microphone Jack"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 78c82a665c84..07f5b86906ed 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -319,15 +319,15 @@ &sound { "Headphone", "Headphone Jack", "Speaker", "Internal Speaker"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", "Speaker Amp INL", "LINEOUT", "Speaker Amp INR", "LINEOUT", "Internal Speaker", "Speaker Amp OUTL", "Internal Speaker", "Speaker Amp OUTR", "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC", "Internal Microphone Left", "MBIAS", "MIC1", "Internal Microphone Left", "Internal Microphone Right", "HBIAS", diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts index 316e8a443913..463b998b3f24 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -421,15 +421,15 @@ &sound { "Headphone", "Headphone Jack", "Speaker", "Internal Speaker"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "Speaker Amp INL", "LINEOUT", - "Speaker Amp INR", "LINEOUT", + "Headphone Jack", "HP", "Internal Speaker", "Speaker Amp OUTL", "Internal Speaker", "Speaker Amp OUTR", - "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "Speaker Amp INL", "LINEOUT", + "Speaker Amp INR", "LINEOUT", + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC", "Internal Microphone Left", "MBIAS", "MIC1", "Internal Microphone Left", "Internal Microphone Right", "HBIAS", diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 920103ec0046..22c937b848d3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -199,11 +199,11 @@ &sound { simple-audio-card,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", "Headphone Jack", "HP", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC", "MIC2", "Microphone Jack"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index 970415106dcf..812fb47b833b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -326,15 +326,15 @@ &sound { "Microphone", "Internal Microphone", "Speaker", "Internal Speaker"; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC", "Headphone Jack", "HP", "Speaker Amp INL", "LINEOUT", "Speaker Amp INR", "LINEOUT", "Internal Speaker", "Speaker Amp OUTL", "Internal Speaker", "Speaker Amp OUTR", + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC", "Internal Microphone", "MBIAS", "MIC1", "Internal Microphone", "Headset Microphone", "HBIAS", diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 6d7aa1736d21..5b688687a2b2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -165,10 +165,10 @@ sound: sound { simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", - "AIF1 Slot 0 Left ADC", "Left ADC", - "AIF1 Slot 0 Right ADC", "Right ADC"; + "Left DAC", "DAC Left", + "Right DAC", "DAC Right", + "ADC Left", "Left ADC", + "ADC Right", "Right ADC"; status = "disabled";
cpudai: simple-audio-card,cpu { diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 83c812742cc1..dca6f4b9d4b8 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -406,6 +406,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0),
+ /* Main DAC Outputs (connected to analog codec DAPM context) */ + SND_SOC_DAPM_PGA("DAC Left", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("DAC Right", SND_SOC_NOPM, 0, 0, NULL, 0), + /* DAC and ADC Mixers */ SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), @@ -416,6 +420,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0, sun8i_input_mixer_controls),
+ /* Main ADC Inputs (connected to analog codec DAPM context) */ + SND_SOC_DAPM_PGA("ADC Left", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("ADC Right", SND_SOC_NOPM, 0, 0, NULL, 0), + /* Clocks */ SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), @@ -460,9 +468,23 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "MODCLK ADC", NULL, "RST ADC" }, { "ADC", NULL, "MODCLK ADC" },
+ /* AIF "ADC" Output Routes */ + { "AIF1 Slot 0 Left ADC", NULL, "Left Digital ADC Mixer" }, + { "AIF1 Slot 0 Right ADC", NULL, "Right Digital ADC Mixer" }, + + { "AIF1 Slot 0 Left ADC", NULL, "MODCLK AIF1" }, + { "AIF1 Slot 0 Right ADC", NULL, "MODCLK AIF1" }, + + /* AIF "DAC" Input Routes */ + { "AIF1 Slot 0 Left", NULL, "MODCLK AIF1" }, + { "AIF1 Slot 0 Right", NULL, "MODCLK AIF1" }, + /* DAC Routes */ - { "AIF1 Slot 0 Right", NULL, "DAC" }, - { "AIF1 Slot 0 Left", NULL, "DAC" }, + { "DAC Left", NULL, "Left Digital DAC Mixer" }, + { "DAC Right", NULL, "Right Digital DAC Mixer" }, + + { "DAC Left", NULL, "DAC" }, + { "DAC Right", NULL, "DAC" },
/* DAC Mixer Routes */ { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", @@ -471,14 +493,14 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { "AIF1 Slot 0 Right"},
/* ADC Routes */ - { "AIF1 Slot 0 Right ADC", NULL, "ADC" }, - { "AIF1 Slot 0 Left ADC", NULL, "ADC" }, + { "ADC Left", NULL, "ADC" }, + { "ADC Right", NULL, "ADC" },
/* ADC Mixer Routes */ { "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", - "AIF1 Slot 0 Left ADC" }, + "ADC Left" }, { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", - "AIF1 Slot 0 Right ADC" }, + "ADC Right" }, };
static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
On Mon, Feb 17, 2020 at 12:42:25AM -0600, Samuel Holland wrote:
This commit provides the minimal necessary changes to the driver's device tree ABI, so that the driver can begin to describe the full hardware topology.
Cc: stable@kernel.org
You're changing the ABI and trying to CC this to stable. This is obviously not at all OK, this would mean that if someone got a stable update with this change the ABI break would mean that their existing device tree would not work. The code should be making every effort to provide a stable ABI over new kernel releases, never mind within a stable point release.
The hardware does not support 64kHz, 88.2kHz, or 176.4kHz sample rates, so the driver should not advertise them. The hardware can handle two additional non-standard sample rates: 12kHz and 24kHz, so declare support for them via SNDRV_PCM_RATE_KNOT.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index dca6f4b9d4b8..bf12f5199e96 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -86,6 +86,11 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
+#define SUN8I_AIF_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ + SNDRV_PCM_RATE_96000|\ + SNDRV_PCM_RATE_192000|\ + SNDRV_PCM_RATE_KNOT) + struct sun8i_codec { struct regmap *regmap; struct clk *clk_module; @@ -515,7 +520,7 @@ static struct snd_soc_dai_driver sun8i_codec_dai = { .stream_name = "Playback", .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, + .rates = SUN8I_AIF_PCM_RATES, .formats = SNDRV_PCM_FMTBIT_S16_LE, }, /* capture capabilities */ @@ -523,7 +528,7 @@ static struct snd_soc_dai_driver sun8i_codec_dai = { .stream_name = "Capture", .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, + .rates = SUN8I_AIF_PCM_RATES, .formats = SNDRV_PCM_FMTBIT_S16_LE, .sig_bits = 24, },
On Mon, Feb 17, 2020 at 12:42:26AM -0600, Samuel Holland wrote:
The hardware does not support 64kHz, 88.2kHz, or 176.4kHz sample rates, so the driver should not advertise them. The hardware can handle two additional non-standard sample rates: 12kHz and 24kHz, so declare support for them via SNDRV_PCM_RATE_KNOT.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org
The new sample rates are new functionality, they are definitely not stable material. For the sample rates you are removing do we understand why they were added - do they work for people, are they perhaps supported for some users and not others for example?
On 2/17/20 9:30 AM, Mark Brown wrote:
On Mon, Feb 17, 2020 at 12:42:26AM -0600, Samuel Holland wrote:
The hardware does not support 64kHz, 88.2kHz, or 176.4kHz sample rates, so the driver should not advertise them. The hardware can handle two additional non-standard sample rates: 12kHz and 24kHz, so declare support for them via SNDRV_PCM_RATE_KNOT.
Cc: stable@kernel.org Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org
The new sample rates are new functionality, they are definitely not stable material. For the sample rates you are removing do we understand why they were added - do they work for people, are they perhaps supported for some users and not others for example?
I do not know why they were added, but the sample rates I removed do not work today, for anyone.
The sample rate must be programmed into the hardware, and the removed sample rates do not map to one of the possible register values, so sun8i_codec_get_hw_rate(), and thus hw_params, will return -EINVAL if one of them is used.
Each of the codec's DAIs has a single set of parameters for its clock, channels, and word size. If both capture and playback are active on a single DAI, they must use compatible parameters. Set the symmetric_* flags in the DAI driver to enforce this.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index bf12f5199e96..3d5ed2f4575a 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -534,6 +534,9 @@ static struct snd_soc_dai_driver sun8i_codec_dai = { }, /* pcm operations */ .ops = &sun8i_codec_dai_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, };
static const struct snd_soc_component_driver sun8i_soc_component = {
It should be "AIF1", not "AFI1".
Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 3d5ed2f4575a..03cfe4e17ff7 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -430,7 +430,7 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_PGA("ADC Right", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Clocks */ - SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA, + SND_SOC_DAPM_SUPPLY("MODCLK AIF1", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), @@ -461,9 +461,9 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF1", NULL, "SYSCLK AIF1" }, { "AIF1 PLL", NULL, "AIF1" }, { "RST AIF1", NULL, "AIF1 PLL" }, - { "MODCLK AFI1", NULL, "RST AIF1" }, - { "DAC", NULL, "MODCLK AFI1" }, - { "ADC", NULL, "MODCLK AFI1" }, + { "MODCLK AIF1", NULL, "RST AIF1" }, + { "DAC", NULL, "MODCLK AIF1" }, + { "ADC", NULL, "MODCLK AIF1" },
{ "RST DAC", NULL, "SYSCLK" }, { "MODCLK DAC", NULL, "RST DAC" },
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
It should be "AIF1", not "AFI1".
Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
They are controlling "AD0" (AIF1 slot 0), not "DA0".
Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 03cfe4e17ff7..8b08cb34c503 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -49,8 +49,8 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 -#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA 15 -#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA 14 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 #define SUN8I_AIF1_DACDAT_CTRL 0x048 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 @@ -406,10 +406,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* Analog ADC AIF */ SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Left ADC", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0), + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Right ADC", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0), + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),
/* Main DAC Outputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_PGA("DAC Left", SND_SOC_NOPM, 0, 0, NULL, 0),
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
They are controlling "AD0" (AIF1 slot 0), not "DA0".
Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
Even though they are for the left channel mixer, they are documented as "MXR_SRC". This matches the naming scheme used for the main DAC.
Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 8b08cb34c503..6c2fe8549668 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -55,10 +55,10 @@ #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 #define SUN8I_AIF1_MXR_SRC 0x04c -#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L 15 -#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL 14 -#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL 13 -#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR 12 +#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 +#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 +#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL 13 +#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR 12 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 @@ -373,18 +373,18 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, - SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR, + SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), };
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
Even though they are for the left channel mixer, they are documented as "MXR_SRC". This matches the naming scheme used for the main DAC.
Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
This is the enable bit for the "AD"C, no the "DA"C.
Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 6c2fe8549668..0063fa301fab 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -64,7 +64,7 @@ #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8 #define SUN8I_ADC_DIG_CTRL 0x100 -#define SUN8I_ADC_DIG_CTRL_ENDA 15 +#define SUN8I_ADC_DIG_CTRL_ENAD 15 #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 #define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1 #define SUN8I_DAC_DIG_CTRL 0x120 @@ -392,7 +392,7 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* Digital parts of the DACs and ADC */ SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENDA, + SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0),
/* Analog DAC AIF */
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
This is the enable bit for the "AD"C, no the "DA"C.
Fixes: eda85d1fee05 ("ASoC: sun8i-codec: Add ADC support for a33") Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
Several fields have inconsistent indentation, presumably because it "looked correct" in the patch due to the additional character at the beginning of the line.
Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 0063fa301fab..559dec719956 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -68,15 +68,15 @@ #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 #define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1 #define SUN8I_DAC_DIG_CTRL 0x120 -#define SUN8I_DAC_DIG_CTRL_ENDA 15 +#define SUN8I_DAC_DIG_CTRL_ENDA 15 #define SUN8I_DAC_MXR_SRC 0x130 -#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15 -#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14 -#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13 +#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15 +#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14 +#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12 -#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11 -#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10 -#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 +#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11 +#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10 +#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
Several fields have inconsistent indentation, presumably because it "looked correct" in the patch due to the additional character at the beginning of the line.
Fixes: 36c684936fae ("ASoC: Add sun8i digital audio codec") Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
All other definitions are sorted from largest to smallest bit number. This makes the AIF1CLK_CTRL mask constants consistent with them.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 559dec719956..36ce281286b5 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -81,10 +81,10 @@
#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) +#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) +#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) +#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)
#define SUN8I_AIF_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ SNDRV_PCM_RATE_96000|\
On Mon, Feb 17, 2020 at 2:43 PM Samuel Holland samuel@sholland.org wrote:
All other definitions are sorted from largest to smallest bit number. This makes the AIF1CLK_CTRL mask constants consistent with them.
Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Chen-Yu Tsai wens@csie.org
Since the hardware has separate bits for BCLK and LRCK inversion, we can support any combination of normal and inverted clocks.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 36ce281286b5..f8cde149a92b 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -41,8 +41,7 @@ #define SUN8I_SYS_SR_CTRL_AIF2_FS 8 #define SUN8I_AIF1CLK_CTRL 0x040 #define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14 -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13 +#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13 #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 @@ -81,6 +80,7 @@
#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) +#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) @@ -205,16 +205,18 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) case SND_SOC_DAIFMT_NB_NF: /* Normal */ value = 0x0; break; - case SND_SOC_DAIFMT_IB_IF: /* Inversion */ + case SND_SOC_DAIFMT_NB_IF: /* Inverted LRCK */ value = 0x1; break; + case SND_SOC_DAIFMT_IB_NF: /* Inverted BCLK */ + value = 0x2; + break; + case SND_SOC_DAIFMT_IB_IF: /* Both inverted */ + value = 0x3; + break; default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV), - value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV); - /* * It appears that the DAI and the codec in the A33 SoC don't * share the same polarity for the LRCK signal when they mean @@ -227,8 +229,8 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) */ value ^= scodec->inverted_lrck; regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV), - value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV); + SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK, + value << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV);
/* DAI format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Calculate the correct clock rate for a mono configuration.
The AIFs have a bit that must be set for mono input/output. Set the bit when the number of channels is 1.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index f8cde149a92b..2df899daec67 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -47,6 +47,7 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 +#define SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM 1 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 @@ -280,10 +281,11 @@ static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = {
static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec, unsigned int rate, + unsigned int channels, unsigned int word_size) { unsigned long clk_rate = clk_get_rate(scodec->clk_module); - unsigned int div = clk_rate / rate / word_size / 2; + unsigned int div = clk_rate / rate / word_size / channels; unsigned int best_val = 0, best_diff = ~0; int i;
@@ -316,8 +318,10 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + unsigned int channels = params_channels(params); int sample_rate, lrck_div; u8 bclk_div; + u32 value;
/* * The CPU DAI handles only a sample of 16 bits. Configure the @@ -327,12 +331,13 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);
- bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16); + bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), + channels, 16); regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
- lrck_div = sun8i_codec_get_lrck_div(params_channels(params), + lrck_div = sun8i_codec_get_lrck_div(channels, params_physical_width(params)); if (lrck_div < 0) return lrck_div; @@ -341,6 +346,11 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);
+ value = channels == 1; + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, + BIT(SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM), + value << SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM); + sample_rate = sun8i_codec_get_hw_rate(params); if (sample_rate < 0) return sample_rate;
The codec hardware natively supports 8, 16, 20, and 24-bit word sizes. However, it only supports slot widths that are a multiple of 16 bits. So we can only support the 20-bit and 24-bit formats that are padded to 32 bits. This doesn't cost anything, because the DMA controller on the CPU side only supports power-of-two byte sizes anyway.
S8, S16_LE, and S24_LE were tested using a modified version of the sun4i-i2s driver as the CPU end of the DAI link. S20_LE was not tested due to poor userspace support; it should work the same.
In 8 bit mono mode, the computed BCLK/LRCK divider will be less than the minimum value 16. This is fine; there will just be padding after the data bits, similar to how S20_LE and S24_LE always have padding.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 47 ++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 15 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 2df899daec67..b915e62fa005 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -45,7 +45,6 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 #define SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM 1 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 @@ -87,6 +86,10 @@ #define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)
+#define SUN8I_AIF_PCM_FMTS (SNDRV_PCM_FMTBIT_S8|\ + SNDRV_PCM_FMTBIT_S16_LE|\ + SNDRV_PCM_FMTBIT_S20_LE|\ + SNDRV_PCM_FMTBIT_S24_LE) #define SUN8I_AIF_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ SNDRV_PCM_RATE_96000|\ SNDRV_PCM_RATE_192000|\ @@ -307,7 +310,9 @@ static int sun8i_codec_get_lrck_div(unsigned int channels, { unsigned int div = word_size * channels;
- if (div < 16 || div > 256) + if (div < 16) + div = 16; + if (div > 256) return -EINVAL;
return ilog2(div) - 4; @@ -318,27 +323,19 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + unsigned int slot_width = params_physical_width(params); unsigned int channels = params_channels(params); int sample_rate, lrck_div; u8 bclk_div; u32 value;
- /* - * The CPU DAI handles only a sample of 16 bits. Configure the - * codec to handle this type of sample resolution. - */ - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, - SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16); - bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), - channels, 16); + channels, slot_width); regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
- lrck_div = sun8i_codec_get_lrck_div(channels, - params_physical_width(params)); + lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); if (lrck_div < 0) return lrck_div;
@@ -346,6 +343,26 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);
+ switch (params_width(params)) { + case 8: + value = 0x0; + break; + case 16: + value = 0x1; + break; + case 20: + value = 0x2; + break; + case 24: + value = 0x3; + break; + default: + return -EINVAL; + } + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, + SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, + value << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ); + value = channels == 1; regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, BIT(SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM), @@ -533,7 +550,7 @@ static struct snd_soc_dai_driver sun8i_codec_dai = { .channels_min = 1, .channels_max = 2, .rates = SUN8I_AIF_PCM_RATES, - .formats = SNDRV_PCM_FMTBIT_S16_LE, + .formats = SUN8I_AIF_PCM_FMTS, }, /* capture capabilities */ .capture = { @@ -541,7 +558,7 @@ static struct snd_soc_dai_driver sun8i_codec_dai = { .channels_min = 1, .channels_max = 2, .rates = SUN8I_AIF_PCM_RATES, - .formats = SNDRV_PCM_FMTBIT_S16_LE, + .formats = SUN8I_AIF_PCM_FMTS, .sig_bits = 24, }, /* pcm operations */
The clock hieriarchy in the codec is:
MCLK/PLL MCLK/PLL | | AIF1CLK AIF2CLK | \ / | | SYSCLK | | || | | MODCLK *** | | || | | RST **** | | / / \ \ | AIF1 ADC DAC AIF2
Currently, this driver makes some design decisions: - AIF1CLK/AIF2CLK should always have the PLL as their parent. MCLK may not be running, and it has the same PLL as its parent anyway. - SYSCLK should always have AIF1CLK as its parent. There is no easy way for DAPM to automatically switch clock parents based on which AIFs are in use, and AIF1 is most likely to be used. Even in the case where only AIF2 is used, the extra power consumption by also running AIF1CLK should be minimal.
This commit updates the driver to match the hardware clock hierarchy: - Since the clock parent decisions are static, they are configured once in the component's probe function. They do not need DAPM widgets. - ADC/DAC supplies are moved immediately after the widgets they supply. - Module resets are moved before module clocks to maintain topological ordering (and they are sorted by bit order within the register). - AIF1 module is supplied by both SYSCLK (via MODCLK AIF1) and AIF1CLK. - ADC/DAC modules are supplied by SYSCLK only, not MODCLK AIF1. - SYSCLK is supplied by AIF1CLK.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 114 ++++++++++++++++++++-------------- 1 file changed, 68 insertions(+), 46 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index b915e62fa005..0561d8d2e941 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -24,10 +24,11 @@
#define SUN8I_SYSCLK_CTL 0x00c #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 -#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL 9 -#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC 8 +#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL (0x3 << 8) #define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0 +#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK (0x0 << 0) +#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF2CLK (0x1 << 0) #define SUN8I_MOD_CLK_ENA 0x010 #define SUN8I_MOD_CLK_ENA_AIF1 15 #define SUN8I_MOD_CLK_ENA_ADC 3 @@ -78,6 +79,7 @@ #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
+#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) #define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) @@ -418,12 +420,6 @@ static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = { };
static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { - /* Digital parts of the DACs and ADC */ - SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, - 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, - 0, NULL, 0), - /* Analog DAC AIF */ SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0, SUN8I_AIF1_DACDAT_CTRL, @@ -444,6 +440,9 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_PGA("DAC Left", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("DAC Right", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, + SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0), + /* DAC and ADC Mixers */ SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), @@ -458,60 +457,43 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_PGA("ADC Left", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("ADC Right", SND_SOC_NOPM, 0, 0, NULL, 0),
- /* Clocks */ + SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, + SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0), + + /* Module Resets */ + SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), + + /* Module Clocks */ SND_SOC_DAPM_SUPPLY("MODCLK AIF1", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, - SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL, + SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), + + /* Clock Supplies */ + SND_SOC_DAPM_SUPPLY("AIF1CLK", SUN8I_SYSCLK_CTL, SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL, SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), - - SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0), - /* Inversion as 0=AIF1, 1=AIF2 */ - SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0), - - /* Module reset */ - SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL, - SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, - SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, - SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), };
static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { - /* Clock Routes */ - { "AIF1", NULL, "SYSCLK AIF1" }, - { "AIF1 PLL", NULL, "AIF1" }, - { "RST AIF1", NULL, "AIF1 PLL" }, - { "MODCLK AIF1", NULL, "RST AIF1" }, - { "DAC", NULL, "MODCLK AIF1" }, - { "ADC", NULL, "MODCLK AIF1" }, - - { "RST DAC", NULL, "SYSCLK" }, - { "MODCLK DAC", NULL, "RST DAC" }, - { "DAC", NULL, "MODCLK DAC" }, - - { "RST ADC", NULL, "SYSCLK" }, - { "MODCLK ADC", NULL, "RST ADC" }, - { "ADC", NULL, "MODCLK ADC" }, - /* AIF "ADC" Output Routes */ { "AIF1 Slot 0 Left ADC", NULL, "Left Digital ADC Mixer" }, { "AIF1 Slot 0 Right ADC", NULL, "Right Digital ADC Mixer" },
- { "AIF1 Slot 0 Left ADC", NULL, "MODCLK AIF1" }, - { "AIF1 Slot 0 Right ADC", NULL, "MODCLK AIF1" }, + { "AIF1 Slot 0 Left ADC", NULL, "AIF1CLK" }, + { "AIF1 Slot 0 Right ADC", NULL, "AIF1CLK" },
/* AIF "DAC" Input Routes */ - { "AIF1 Slot 0 Left", NULL, "MODCLK AIF1" }, - { "AIF1 Slot 0 Right", NULL, "MODCLK AIF1" }, + { "AIF1 Slot 0 Left", NULL, "AIF1CLK" }, + { "AIF1 Slot 0 Right", NULL, "AIF1CLK" },
/* DAC Routes */ { "DAC Left", NULL, "Left Digital DAC Mixer" }, @@ -535,8 +517,47 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { "ADC Left" }, { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADC Right" }, + + /* Module Supply Routes */ + { "AIF1 Slot 0 Left ADC", NULL, "RST AIF1" }, + { "AIF1 Slot 0 Right ADC", NULL, "RST AIF1" }, + { "AIF1 Slot 0 Left", NULL, "RST AIF1" }, + { "AIF1 Slot 0 Right", NULL, "RST AIF1" }, + + { "ADC", NULL, "RST ADC" }, + { "DAC", NULL, "RST DAC" }, + + /* Module Reset Routes */ + { "RST AIF1", NULL, "MODCLK AIF1" }, + { "RST ADC", NULL, "MODCLK ADC" }, + { "RST DAC", NULL, "MODCLK DAC" }, + + /* Module Clock Routes */ + { "MODCLK AIF1", NULL, "SYSCLK" }, + { "MODCLK ADC", NULL, "SYSCLK" }, + { "MODCLK DAC", NULL, "SYSCLK" }, + + /* Clock Supply Routes */ + { "SYSCLK", NULL, "AIF1CLK" }, };
+static int sun8i_codec_component_probe(struct snd_soc_component *component) +{ + struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); + + /* Set AIF1CLK clock source to PLL */ + regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, + SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK, + SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL); + + /* Set SYSCLK clock source to AIF1CLK */ + regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, + BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC), + SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK); + + return 0; +} + static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { .hw_params = sun8i_codec_hw_params, .set_fmt = sun8i_set_fmt, @@ -573,6 +594,7 @@ static const struct snd_soc_component_driver sun8i_soc_component = { .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), .dapm_routes = sun8i_codec_dapm_routes, .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes), + .probe = sun8i_codec_component_probe, .idle_bias_on = 1, .use_pmdown_time = 1, .endianness = 1,
The driver currently confuses AIF1 AD0 with the ADC. They are independent. The ADC can be used without AIF1, and AIF1 AD0 can pull audio from other sources, such as AIF1 DA0 and AIF2. There is no mixer associated with the main ADC; the mixers are associated with an output, in this case AIF1 AD0.
This commit renames the AIF1 Slot 0 widgets and routes to match their actual usage, and sorts them in a topological sink<-source ordering.
Because each of the inputs is sent to multiple mixers, the controls must be renamed to include both the input name and the mixer name.
It also sets the correct channel for the AIF inputs/outputs, so that the minimal number of DAPM widgets are turned on for mono routing.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 80 ++++++++++++++++++----------------- 1 file changed, 42 insertions(+), 38 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 0561d8d2e941..6f589e93850a 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -401,41 +401,48 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), };
-static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = { - SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", +static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { + SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF1 DA0 Capture Switch", SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), - SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, + SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF2 DAC Capture Switch", + SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), - SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", + SOC_DAPM_DOUBLE("AIF1 AD0 Mixer ADC Capture Switch", SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), - SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", + SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), };
static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { - /* Analog DAC AIF */ - SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0, - SUN8I_AIF1_DACDAT_CTRL, - SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0, - SUN8I_AIF1_DACDAT_CTRL, - SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), - - /* Analog ADC AIF */ - SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Left ADC", "Capture", 0, + /* AIF "ADC" Outputs */ + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), - SND_SOC_DAPM_AIF_OUT("AIF1 Slot 0 Right ADC", "Capture", 0, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Right", "Capture", 1, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),
+ /* AIF "ADC" Mixers */ + SOC_MIXER_ARRAY("AIF1 AD0 Left Mixer", SND_SOC_NOPM, 0, 0, + sun8i_aif1_ad0_mixer_controls), + SOC_MIXER_ARRAY("AIF1 AD0 Right Mixer", SND_SOC_NOPM, 0, 0, + sun8i_aif1_ad0_mixer_controls), + + /* AIF "DAC" Inputs */ + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "Playback", 0, + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Right", "Playback", 1, + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), + /* Main DAC Outputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_PGA("DAC Left", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("DAC Right", SND_SOC_NOPM, 0, 0, NULL, 0), @@ -448,10 +455,6 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { sun8i_dac_mixer_controls), SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), - SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0, - sun8i_input_mixer_controls), - SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0, - sun8i_input_mixer_controls),
/* Main ADC Inputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_PGA("ADC Left", SND_SOC_NOPM, 0, 0, NULL, 0), @@ -485,15 +488,22 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { /* AIF "ADC" Output Routes */ - { "AIF1 Slot 0 Left ADC", NULL, "Left Digital ADC Mixer" }, - { "AIF1 Slot 0 Right ADC", NULL, "Right Digital ADC Mixer" }, + { "AIF1 AD0 Left", NULL, "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Right", NULL, "AIF1 AD0 Right Mixer" },
- { "AIF1 Slot 0 Left ADC", NULL, "AIF1CLK" }, - { "AIF1 Slot 0 Right ADC", NULL, "AIF1CLK" }, + { "AIF1 AD0 Left", NULL, "AIF1CLK" }, + { "AIF1 AD0 Right", NULL, "AIF1CLK" }, + + /* AIF "ADC" Mixer Routes */ + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Left" }, + + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Right" },
/* AIF "DAC" Input Routes */ - { "AIF1 Slot 0 Left", NULL, "AIF1CLK" }, - { "AIF1 Slot 0 Right", NULL, "AIF1CLK" }, + { "AIF1 DA0 Left", NULL, "AIF1CLK" }, + { "AIF1 DA0 Right", NULL, "AIF1CLK" },
/* DAC Routes */ { "DAC Left", NULL, "Left Digital DAC Mixer" }, @@ -504,25 +514,19 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
/* DAC Mixer Routes */ { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", - "AIF1 Slot 0 Left"}, + "AIF1 DA0 Left"}, { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", - "AIF1 Slot 0 Right"}, + "AIF1 DA0 Right"},
/* ADC Routes */ { "ADC Left", NULL, "ADC" }, { "ADC Right", NULL, "ADC" },
- /* ADC Mixer Routes */ - { "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", - "ADC Left" }, - { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", - "ADC Right" }, - /* Module Supply Routes */ - { "AIF1 Slot 0 Left ADC", NULL, "RST AIF1" }, - { "AIF1 Slot 0 Right ADC", NULL, "RST AIF1" }, - { "AIF1 Slot 0 Left", NULL, "RST AIF1" }, - { "AIF1 Slot 0 Right", NULL, "RST AIF1" }, + { "AIF1 AD0 Left", NULL, "RST AIF1" }, + { "AIF1 AD0 Right", NULL, "RST AIF1" }, + { "AIF1 DA0 Left", NULL, "RST AIF1" }, + { "AIF1 DA0 Right", NULL, "RST AIF1" },
{ "ADC", NULL, "RST ADC" }, { "DAC", NULL, "RST DAC" },
Again, rename the widgets and controls to match their actual function (and disambiguate the mixers), then sort the widgets and routes in a topological sink<-source ordering.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 61 ++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 29 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 6f589e93850a..5dfaf656b5b1 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -384,23 +384,6 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, return 0; }
-static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { - SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", - SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), - SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", - SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), - SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), - SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), -}; - static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF1 DA0 Capture Switch", SUN8I_AIF1_MXR_SRC, @@ -420,6 +403,25 @@ static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), };
+static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { + SOC_DAPM_DOUBLE("DAC Mixer AIF1 DA0 Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), + SOC_DAPM_DOUBLE("DAC Mixer AIF1 DA1 Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), + SOC_DAPM_DOUBLE("DAC Mixer AIF2 DAC Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), + SOC_DAPM_DOUBLE("DAC Mixer ADC Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), +}; + static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* AIF "ADC" Outputs */ SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "Capture", 0, @@ -450,10 +452,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0),
- /* DAC and ADC Mixers */ - SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, + /* Main DAC Mixers */ + SOC_MIXER_ARRAY("DAC Left Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), - SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0, + SOC_MIXER_ARRAY("DAC Right Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls),
/* Main ADC Inputs (connected to analog codec DAPM context) */ @@ -505,20 +507,21 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF1 DA0 Left", NULL, "AIF1CLK" }, { "AIF1 DA0 Right", NULL, "AIF1CLK" },
- /* DAC Routes */ - { "DAC Left", NULL, "Left Digital DAC Mixer" }, - { "DAC Right", NULL, "Right Digital DAC Mixer" }, + /* Main DAC Output Routes */ + { "DAC Left", NULL, "DAC Left Mixer" }, + { "DAC Right", NULL, "DAC Right Mixer" },
{ "DAC Left", NULL, "DAC" }, { "DAC Right", NULL, "DAC" },
- /* DAC Mixer Routes */ - { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", - "AIF1 DA0 Left"}, - { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", - "AIF1 DA0 Right"}, + /* Main DAC Mixer Routes */ + { "DAC Left Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Left" }, + { "DAC Left Mixer", "DAC Mixer ADC Playback Switch", "ADC Left" }, + + { "DAC Right Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Right" }, + { "DAC Right Mixer", "DAC Mixer ADC Playback Switch", "ADC Right" },
- /* ADC Routes */ + /* Main ADC Input Routes */ { "ADC Left", NULL, "ADC" }, { "ADC Right", NULL, "ADC" },
The clock control registers for AIF1 and AIF2 have an identical layout (other than the unused bit 0 for TDM mode). Rename the offsets/masks to signify that they are shared between AIFs, and get the register address from the AIF ID (this requires filling in the AIF ID). We also need to rename the DAI and DAI streams, so they are still unique once AIF2 is added. Finally, we convert the AIF driver struct to an array. Since this already breaks `git blame`, we clean it up a bit by moving it and the DAI ops up near the DAI driver implementation; this stops the ASoC DAPM component driver splitting the DAI driver in half.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 159 +++++++++++++++++----------------- 1 file changed, 80 insertions(+), 79 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 5dfaf656b5b1..aaea9aaa5632 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -38,16 +38,15 @@ #define SUN8I_MOD_RST_CTL_ADC 3 #define SUN8I_MOD_RST_CTL_DAC 2 #define SUN8I_SYS_SR_CTRL 0x018 -#define SUN8I_SYS_SR_CTRL_AIF1_FS 12 -#define SUN8I_SYS_SR_CTRL_AIF2_FS 8 -#define SUN8I_AIF1CLK_CTRL 0x040 -#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15 -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13 -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9 -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6 -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 -#define SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM 1 +#define SUN8I_SYS_SR_CTRL_AIF_FS(n) (16 - 4 * (n)) +#define SUN8I_AIF_CLK_CTRL(n) (0x040 * (n)) +#define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15 +#define SUN8I_AIF_CLK_CTRL_CLK_INV 13 +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9 +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6 +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4 +#define SUN8I_AIF_CLK_CTRL_DATA_FMT 2 +#define SUN8I_AIF_CLK_CTRL_MONO_PCM 1 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 @@ -80,13 +79,12 @@ #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) -#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) -#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13) -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6) -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4) -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2) +#define SUN8I_SYS_SR_CTRL_AIF_FS_MASK(n) (GENMASK(19, 16) >> (4 * (n))) +#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13) +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9) +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6) +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4) +#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2)
#define SUN8I_AIF_PCM_FMTS (SNDRV_PCM_FMTBIT_S8|\ SNDRV_PCM_FMTBIT_S16_LE|\ @@ -189,6 +187,7 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); u32 value;
/* clock masters */ @@ -202,9 +201,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD), - value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD); + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), + value << SUN8I_AIF_CLK_CTRL_MSTR_MOD);
/* clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { @@ -234,9 +233,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) * invert the value here. */ value ^= scodec->inverted_lrck; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_CLK_INV_MASK, + value << SUN8I_AIF_CLK_CTRL_CLK_INV);
/* DAI format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -255,9 +254,9 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, + value << SUN8I_AIF_CLK_CTRL_DATA_FMT);
return 0; } @@ -327,23 +326,24 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); unsigned int slot_width = params_physical_width(params); unsigned int channels = params_channels(params); + unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); int sample_rate, lrck_div; u8 bclk_div; u32 value;
bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), channels, slot_width); - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, - bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, + bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV);
lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); if (lrck_div < 0) return lrck_div;
- regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, - lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, + lrck_div << SUN8I_AIF_CLK_CTRL_LRCK_DIV);
switch (params_width(params)) { case 8: @@ -361,29 +361,60 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, default: return -EINVAL; } - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, - value << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK, + value << SUN8I_AIF_CLK_CTRL_WORD_SIZ);
value = channels == 1; - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - BIT(SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM), - value << SUN8I_AIF1CLK_CTRL_AIF1_MONO_PCM); + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MONO_PCM), + value << SUN8I_AIF_CLK_CTRL_MONO_PCM);
sample_rate = sun8i_codec_get_hw_rate(params); if (sample_rate < 0) return sample_rate;
regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); - regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF2_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS); + SUN8I_SYS_SR_CTRL_AIF_FS_MASK(dai->id), + sample_rate << SUN8I_SYS_SR_CTRL_AIF_FS(dai->id));
return 0; }
+static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { + .hw_params = sun8i_codec_hw_params, + .set_fmt = sun8i_set_fmt, +}; + +static struct snd_soc_dai_driver sun8i_codec_dais[] = { + { + .name = "sun8i-codec-aif1", + .id = 1, + /* playback capabilities */ + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + }, + /* capture capabilities */ + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + .sig_bits = 24, + }, + /* pcm operations */ + .ops = &sun8i_codec_dai_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, +}; + static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF1 DA0 Capture Switch", SUN8I_AIF1_MXR_SRC, @@ -424,10 +455,10 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* AIF "ADC" Outputs */ - SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "Capture", 0, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "AIF1 Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), - SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Right", "Capture", 1, + SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Right", "AIF1 Capture", 1, SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),
@@ -438,10 +469,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { sun8i_aif1_ad0_mixer_controls),
/* AIF "DAC" Inputs */ - SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "Playback", 0, + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 DA0 Right", "Playback", 1, + SND_SOC_DAPM_AIF_IN("AIF1 DA0 Right", "AIF1 Playback", 1, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
@@ -565,37 +596,6 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) return 0; }
-static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { - .hw_params = sun8i_codec_hw_params, - .set_fmt = sun8i_set_fmt, -}; - -static struct snd_soc_dai_driver sun8i_codec_dai = { - .name = "sun8i", - /* playback capabilities */ - .playback = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = 2, - .rates = SUN8I_AIF_PCM_RATES, - .formats = SUN8I_AIF_PCM_FMTS, - }, - /* capture capabilities */ - .capture = { - .stream_name = "Capture", - .channels_min = 1, - .channels_max = 2, - .rates = SUN8I_AIF_PCM_RATES, - .formats = SUN8I_AIF_PCM_FMTS, - .sig_bits = 24, - }, - /* pcm operations */ - .ops = &sun8i_codec_dai_ops, - .symmetric_rates = 1, - .symmetric_channels = 1, - .symmetric_samplebits = 1, -}; - static const struct snd_soc_component_driver sun8i_soc_component = { .dapm_widgets = sun8i_codec_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), @@ -664,7 +664,8 @@ static int sun8i_codec_probe(struct platform_device *pdev) }
ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component, - &sun8i_codec_dai, 1); + sun8i_codec_dais, + ARRAY_SIZE(sun8i_codec_dais)); if (ret) { dev_err(&pdev->dev, "Failed to register codec\n"); goto err_suspend;
This adds the new DAI, clocks, widgets, and routes for AIF2.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 125 ++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index aaea9aaa5632..ce7038bcbdc1 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -25,16 +25,20 @@ #define SUN8I_SYSCLK_CTL 0x00c #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL (0x3 << 8) +#define SUN8I_SYSCLK_CTL_AIF2CLK_ENA 7 +#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL (0x3 << 4) #define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK (0x0 << 0) #define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF2CLK (0x1 << 0) #define SUN8I_MOD_CLK_ENA 0x010 #define SUN8I_MOD_CLK_ENA_AIF1 15 +#define SUN8I_MOD_CLK_ENA_AIF2 14 #define SUN8I_MOD_CLK_ENA_ADC 3 #define SUN8I_MOD_CLK_ENA_DAC 2 #define SUN8I_MOD_RST_CTL 0x014 #define SUN8I_MOD_RST_CTL_AIF1 15 +#define SUN8I_MOD_RST_CTL_AIF2 14 #define SUN8I_MOD_RST_CTL_ADC 3 #define SUN8I_MOD_RST_CTL_DAC 2 #define SUN8I_SYS_SR_CTRL 0x018 @@ -62,6 +66,21 @@ #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8 +#define SUN8I_AIF2_ADCDAT_CTRL 0x084 +#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA 15 +#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA 14 +#define SUN8I_AIF2_DACDAT_CTRL 0x088 +#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA 15 +#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA 14 +#define SUN8I_AIF2_MXR_SRC 0x08c +#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L 15 +#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L 14 +#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR 13 +#define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL 12 +#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R 11 +#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R 10 +#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL 9 +#define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR 8 #define SUN8I_ADC_DIG_CTRL 0x100 #define SUN8I_ADC_DIG_CTRL_ENAD 15 #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 @@ -79,6 +98,7 @@ #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) +#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(7, 4) #define SUN8I_SYS_SR_CTRL_AIF_FS_MASK(n) (GENMASK(19, 16) >> (4 * (n))) #define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13) #define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9) @@ -413,6 +433,32 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { .symmetric_channels = 1, .symmetric_samplebits = 1, }, + { + .name = "sun8i-codec-aif2", + .id = 2, + /* playback capabilities */ + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + }, + /* capture capabilities */ + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + .sig_bits = 24, + }, + /* pcm operations */ + .ops = &sun8i_codec_dai_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, };
static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { @@ -434,6 +480,25 @@ static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), };
+static const struct snd_kcontrol_new sun8i_aif2_adc_mixer_controls[] = { + SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA0 Capture Switch", + SUN8I_AIF2_MXR_SRC, + SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L, + SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R, 1, 0), + SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA1 Capture Switch", + SUN8I_AIF2_MXR_SRC, + SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L, + SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R, 1, 0), + SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", + SUN8I_AIF2_MXR_SRC, + SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR, + SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL, 1, 0), + SOC_DAPM_DOUBLE("AIF2 ADC Mixer ADC Capture Switch", + SUN8I_AIF2_MXR_SRC, + SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL, + SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR, 1, 0), +}; + static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { SOC_DAPM_DOUBLE("DAC Mixer AIF1 DA0 Playback Switch", SUN8I_DAC_MXR_SRC, @@ -462,12 +527,24 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_AIF1_ADCDAT_CTRL, SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF2 ADC Left", "AIF2 Capture", 0, + SUN8I_AIF2_ADCDAT_CTRL, + SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA, 0), + SND_SOC_DAPM_AIF_OUT("AIF2 ADC Right", "AIF2 Capture", 1, + SUN8I_AIF2_ADCDAT_CTRL, + SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA, 0), + /* AIF "ADC" Mixers */ SOC_MIXER_ARRAY("AIF1 AD0 Left Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls), SOC_MIXER_ARRAY("AIF1 AD0 Right Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls),
+ SOC_MIXER_ARRAY("AIF2 ADC Left Mixer", SND_SOC_NOPM, 0, 0, + sun8i_aif2_adc_mixer_controls), + SOC_MIXER_ARRAY("AIF2 ADC Right Mixer", SND_SOC_NOPM, 0, 0, + sun8i_aif2_adc_mixer_controls), + /* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, @@ -476,6 +553,13 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
+ SND_SOC_DAPM_AIF_IN("AIF2 DAC Left", "AIF2 Playback", 0, + SUN8I_AIF2_DACDAT_CTRL, + SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA, 0), + SND_SOC_DAPM_AIF_IN("AIF2 DAC Right", "AIF2 Playback", 1, + SUN8I_AIF2_DACDAT_CTRL, + SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA, 0), + /* Main DAC Outputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_PGA("DAC Left", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("DAC Right", SND_SOC_NOPM, 0, 0, NULL, 0), @@ -499,6 +583,8 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* Module Resets */ SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RST AIF2", SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_AIF2, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, @@ -507,6 +593,8 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* Module Clocks */ SND_SOC_DAPM_SUPPLY("MODCLK AIF1", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MODCLK AIF2", SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_AIF2, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, @@ -515,6 +603,8 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { /* Clock Supplies */ SND_SOC_DAPM_SUPPLY("AIF1CLK", SUN8I_SYSCLK_CTL, SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("AIF2CLK", SUN8I_SYSCLK_CTL, + SUN8I_SYSCLK_CTL_AIF2CLK_ENA, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL, SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), }; @@ -527,17 +617,38 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF1 AD0 Left", NULL, "AIF1CLK" }, { "AIF1 AD0 Right", NULL, "AIF1CLK" },
+ { "AIF2 ADC Left", NULL, "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Right", NULL, "AIF2 ADC Right Mixer" }, + + { "AIF2 ADC Left", NULL, "AIF2CLK" }, + { "AIF2 ADC Right", NULL, "AIF2CLK" }, + /* AIF "ADC" Mixer Routes */ { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Left" }, { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Left" }, + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right" },
{ "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Right" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Right" }, + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left" }, + + { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, + { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right" }, + { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Left" }, + + { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, + { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left" }, + { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Right" },
/* AIF "DAC" Input Routes */ { "AIF1 DA0 Left", NULL, "AIF1CLK" }, { "AIF1 DA0 Right", NULL, "AIF1CLK" },
+ { "AIF2 DAC Left", NULL, "AIF2CLK" }, + { "AIF2 DAC Right", NULL, "AIF2CLK" }, + /* Main DAC Output Routes */ { "DAC Left", NULL, "DAC Left Mixer" }, { "DAC Right", NULL, "DAC Right Mixer" }, @@ -547,9 +658,11 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
/* Main DAC Mixer Routes */ { "DAC Left Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Left" }, + { "DAC Left Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Left" }, { "DAC Left Mixer", "DAC Mixer ADC Playback Switch", "ADC Left" },
{ "DAC Right Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Right" }, + { "DAC Right Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Right" }, { "DAC Right Mixer", "DAC Mixer ADC Playback Switch", "ADC Right" },
/* Main ADC Input Routes */ @@ -562,16 +675,23 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF1 DA0 Left", NULL, "RST AIF1" }, { "AIF1 DA0 Right", NULL, "RST AIF1" },
+ { "AIF2 ADC Left", NULL, "RST AIF2" }, + { "AIF2 ADC Right", NULL, "RST AIF2" }, + { "AIF2 DAC Left", NULL, "RST AIF2" }, + { "AIF2 DAC Right", NULL, "RST AIF2" }, + { "ADC", NULL, "RST ADC" }, { "DAC", NULL, "RST DAC" },
/* Module Reset Routes */ { "RST AIF1", NULL, "MODCLK AIF1" }, + { "RST AIF2", NULL, "MODCLK AIF2" }, { "RST ADC", NULL, "MODCLK ADC" }, { "RST DAC", NULL, "MODCLK DAC" },
/* Module Clock Routes */ { "MODCLK AIF1", NULL, "SYSCLK" }, + { "MODCLK AIF2", NULL, "SYSCLK" }, { "MODCLK ADC", NULL, "SYSCLK" }, { "MODCLK DAC", NULL, "SYSCLK" },
@@ -588,6 +708,11 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK, SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL);
+ /* Set AIF2CLK clock source to PLL */ + regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, + SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK, + SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL); + /* Set SYSCLK clock source to AIF1CLK */ regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC),
This adds the new DAI, clocks, widgets, and routes for AIF2.
AIF3 lacks some of the configuration of the other AIFs. Skip setting bits that are unavailable on AIF3. It is not documented what the actual settings for AIF3 are, so those parameters cannot be validated.
AIF3 can pull its bitclock from AIF1 or AIF2. Since the normal usage of AIF3 is for low-bitrate mono audio, similar to AIF2, let's set the AIF3 clock to AIF2 for now.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 241 +++++++++++++++++++++++++--------- 1 file changed, 178 insertions(+), 63 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index ce7038bcbdc1..71c4c1f47201 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -34,11 +34,13 @@ #define SUN8I_MOD_CLK_ENA 0x010 #define SUN8I_MOD_CLK_ENA_AIF1 15 #define SUN8I_MOD_CLK_ENA_AIF2 14 +#define SUN8I_MOD_CLK_ENA_AIF3 13 #define SUN8I_MOD_CLK_ENA_ADC 3 #define SUN8I_MOD_CLK_ENA_DAC 2 #define SUN8I_MOD_RST_CTL 0x014 #define SUN8I_MOD_RST_CTL_AIF1 15 #define SUN8I_MOD_RST_CTL_AIF2 14 +#define SUN8I_MOD_RST_CTL_AIF3 13 #define SUN8I_MOD_RST_CTL_ADC 3 #define SUN8I_MOD_RST_CTL_DAC 2 #define SUN8I_SYS_SR_CTRL 0x018 @@ -81,6 +83,15 @@ #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R 10 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL 9 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR 8 +#define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF1 (0x0 << 0) +#define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF2 (0x1 << 0) +#define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF1CLK (0x2 << 0) +#define SUN8I_AIF3_DACDAT_CTRL 0x0c8 +#define SUN8I_AIF3_DACDAT_CTRL_AIF3_LOOP_ENA 0 +#define SUN8I_AIF3_PATH_CTRL 0x0cc +#define SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC 10 +#define SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC 8 +#define SUN8I_AIF3_PATH_CTRL_AIF3_PINS_TRI 7 #define SUN8I_ADC_DIG_CTRL 0x100 #define SUN8I_ADC_DIG_CTRL_ENAD 15 #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 @@ -105,6 +116,7 @@ #define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6) #define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4) #define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2) +#define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_MASK GENMASK(1, 0)
#define SUN8I_AIF_PCM_FMTS (SNDRV_PCM_FMTBIT_S8|\ SNDRV_PCM_FMTBIT_S16_LE|\ @@ -210,20 +222,22 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) unsigned int reg = SUN8I_AIF_CLK_CTRL(dai->id); u32 value;
- /* clock masters */ - switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { - case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ - value = 0x1; - break; - case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */ - value = 0x0; - break; - default: - return -EINVAL; + if (dai->id < 3) { + /* clock masters */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */ + value = 0x1; + break; + case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */ + value = 0x0; + break; + default: + return -EINVAL; + } + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), + value << SUN8I_AIF_CLK_CTRL_MSTR_MOD); } - regmap_update_bits(scodec->regmap, reg, - BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), - value << SUN8I_AIF_CLK_CTRL_MSTR_MOD);
/* clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { @@ -257,26 +271,28 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) SUN8I_AIF_CLK_CTRL_CLK_INV_MASK, value << SUN8I_AIF_CLK_CTRL_CLK_INV);
- /* DAI format */ - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_I2S: - value = 0x0; - break; - case SND_SOC_DAIFMT_LEFT_J: - value = 0x1; - break; - case SND_SOC_DAIFMT_RIGHT_J: - value = 0x2; - break; - case SND_SOC_DAIFMT_DSP_A: - value = 0x3; - break; - default: - return -EINVAL; + if (dai->id < 3) { + /* DAI format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + value = 0x0; + break; + case SND_SOC_DAIFMT_LEFT_J: + value = 0x1; + break; + case SND_SOC_DAIFMT_RIGHT_J: + value = 0x2; + break; + case SND_SOC_DAIFMT_DSP_A: + value = 0x3; + break; + default: + return -EINVAL; + } + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, + value << SUN8I_AIF_CLK_CTRL_DATA_FMT); } - regmap_update_bits(scodec->regmap, reg, - SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, - value << SUN8I_AIF_CLK_CTRL_DATA_FMT);
return 0; } @@ -351,19 +367,25 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, u8 bclk_div; u32 value;
- bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), - channels, slot_width); - regmap_update_bits(scodec->regmap, reg, - SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, - bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV); - - lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); - if (lrck_div < 0) - return lrck_div; - - regmap_update_bits(scodec->regmap, reg, - SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, - lrck_div << SUN8I_AIF_CLK_CTRL_LRCK_DIV); + if (dai->id < 3) { + bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), + channels, slot_width); + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, + bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV); + + lrck_div = sun8i_codec_get_lrck_div(channels, slot_width); + if (lrck_div < 0) + return lrck_div; + + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, + lrck_div << SUN8I_AIF_CLK_CTRL_LRCK_DIV); + } else { + regmap_update_bits(scodec->regmap, reg, + SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_MASK, + SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF2); + }
switch (params_width(params)) { case 8: @@ -385,18 +407,20 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK, value << SUN8I_AIF_CLK_CTRL_WORD_SIZ);
- value = channels == 1; - regmap_update_bits(scodec->regmap, reg, - BIT(SUN8I_AIF_CLK_CTRL_MONO_PCM), - value << SUN8I_AIF_CLK_CTRL_MONO_PCM); + if (dai->id < 3) { + value = channels == 1; + regmap_update_bits(scodec->regmap, reg, + BIT(SUN8I_AIF_CLK_CTRL_MONO_PCM), + value << SUN8I_AIF_CLK_CTRL_MONO_PCM);
- sample_rate = sun8i_codec_get_hw_rate(params); - if (sample_rate < 0) - return sample_rate; + sample_rate = sun8i_codec_get_hw_rate(params); + if (sample_rate < 0) + return sample_rate;
- regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF_FS_MASK(dai->id), - sample_rate << SUN8I_SYS_SR_CTRL_AIF_FS(dai->id)); + regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, + SUN8I_SYS_SR_CTRL_AIF_FS_MASK(dai->id), + sample_rate << SUN8I_SYS_SR_CTRL_AIF_FS(dai->id)); + }
return 0; } @@ -459,8 +483,56 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { .symmetric_channels = 1, .symmetric_samplebits = 1, }, + { + .name = "sun8i-codec-aif3", + .id = 3, + /* playback capabilities */ + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 1, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + }, + /* capture capabilities */ + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 1, + .rates = SUN8I_AIF_PCM_RATES, + .formats = SUN8I_AIF_PCM_FMTS, + .sig_bits = 24, + }, + /* pcm operations */ + .ops = &sun8i_codec_dai_ops, + .symmetric_rates = 1, + .symmetric_channels = 1, + .symmetric_samplebits = 1, + }, };
+static const char *const sun8i_aif3_mux_enum_names[] = { + "None", "AIF2 Left", "AIF2 Right" +}; + +static SOC_ENUM_SINGLE_DECL(sun8i_aif3_adc_mux_enum, + SUN8I_AIF3_PATH_CTRL, + SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC, + sun8i_aif3_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif3_adc_mux_control = + SOC_DAPM_ENUM("AIF3 ADC Capture Route", + sun8i_aif3_adc_mux_enum); + +static SOC_ENUM_SINGLE_DECL(sun8i_aif2_dac_mux_enum, + SUN8I_AIF3_PATH_CTRL, + SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC, + sun8i_aif3_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif2_dac_mux_control = + SOC_DAPM_ENUM("AIF3 DAC Playback Route", + sun8i_aif2_dac_mux_enum); + static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 AD0 Mixer AIF1 DA0 Capture Switch", SUN8I_AIF1_MXR_SRC, @@ -534,6 +606,13 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_AIF2_ADCDAT_CTRL, SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA, 0),
+ SND_SOC_DAPM_AIF_OUT("AIF3 ADC", "AIF3 Capture", 0, + SND_SOC_NOPM, 0, 0), + + /* AIF "ADC" Muxes */ + SND_SOC_DAPM_MUX("AIF3 ADC Capture Route", SND_SOC_NOPM, 0, 0, + &sun8i_aif3_adc_mux_control), + /* AIF "ADC" Mixers */ SOC_MIXER_ARRAY("AIF1 AD0 Left Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif1_ad0_mixer_controls), @@ -545,6 +624,12 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SOC_MIXER_ARRAY("AIF2 ADC Right Mixer", SND_SOC_NOPM, 0, 0, sun8i_aif2_adc_mixer_controls),
+ /* AIF "DAC" Muxes */ + SND_SOC_DAPM_MUX("AIF2 DAC Left Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_dac_mux_control), + SND_SOC_DAPM_MUX("AIF2 DAC Right Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_dac_mux_control), + /* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, @@ -560,6 +645,9 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_AIF2_DACDAT_CTRL, SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA, 0),
+ SND_SOC_DAPM_AIF_IN("AIF3 DAC", "AIF3 Playback", 0, + SND_SOC_NOPM, 0, 0), + /* Main DAC Outputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_PGA("DAC Left", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("DAC Right", SND_SOC_NOPM, 0, 0, NULL, 0), @@ -585,6 +673,8 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST AIF2", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_AIF2, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RST AIF3", SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_AIF3, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, @@ -595,6 +685,8 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK AIF2", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_AIF2, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MODCLK AIF3", SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_AIF3, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA, SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, @@ -623,25 +715,40 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF2 ADC Left", NULL, "AIF2CLK" }, { "AIF2 ADC Right", NULL, "AIF2CLK" },
+ { "AIF3 ADC", NULL, "AIF3 ADC Capture Route" }, + + /* AIF "ADC" Mux Routes */ + { "AIF3 ADC Capture Route", "AIF2 Left", "AIF2 ADC Left Mixer" }, + { "AIF3 ADC Capture Route", "AIF2 Right", "AIF2 ADC Right Mixer" }, + /* AIF "ADC" Mixer Routes */ { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, - { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Left" }, + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Left Mux" }, { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Left" }, - { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right" }, + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right Mux" },
{ "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, - { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Right" }, + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Right Mux" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Right" }, - { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left" }, + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left Mux" },
{ "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, - { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right" }, + { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right Mux" }, { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Left" },
{ "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, - { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left" }, + { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left Mux" }, { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Right" },
+ /* AIF "DAC" Mux Routes */ + { "AIF2 DAC Left Mux", "None", "AIF2 DAC Left" }, + { "AIF2 DAC Left Mux", "AIF2 Left", "AIF3 DAC" }, + { "AIF2 DAC Left Mux", "AIF2 Right", "AIF2 DAC Left" }, + + { "AIF2 DAC Right Mux", "None", "AIF2 DAC Right" }, + { "AIF2 DAC Right Mux", "AIF2 Left", "AIF2 DAC Right" }, + { "AIF2 DAC Right Mux", "AIF2 Right", "AIF3 DAC" }, + /* AIF "DAC" Input Routes */ { "AIF1 DA0 Left", NULL, "AIF1CLK" }, { "AIF1 DA0 Right", NULL, "AIF1CLK" }, @@ -658,11 +765,11 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
/* Main DAC Mixer Routes */ { "DAC Left Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Left" }, - { "DAC Left Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Left" }, + { "DAC Left Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Left Mux" }, { "DAC Left Mixer", "DAC Mixer ADC Playback Switch", "ADC Left" },
{ "DAC Right Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Right" }, - { "DAC Right Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Right" }, + { "DAC Right Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Right Mux" }, { "DAC Right Mixer", "DAC Mixer ADC Playback Switch", "ADC Right" },
/* Main ADC Input Routes */ @@ -680,18 +787,26 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF2 DAC Left", NULL, "RST AIF2" }, { "AIF2 DAC Right", NULL, "RST AIF2" },
+ /* AIF3 gets its bitclock from AIF2 */ + { "AIF3 ADC", NULL, "RST AIF2" }, + { "AIF3 ADC", NULL, "RST AIF3" }, + { "AIF3 DAC", NULL, "RST AIF2" }, + { "AIF3 DAC", NULL, "RST AIF3" }, + { "ADC", NULL, "RST ADC" }, { "DAC", NULL, "RST DAC" },
/* Module Reset Routes */ { "RST AIF1", NULL, "MODCLK AIF1" }, { "RST AIF2", NULL, "MODCLK AIF2" }, + { "RST AIF3", NULL, "MODCLK AIF3" }, { "RST ADC", NULL, "MODCLK ADC" }, { "RST DAC", NULL, "MODCLK DAC" },
/* Module Clock Routes */ { "MODCLK AIF1", NULL, "SYSCLK" }, { "MODCLK AIF2", NULL, "SYSCLK" }, + { "MODCLK AIF3", NULL, "SYSCLK" }, { "MODCLK ADC", NULL, "SYSCLK" }, { "MODCLK DAC", NULL, "SYSCLK" },
This allows changing the channel mapping for each digital input/output. This is useful when the DAI (or the device on the other end of the link) supports a different number of channels than are desired for routing, for example when using an I2S-format DAI link with a mono endpoint.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 160 +++++++++++++++++++++++++++++++--- 1 file changed, 146 insertions(+), 14 deletions(-)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 71c4c1f47201..fdb9bf346cc2 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -56,9 +56,13 @@ #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8 #define SUN8I_AIF1_DACDAT_CTRL 0x048 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 +#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10 +#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8 #define SUN8I_AIF1_MXR_SRC 0x04c #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 @@ -71,9 +75,13 @@ #define SUN8I_AIF2_ADCDAT_CTRL 0x084 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA 15 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA 14 +#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC 10 +#define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC 8 #define SUN8I_AIF2_DACDAT_CTRL 0x088 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA 15 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA 14 +#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC 10 +#define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC 8 #define SUN8I_AIF2_MXR_SRC 0x08c #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L 15 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L 14 @@ -511,6 +519,50 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { }, };
+static const char *const sun8i_aif_stereo_mux_enum_names[] = { + "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" +}; + +static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC, + sun8i_aif_stereo_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif1_ad0_stereo_mux_control = + SOC_DAPM_ENUM("AIF1 AD0 Stereo Capture Route", + sun8i_aif1_ad0_stereo_mux_enum); + +static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_da0_stereo_mux_enum, + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC, + sun8i_aif_stereo_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif1_da0_stereo_mux_control = + SOC_DAPM_ENUM("AIF1 DA0 Stereo Playback Route", + sun8i_aif1_da0_stereo_mux_enum); + +static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_adc_stereo_mux_enum, + SUN8I_AIF2_ADCDAT_CTRL, + SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC, + SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC, + sun8i_aif_stereo_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif2_adc_stereo_mux_control = + SOC_DAPM_ENUM("AIF2 ADC Stereo Capture Route", + sun8i_aif2_adc_stereo_mux_enum); + +static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_dac_stereo_mux_enum, + SUN8I_AIF2_DACDAT_CTRL, + SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC, + SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC, + sun8i_aif_stereo_mux_enum_names); + +static const struct snd_kcontrol_new sun8i_aif2_dac_stereo_mux_control = + SOC_DAPM_ENUM("AIF2 DAC Stereo Playback Route", + sun8i_aif2_dac_stereo_mux_enum); + static const char *const sun8i_aif3_mux_enum_names[] = { "None", "AIF2 Left", "AIF2 Right" }; @@ -609,6 +661,17 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_AIF_OUT("AIF3 ADC", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
+ /* AIF "ADC" Mono/Stereo Muxes */ + SND_SOC_DAPM_MUX("AIF1 AD0 Left Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_ad0_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF1 AD0 Right Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_ad0_stereo_mux_control), + + SND_SOC_DAPM_MUX("AIF2 ADC Left Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_adc_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF2 ADC Right Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_adc_stereo_mux_control), + /* AIF "ADC" Muxes */ SND_SOC_DAPM_MUX("AIF3 ADC Capture Route", SND_SOC_NOPM, 0, 0, &sun8i_aif3_adc_mux_control), @@ -630,6 +693,17 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_MUX("AIF2 DAC Right Mux", SND_SOC_NOPM, 0, 0, &sun8i_aif2_dac_mux_control),
+ /* AIF "DAC" Mono/Stereo Muxes */ + SND_SOC_DAPM_MUX("AIF1 DA0 Left Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_da0_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF1 DA0 Right Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_da0_stereo_mux_control), + + SND_SOC_DAPM_MUX("AIF2 DAC Left Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_dac_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF2 DAC Right Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_dac_stereo_mux_control), + /* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0 Left", "AIF1 Playback", 0, SUN8I_AIF1_DACDAT_CTRL, @@ -703,52 +777,110 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { /* AIF "ADC" Output Routes */ - { "AIF1 AD0 Left", NULL, "AIF1 AD0 Left Mixer" }, - { "AIF1 AD0 Right", NULL, "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Left", NULL, "AIF1 AD0 Left Stereo Mux" }, + { "AIF1 AD0 Right", NULL, "AIF1 AD0 Right Stereo Mux" },
{ "AIF1 AD0 Left", NULL, "AIF1CLK" }, { "AIF1 AD0 Right", NULL, "AIF1CLK" },
- { "AIF2 ADC Left", NULL, "AIF2 ADC Left Mixer" }, - { "AIF2 ADC Right", NULL, "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Left", NULL, "AIF2 ADC Left Stereo Mux" }, + { "AIF2 ADC Right", NULL, "AIF2 ADC Right Stereo Mux" },
{ "AIF2 ADC Left", NULL, "AIF2CLK" }, { "AIF2 ADC Right", NULL, "AIF2CLK" },
{ "AIF3 ADC", NULL, "AIF3 ADC Capture Route" },
+ /* AIF "ADC" Mono/Stereo Mux Routes */ + { "AIF1 AD0 Left Stereo Mux", "Stereo", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Reverse Stereo", "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Sum Mono", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Sum Mono", "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Mix Mono", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Left Stereo Mux", "Mix Mono", "AIF1 AD0 Right Mixer" }, + + { "AIF1 AD0 Right Stereo Mux", "Stereo", "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Reverse Stereo", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Sum Mono", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Sum Mono", "AIF1 AD0 Right Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Mix Mono", "AIF1 AD0 Left Mixer" }, + { "AIF1 AD0 Right Stereo Mux", "Mix Mono", "AIF1 AD0 Right Mixer" }, + + { "AIF2 ADC Left Stereo Mux", "Stereo", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Reverse Stereo", "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Sum Mono", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Sum Mono", "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Mix Mono", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Left Stereo Mux", "Mix Mono", "AIF2 ADC Right Mixer" }, + + { "AIF2 ADC Right Stereo Mux", "Stereo", "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Reverse Stereo", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Sum Mono", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Sum Mono", "AIF2 ADC Right Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Mix Mono", "AIF2 ADC Left Mixer" }, + { "AIF2 ADC Right Stereo Mux", "Mix Mono", "AIF2 ADC Right Mixer" }, + /* AIF "ADC" Mux Routes */ { "AIF3 ADC Capture Route", "AIF2 Left", "AIF2 ADC Left Mixer" }, { "AIF3 ADC Capture Route", "AIF2 Right", "AIF2 ADC Right Mixer" },
/* AIF "ADC" Mixer Routes */ - { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, + { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left Stereo Mux" }, { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Left Mux" }, { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Left" }, { "AIF1 AD0 Left Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right Mux" },
- { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, + { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right Stereo Mux" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Capture Switch", "AIF2 DAC Right Mux" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer ADC Capture Switch", "ADC Right" }, { "AIF1 AD0 Right Mixer", "AIF1 AD0 Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left Mux" },
- { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left" }, + { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Left Stereo Mux" }, { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Right Mux" }, { "AIF2 ADC Left Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Left" },
- { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right" }, + { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0 Right Stereo Mux" }, { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DAC Left Mux" }, { "AIF2 ADC Right Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADC Right" },
/* AIF "DAC" Mux Routes */ - { "AIF2 DAC Left Mux", "None", "AIF2 DAC Left" }, + { "AIF2 DAC Left Mux", "None", "AIF2 DAC Left Stereo Mux" }, { "AIF2 DAC Left Mux", "AIF2 Left", "AIF3 DAC" }, - { "AIF2 DAC Left Mux", "AIF2 Right", "AIF2 DAC Left" }, + { "AIF2 DAC Left Mux", "AIF2 Right", "AIF2 DAC Left Stereo Mux" },
- { "AIF2 DAC Right Mux", "None", "AIF2 DAC Right" }, - { "AIF2 DAC Right Mux", "AIF2 Left", "AIF2 DAC Right" }, + { "AIF2 DAC Right Mux", "None", "AIF2 DAC Right Stereo Mux" }, + { "AIF2 DAC Right Mux", "AIF2 Left", "AIF2 DAC Right Stereo Mux" }, { "AIF2 DAC Right Mux", "AIF2 Right", "AIF3 DAC" },
+ /* AIF "DAC" Mono/Stereo Mux Routes */ + { "AIF1 DA0 Left Stereo Mux", "Stereo", "AIF1 DA0 Left" }, + { "AIF1 DA0 Left Stereo Mux", "Reverse Stereo", "AIF1 DA0 Right" }, + { "AIF1 DA0 Left Stereo Mux", "Sum Mono", "AIF1 DA0 Left" }, + { "AIF1 DA0 Left Stereo Mux", "Sum Mono", "AIF1 DA0 Right" }, + { "AIF1 DA0 Left Stereo Mux", "Mix Mono", "AIF1 DA0 Left" }, + { "AIF1 DA0 Left Stereo Mux", "Mix Mono", "AIF1 DA0 Right" }, + + { "AIF1 DA0 Right Stereo Mux", "Stereo", "AIF1 DA0 Right" }, + { "AIF1 DA0 Right Stereo Mux", "Reverse Stereo", "AIF1 DA0 Left" }, + { "AIF1 DA0 Right Stereo Mux", "Sum Mono", "AIF1 DA0 Left" }, + { "AIF1 DA0 Right Stereo Mux", "Sum Mono", "AIF1 DA0 Right" }, + { "AIF1 DA0 Right Stereo Mux", "Mix Mono", "AIF1 DA0 Left" }, + { "AIF1 DA0 Right Stereo Mux", "Mix Mono", "AIF1 DA0 Right" }, + + { "AIF2 DAC Left Stereo Mux", "Stereo", "AIF2 DAC Left" }, + { "AIF2 DAC Left Stereo Mux", "Reverse Stereo", "AIF2 DAC Right" }, + { "AIF2 DAC Left Stereo Mux", "Sum Mono", "AIF2 DAC Left" }, + { "AIF2 DAC Left Stereo Mux", "Sum Mono", "AIF2 DAC Right" }, + { "AIF2 DAC Left Stereo Mux", "Mix Mono", "AIF2 DAC Left" }, + { "AIF2 DAC Left Stereo Mux", "Mix Mono", "AIF2 DAC Right" }, + + { "AIF2 DAC Right Stereo Mux", "Stereo", "AIF2 DAC Right" }, + { "AIF2 DAC Right Stereo Mux", "Reverse Stereo", "AIF2 DAC Left" }, + { "AIF2 DAC Right Stereo Mux", "Sum Mono", "AIF2 DAC Left" }, + { "AIF2 DAC Right Stereo Mux", "Sum Mono", "AIF2 DAC Right" }, + { "AIF2 DAC Right Stereo Mux", "Mix Mono", "AIF2 DAC Left" }, + { "AIF2 DAC Right Stereo Mux", "Mix Mono", "AIF2 DAC Right" }, + /* AIF "DAC" Input Routes */ { "AIF1 DA0 Left", NULL, "AIF1CLK" }, { "AIF1 DA0 Right", NULL, "AIF1CLK" }, @@ -764,11 +896,11 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "DAC Right", NULL, "DAC" },
/* Main DAC Mixer Routes */ - { "DAC Left Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Left" }, + { "DAC Left Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Left Stereo Mux" }, { "DAC Left Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Left Mux" }, { "DAC Left Mixer", "DAC Mixer ADC Playback Switch", "ADC Left" },
- { "DAC Right Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Right" }, + { "DAC Right Mixer", "DAC Mixer AIF1 DA0 Playback Switch", "AIF1 DA0 Right Stereo Mux" }, { "DAC Right Mixer", "DAC Mixer AIF2 DAC Playback Switch", "AIF2 DAC Right Mux" }, { "DAC Right Mixer", "DAC Mixer ADC Playback Switch", "ADC Right" },
This allows controlling the loopback flag for each AIF. This is useful for developing/testing complicated audio routing scenarios (such as recording a phone call while using a BT headset for mic/earpiece) without needing to involve the devices on the other end of the DAI links.
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 48 +++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index fdb9bf346cc2..245145e36357 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -63,6 +63,7 @@ #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8 +#define SUN8I_AIF1_DACDAT_CTRL_AIF1_LOOP_ENA 0 #define SUN8I_AIF1_MXR_SRC 0x04c #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 @@ -82,6 +83,7 @@ #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA 14 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC 10 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC 8 +#define SUN8I_AIF2_DACDAT_CTRL_AIF2_LOOP_ENA 0 #define SUN8I_AIF2_MXR_SRC 0x08c #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L 15 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L 14 @@ -519,6 +521,21 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { }, };
+static const struct snd_kcontrol_new sun8i_aif1_loopback_switch = + SOC_DAPM_SINGLE("AIF1 Loopback Switch", + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_LOOP_ENA, 1, 0); + +static const struct snd_kcontrol_new sun8i_aif2_loopback_switch = + SOC_DAPM_SINGLE("AIF2 Loopback Switch", + SUN8I_AIF2_DACDAT_CTRL, + SUN8I_AIF2_DACDAT_CTRL_AIF2_LOOP_ENA, 1, 0); + +static const struct snd_kcontrol_new sun8i_aif3_loopback_switch = + SOC_DAPM_SINGLE("Switch", + SUN8I_AIF3_DACDAT_CTRL, + SUN8I_AIF3_DACDAT_CTRL_AIF3_LOOP_ENA, 1, 0); + static const char *const sun8i_aif_stereo_mux_enum_names[] = { "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" }; @@ -643,6 +660,20 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { };
static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { + /* AIF Loopback Switches */ + SND_SOC_DAPM_SWITCH("AIF1 Slot 0 Left Loopback", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_loopback_switch), + SND_SOC_DAPM_SWITCH("AIF1 Slot 0 Right Loopback", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_loopback_switch), + + SND_SOC_DAPM_SWITCH("AIF2 Left Loopback", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_loopback_switch), + SND_SOC_DAPM_SWITCH("AIF2 Right Loopback", SND_SOC_NOPM, 0, 0, + &sun8i_aif2_loopback_switch), + + SND_SOC_DAPM_SWITCH("AIF3 Loopback", SND_SOC_NOPM, 0, 0, + &sun8i_aif3_loopback_switch), + /* AIF "ADC" Outputs */ SND_SOC_DAPM_AIF_OUT("AIF1 AD0 Left", "AIF1 Capture", 0, SUN8I_AIF1_ADCDAT_CTRL, @@ -776,6 +807,15 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { };
static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { + /* AIF Loopback Routes */ + { "AIF1 Slot 0 Left Loopback", "AIF1 Loopback Switch", "AIF1 AD0 Left" }, + { "AIF1 Slot 0 Right Loopback", "AIF1 Loopback Switch", "AIF1 AD0 Right" }, + + { "AIF2 Left Loopback", "AIF2 Loopback Switch", "AIF2 ADC Left" }, + { "AIF2 Right Loopback", "AIF2 Loopback Switch", "AIF2 ADC Right" }, + + { "AIF3 Loopback", "Switch", "AIF3 ADC" }, + /* AIF "ADC" Output Routes */ { "AIF1 AD0 Left", NULL, "AIF1 AD0 Left Stereo Mux" }, { "AIF1 AD0 Right", NULL, "AIF1 AD0 Right Stereo Mux" }, @@ -882,12 +922,20 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { { "AIF2 DAC Right Stereo Mux", "Mix Mono", "AIF2 DAC Right" },
/* AIF "DAC" Input Routes */ + { "AIF1 DA0 Left", NULL, "AIF1 Slot 0 Left Loopback" }, + { "AIF1 DA0 Right", NULL, "AIF1 Slot 0 Right Loopback" }, + { "AIF1 DA0 Left", NULL, "AIF1CLK" }, { "AIF1 DA0 Right", NULL, "AIF1CLK" },
+ { "AIF2 DAC Left", NULL, "AIF2 Left Loopback" }, + { "AIF2 DAC Right", NULL, "AIF2 Right Loopback" }, + { "AIF2 DAC Left", NULL, "AIF2CLK" }, { "AIF2 DAC Right", NULL, "AIF2CLK" },
+ { "AIF3 DAC", NULL, "AIF3 Loopback" }, + /* Main DAC Output Routes */ { "DAC Left", NULL, "DAC Left Mixer" }, { "DAC Right", NULL, "DAC Right Mixer" },
This allows changing the volume of each digital input/output independently, and provides the only "master volume" for the DAC. (The ADC also has a gain control on the analog side.)
While the hardware supports volumes up to +72dB, the controls here are limited to +24dB maximum, as anything more makes volume sliders difficult to use, and is extremely likely to cause clipping (this is simple digital gain).
Signed-off-by: Samuel Holland samuel@sholland.org --- sound/soc/sunxi/sun8i-codec.c | 56 +++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+)
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 245145e36357..71cd7646a895 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -21,6 +21,7 @@ #include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/soc-dapm.h> +#include <sound/tlv.h>
#define SUN8I_SYSCLK_CTL 0x00c #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 @@ -73,6 +74,12 @@ #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8 +#define SUN8I_AIF1_VOL_CTRL1 0x050 +#define SUN8I_AIF1_VOL_CTRL1_AD0L_VOL 8 +#define SUN8I_AIF1_VOL_CTRL1_AD0R_VOL 0 +#define SUN8I_AIF1_VOL_CTRL3 0x058 +#define SUN8I_AIF1_VOL_CTRL3_DA0L_VOL 8 +#define SUN8I_AIF1_VOL_CTRL3_DA0R_VOL 0 #define SUN8I_AIF2_ADCDAT_CTRL 0x084 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA 15 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA 14 @@ -93,6 +100,12 @@ #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R 10 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL 9 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR 8 +#define SUN8I_AIF2_VOL_CTRL1 0x090 +#define SUN8I_AIF2_VOL_CTRL1_ADCL_VOL 8 +#define SUN8I_AIF2_VOL_CTRL1_ADCR_VOL 0 +#define SUN8I_AIF2_VOL_CTRL2 0x098 +#define SUN8I_AIF2_VOL_CTRL2_DACL_VOL 8 +#define SUN8I_AIF2_VOL_CTRL2_DACR_VOL 0 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF1 (0x0 << 0) #define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF2 (0x1 << 0) #define SUN8I_AIF3_CLK_CTRL_AIF3_CLOCK_SRC_AIF1CLK (0x2 << 0) @@ -106,8 +119,14 @@ #define SUN8I_ADC_DIG_CTRL_ENAD 15 #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 #define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1 +#define SUN8I_ADC_VOL_CTRL 0x104 +#define SUN8I_ADC_VOL_CTRL_ADCL_VOL 8 +#define SUN8I_ADC_VOL_CTRL_ADCR_VOL 0 #define SUN8I_DAC_DIG_CTRL 0x120 #define SUN8I_DAC_DIG_CTRL_ENDA 15 +#define SUN8I_DAC_VOL_CTRL 0x124 +#define SUN8I_DAC_VOL_CTRL_DACL_VOL 8 +#define SUN8I_DAC_VOL_CTRL_DACR_VOL 0 #define SUN8I_DAC_MXR_SRC 0x130 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14 @@ -521,6 +540,41 @@ static struct snd_soc_dai_driver sun8i_codec_dais[] = { }, };
+static const DECLARE_TLV_DB_SCALE(sun8i_codec_vol_scale, -12000, 75, 1); + +static const struct snd_kcontrol_new sun8i_codec_controls[] = { + SOC_DOUBLE_TLV("AIF1 AD0 Capture Volume", + SUN8I_AIF1_VOL_CTRL1, + SUN8I_AIF1_VOL_CTRL1_AD0L_VOL, + SUN8I_AIF1_VOL_CTRL1_AD0R_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("AIF1 DA0 Playback Volume", + SUN8I_AIF1_VOL_CTRL3, + SUN8I_AIF1_VOL_CTRL3_DA0L_VOL, + SUN8I_AIF1_VOL_CTRL3_DA0R_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("AIF2 ADC Capture Volume", + SUN8I_AIF2_VOL_CTRL1, + SUN8I_AIF2_VOL_CTRL1_ADCL_VOL, + SUN8I_AIF2_VOL_CTRL1_ADCR_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("AIF2 DAC Playback Volume", + SUN8I_AIF2_VOL_CTRL2, + SUN8I_AIF2_VOL_CTRL2_DACL_VOL, + SUN8I_AIF2_VOL_CTRL2_DACR_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("ADC Capture Volume", + SUN8I_ADC_VOL_CTRL, + SUN8I_ADC_VOL_CTRL_ADCL_VOL, + SUN8I_ADC_VOL_CTRL_ADCR_VOL, + 0xc0, 0, sun8i_codec_vol_scale), + SOC_DOUBLE_TLV("DAC Playback Volume", + SUN8I_DAC_VOL_CTRL, + SUN8I_DAC_VOL_CTRL_DACL_VOL, + SUN8I_DAC_VOL_CTRL_DACR_VOL, + 0xc0, 0, sun8i_codec_vol_scale), +}; + static const struct snd_kcontrol_new sun8i_aif1_loopback_switch = SOC_DAPM_SINGLE("AIF1 Loopback Switch", SUN8I_AIF1_DACDAT_CTRL, @@ -1017,6 +1071,8 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) }
static const struct snd_soc_component_driver sun8i_soc_component = { + .controls = sun8i_codec_controls, + .num_controls = ARRAY_SIZE(sun8i_codec_controls), .dapm_widgets = sun8i_codec_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), .dapm_routes = sun8i_codec_dapm_routes,
The generic ASoC OF code supports a sound-dai-cells value of 0 or 1 with no impact to the driver. Bump sound-dai-cells to 1 to allow using the secondary DAIs in the codec.
Signed-off-by: Samuel Holland samuel@sholland.org --- .../devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml index 7c66409f13ea..97d4bf0d9a73 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml @@ -12,7 +12,7 @@ maintainers:
properties: "#sound-dai-cells": - const: 0 + const: 1
compatible: enum:
On Mon, 17 Feb 2020 00:42:46 -0600, Samuel Holland wrote:
The generic ASoC OF code supports a sound-dai-cells value of 0 or 1 with no impact to the driver. Bump sound-dai-cells to 1 to allow using the secondary DAIs in the codec.
Signed-off-by: Samuel Holland samuel@sholland.org
.../devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.example.dt.yaml: audio-codec@1c22e00: #sound-dai-cells:0:0: 1 was expected
See https://patchwork.ozlabs.org/patch/1238984 Please check and re-submit.
The generic ASoC OF code supports a sound-dai-cells value of 0 or 1 with no impact to the driver. Bump sound-dai-cells to 1 to allow using the secondary DAIs in the codec.
Signed-off-by: Samuel Holland samuel@sholland.org --- arch/arm/boot/dts/sun8i-a33.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 40b903fa73da..a16c2ca11131 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -200,7 +200,7 @@ simple-audio-card,cpu { };
link_codec: simple-audio-card,codec { - sound-dai = <&codec>; + sound-dai = <&codec 0>; }; };
@@ -240,7 +240,7 @@ dai: dai@1c22c00 { };
codec: codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
The generic ASoC OF code supports a sound-dai-cells value of 0 or 1 with no impact to the driver. Bump sound-dai-cells to 1 to allow using the secondary DAIs in the codec.
Signed-off-by: Samuel Holland samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 5b688687a2b2..a7470f2ab975 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -176,7 +176,7 @@ cpudai: simple-audio-card,cpu { };
link_codec: simple-audio-card,codec { - sound-dai = <&codec>; + sound-dai = <&codec 0>; }; };
@@ -801,7 +801,7 @@ dai: dai@1c22c00 { };
codec: codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun50i-a64-codec"; reg = <0x01c22e00 0x600>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
simple-audio-card supports either a single DAI link at the top level, or subnodes with one or more DAI links. To use the secondary AIFs on the codec, we need to add additional DAI links to the same sound card, so we need to use the other binding.
Signed-off-by: Samuel Holland samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 23 +++++++++++-------- 1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index a7470f2ab975..78353893c3b9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -157,12 +157,10 @@ psci { };
sound: sound { + #address-cells = <1>; + #size-cells = <0>; compatible = "simple-audio-card"; simple-audio-card,name = "sun50i-a64-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = "Left DAC", "DAC Left", @@ -171,12 +169,19 @@ sound: sound { "ADC Right", "Right ADC"; status = "disabled";
- cpudai: simple-audio-card,cpu { - sound-dai = <&dai>; - }; + simple-audio-card,dai-link@0 { + format = "i2s"; + frame-master = <&link0_cpu>; + bitclock-master = <&link0_cpu>; + mclk-fs = <128>;
- link_codec: simple-audio-card,codec { - sound-dai = <&codec 0>; + link0_cpu: cpu { + sound-dai = <&dai>; + }; + + link0_codec: codec { + sound-dai = <&codec 0>; + }; }; };
Now that the codec driver supports AIF2 and AIF3, boards can use them in DAI links.
Add the pinmux nodes.
Signed-off-by: Samuel Holland samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 78353893c3b9..ee09a2dd6f69 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -605,6 +605,18 @@ pio: pinctrl@1c20800 { interrupt-controller; #interrupt-cells = <3>;
+ /omit-if-no-ref/ + aif2_pins: aif2-pins { + pins = "PB4", "PB5", "PB6", "PB7"; + function = "aif2"; + }; + + /omit-if-no-ref/ + aif3_pins: aif3-pins { + pins = "PG10", "PG11", "PG12", "PG13"; + function = "aif3"; + }; + csi_pins: csi-pins { pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
Hi,
On Mon, Feb 17, 2020 at 12:42:16AM -0600, Samuel Holland wrote:
The sun8i-codec driver, as used in the Allwinner A33 and A64, currently only exposes a small subset of the available hardware features. In order to use the A64 in a smartphone (the PinePhone), I've added the necessary functionality to the driver:
- The full set of supported DAI format options
- Support for AIF2 and AIF3
- Additional routing knobs
- Additional volume controls
Unfortunately, due to preexisting issues with the driver, there are some breaking changes, as explained further in the commit messages:
- The LRCK inversion issue means we need a new compatible for the A64.
- Some controls are named inaccurately, so they are renamed.
- Likewise, the DAPM widgets used in device trees were either named wrong, or the device trees were using the wrong widgets in the first place. (Specifically, the links between the analog codec and digital codec happen at the ADC and DAC, not AIF1.)
I tended to take the philosophy of "while I'm breaking things, I might as well do them right", so I've probably made a few more changes than absolutely necessary. I'm not sure about where all of the policy boundaries are, about how far I should go to maintain compatibility. For example, for the DT widget usage, I could:
- Rename everything and update the DTS files (which is what I did)
- Keep the old (misleading/wrong) name for the widgets, but repurpose them to work correctly (i.e. "ADC Left" would be named "AIF1 Slot 0 Left ADC", but it would work just like "ADC Left" does in this patchset)
- Keep the old widgets around as a compatibility layer, but add new widgets and update the in-tree DTS files to use them (i.e. "ADC Left" would have a path from "AIF1 Slot 0 Left ADC", but "AIF1 Slot 0 Left ADC" would be a no-op widget)
- Something else entirely
I'm not sure this is really a concern here. We need to maintain the compatibility with old DT's, but those will have an A33 compatible too, and as far as I can see, you're not changing anything for that compatible, so we're in the clear?
If not, then the third option would probably be the best, especially since it's only a couple of them.
Maxime
On Mon, Feb 17, 2020 at 5:14 PM Maxime Ripard maxime@cerno.tech wrote:
Hi,
On Mon, Feb 17, 2020 at 12:42:16AM -0600, Samuel Holland wrote:
The sun8i-codec driver, as used in the Allwinner A33 and A64, currently only exposes a small subset of the available hardware features. In order to use the A64 in a smartphone (the PinePhone), I've added the necessary functionality to the driver:
- The full set of supported DAI format options
- Support for AIF2 and AIF3
- Additional routing knobs
- Additional volume controls
Unfortunately, due to preexisting issues with the driver, there are some breaking changes, as explained further in the commit messages:
- The LRCK inversion issue means we need a new compatible for the A64.
- Some controls are named inaccurately, so they are renamed.
- Likewise, the DAPM widgets used in device trees were either named wrong, or the device trees were using the wrong widgets in the first place. (Specifically, the links between the analog codec and digital codec happen at the ADC and DAC, not AIF1.)
I tended to take the philosophy of "while I'm breaking things, I might as well do them right", so I've probably made a few more changes than absolutely necessary. I'm not sure about where all of the policy boundaries are, about how far I should go to maintain compatibility. For example, for the DT widget usage, I could:
- Rename everything and update the DTS files (which is what I did)
- Keep the old (misleading/wrong) name for the widgets, but repurpose them to work correctly (i.e. "ADC Left" would be named "AIF1 Slot 0 Left ADC", but it would work just like "ADC Left" does in this patchset)
- Keep the old widgets around as a compatibility layer, but add new widgets and update the in-tree DTS files to use them (i.e. "ADC Left" would have a path from "AIF1 Slot 0 Left ADC", but "AIF1 Slot 0 Left ADC" would be a no-op widget)
- Something else entirely
I'm not sure this is really a concern here. We need to maintain the compatibility with old DT's, but those will have an A33 compatible too, and as far as I can see, you're not changing anything for that compatible, so we're in the clear?
If not, then the third option would probably be the best, especially since it's only a couple of them.
Unfortunately the description for both chips are shared, and they're wrong. So we probably need a new compatible (or a new driver)... or like options 2 or 3, keep the DT visible endpoints (but deprecate them), and route them to a new set of proper widgets.
ChenYu
On Mon, Feb 17, 2020 at 05:44:36PM +0800, Chen-Yu Tsai wrote:
On Mon, Feb 17, 2020 at 5:14 PM Maxime Ripard maxime@cerno.tech wrote:
Hi,
On Mon, Feb 17, 2020 at 12:42:16AM -0600, Samuel Holland wrote:
The sun8i-codec driver, as used in the Allwinner A33 and A64, currently only exposes a small subset of the available hardware features. In order to use the A64 in a smartphone (the PinePhone), I've added the necessary functionality to the driver:
- The full set of supported DAI format options
- Support for AIF2 and AIF3
- Additional routing knobs
- Additional volume controls
Unfortunately, due to preexisting issues with the driver, there are some breaking changes, as explained further in the commit messages:
- The LRCK inversion issue means we need a new compatible for the A64.
- Some controls are named inaccurately, so they are renamed.
- Likewise, the DAPM widgets used in device trees were either named wrong, or the device trees were using the wrong widgets in the first place. (Specifically, the links between the analog codec and digital codec happen at the ADC and DAC, not AIF1.)
I tended to take the philosophy of "while I'm breaking things, I might as well do them right", so I've probably made a few more changes than absolutely necessary. I'm not sure about where all of the policy boundaries are, about how far I should go to maintain compatibility. For example, for the DT widget usage, I could:
- Rename everything and update the DTS files (which is what I did)
- Keep the old (misleading/wrong) name for the widgets, but repurpose them to work correctly (i.e. "ADC Left" would be named "AIF1 Slot 0 Left ADC", but it would work just like "ADC Left" does in this patchset)
- Keep the old widgets around as a compatibility layer, but add new widgets and update the in-tree DTS files to use them (i.e. "ADC Left" would have a path from "AIF1 Slot 0 Left ADC", but "AIF1 Slot 0 Left ADC" would be a no-op widget)
- Something else entirely
I'm not sure this is really a concern here. We need to maintain the compatibility with old DT's, but those will have an A33 compatible too, and as far as I can see, you're not changing anything for that compatible, so we're in the clear?
If not, then the third option would probably be the best, especially since it's only a couple of them.
Unfortunately the description for both chips are shared, and they're wrong. So we probably need a new compatible (or a new driver)... or like options 2 or 3, keep the DT visible endpoints (but deprecate them), and route them to a new set of proper widgets.
And hmm, it might be a bit wild, but since it's basically just a sed on a string in DT, can't we leverage the dynamic DT stuff to rewrite the property if we find the old one at probe? That would keep the driver clean.
Maxime
On Mon, Feb 17, 2020 at 12:42:16AM -0600, Samuel Holland wrote:
There are several trivial fixes in here, and there are several commits that just add new features without changing any existing behavior, but there is enough changing that I thought it would be best to send the whole thing as an RFC. I'm more than happy to reorganize this into one or several patchsets in future revisions. It doesn't have to all go in at once.
This could definitely use being both split up and reordered, it's a 34 patch series as things stand which is just far too big and I don't understand the ordering within the series - there's a mix of fixes, cleanups and new features which should come in that order but don't. This makes it difficult to get a handle on what's going on because what the series is doing jumps about a lot. There's also a lot of overuse of fixes tags and stable tags which also makes things less clear. I'd suggest first sending all the clear fixes as a separate series with the cleanups and new functionality separate.
With regard to the ABI breaks they *may* be OK for mainline if we're confident that there's not going to be anyone broken by them but we should be looking to maintain compatibility if we can even if that's the case.
participants (5)
-
Chen-Yu Tsai -
Mark Brown -
Maxime Ripard -
Rob Herring -
Samuel Holland