[PATCH 00/10] Introduce STM32 Firewall framework
Introduce STM32 Firewall framework for STM32MP1x and STM32MP2x platforms. STM32MP1x(ETZPC) and STM32MP2x(RIFSC) Firewall controllers register to the framework to offer firewall services such as access granting.
This series of patches is a new approach on the previous STM32 system bus, history is available here: https://lore.kernel.org/lkml/20230127164040.1047583/
The need for such framework arises from the fact that there are now multiple hardware firewalls implemented across multiple products. Drivers are shared between different products, using the same code. When it comes to firewalls, the purpose mostly stays the same: Protect hardware resources. But the implementation differs, and there are multiple types of firewalls: peripheral, memory, ...
Some hardware firewall controllers such as the RIFSC implemented on STM32MP2x platforms may require to take ownership of a resource before being able to use it, hence the requirement for firewall services to take/release the ownership of such resources.
On the other hand, hardware firewall configurations are becoming more and more complex. These mecanisms prevent platform crashes or other firewall-related incoveniences by denying access to some resources.
The stm32 firewall framework offers an API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
For every peripherals protected by either the ETZPC or the RIFSC, the firewall framework checks the firewall controlelr registers to see if the peripheral's access is granted to the Linux kernel. If not, the peripheral is configured as secure, the node is marked populated, so that the driver is not probed for that device.
The firewall framework relies on the feature-domain-controller device tree bindings: https://lore.kernel.org/lkml/0c0a82bb-18ae-d057-562b. It is used by peripherals to reference a domain controller, in this case a firewall feature domain. The bus uses the ID referenced by the feature-domains property to know where to look in the firewall to get the security configuration for the peripheral. This allows a device tree description rather than a hardcoded peripheral table in the bus driver.
The STM32 ETZPC device is responsible for filtering accesses based on security level, or co-processor isolation for any resource connected to it.
The RIFSC is responsible for filtering accesses based on Compartment ID / security level / privilege level for any resource connected to it.
STM32MP13/15/25 SoC device tree files are updated in this series to implement this mecanism.
Oleksii Moisieiev (1): dt-bindings: Document common device controller bindings
Gatien Chevallier (9): dt-bindings: bus: add device tree bindings for RIFSC dt-bindings: bus: add device tree bindings for ETZPC dt-bindings: treewide: add feature-domains description in binding files firewall: introduce stm32_firewall framework bus: rifsc: introduce RIFSC firewall controller driver arm64: dts: st: add RIFSC as a domain controller for STM32MP25x boards bus: etzpc: introduce ETZPC firewall controller driver ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
.../bindings/bus/st,stm32-etzpc.yaml | 90 + .../bindings/bus/st,stm32-rifsc.yaml | 101 + .../bindings/crypto/st,stm32-hash.yaml | 4 + .../devicetree/bindings/dma/st,stm32-dma.yaml | 4 + .../bindings/dma/st,stm32-dmamux.yaml | 4 + .../feature-domain-controller.yaml | 84 + .../devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 + .../bindings/iio/adc/st,stm32-adc.yaml | 4 + .../bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 + .../bindings/iio/dac/st,stm32-dac.yaml | 4 + .../bindings/media/cec/st,stm32-cec.yaml | 4 + .../bindings/media/st,stm32-dcmi.yaml | 4 + .../memory-controllers/st,stm32-fmc2-ebi.yaml | 4 + .../bindings/mfd/st,stm32-lptimer.yaml | 4 + .../bindings/mfd/st,stm32-timers.yaml | 5 + .../devicetree/bindings/mmc/arm,pl18x.yaml | 4 + .../devicetree/bindings/net/stm32-dwmac.yaml | 4 + .../bindings/phy/phy-stm32-usbphyc.yaml | 4 + .../bindings/regulator/st,stm32-vrefbuf.yaml | 4 + .../devicetree/bindings/rng/st,stm32-rng.yaml | 4 + .../bindings/serial/st,stm32-uart.yaml | 4 + .../bindings/sound/st,stm32-i2s.yaml | 4 + .../bindings/sound/st,stm32-sai.yaml | 4 + .../bindings/sound/st,stm32-spdifrx.yaml | 4 + .../bindings/spi/st,stm32-qspi.yaml | 4 + .../devicetree/bindings/spi/st,stm32-spi.yaml | 4 + .../devicetree/bindings/usb/dwc2.yaml | 4 + MAINTAINERS | 7 + arch/arm/boot/dts/st/stm32mp131.dtsi | 1027 +++--- arch/arm/boot/dts/st/stm32mp133.dtsi | 51 +- arch/arm/boot/dts/st/stm32mp13xc.dtsi | 19 +- arch/arm/boot/dts/st/stm32mp13xf.dtsi | 19 +- arch/arm/boot/dts/st/stm32mp151.dtsi | 2757 +++++++++-------- arch/arm/boot/dts/st/stm32mp153.dtsi | 52 +- arch/arm/boot/dts/st/stm32mp15xc.dtsi | 19 +- arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/st/stm32mp251.dtsi | 5 +- drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_etzpc.c | 137 + drivers/bus/stm32_firewall.c | 252 ++ drivers/bus/stm32_firewall.h | 83 + drivers/bus/stm32_rifsc.c | 248 ++ include/linux/bus/stm32_firewall_device.h | 134 + 44 files changed, 3276 insertions(+), 1918 deletions(-) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml create mode 100644 drivers/bus/stm32_etzpc.c create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 drivers/bus/stm32_rifsc.c create mode 100644 include/linux/bus/stm32_firewall_device.h
From: Oleksii Moisieiev Oleksii_Moisieiev@epam.com
Introducing of the common device controller bindings for the controller provider and consumer devices. Those bindings are intended to allow divided system on chip into muliple domains, that can be used to configure hardware permissions.
Signed-off-by: Oleksii Moisieiev oleksii_moisieiev@epam.com ---
Depends-on: https://lore.kernel.org/lkml/c869d2751125181a55bc8a88c96e3a892b42f37a.166807...
.../feature-domain-controller.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
diff --git a/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml new file mode 100644 index 000000000000..90a7c38c833c --- /dev/null +++ b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/feature-controllers/feature-domain-controller.... +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Domain Controller bindings + +maintainers: + - Oleksii Moisieiev oleksii_moisieiev@epam.com + +description: |+ + Common Feature Domains Controller bindings properties + + Domain controllers allow to divided system on chip into multiple feature + domains that can be used to select by who hardware blocks could be accessed. + A feature domain could be a cluster of CPUs (or coprocessors), a range of + addresses or a group of hardware blocks. + + This device tree bindings can be used to bind feature domain consumer devices + with their feature domains provided by feature-domains controllers. + Feature omain controller provider can be represened by any node in the + device tree and can provide one or more configuration parameters, needed to + control parameters of the consumer device. A consumer node can refer to the + provider by phandle and a set of phandle arguments, specified by + '#feature-domain-cells' property in the device controller provider node. + + Device controllers are typically used to set the permissions of the hardware + block. The contents of the feature-domains configuration properties are + defined by the binding for the individual feature-domains controller device. + + Each node can be a consumer for the several providers. The first + configuration of 'feature-domains' or the one named 'default' is applied + before probing the device itself. + +# always select the core schema +select: true + +properties: + '#feature-domain-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of cells in a feature-domains controller specifier; + Can be any value as specified by device tree binding documentation + of a particular provider. + + feature-domain-controller: + description: + Indicates that the node is feature-domain-controller provider. + + feature-domain-names: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: + A list of feature-domains names, sorted in the same order as + feature-domains entries. Consumer drivers will use feature-domain-names + to match with existing feature-domains entries. + + feature-domains: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + A list of feature-domains controller specifiers, as defined by the + bindings of the feature-domain-controller provider. + +additionalProperties: true + +examples: + - | + ctrl0: ctrl@100 { + feature-domain-controller; + reg = <0x100 0x10>; + #feature-domain-cells = <2>; + }; + + ctrl1: ctrl@110 { + feature-domain-controller; + reg = <0x110 0x10>; + #feature-domain-cells = <3>; + }; + + foo@0 { + reg = <0x0 0x1>; + feature-domains = <&ctrl0 1 2>, <&ctrl1 3 4 5>; + feature-domain-names = "default", "unbind"; + };
On Wed, 05 Jul 2023 19:27:50 +0200, Gatien Chevallier wrote:
From: Oleksii Moisieiev Oleksii_Moisieiev@epam.com
Introducing of the common device controller bindings for the controller provider and consumer devices. Those bindings are intended to allow divided system on chip into muliple domains, that can be used to configure hardware permissions.
Signed-off-by: Oleksii Moisieiev oleksii_moisieiev@epam.com
Depends-on: https://lore.kernel.org/lkml/c869d2751125181a55bc8a88c96e3a892b42f37a.166807...
.../feature-domain-controller.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml: title: 'Generic Domain Controller bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'} hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for. from schema $id: http://devicetree.org/meta-schemas/core.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/2023070517275...
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com --- .../bindings/bus/st,stm32-rifsc.yaml | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml new file mode 100644 index 000000000000..68d585ed369c --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Resource isolation framework security controller bindings + +maintainers: + - Gatien Chevallier gatien.chevallier@foss.st.com + +description: | + Resource isolation framework (RIF) is a comprehensive set of hardware blocks + designed to enforce and manage isolation of STM32 hardware resources like + memory and peripherals. + + The RIFSC (RIF security controller) is composed of three sets of registers, + each managing a specific set of hardware resources: + - RISC registers associated with RISUP logic (resource isolation device unit + for peripherals), assign all non-RIF aware peripherals to zero, one or + any security domains (secure, privilege, compartment). + - RIMC registers: associated with RIMU logic (resource isolation master + unit), assign all non RIF-aware bus master to one security domain by + setting secure, privileged and compartment information on the system bus. + Alternatively, the RISUP logic controlling the device port access to a + peripheral can assign target bus attributes to this peripheral master port + (supported attribute: CID). + - RISC registers associated with RISAL logic (resource isolation device unit + for address space - Lite version), assign address space subregions to one + security domains (secure, privilege, compartment). + +properties: + compatible: + const: st,stm32mp25-rifsc + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#feature-domain-cells": + const: 1 + + ranges: true + + feature-domain-controller: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + properties: + feature-domains: + minItems: 1 + maxItems: 2 + description: + The first argument must always be a phandle that references to the + firewall controller of the peripheral. The second can contain the + platform specific firewall ID of the peripheral. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - feature-domain-controller + - "#feature-domain-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its domain + // controller. + // Access rights are verified before creating devices. + + #include <dt-bindings/interrupt-controller/arm-gic.h> + + rifsc: rifsc-bus@42080000 { + compatible = "st,stm32mp25-rifsc"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + feature-domain-controller; + #feature-domain-cells = <1>; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_flexgen_08>; + feature-domains = <&rifsc 32>; + status = "disabled"; + }; + };
On Wed, 05 Jul 2023 19:27:51 +0200, Gatien Chevallier wrote:
Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
.../bindings/bus/st,stm32-rifsc.yaml | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml: title: 'STM32 Resource isolation framework security controller bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'} hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for. from schema $id: http://devicetree.org/meta-schemas/core.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/2023070517275...
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 05/07/2023 19:27, Gatien Chevallier wrote:
Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
A nit, subject: drop second/last, redundant "device tree bindings for". The "dt-bindings" prefix is already stating that these are bindings. 4 words of your 6 word subject is meaningless...
.../bindings/bus/st,stm32-rifsc.yaml | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml new file mode 100644 index 000000000000..68d585ed369c --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml
Filename like compatible, unless you know list of compatibles will grow... but then add them.
@@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: STM32 Resource isolation framework security controller bindings
Drop bindings
+maintainers:
- Gatien Chevallier gatien.chevallier@foss.st.com
+description: |
- Resource isolation framework (RIF) is a comprehensive set of hardware blocks
- designed to enforce and manage isolation of STM32 hardware resources like
- memory and peripherals.
- The RIFSC (RIF security controller) is composed of three sets of registers,
- each managing a specific set of hardware resources:
- RISC registers associated with RISUP logic (resource isolation device unit
for peripherals), assign all non-RIF aware peripherals to zero, one orany security domains (secure, privilege, compartment).
- RIMC registers: associated with RIMU logic (resource isolation master
unit), assign all non RIF-aware bus master to one security domain bysetting secure, privileged and compartment information on the system bus.Alternatively, the RISUP logic controlling the device port access to aperipheral can assign target bus attributes to this peripheral master port(supported attribute: CID).
- RISC registers associated with RISAL logic (resource isolation device unit
for address space - Lite version), assign address space subregions to onesecurity domains (secure, privilege, compartment).+properties:
- compatible:
- const: st,stm32mp25-rifsc
- reg:
- maxItems: 1
- "#address-cells":
- const: 1
- "#size-cells":
- const: 1
- "#feature-domain-cells":
- const: 1
- ranges: true
- feature-domain-controller: true
+patternProperties:
- "^.*@[0-9a-f]+$":
- description: Peripherals
- type: object
- properties:
feature-domains:minItems: 1maxItems: 2description:The first argument must always be a phandle that references to thefirewall controller of the peripheral. The second can contain theplatform specific firewall ID of the peripheral.
It does not make much sense to me to have hierarchy parent-child and via phandle at the same time. You express the similar relationship twice.
+required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- feature-domain-controller
- "#feature-domain-cells"
- ranges
+additionalProperties: false
+examples:
- |
- // In this example, the usart2 device refers to rifsc as its domain
- // controller.
- // Access rights are verified before creating devices.
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- rifsc: rifsc-bus@42080000 {
compatible = "st,stm32mp25-rifsc";reg = <0x42080000 0x1000>;#address-cells = <1>;#size-cells = <1>;ranges;feature-domain-controller;#feature-domain-cells = <1>;usart2: serial@400e0000 {compatible = "st,stm32h7-uart";reg = <0x400e0000 0x400>;interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;clocks = <&ck_flexgen_08>;feature-domains = <&rifsc 32>;status = "disabled";
No status in the examples.
};- };
Best regards, Krzysztof
Hello Krzysztof,
Firstly, I will correct the bindings error pointed by Rob's robot. Obviously, I did not pass the bindings check the proper way or maybe I'm running an old version.
On 7/6/23 08:28, Krzysztof Kozlowski wrote:
On 05/07/2023 19:27, Gatien Chevallier wrote:
Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
A nit, subject: drop second/last, redundant "device tree bindings for". The "dt-bindings" prefix is already stating that these are bindings. 4 words of your 6 word subject is meaningless...
Ack, I will rephrase, it is indeed redundant
.../bindings/bus/st,stm32-rifsc.yaml | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml new file mode 100644 index 000000000000..68d585ed369c --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml
Filename like compatible, unless you know list of compatibles will grow... but then add them.
@@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: STM32 Resource isolation framework security controller bindings
Drop bindings
Ack
+maintainers:
- Gatien Chevallier gatien.chevallier@foss.st.com
+description: |
- Resource isolation framework (RIF) is a comprehensive set of hardware blocks
- designed to enforce and manage isolation of STM32 hardware resources like
- memory and peripherals.
- The RIFSC (RIF security controller) is composed of three sets of registers,
- each managing a specific set of hardware resources:
- RISC registers associated with RISUP logic (resource isolation device unit
for peripherals), assign all non-RIF aware peripherals to zero, one orany security domains (secure, privilege, compartment).
- RIMC registers: associated with RIMU logic (resource isolation master
unit), assign all non RIF-aware bus master to one security domain bysetting secure, privileged and compartment information on the system bus.Alternatively, the RISUP logic controlling the device port access to aperipheral can assign target bus attributes to this peripheral master port(supported attribute: CID).
- RISC registers associated with RISAL logic (resource isolation device unit
for address space - Lite version), assign address space subregions to onesecurity domains (secure, privilege, compartment).+properties:
- compatible:
- const: st,stm32mp25-rifsc
- reg:
- maxItems: 1
- "#address-cells":
- const: 1
- "#size-cells":
- const: 1
- "#feature-domain-cells":
- const: 1
- ranges: true
- feature-domain-controller: true
+patternProperties:
- "^.*@[0-9a-f]+$":
- description: Peripherals
- type: object
- properties:
feature-domains:minItems: 1maxItems: 2description:The first argument must always be a phandle that references to thefirewall controller of the peripheral. The second can contain theplatform specific firewall ID of the peripheral.It does not make much sense to me to have hierarchy parent-child and via phandle at the same time. You express the similar relationship twice
Thank you for pointing this out.
About the parent-child relation:
The bus-like device tree architecture allows a bus-probe mechanism with which we want to check accesses of peripherals before probing their driver. This has several advantages: -This bus architecture provides a clearer view of the hardware. -No peripheral driver modifications as it is fully handled by the firewall drivers. -Drivers for devices that aren't accessible will not even be probed => no probe fail.
It would be possible to manage this mechanism another way by handling probe deferrals in drivers. But it would mean modifying every driver with a check on ST firewall that we probe and some of them aren't from STMicroelectronics.
About the phandle relation:
I agree on the fact that this double expression of the relationship is redundant.
I've done it this way because there will be other nodes outside the RIFSC node that will need to reference it as their feature-domain controller. I kept the same information in the property to be coherent between all.
For nodes under the RIFSC, the phandle is indeed useless and could be removed, just to leave the firewall ID. And I'm inclined to do so. I just have one worry on the YAML binding files where I will have a pattern property in the RIFSC that will state something and maybe another description in the peripheral YAML files. What is your take on that?
+required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- feature-domain-controller
- "#feature-domain-cells"
- ranges
+additionalProperties: false
+examples:
- |
- // In this example, the usart2 device refers to rifsc as its domain
- // controller.
- // Access rights are verified before creating devices.
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- rifsc: rifsc-bus@42080000 {
compatible = "st,stm32mp25-rifsc";reg = <0x42080000 0x1000>;#address-cells = <1>;#size-cells = <1>;ranges;feature-domain-controller;#feature-domain-cells = <1>;usart2: serial@400e0000 {compatible = "st,stm32h7-uart";reg = <0x400e0000 0x400>;interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;clocks = <&ck_flexgen_08>;feature-domains = <&rifsc 32>;status = "disabled";No status in the examples.
};- };
Best regards, Krzysztof
Best regards, Gatien
Hello Krzysztof,
On 7/6/23 11:29, Gatien CHEVALLIER wrote:
Hello Krzysztof,
Firstly, I will correct the bindings error pointed by Rob's robot. Obviously, I did not pass the bindings check the proper way or maybe I'm running an old version.
On 7/6/23 08:28, Krzysztof Kozlowski wrote:
On 05/07/2023 19:27, Gatien Chevallier wrote:
Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
A nit, subject: drop second/last, redundant "device tree bindings for". The "dt-bindings" prefix is already stating that these are bindings. 4 words of your 6 word subject is meaningless...
Ack, I will rephrase, it is indeed redundant
.../bindings/bus/st,stm32-rifsc.yaml         | 101 ++++++++++++++++++  1 file changed, 101 insertions(+)  create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml new file mode 100644 index 000000000000..68d585ed369c --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32-rifsc.yaml
Filename like compatible, unless you know list of compatibles will grow... but then add them.
@@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: STM32 Resource isolation framework security controller bindings
Drop bindings
Ack
+maintainers: +Â - Gatien Chevallier gatien.chevallier@foss.st.com
+description: | +Â Resource isolation framework (RIF) is a comprehensive set of hardware blocks +Â designed to enforce and manage isolation of STM32 hardware resources like +Â memory and peripherals.
+Â The RIFSC (RIF security controller) is composed of three sets of registers, +Â each managing a specific set of hardware resources: +Â Â Â - RISC registers associated with RISUP logic (resource isolation device unit +Â Â Â Â Â for peripherals), assign all non-RIF aware peripherals to zero, one or +Â Â Â Â Â any security domains (secure, privilege, compartment). +Â Â Â - RIMC registers: associated with RIMU logic (resource isolation master +Â Â Â Â Â unit), assign all non RIF-aware bus master to one security domain by +Â Â Â Â Â setting secure, privileged and compartment information on the system bus. +Â Â Â Â Â Alternatively, the RISUP logic controlling the device port access to a +Â Â Â Â Â peripheral can assign target bus attributes to this peripheral master port +Â Â Â Â Â (supported attribute: CID). +Â Â Â - RISC registers associated with RISAL logic (resource isolation device unit +Â Â Â Â Â for address space - Lite version), assign address space subregions to one +Â Â Â Â Â security domains (secure, privilege, compartment).
+properties: +Â compatible: +Â Â Â const: st,stm32mp25-rifsc
+Â reg: +Â Â Â maxItems: 1
+Â "#address-cells": +Â Â Â const: 1
+Â "#size-cells": +Â Â Â const: 1
+Â "#feature-domain-cells": +Â Â Â const: 1
+Â ranges: true
+Â feature-domain-controller: true
+patternProperties: +Â "^.*@[0-9a-f]+$": +Â Â Â description: Peripherals +Â Â Â type: object +Â Â Â properties: +Â Â Â Â Â feature-domains: +Â Â Â Â Â Â Â minItems: 1 +Â Â Â Â Â Â Â maxItems: 2 +Â Â Â Â Â Â Â description: +Â Â Â Â Â Â Â Â Â The first argument must always be a phandle that references to the +Â Â Â Â Â Â Â Â Â firewall controller of the peripheral. The second can contain the +Â Â Â Â Â Â Â Â Â platform specific firewall ID of the peripheral.
It does not make much sense to me to have hierarchy parent-child and via phandle at the same time. You express the similar relationship twice
Thank you for pointing this out.
About the parent-child relation:
The bus-like device tree architecture allows a bus-probe mechanism with which we want to check accesses of peripherals before probing their driver. This has several advantages: -This bus architecture provides a clearer view of the hardware. -No peripheral driver modifications as it is fully handled by the firewall drivers. -Drivers for devices that aren't accessible will not even be probed => no probe fail.
It would be possible to manage this mechanism another way by handling probe deferrals in drivers. But it would mean modifying every driver with a check on ST firewall that we probe and some of them aren't from STMicroelectronics.
About the phandle relation:
I agree on the fact that this double expression of the relationship is redundant.
I've done it this way because there will be other nodes outside the RIFSC node that will need to reference it as their feature-domain controller. I kept the same information in the property to be coherent between all.
For nodes under the RIFSC, the phandle is indeed useless and could be removed, just to leave the firewall ID. And I'm inclined to do so. I just have one worry on the YAML binding files where I will have a pattern property in the RIFSC that will state something and maybe another description in the peripheral YAML files. What is your take on that?
Looking back at it, feature-domains is a phandle-array. I guess I can't derogate to the following architecture:
items: - items: - description: A phandle - description: 1st arg cell - description: 2nd arg cell
can I?
Some devices' nodes that are not subnodes of the firewall controllers will need the phandle reference. Should I keep the redundant information then?
Best regards, Gatien
+required: +Â - compatible +Â - reg +Â - "#address-cells" +Â - "#size-cells" +Â - feature-domain-controller +Â - "#feature-domain-cells" +Â - ranges
+additionalProperties: false
+examples: +Â - | +Â Â Â // In this example, the usart2 device refers to rifsc as its domain +Â Â Â // controller. +Â Â Â // Access rights are verified before creating devices.
+Â Â Â #include <dt-bindings/interrupt-controller/arm-gic.h>
+Â Â Â rifsc: rifsc-bus@42080000 { +Â Â Â Â Â Â Â compatible = "st,stm32mp25-rifsc"; +Â Â Â Â Â Â Â reg = <0x42080000 0x1000>; +Â Â Â Â Â Â Â #address-cells = <1>; +Â Â Â Â Â Â Â #size-cells = <1>; +Â Â Â Â Â Â Â ranges; +Â Â Â Â Â Â Â feature-domain-controller; +Â Â Â Â Â Â Â #feature-domain-cells = <1>;
+Â Â Â Â Â Â Â usart2: serial@400e0000 { +Â Â Â Â Â Â Â Â Â Â Â compatible = "st,stm32h7-uart"; +Â Â Â Â Â Â Â Â Â Â Â reg = <0x400e0000 0x400>; +Â Â Â Â Â Â Â Â Â Â Â interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; +Â Â Â Â Â Â Â Â Â Â Â clocks = <&ck_flexgen_08>; +Â Â Â Â Â Â Â Â Â Â Â feature-domains = <&rifsc 32>; +Â Â Â Â Â Â Â Â Â Â Â status = "disabled";
No status in the examples.
+Â Â Â Â Â Â Â }; +Â Â Â };
Best regards, Krzysztof
Best regards, Gatien
Document ETZPC (Extended TrustZone protection controller). ETZPC is a firewall controller.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com --- .../bindings/bus/st,stm32-etzpc.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml new file mode 100644 index 000000000000..327fb0b84c0b --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Extended TrustZone protection controller bindings + +description: | + The ETZPC configures TrustZone security in a SoC having bus masters and + devices with programmable-security attributes (securable resources). + +maintainers: + - Gatien Chevallier gatien.chevallier@foss.st.com + +properties: + compatible: + const: "st,stm32-etzpc" + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + feature-domain-controller: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + properties: + feature-domains: + minItems: 1 + maxItems: 2 + description: + The first argument must always be a phandle that references to the + firewall controller of the peripheral. The second can contain the + platform specific firewall ID of the peripheral. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - feature-domain-controller + - "#feature-domain-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its domain + // controller. + // Access rights are verified before creating devices. + + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp13-clks.h> + #include <dt-bindings/reset/stm32mp13-resets.h> + + etzpc: etzpc@5c007000 { + compatible = "st,stm32mp13-sys-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + feature-domain-controller; + #feature-domain-cells = <1>; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 17>; + status = "disabled"; + }; + };
On Wed, 05 Jul 2023 19:27:52 +0200, Gatien Chevallier wrote:
Document ETZPC (Extended TrustZone protection controller). ETZPC is a firewall controller.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
.../bindings/bus/st,stm32-etzpc.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml: title: 'STM32 Extended TrustZone protection controller bindings' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'} hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for. from schema $id: http://devicetree.org/meta-schemas/core.yaml# Documentation/devicetree/bindings/bus/st,stm32-etzpc.example.dtb: /example-0/etzpc@5c007000: failed to match any schema with compatible: ['st,stm32mp13-sys-bus']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/2023070517275...
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com ---
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml index 329847ef096a..2236ac95574b 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -82,6 +82,10 @@ properties: description: if defined, it indicates that the controller supports memory-to-memory transfer
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml index e722fbcd8a5f..47ae890f5bd9 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml @@ -28,6 +28,10 @@ properties: resets: maxItems: 1
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index 94b75d9f66cd..326a96741f50 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -99,6 +99,10 @@ properties:
wakeup-source: true
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index 995cbf8cefc6..3eb20d67f0fc 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -93,6 +93,10 @@ properties: '#size-cells': const: 0
+ feature-domains: + minItems: 1 + maxItems: 3 + allOf: - if: properties: diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 1970503389aa..bc34ae172417 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -59,6 +59,10 @@ properties: If not, SPI CLKOUT frequency will not be accurate. maximum: 20000000
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml index 04045b932bd2..90d35a2a6504 100644 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -45,6 +45,10 @@ properties: '#size-cells': const: 0
+ feature-domains: + minItems: 1 + maxItems: 3 + additionalProperties: false
required: diff --git a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml index 2314a9a14650..f88e3c0e6175 100644 --- a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml @@ -29,6 +29,10 @@ properties: - const: cec - const: hdmi-cec
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index 6b3e413cedb2..4fa1d14910df 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -36,6 +36,10 @@ properties: resets: maxItems: 1
+ feature-domains: + minItems: 1 + maxItems: 3 + port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 14f1833d37c9..63b3d012147b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -45,6 +45,10 @@ properties: Reflects the memory layout with four integer values per bank. Format: <bank-number> 0 <address of the bank> <size>
+ feature-domains: + minItems: 1 + maxItems: 3 + patternProperties: "^.*@[0-4],[a-f0-9]+$": additionalProperties: true diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index 27329c5dc38e..59d770544950 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -44,6 +44,10 @@ properties:
wakeup-source: true
+ feature-domains: + minItems: 1 + maxItems: 3 + pwm: type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index f84e09a5743b..d5ad097e94ec 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -67,6 +67,11 @@ properties: "#size-cells": const: 0
+ feature-domains: + minItems: 1 + maxItems: 3 + + pwm: type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml index 2459a55ed540..6ebedee65153 100644 --- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml +++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml @@ -79,6 +79,10 @@ properties: - const: rx - const: tx
+ feature-domains: + minItems: 1 + maxItems: 3 + power-domains: true
resets: diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index fc8c96b08d7d..0e408dc85c13 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -93,6 +93,10 @@ properties: select RCC clock instead of ETH_REF_CLK. type: boolean
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 24a3dbde223b..b9ac20c8bf05 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -55,6 +55,10 @@ properties: description: number of clock cells for ck_usbo_48m consumer const: 0
+ feature-domains: + minItems: 1 + maxItems: 3 + # Required child nodes:
patternProperties: diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml index 05f4ad2c7d3a..02cefe4ef42b 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml @@ -30,6 +30,10 @@ properties: vdda-supply: description: phandle to the vdda input analog voltage.
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml index 187b172d0cca..79eb5f5bd252 100644 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml +++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml @@ -30,6 +30,10 @@ properties: type: boolean description: If set enable the clock detection management
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 1df8ffe95fc6..893978e7170f 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -70,6 +70,10 @@ properties: enum: [1, 2, 4, 8, 12, 14, 16] default: 8
+ feature-domains: + minItems: 1 + maxItems: 3 + allOf: - $ref: rs485.yaml# - $ref: serial.yaml# diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml index b9111d375b93..64c5898e51f8 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml @@ -65,6 +65,10 @@ properties: $ref: audio-graph-port.yaml# unevaluatedProperties: false
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - "#sound-dai-cells" diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml index 56d206f97a96..9bc08b7645dc 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -48,6 +48,10 @@ properties: clock-names: maxItems: 3
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml index bc48151b9adb..f00e5db9ee3b 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml @@ -50,6 +50,10 @@ properties: resets: maxItems: 1
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - "#sound-dai-cells" diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml index 8bba965a9ae6..2ac136802467 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml @@ -46,6 +46,10 @@ properties: - const: tx - const: rx
+ feature-domains: + minItems: 1 + maxItems: 3 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index 9ca1a843c820..725c26daabe4 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -59,6 +59,10 @@ properties: - const: rx - const: tx
+ feature-domains: + minItems: 1 + maxItems: 3 + patternProperties: "^[a-zA-Z][a-zA-Z0-9,+\-._]{0,63}@[0-9a-f]+$": type: object diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index d3506090f8b1..c372caf154fc 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -171,6 +171,10 @@ properties:
tpl-support: true
+ feature-domains: + minItems: 1 + maxItems: 3 + dependencies: port: [ usb-role-switch ] role-switch-default-mode: [ usb-role-switch ]
On Wed, Jul 05, 2023 at 07:27:53PM +0200, Gatien Chevallier wrote:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
What are the 3 entries?
Rob
Hello Rob,
On 7/6/23 16:51, Rob Herring wrote:
On Wed, Jul 05, 2023 at 07:27:53PM +0200, Gatien Chevallier wrote:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
What are the 3 entries?
Rob
I thought I was benefiting from the description of the pattern-property in the RIFSC YAML file. But yes anyway, it seems like it needs some description here as the dependency does not appear in this file.
I picked 3 as a maxItems for our ST needs, I'll give it some more thought when coming back with something clearer.
I will change that in V2, thank you for pointing that out.
Best regards, Gatien
On Fri, Jul 07, 2023 at 02:28:28PM +0200, Gatien CHEVALLIER wrote:
Hello Rob,
On 7/6/23 16:51, Rob Herring wrote:
On Wed, Jul 05, 2023 at 07:27:53PM +0200, Gatien Chevallier wrote:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
What are the 3 entries?
Rob
I thought I was benefiting from the description of the pattern-property in the RIFSC YAML file. But yes anyway, it seems like it needs some description here as the dependency does not appear in this file.
Humm, that should limit the maximum entries to 2, so 3 would never work (if RIFSC is the parent).
I picked 3 as a maxItems for our ST needs, I'll give it some more thought when coming back with something clearer.
I'd expect you have 1 entry for register bus and 1 entry for DMA bus if there is one. It's block specific for how many entries, so the RIFSC schema should not be setting that. You could possibly say that 'feature-domains' is required for all the child nodes though.
Rob
On 7/7/23 17:20, Rob Herring wrote:
On Fri, Jul 07, 2023 at 02:28:28PM +0200, Gatien CHEVALLIER wrote:
Hello Rob,
On 7/6/23 16:51, Rob Herring wrote:
On Wed, Jul 05, 2023 at 07:27:53PM +0200, Gatien Chevallier wrote:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
What are the 3 entries?
Rob
I thought I was benefiting from the description of the pattern-property in the RIFSC YAML file. But yes anyway, it seems like it needs some description here as the dependency does not appear in this file.
Humm, that should limit the maximum entries to 2, so 3 would never work (if RIFSC is the parent).
I picked 3 as a maxItems for our ST needs, I'll give it some more thought when coming back with something clearer.
I'd expect you have 1 entry for register bus and 1 entry for DMA bus if there is one. It's block specific for how many entries, so the RIFSC schema should not be setting that. You could possibly say that 'feature-domains' is required for all the child nodes though.
Ok, I will change to not specifying the number of entries in the RIFSC YAML file for V2.
Rob
Some hardware blocks may have a firewall ID for their device part and another ID for their master part as well. In the end, the number of entries could very well vary between different platforms. And the YAML files are common to these platforms.
This property could be used for "extra" arguments as well, that are not firewall IDs.
What do you suggest between picking a high maxItems value that would (hopefully) cover all cases and not specifying maxItems at all? Or maybe another property dedicated to such arguments?
Best regards, Gatien
On Mon, Jul 10, 2023 at 10:22:10AM +0200, Gatien CHEVALLIER wrote:
On 7/7/23 17:20, Rob Herring wrote:
On Fri, Jul 07, 2023 at 02:28:28PM +0200, Gatien CHEVALLIER wrote:
Hello Rob,
On 7/6/23 16:51, Rob Herring wrote:
On Wed, Jul 05, 2023 at 07:27:53PM +0200, Gatien Chevallier wrote:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
What are the 3 entries?
Rob
I thought I was benefiting from the description of the pattern-property in the RIFSC YAML file. But yes anyway, it seems like it needs some description here as the dependency does not appear in this file.
Humm, that should limit the maximum entries to 2, so 3 would never work (if RIFSC is the parent).
I picked 3 as a maxItems for our ST needs, I'll give it some more thought when coming back with something clearer.
I'd expect you have 1 entry for register bus and 1 entry for DMA bus if there is one. It's block specific for how many entries, so the RIFSC schema should not be setting that. You could possibly say that 'feature-domains' is required for all the child nodes though.
Ok, I will change to not specifying the number of entries in the RIFSC YAML file for V2.
Rob
Some hardware blocks may have a firewall ID for their device part and another ID for their master part as well. In the end, the number of entries could very well vary between different platforms. And the YAML files are common to these platforms.
A given device has a fixed number of buses. Usually 1 or 2. That does *not* vary by platform (unless the device is modified). You could have the same firewall controller and id for multiple buses, but that should not change the number of entries for the device. Now maybe a bus has no firewall on some platforms. In that case, you should make the optional firewall entry the last one, have a null phandle (0 or -1), or use -names to distinguish the entries.
This property could be used for "extra" arguments as well, that are not firewall IDs.
The arg cells are dictated by the provider and opaque to the client.
What do you suggest between picking a high maxItems value that would (hopefully) cover all cases and not specifying maxItems at all? Or maybe another property dedicated to such arguments?
You should not specify maxItems in the firewall controller binding.
Rob
Gatien Chevallier gatien.chevallier@foss.st.com writes:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
I beliewe feature-domains is generic binding. This means that maxItems can be implementation dependend. I would rather drop maxItems so the following format will be possible:
feature-domains = <&etzpc 1>, <&etzpc 2>, <&some_other_domain 1 2 3 4> feature-domain-names = "firewall 1", "firewall 2", "other_domain"
Also I beliewe driver will handle feature-domain-names property so it will parse feature-domains only related to the firewall.
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml index 329847ef096a..2236ac95574b 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -82,6 +82,10 @@ properties: description: if defined, it indicates that the controller supports memory-to-memory transfer
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml index e722fbcd8a5f..47ae890f5bd9 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml @@ -28,6 +28,10 @@ properties: resets: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index 94b75d9f66cd..326a96741f50 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -99,6 +99,10 @@ properties:
wakeup-source: true
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index 995cbf8cefc6..3eb20d67f0fc 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -93,6 +93,10 @@ properties: '#size-cells': const: 0
- feature-domains:
- minItems: 1
- maxItems: 3
allOf:
- if: properties:
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 1970503389aa..bc34ae172417 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -59,6 +59,10 @@ properties: If not, SPI CLKOUT frequency will not be accurate. maximum: 20000000
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml index 04045b932bd2..90d35a2a6504 100644 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -45,6 +45,10 @@ properties: '#size-cells': const: 0
- feature-domains:
- minItems: 1
- maxItems: 3
additionalProperties: false
required: diff --git a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml index 2314a9a14650..f88e3c0e6175 100644 --- a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml @@ -29,6 +29,10 @@ properties: - const: cec - const: hdmi-cec
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index 6b3e413cedb2..4fa1d14910df 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -36,6 +36,10 @@ properties: resets: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
- port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 14f1833d37c9..63b3d012147b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -45,6 +45,10 @@ properties: Reflects the memory layout with four integer values per bank. Format: <bank-number> 0 <address of the bank> <size>
- feature-domains:
- minItems: 1
- maxItems: 3
patternProperties: "^.*@[0-4],[a-f0-9]+$": additionalProperties: true diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index 27329c5dc38e..59d770544950 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -44,6 +44,10 @@ properties:
wakeup-source: true
- feature-domains:
- minItems: 1
- maxItems: 3
- pwm: type: object additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index f84e09a5743b..d5ad097e94ec 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -67,6 +67,11 @@ properties: "#size-cells": const: 0
- feature-domains:
- minItems: 1
- maxItems: 3
- pwm: type: object additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml index 2459a55ed540..6ebedee65153 100644 --- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml +++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml @@ -79,6 +79,10 @@ properties: - const: rx - const: tx
feature-domains:
minItems: 1
maxItems: 3
power-domains: true
resets:
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index fc8c96b08d7d..0e408dc85c13 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -93,6 +93,10 @@ properties: select RCC clock instead of ETH_REF_CLK. type: boolean
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- clocks
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 24a3dbde223b..b9ac20c8bf05 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -55,6 +55,10 @@ properties: description: number of clock cells for ck_usbo_48m consumer const: 0
- feature-domains:
- minItems: 1
- maxItems: 3
# Required child nodes:
patternProperties: diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml index 05f4ad2c7d3a..02cefe4ef42b 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml @@ -30,6 +30,10 @@ properties: vdda-supply: description: phandle to the vdda input analog voltage.
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml index 187b172d0cca..79eb5f5bd252 100644 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml +++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml @@ -30,6 +30,10 @@ properties: type: boolean description: If set enable the clock detection management
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 1df8ffe95fc6..893978e7170f 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -70,6 +70,10 @@ properties: enum: [1, 2, 4, 8, 12, 14, 16] default: 8
- feature-domains:
- minItems: 1
- maxItems: 3
allOf:
- $ref: rs485.yaml#
- $ref: serial.yaml#
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml index b9111d375b93..64c5898e51f8 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml @@ -65,6 +65,10 @@ properties: $ref: audio-graph-port.yaml# unevaluatedProperties: false
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml index 56d206f97a96..9bc08b7645dc 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -48,6 +48,10 @@ properties: clock-names: maxItems: 3
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml index bc48151b9adb..f00e5db9ee3b 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml @@ -50,6 +50,10 @@ properties: resets: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml index 8bba965a9ae6..2ac136802467 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml @@ -46,6 +46,10 @@ properties: - const: tx - const: rx
- feature-domains:
- minItems: 1
- maxItems: 3
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index 9ca1a843c820..725c26daabe4 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -59,6 +59,10 @@ properties: - const: rx - const: tx
- feature-domains:
- minItems: 1
- maxItems: 3
patternProperties: "^[a-zA-Z][a-zA-Z0-9,+\-._]{0,63}@[0-9a-f]+$": type: object diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index d3506090f8b1..c372caf154fc 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -171,6 +171,10 @@ properties:
tpl-support: true
- feature-domains:
- minItems: 1
- maxItems: 3
dependencies: port: [ usb-role-switch ] role-switch-default-mode: [ usb-role-switch ]
On 7/7/23 16:07, Oleksii Moisieiev wrote:
Gatien Chevallier gatien.chevallier@foss.st.com writes:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
I beliewe feature-domains is generic binding. This means that maxItems can be implementation dependend. I would rather drop maxItems so the following format will be possible:
feature-domains = <&etzpc 1>, <&etzpc 2>, <&some_other_domain 1 2 3 4> feature-domain-names = "firewall 1", "firewall 2", "other_domain"
I'd prefer to drop the maxItems as well. I've been told at one point in the first series to choose a number for this maybe picking a high but reasonnable number is preferrable.
Based on How to Get Your DT Schema Bindings Accepted in Less than 10 Iterations pdf published by Krzysztof, I see that examples use minItems/maxItems. But I can't find if it's mandatory
Also I beliewe driver will handle feature-domain-names property so it will parse feature-domains only related to the firewall.
Yep, in case of multiple feature-domains, it could be nice.
required: - compatible - reg diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml index 329847ef096a..2236ac95574b 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -82,6 +82,10 @@ properties: description: if defined, it indicates that the controller supports memory-to-memory transfer
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml index e722fbcd8a5f..47ae890f5bd9 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml @@ -28,6 +28,10 @@ properties: resets: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index 94b75d9f66cd..326a96741f50 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -99,6 +99,10 @@ properties:
wakeup-source: true
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index 995cbf8cefc6..3eb20d67f0fc 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -93,6 +93,10 @@ properties: '#size-cells': const: 0
- feature-domains:
- minItems: 1
- maxItems: 3
- allOf:
- if: properties:
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 1970503389aa..bc34ae172417 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -59,6 +59,10 @@ properties: If not, SPI CLKOUT frequency will not be accurate. maximum: 20000000
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml index 04045b932bd2..90d35a2a6504 100644 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -45,6 +45,10 @@ properties: '#size-cells': const: 0
feature-domains:
minItems: 1
maxItems: 3
additionalProperties: false
required:
diff --git a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml index 2314a9a14650..f88e3c0e6175 100644 --- a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml @@ -29,6 +29,10 @@ properties: - const: cec - const: hdmi-cec
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index 6b3e413cedb2..4fa1d14910df 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -36,6 +36,10 @@ properties: resets: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
- port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 14f1833d37c9..63b3d012147b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -45,6 +45,10 @@ properties: Reflects the memory layout with four integer values per bank. Format: <bank-number> 0 <address of the bank> <size>
- feature-domains:
- minItems: 1
- maxItems: 3
- patternProperties: "^.*@[0-4],[a-f0-9]+$": additionalProperties: true
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index 27329c5dc38e..59d770544950 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -44,6 +44,10 @@ properties:
wakeup-source: true
- feature-domains:
- minItems: 1
- maxItems: 3
- pwm: type: object additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index f84e09a5743b..d5ad097e94ec 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -67,6 +67,11 @@ properties: "#size-cells": const: 0
- feature-domains:
- minItems: 1
- maxItems: 3
- pwm: type: object additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml index 2459a55ed540..6ebedee65153 100644 --- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml +++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml @@ -79,6 +79,10 @@ properties: - const: rx - const: tx
feature-domains:
minItems: 1
maxItems: 3
power-domains: true
resets:
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index fc8c96b08d7d..0e408dc85c13 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -93,6 +93,10 @@ properties: select RCC clock instead of ETH_REF_CLK. type: boolean
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- clocks
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 24a3dbde223b..b9ac20c8bf05 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -55,6 +55,10 @@ properties: description: number of clock cells for ck_usbo_48m consumer const: 0
feature-domains:
minItems: 1
maxItems: 3
# Required child nodes:
patternProperties:
diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml index 05f4ad2c7d3a..02cefe4ef42b 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml @@ -30,6 +30,10 @@ properties: vdda-supply: description: phandle to the vdda input analog voltage.
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml index 187b172d0cca..79eb5f5bd252 100644 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml +++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml @@ -30,6 +30,10 @@ properties: type: boolean description: If set enable the clock detection management
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 1df8ffe95fc6..893978e7170f 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -70,6 +70,10 @@ properties: enum: [1, 2, 4, 8, 12, 14, 16] default: 8
- feature-domains:
- minItems: 1
- maxItems: 3
- allOf:
- $ref: rs485.yaml#
- $ref: serial.yaml#
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml index b9111d375b93..64c5898e51f8 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml @@ -65,6 +65,10 @@ properties: $ref: audio-graph-port.yaml# unevaluatedProperties: false
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml index 56d206f97a96..9bc08b7645dc 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -48,6 +48,10 @@ properties: clock-names: maxItems: 3
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml index bc48151b9adb..f00e5db9ee3b 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml @@ -50,6 +50,10 @@ properties: resets: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml index 8bba965a9ae6..2ac136802467 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml @@ -46,6 +46,10 @@ properties: - const: tx - const: rx
- feature-domains:
- minItems: 1
- maxItems: 3
- required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index 9ca1a843c820..725c26daabe4 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -59,6 +59,10 @@ properties: - const: rx - const: tx
- feature-domains:
- minItems: 1
- maxItems: 3
- patternProperties: "^[a-zA-Z][a-zA-Z0-9,+\-._]{0,63}@[0-9a-f]+$": type: object
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index d3506090f8b1..c372caf154fc 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -171,6 +171,10 @@ properties:
tpl-support: true
- feature-domains:
- minItems: 1
- maxItems: 3
- dependencies: port: [ usb-role-switch ] role-switch-default-mode: [ usb-role-switch ]
On Fri, Jul 07, 2023 at 02:07:18PM +0000, Oleksii Moisieiev wrote:
Gatien Chevallier gatien.chevallier@foss.st.com writes:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
I beliewe feature-domains is generic binding. This means that maxItems can be implementation dependend. I would rather drop maxItems so the following format will be possible:
feature-domains = <&etzpc 1>, <&etzpc 2>, <&some_other_domain 1 2 3 4> feature-domain-names = "firewall 1", "firewall 2", "other_domain"
The above already allows this (not -names, but the number of entries).
Also I beliewe driver will handle feature-domain-names property so it will parse feature-domains only related to the firewall.
Now I'm curious. What's an example that's not a firewall?
(Note I'm still not happy with the naming of 'feature' as anything is a feature, but that's the least of the issues really.)
Rob
Hi Rob,
Rob Herring robh@kernel.org writes:
On Fri, Jul 07, 2023 at 02:07:18PM +0000, Oleksii Moisieiev wrote:
Gatien Chevallier gatien.chevallier@foss.st.com writes:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
I beliewe feature-domains is generic binding. This means that maxItems can be implementation dependend. I would rather drop maxItems so the following format will be possible:
feature-domains = <&etzpc 1>, <&etzpc 2>, <&some_other_domain 1 2 3 4> feature-domain-names = "firewall 1", "firewall 2", "other_domain"The above already allows this (not -names, but the number of entries).
Also I beliewe driver will handle feature-domain-names property so it will parse feature-domains only related to the firewall.
Now I'm curious. What's an example that's not a firewall?
(Note I'm still not happy with the naming of 'feature' as anything is a feature, but that's the least of the issues really.)
The alternative usages of feature-domains was originally proposed by me here: https://lore.kernel.org/lkml/c869d2751125181a55bc8a88c96e3a892b42f37a.166807...
Also I remember Peng Fan also was interested in those bindings. I think the use-case when one node is protected by firewall and also is controlled by scmi feature-domain-controller (As was proposed in my patch series) may take place.
As for the naming maybe you have some thoughts about better name?
On Fri, Jul 7, 2023 at 10:10 AM Oleksii Moisieiev Oleksii_Moisieiev@epam.com wrote:
Hi Rob,
Rob Herring robh@kernel.org writes:
On Fri, Jul 07, 2023 at 02:07:18PM +0000, Oleksii Moisieiev wrote:
Gatien Chevallier gatien.chevallier@foss.st.com writes:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
I beliewe feature-domains is generic binding. This means that maxItems can be implementation dependend. I would rather drop maxItems so the following format will be possible:
feature-domains = <&etzpc 1>, <&etzpc 2>, <&some_other_domain 1 2 3 4> feature-domain-names = "firewall 1", "firewall 2", "other_domain"The above already allows this (not -names, but the number of entries).
Also I beliewe driver will handle feature-domain-names property so it will parse feature-domains only related to the firewall.
Now I'm curious. What's an example that's not a firewall?
(Note I'm still not happy with the naming of 'feature' as anything is a feature, but that's the least of the issues really.)
The alternative usages of feature-domains was originally proposed by me here: https://lore.kernel.org/lkml/c869d2751125181a55bc8a88c96e3a892b42f37a.166807...
Also I remember Peng Fan also was interested in those bindings.
It helps to Cc people when you talk about them.
If the parties interested in this want to see progress on this, you all must work together and show this is a solution for multiple platforms.
I think the use-case when one node is protected by firewall and also is controlled by scmi feature-domain-controller (As was proposed in my patch series) may take place.
But isn't the SCMI device protection interface the same thing? Some interface to say "can I access this device?" and/or control access to it.
The other possible use I'm aware of is system partitioning. OpenAMP or similar where an SoC is partitioned into multiple OS instances and peripherals are assigned to different partitions.
As for the naming maybe you have some thoughts about better name?
If I did, I would have. Something with 'access' in it is as far as I've gotten.
Rob
Hi Rob,
Rob Herring robh@kernel.org writes:
On Fri, Jul 7, 2023 at 10:10 AM Oleksii Moisieiev Oleksii_Moisieiev@epam.com wrote:
Hi Rob,
Rob Herring robh@kernel.org writes:
On Fri, Jul 07, 2023 at 02:07:18PM +0000, Oleksii Moisieiev wrote:
Gatien Chevallier gatien.chevallier@foss.st.com writes:
feature-domains is an optional property that allows a peripheral to refer to one or more feature domain controller(s).
Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controllers. It allows an accurate representation of the hardware, where various peripherals are connected to this firewall bus. The firewall can then check the peripheral accesses before allowing it to probe.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
Disclaimer: Some error with dtbs_check will be observed as I've considered the property to be generic, as Rob asked
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ .../devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 5 +++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ .../devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 24 files changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index b767ec72a999..daf8dcaef627 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -50,6 +50,10 @@ properties: power-domains: maxItems: 1
- feature-domains:
- minItems: 1
- maxItems: 3
I beliewe feature-domains is generic binding. This means that maxItems can be implementation dependend. I would rather drop maxItems so the following format will be possible:
feature-domains = <&etzpc 1>, <&etzpc 2>, <&some_other_domain 1 2 3 4> feature-domain-names = "firewall 1", "firewall 2", "other_domain"The above already allows this (not -names, but the number of entries).
Also I beliewe driver will handle feature-domain-names property so it will parse feature-domains only related to the firewall.
Now I'm curious. What's an example that's not a firewall?
(Note I'm still not happy with the naming of 'feature' as anything is a feature, but that's the least of the issues really.)
The alternative usages of feature-domains was originally proposed by me here: https://urldefense.com/v3/__https://lore.kernel.org/lkml/c869d2751125181a55b... [lore[.]kernel[.]org]
Also I remember Peng Fan also was interested in those bindings.
It helps to Cc people when you talk about them.
If the parties interested in this want to see progress on this, you all must work together and show this is a solution for multiple platforms.
Sorry. Missed that.
I think the use-case when one node is protected by firewall and also is controlled by scmi feature-domain-controller (As was proposed in my patch series) may take place.
But isn't the SCMI device protection interface the same thing? Some interface to say "can I access this device?" and/or control access to it.
My patch series introduce using of the feature-domain-controller to control access for the devices across the VMs. In our case we have virtualized system, controlled by Xen hypervisor with some amount of the VMs called Domains. Each Domain is the complete OS and HW is separated between them. We need SCMI to control power/clocks/resets etc from each Domain. feature-domain-controller in our case is SCMI node and each device will receive unique ID which match the ID from SCP firmware to set the device permissions so the SCP will know whether to give access to the resource for the Domain or not.
Those feature-domain-controller node and links from devices will be processed by Xen during Domain creation and the DT for the Domain will be generated without those bindings.
So probably Firewall will not see the scmi related links in the device nodes, but I think that the case when the device node is linked to more then one feature-domain-controller is possible because bindings are generic.
The other possible use I'm aware of is system partitioning. OpenAMP or similar where an SoC is partitioned into multiple OS instances and peripherals are assigned to different partitions.
i.MX boards are also have system partitioning concept in SCFW.
As for the naming maybe you have some thoughts about better name?
If I did, I would have. Something with 'access' in it is as far as I've gotten.
What do you think about access-controller or feature-access-controller? Maybe it will fit better here if all potential use cases for this bingins is to say if the device can be accessed.
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com --- MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++ include/linux/bus/stm32_firewall_device.h | 134 ++++++++++++ 7 files changed, 486 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h
diff --git a/MAINTAINERS b/MAINTAINERS index 41385f01fa98..fabf95ba9b86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20123,6 +20123,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c
+ST STM32 FIREWALL +M: Gatien Chevallier gatien.chevallier@foss.st.com +S: Maintained +F: drivers/bus/stm32_firewall.c + ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET pierre-yves.mordret@foss.st.com M: Alain Volmat alain.volmat@foss.st.com diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..5a46e90f1e4e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -293,6 +293,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI + select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including: diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fcfa280df98a..4d54a7ea52b2 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above.
+config STM32_FIREWALL + bool "STM32 Firewall framework" + depends on ARCH_STM32 + default MACH_STM32MP157 || MACH_STM32MP13 || MACH_STM32MP25 + help + Say y to enable firewall framework and its services. Firewall + controllers will be able to register to the framework. Firewall + controllers must be initialized and register to the firewall framework + at arch_initcall level. + config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64 diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..510db5bc6eaf --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/bus/stm32_firewall_device.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/types.h> + +#include "stm32_firewall.h" + +/* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall controller reference + firewall ID */ +#define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 2) + +static LIST_HEAD(firewall_controller_list); +static DEFINE_MUTEX(firewall_controller_list_lock); + +static int stm32_firewall_get_id(struct device_node *np, u32 *id) +{ + u32 feature_domain_cell[2]; + + /* Get property from device node */ + if (of_property_read_u32_array(np, "feature-domains", + feature_domain_cell, + ARRAY_SIZE(feature_domain_cell))) { + pr_err("Unable to find get firewall ID property\n"); + return -ENODEV; + } + + *id = feature_domain_cell[1]; + + return 0; +} + +/* Firewall device API */ + +int stm32_firewall_get_firewall(struct device_node *np, + struct stm32_firewall *firewall) +{ + struct stm32_firewall_controller *ctrl; + struct of_phandle_args args; + u32 controller_phandle; + bool match = false; + size_t i; + int err; + + if (!firewall) + return -EINVAL; + + /* The controller phandle is always the first argument of the feature-domains property. */ + err = of_property_read_u32(np, "feature-domains", &controller_phandle); + if (err) { + pr_err("Unable to get feature-domains property for node %s\n", np->full_name); + return err; + } + + /* Parse property with phandle parsed out */ + err = of_parse_phandle_with_args(np, "feature-domains", "#feature-domain-cells", 0, &args); + if (err) { + pr_err("Unable to read feature-domains arguments for node %s\n", np->full_name); + return err; + } + + /* The phandle is parsed out */ + if (args.args_count > STM32_FIREWALL_MAX_ARGS - 1) + return -EINVAL; + + of_node_put(np); + + /* Check if the parsed phandle corresponds to a registered firewall controller */ + mutex_lock(&firewall_controller_list_lock); + list_for_each_entry(ctrl, &firewall_controller_list, entry) { + if (ctrl->dev->of_node->phandle == controller_phandle) { + match = true; + firewall->firewall_ctrl = ctrl; + break; + } + } + mutex_unlock(&firewall_controller_list_lock); + if (!match) { + firewall->firewall_ctrl = NULL; + pr_err("No firewall controller registered for %s\n", np->full_name); + return -ENODEV; + } + + /* + * The firewall ID is always the second argument of the feature-domains property. + * The first argument is already parsed out, so args.args[0] is the second argument. + */ + firewall->firewall_id = args.args[0]; + + /* Extra args start at the third argument */ + for (i = 0; i < args.args_count; i++) + firewall->extra_args[i] = args.args[i + 1]; + + /* Remove the firewall ID arg that is not an extra argument */ + if (args.args_count >= 1) + firewall->extra_args_size = args.args_count - 1; + + return 0; +} +EXPORT_SYMBOL_GPL(stm32_firewall_get_firewall); + +int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || firewall->firewall_id == U32_MAX) + return -EINVAL; + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) + return -ENODEV; + + return firewall_controller->grant_access(firewall_controller, firewall->firewall_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access); + +int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) + return -EINVAL; + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) + return -ENODEV; + + return firewall_controller->grant_access(firewall_controller, subsystem_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access_by_id); + +void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || firewall->firewall_id == U32_MAX) { + pr_err("Incorrect arguments when releasing a firewall access"); + return; + } + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) { + pr_debug("No firewall controller to release"); + return; + } + + firewall_controller->release_access(firewall_controller, firewall->firewall_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access); + +void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) { + pr_err("Incorrect arguments when releasing a firewall access"); + return; + } + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) { + pr_debug("No firewall controller to release"); + return; + } + + firewall_controller->release_access(firewall_controller, subsystem_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id); + +/* Firewall controller API */ + +int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller) +{ + pr_info("Registering firewall controller %s", dev_name(firewall_controller->dev)); + + if (!firewall_controller) + return -ENODEV; + + mutex_lock(&firewall_controller_list_lock); + list_add_tail(&firewall_controller->entry, &firewall_controller_list); + mutex_unlock(&firewall_controller_list_lock); + + return 0; + +} + +void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller) +{ + struct stm32_firewall_controller *ctrl, *tmp; + bool controller_removed = false; + + if (!firewall_controller) { + pr_debug("Null reference while unregistering firewall controller"); + return; + } + + mutex_lock(&firewall_controller_list_lock); + list_for_each_entry_safe(ctrl, tmp, &firewall_controller_list, entry) { + if (ctrl == firewall_controller) { + controller_removed = true; + list_del_init(&ctrl->entry); + break; + } + } + mutex_unlock(&firewall_controller_list_lock); + + if (!controller_removed) + pr_debug("There was no firewall controller named %s to unregister", + dev_name(firewall_controller->dev)); +} + +void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller) +{ + struct device_node *child; + struct device *parent; + u32 firewall_id; + int err; + + parent = firewall_controller->dev; + + dev_dbg(parent, "Populating %s system bus\n", dev_name(firewall_controller->dev)); + + for_each_available_child_of_node(dev_of_node(parent), child) { + err = stm32_firewall_get_id(child, &firewall_id); + if (err < 0 || + firewall_controller->grant_access(firewall_controller, firewall_id)) { + /* + * Peripheral access not allowed or not defined. + * Mark the node as populated so platform bus won't probe it + */ + of_node_set_flag(child, OF_POPULATED); + dev_err(parent, "%s: Device driver will not be probed\n", + child->full_name); + } + } +} diff --git a/drivers/bus/stm32_firewall.h b/drivers/bus/stm32_firewall.h new file mode 100644 index 000000000000..8d92e8c1ab77 --- /dev/null +++ b/drivers/bus/stm32_firewall.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef _STM32_FIREWALL_H +#define _STM32_FIREWALL_H + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h> + +/** + * STM32_PERIPHERAL_FIREWALL: This type of firewall protects peripherals + * STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory + * zones + * STM32_RESOURCE_FIREWALL: This type of firewall protects internal resources + * STM32_NOTYPE_FIREWALL: Undefined firewall type + */ + +#define STM32_PERIPHERAL_FIREWALL BIT(1) +#define STM32_MEMORY_FIREWALL BIT(2) +#define STM32_RESOURCE_FIREWALL BIT(3) +#define STM32_NOTYPE_FIREWALL BIT(4) + +/** + * struct stm32_firewall_controller - Information on firewall controller supplying services + * + * @name Name of the firewall controller + * @dev Device reference of the firewall controller + * @mmio Base address of the firewall controller + * @entry List entry of the firewall controller list + * @type Type of firewall + * @max_entries Number of entries covered by the firewall + * @grant_access Callback used to grant access for a device access against a + * firewall controller + * @release_access Callback used to release resources taken by a device when access was + * granted + * @grant_memory_range_access Callback used to grant access for a device to a given memory region + */ +struct stm32_firewall_controller { + const char *name; + struct device *dev; + void __iomem *mmio; + struct list_head entry; + unsigned int type; + unsigned int max_entries; + + int (*grant_access)(struct stm32_firewall_controller *ctrl, u32 id); + void (*release_access)(struct stm32_firewall_controller *ctrl, u32 id); + int (*grant_memory_range_access)(struct stm32_firewall_controller *ctrl, phys_addr_t paddr, + size_t size); +}; + +/** + * int stm32_firewall_controller_register - Register a firewall controller to the STM32 firewall + * framework + * @firewall_controller Firewall controller to register + * + * Returns 0 in case of success or -ENODEV if no controller was given. + */ +int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller); + +/** + * int stm32_firewall_controller_unregister - Unregister a firewall controller from the STM32 + * firewall framework + * @firewall_controller Firewall controller to unregister + */ +void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller); + +/** + * stm32_firewall_populate_bus - Populate device tree nodes that have a correct firewall + * configuration. This is used at boot-time only, as a sanity check + * between device tree and firewalls hardware configurations to + * prevent a kernel crash when a device driver is not granted access + * + * @firewall_controller Firewall controller which nodes will be populated or not + */ +void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller); + +#endif /* _STM32_FIREWALL_H */ diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h new file mode 100644 index 000000000000..ccaecea7fc6c --- /dev/null +++ b/include/linux/bus/stm32_firewall_device.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef STM32_FIREWALL_DEVICE_H +#define STM32_FIREWALL_DEVICE_H + +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h> + +#define STM32_FIREWALL_MAX_EXTRA_ARGS 5 + +/* Opaque reference to stm32_firewall_controller */ +struct stm32_firewall_controller; + +/** + * stm32_firewall - Information on a device's firewall. Each device can have more than one firewall. + * + * @firewall_ctrl Pointer referencing a firewall controller of the device. It is + * opaque so a device cannot manipulate the controller's ops or access + * the controller's data + * @extra_args Extra arguments that are implementation dependent + * @extra_args_size Number of extra arguments + * @firewall_id Firewall ID associated the device for this firewall controller + */ +struct stm32_firewall { + struct stm32_firewall_controller *firewall_ctrl; + u32 extra_args[STM32_FIREWALL_MAX_EXTRA_ARGS]; + size_t extra_args_size; + u32 firewall_id; +}; + +#if IS_ENABLED(CONFIG_STM32_FIREWALL) +/** + * stm32_firewall_get_firewall - Get the firewall(s) associated to given device. + * The firewall controller reference is always the first argument + * of the feature-domains property. + * The firewall ID is always the second argument of the + * feature-domains property. + * + * @np Device node to parse + * @firewall Resulting firewall reference(s) + * + * Returns 0 on success, -ENODEV if there's no match with a firewall controller or appropriate errno + * code if error occurred. + */ +int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall); + +/** + * stm32_firewall_grant_access - Request firewall access rights and grant access. + * + * @firewall Firewall reference containing the ID to check against its firewall + * controller + * + * Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or + * appropriate errno code if error occurred + */ +int stm32_firewall_grant_access(struct stm32_firewall *firewall); + +/** + * stm32_firewall_release_access - Release access granted from a call to + * stm32_firewall_grant_access(). + * + * @firewall Firewall reference containing the ID to check against its firewall + * controller + */ +void stm32_firewall_release_access(struct stm32_firewall *firewall); + +/** + * stm32_firewall_grant_access_by_id - Request firewall access rights of a given device + * based on a specific firewall ID + * + * Warnings: + * There is no way to ensure that the given ID will correspond to the firewall referenced in the + * device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this + * function must be used with caution. + * This function should be used for subsystem resources that do not have the same firewall ID + * as their parent. + * U32_MAX is an invalid ID. + * + * @firewall Firewall reference containing the firewall controller + * @subsystem_id Firewall ID of the subsystem resource + * + * Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or + * appropriate errno code if error occurred + */ +int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id); + +/** + * stm32_firewall_release_access_by_id - Release access granted from a call to + * stm32_firewall_grant_access_by_id(). + * + * Warnings: + * There is no way to ensure that the given ID will correspond to the firewall referenced in the + * device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this + * function must be used with caution. + * This function should be used for subsystem resources that do not have the same firewall ID + * as their parent. + * U32_MAX is an invalid ID. + * + * @firewall Firewall reference containing the firewall controller + * @subsystem_id Firewall ID of the subsystem resource + */ +void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id); + +#else /* CONFIG_STM32_FIREWALL */ + +int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall) +{ + return -ENODEV; +} + +int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{ + return -ENODEV; +} + +void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ +} + +int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ + return -ENODEV; +} + +void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ +} + +#endif /* CONFIG_STM32_FIREWALL */ +#endif /* STM32_FIREWALL_DEVICE_H */
On Wed, Jul 05, 2023 at 07:27:54PM +0200, Gatien Chevallier wrote:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
How do resource firewalls work? Access to registers for some clocks in a clock controller are disabled? Or something gates off clocks/resets to a block?
It might make more sense for "resource" accesses to be managed within those resource APIs (i.e. the clock and reset frameworks) and leave this framework to bus accesses.
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
initcall ordering hacks should not be needed. We have both deferred probe and fw_devlinks to avoid that problem.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++
Why something stm32 specific? We know there are multiple platforms wanting something in this area. Wasn't the last attempt common?
For a common binding, I'm not eager to accept anything new with only 1 user.
include/linux/bus/stm32_firewall_device.h | 134 ++++++++++++ 7 files changed, 486 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h
diff --git a/MAINTAINERS b/MAINTAINERS index 41385f01fa98..fabf95ba9b86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20123,6 +20123,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c
+ST STM32 FIREWALL +M: Gatien Chevallier gatien.chevallier@foss.st.com +S: Maintained +F: drivers/bus/stm32_firewall.c
ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET pierre-yves.mordret@foss.st.com M: Alain Volmat alain.volmat@foss.st.com diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..5a46e90f1e4e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -293,6 +293,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI
- select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including:
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fcfa280df98a..4d54a7ea52b2 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above.
+config STM32_FIREWALL
- bool "STM32 Firewall framework"
- depends on ARCH_STM32
- default MACH_STM32MP157 || MACH_STM32MP13 || MACH_STM32MP25
- help
Say y to enable firewall framework and its services. Firewallcontrollers will be able to register to the framework. Firewallcontrollers must be initialized and register to the firewall frameworkat arch_initcall level.config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64 diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..510db5bc6eaf --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-or-later
The default kernel license is GPL-2.0-only. Why the deviation?
+/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/bus/stm32_firewall_device.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#include "stm32_firewall.h"
+/* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall controller reference + firewall ID */ +#define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 2)
+static LIST_HEAD(firewall_controller_list); +static DEFINE_MUTEX(firewall_controller_list_lock);
+static int stm32_firewall_get_id(struct device_node *np, u32 *id) +{
- u32 feature_domain_cell[2];
- /* Get property from device node */
- if (of_property_read_u32_array(np, "feature-domains",
feature_domain_cell,ARRAY_SIZE(feature_domain_cell))) {pr_err("Unable to find get firewall ID property\n");return -ENODEV;- }
- *id = feature_domain_cell[1];
- return 0;
+}
+/* Firewall device API */
+int stm32_firewall_get_firewall(struct device_node *np,
struct stm32_firewall *firewall)+{
- struct stm32_firewall_controller *ctrl;
- struct of_phandle_args args;
- u32 controller_phandle;
- bool match = false;
- size_t i;
- int err;
- if (!firewall)
return -EINVAL;- /* The controller phandle is always the first argument of the feature-domains property. */
- err = of_property_read_u32(np, "feature-domains", &controller_phandle);
Why do you need to parse the property twice?
- if (err) {
pr_err("Unable to get feature-domains property for node %s\n", np->full_name);return err;- }
- /* Parse property with phandle parsed out */
- err = of_parse_phandle_with_args(np, "feature-domains", "#feature-domain-cells", 0, &args);
- if (err) {
pr_err("Unable to read feature-domains arguments for node %s\n", np->full_name);return err;- }
- /* The phandle is parsed out */
- if (args.args_count > STM32_FIREWALL_MAX_ARGS - 1)
return -EINVAL;- of_node_put(np);
- /* Check if the parsed phandle corresponds to a registered firewall controller */
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry(ctrl, &firewall_controller_list, entry) {
if (ctrl->dev->of_node->phandle == controller_phandle) {match = true;firewall->firewall_ctrl = ctrl;break;}- }
- mutex_unlock(&firewall_controller_list_lock);
- if (!match) {
firewall->firewall_ctrl = NULL;pr_err("No firewall controller registered for %s\n", np->full_name);return -ENODEV;- }
- /*
* The firewall ID is always the second argument of the feature-domains property.* The first argument is already parsed out, so args.args[0] is the second argument.*/- firewall->firewall_id = args.args[0];
- /* Extra args start at the third argument */
- for (i = 0; i < args.args_count; i++)
firewall->extra_args[i] = args.args[i + 1];- /* Remove the firewall ID arg that is not an extra argument */
- if (args.args_count >= 1)
firewall->extra_args_size = args.args_count - 1;- return 0;
+} +EXPORT_SYMBOL_GPL(stm32_firewall_get_firewall);
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access);
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access_by_id);
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access);
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id);
+/* Firewall controller API */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller) +{
- pr_info("Registering firewall controller %s", dev_name(firewall_controller->dev));
- if (!firewall_controller)
return -ENODEV;- mutex_lock(&firewall_controller_list_lock);
- list_add_tail(&firewall_controller->entry, &firewall_controller_list);
- mutex_unlock(&firewall_controller_list_lock);
- return 0;
+}
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller) +{
- struct stm32_firewall_controller *ctrl, *tmp;
- bool controller_removed = false;
- if (!firewall_controller) {
pr_debug("Null reference while unregistering firewall controller");return;- }
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry_safe(ctrl, tmp, &firewall_controller_list, entry) {
if (ctrl == firewall_controller) {controller_removed = true;list_del_init(&ctrl->entry);break;}- }
- mutex_unlock(&firewall_controller_list_lock);
- if (!controller_removed)
pr_debug("There was no firewall controller named %s to unregister",dev_name(firewall_controller->dev));+}
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller) +{
- struct device_node *child;
- struct device *parent;
- u32 firewall_id;
- int err;
- parent = firewall_controller->dev;
- dev_dbg(parent, "Populating %s system bus\n", dev_name(firewall_controller->dev));
- for_each_available_child_of_node(dev_of_node(parent), child) {
err = stm32_firewall_get_id(child, &firewall_id);if (err < 0 ||firewall_controller->grant_access(firewall_controller, firewall_id)) {/** Peripheral access not allowed or not defined.* Mark the node as populated so platform bus won't probe it*/of_node_set_flag(child, OF_POPULATED);dev_err(parent, "%s: Device driver will not be probed\n",child->full_name);}- }
+} diff --git a/drivers/bus/stm32_firewall.h b/drivers/bus/stm32_firewall.h new file mode 100644 index 000000000000..8d92e8c1ab77 --- /dev/null +++ b/drivers/bus/stm32_firewall.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef _STM32_FIREWALL_H +#define _STM32_FIREWALL_H
+#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+/**
- STM32_PERIPHERAL_FIREWALL: This type of firewall protects peripherals
- STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory
zones
- STM32_RESOURCE_FIREWALL: This type of firewall protects internal resources
- STM32_NOTYPE_FIREWALL: Undefined firewall type
- */
+#define STM32_PERIPHERAL_FIREWALL BIT(1) +#define STM32_MEMORY_FIREWALL BIT(2) +#define STM32_RESOURCE_FIREWALL BIT(3) +#define STM32_NOTYPE_FIREWALL BIT(4)
+/**
- struct stm32_firewall_controller - Information on firewall controller supplying services
- @name Name of the firewall controller
- @dev Device reference of the firewall controller
- @mmio Base address of the firewall controller
- @entry List entry of the firewall controller list
- @type Type of firewall
- @max_entries Number of entries covered by the firewall
- @grant_access Callback used to grant access for a device access against a
firewall controller
- @release_access Callback used to release resources taken by a device when access was
granted
- @grant_memory_range_access Callback used to grant access for a device to a given memory region
- */
+struct stm32_firewall_controller {
- const char *name;
- struct device *dev;
- void __iomem *mmio;
- struct list_head entry;
- unsigned int type;
- unsigned int max_entries;
- int (*grant_access)(struct stm32_firewall_controller *ctrl, u32 id);
- void (*release_access)(struct stm32_firewall_controller *ctrl, u32 id);
- int (*grant_memory_range_access)(struct stm32_firewall_controller *ctrl, phys_addr_t paddr,
size_t size);+};
+/**
- int stm32_firewall_controller_register - Register a firewall controller to the STM32 firewall
framework
- @firewall_controller Firewall controller to register
- Returns 0 in case of success or -ENODEV if no controller was given.
- */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller);
+/**
- int stm32_firewall_controller_unregister - Unregister a firewall controller from the STM32
firewall framework
- @firewall_controller Firewall controller to unregister
- */
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller);
+/**
- stm32_firewall_populate_bus - Populate device tree nodes that have a correct firewall
configuration. This is used at boot-time only, as a sanity check
between device tree and firewalls hardware configurations to
prevent a kernel crash when a device driver is not granted access
- @firewall_controller Firewall controller which nodes will be populated or not
- */
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller);
+#endif /* _STM32_FIREWALL_H */ diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h new file mode 100644 index 000000000000..ccaecea7fc6c --- /dev/null +++ b/include/linux/bus/stm32_firewall_device.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef STM32_FIREWALL_DEVICE_H +#define STM32_FIREWALL_DEVICE_H
+#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#define STM32_FIREWALL_MAX_EXTRA_ARGS 5
+/* Opaque reference to stm32_firewall_controller */ +struct stm32_firewall_controller;
+/**
- stm32_firewall - Information on a device's firewall. Each device can have more than one firewall.
- @firewall_ctrl Pointer referencing a firewall controller of the device. It is
opaque so a device cannot manipulate the controller's ops or access
the controller's data
- @extra_args Extra arguments that are implementation dependent
- @extra_args_size Number of extra arguments
- @firewall_id Firewall ID associated the device for this firewall controller
- */
+struct stm32_firewall {
- struct stm32_firewall_controller *firewall_ctrl;
- u32 extra_args[STM32_FIREWALL_MAX_EXTRA_ARGS];
- size_t extra_args_size;
- u32 firewall_id;
+};
+#if IS_ENABLED(CONFIG_STM32_FIREWALL) +/**
- stm32_firewall_get_firewall - Get the firewall(s) associated to given device.
The firewall controller reference is always the first argument
of the feature-domains property.
The firewall ID is always the second argument of the
feature-domains property.
- @np Device node to parse
- @firewall Resulting firewall reference(s)
- Returns 0 on success, -ENODEV if there's no match with a firewall controller or appropriate errno
- code if error occurred.
- */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access - Request firewall access rights and grant access.
- @firewall Firewall reference containing the ID to check against its firewall
controller
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_release_access - Release access granted from a call to
stm32_firewall_grant_access().
- @firewall Firewall reference containing the ID to check against its firewall
controller- */
+void stm32_firewall_release_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access_by_id - Request firewall access rights of a given device
based on a specific firewall ID
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+/**
- stm32_firewall_release_access_by_id - Release access granted from a call to
stm32_firewall_grant_access_by_id().
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- */
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+#else /* CONFIG_STM32_FIREWALL */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ +}
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ +}
+#endif /* CONFIG_STM32_FIREWALL */
+#endif /* STM32_FIREWALL_DEVICE_H */
2.25.1
On 7/6/23 17:09, Rob Herring wrote:
On Wed, Jul 05, 2023 at 07:27:54PM +0200, Gatien Chevallier wrote:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
How do resource firewalls work? Access to registers for some clocks in a clock controller are disabled? Or something gates off clocks/resets to a block?
To take a practical example:
A clock controller can be firewall-aware and have its own firewall registers to configure. To access a clock/reset that is handled this way, a device would need to check this "resource firewall". I thought that for these kinds of hardware blocks, having a common API would help.
It might make more sense for "resource" accesses to be managed within those resource APIs (i.e. the clock and reset frameworks) and leave this framework to bus accesses.
Okay, I'll drop this for V2 if you find that the above explaination do not justify this.
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
initcall ordering hacks should not be needed. We have both deferred probe and fw_devlinks to avoid that problem.
Greg also doubts this.
Drivers like reset/clock controllers drivers (core_initcall level) will have a dependency on the firewall controllers in order to initialize their resources. I was not sure how to manage these dependencies.
Now, looking at init/main.c, I've realized that core_initcall() level comes before arch_initcall() level...
If managed by fw_devlink, the feature-domains property should be supported as well I suppose? I'm not sure how to handle this properly. I'd welcome your suggestion.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++
Why something stm32 specific? We know there are multiple platforms wanting something in this area. Wasn't the last attempt common?
For a common binding, I'm not eager to accept anything new with only 1 user.
Last attempt was common for the feature-domain bindings. The system-bus driver was ST-specific. I don't know if other platforms needs this kind of framework. Are you suggesting that this framework should be generic? Or that this framework should have a st-specific property?
I've oriented this firewall framework to serve ST purpose. There may be a need for other platforms but I'm not sure that this framework serves them well. One can argue that it is quite minimalist and covers basic purposes of a hardware firewall but I would need more feedback from other vendors to submit it as a generic one.
include/linux/bus/stm32_firewall_device.h | 134 ++++++++++++ 7 files changed, 486 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h
diff --git a/MAINTAINERS b/MAINTAINERS index 41385f01fa98..fabf95ba9b86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20123,6 +20123,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c
+ST STM32 FIREWALL +M: Gatien Chevallier gatien.chevallier@foss.st.com +S: Maintained +F: drivers/bus/stm32_firewall.c
- ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET pierre-yves.mordret@foss.st.com M: Alain Volmat alain.volmat@foss.st.com
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..5a46e90f1e4e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -293,6 +293,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI
- select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including:
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fcfa280df98a..4d54a7ea52b2 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above.
+config STM32_FIREWALL
- bool "STM32 Firewall framework"
- depends on ARCH_STM32
- default MACH_STM32MP157 || MACH_STM32MP13 || MACH_STM32MP25
- help
Say y to enable firewall framework and its services. Firewallcontrollers will be able to register to the framework. Firewallcontrollers must be initialized and register to the firewall frameworkat arch_initcall level.- config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..510db5bc6eaf --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-or-later
The default kernel license is GPL-2.0-only. Why the deviation?
+/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/bus/stm32_firewall_device.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#include "stm32_firewall.h"
+/* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall controller reference + firewall ID */ +#define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 2)
+static LIST_HEAD(firewall_controller_list); +static DEFINE_MUTEX(firewall_controller_list_lock);
+static int stm32_firewall_get_id(struct device_node *np, u32 *id) +{
- u32 feature_domain_cell[2];
- /* Get property from device node */
- if (of_property_read_u32_array(np, "feature-domains",
feature_domain_cell,ARRAY_SIZE(feature_domain_cell))) {pr_err("Unable to find get firewall ID property\n");return -ENODEV;- }
- *id = feature_domain_cell[1];
- return 0;
+}
+/* Firewall device API */
+int stm32_firewall_get_firewall(struct device_node *np,
struct stm32_firewall *firewall)+{
- struct stm32_firewall_controller *ctrl;
- struct of_phandle_args args;
- u32 controller_phandle;
- bool match = false;
- size_t i;
- int err;
- if (!firewall)
return -EINVAL;- /* The controller phandle is always the first argument of the feature-domains property. */
- err = of_property_read_u32(np, "feature-domains", &controller_phandle);
Why do you need to parse the property twice?
The first parsing is to have the first argument, which is the controller phandle. The second parsing is here to get the firewall arguments based on the number of arguments defined by #feature-domain-cells. Maybe using of_property_read_u32_array() would be better. I did not want to close the door for supporting several feature domain controllers, hence multiple phandles. of_parse_phandle_with_args() seemed fine for this purpose but the phandle is parsed out.
Best regards, Gatien
- if (err) {
pr_err("Unable to get feature-domains property for node %s\n", np->full_name);return err;- }
- /* Parse property with phandle parsed out */
- err = of_parse_phandle_with_args(np, "feature-domains", "#feature-domain-cells", 0, &args);
- if (err) {
pr_err("Unable to read feature-domains arguments for node %s\n", np->full_name);return err;- }
- /* The phandle is parsed out */
- if (args.args_count > STM32_FIREWALL_MAX_ARGS - 1)
return -EINVAL;- of_node_put(np);
- /* Check if the parsed phandle corresponds to a registered firewall controller */
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry(ctrl, &firewall_controller_list, entry) {
if (ctrl->dev->of_node->phandle == controller_phandle) {match = true;firewall->firewall_ctrl = ctrl;break;}- }
- mutex_unlock(&firewall_controller_list_lock);
- if (!match) {
firewall->firewall_ctrl = NULL;pr_err("No firewall controller registered for %s\n", np->full_name);return -ENODEV;- }
- /*
* The firewall ID is always the second argument of the feature-domains property.* The first argument is already parsed out, so args.args[0] is the second argument.*/- firewall->firewall_id = args.args[0];
- /* Extra args start at the third argument */
- for (i = 0; i < args.args_count; i++)
firewall->extra_args[i] = args.args[i + 1];- /* Remove the firewall ID arg that is not an extra argument */
- if (args.args_count >= 1)
firewall->extra_args_size = args.args_count - 1;- return 0;
+} +EXPORT_SYMBOL_GPL(stm32_firewall_get_firewall);
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access);
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access_by_id);
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access);
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id);
+/* Firewall controller API */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller) +{
- pr_info("Registering firewall controller %s", dev_name(firewall_controller->dev));
- if (!firewall_controller)
return -ENODEV;- mutex_lock(&firewall_controller_list_lock);
- list_add_tail(&firewall_controller->entry, &firewall_controller_list);
- mutex_unlock(&firewall_controller_list_lock);
- return 0;
+}
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller) +{
- struct stm32_firewall_controller *ctrl, *tmp;
- bool controller_removed = false;
- if (!firewall_controller) {
pr_debug("Null reference while unregistering firewall controller");return;- }
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry_safe(ctrl, tmp, &firewall_controller_list, entry) {
if (ctrl == firewall_controller) {controller_removed = true;list_del_init(&ctrl->entry);break;}- }
- mutex_unlock(&firewall_controller_list_lock);
- if (!controller_removed)
pr_debug("There was no firewall controller named %s to unregister",dev_name(firewall_controller->dev));+}
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller) +{
- struct device_node *child;
- struct device *parent;
- u32 firewall_id;
- int err;
- parent = firewall_controller->dev;
- dev_dbg(parent, "Populating %s system bus\n", dev_name(firewall_controller->dev));
- for_each_available_child_of_node(dev_of_node(parent), child) {
err = stm32_firewall_get_id(child, &firewall_id);if (err < 0 ||firewall_controller->grant_access(firewall_controller, firewall_id)) {/** Peripheral access not allowed or not defined.* Mark the node as populated so platform bus won't probe it*/of_node_set_flag(child, OF_POPULATED);dev_err(parent, "%s: Device driver will not be probed\n",child->full_name);}- }
+} diff --git a/drivers/bus/stm32_firewall.h b/drivers/bus/stm32_firewall.h new file mode 100644 index 000000000000..8d92e8c1ab77 --- /dev/null +++ b/drivers/bus/stm32_firewall.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef _STM32_FIREWALL_H +#define _STM32_FIREWALL_H
+#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+/**
- STM32_PERIPHERAL_FIREWALL: This type of firewall protects peripherals
- STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory
zones
- STM32_RESOURCE_FIREWALL: This type of firewall protects internal resources
- STM32_NOTYPE_FIREWALL: Undefined firewall type
- */
+#define STM32_PERIPHERAL_FIREWALL BIT(1) +#define STM32_MEMORY_FIREWALL BIT(2) +#define STM32_RESOURCE_FIREWALL BIT(3) +#define STM32_NOTYPE_FIREWALL BIT(4)
+/**
- struct stm32_firewall_controller - Information on firewall controller supplying services
- @name Name of the firewall controller
- @dev Device reference of the firewall controller
- @mmio Base address of the firewall controller
- @entry List entry of the firewall controller list
- @type Type of firewall
- @max_entries Number of entries covered by the firewall
- @grant_access Callback used to grant access for a device access against a
firewall controller
- @release_access Callback used to release resources taken by a device when access was
granted
- @grant_memory_range_access Callback used to grant access for a device to a given memory region
- */
+struct stm32_firewall_controller {
- const char *name;
- struct device *dev;
- void __iomem *mmio;
- struct list_head entry;
- unsigned int type;
- unsigned int max_entries;
- int (*grant_access)(struct stm32_firewall_controller *ctrl, u32 id);
- void (*release_access)(struct stm32_firewall_controller *ctrl, u32 id);
- int (*grant_memory_range_access)(struct stm32_firewall_controller *ctrl, phys_addr_t paddr,
size_t size);+};
+/**
- int stm32_firewall_controller_register - Register a firewall controller to the STM32 firewall
framework
- @firewall_controller Firewall controller to register
- Returns 0 in case of success or -ENODEV if no controller was given.
- */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller);
+/**
- int stm32_firewall_controller_unregister - Unregister a firewall controller from the STM32
firewall framework
- @firewall_controller Firewall controller to unregister
- */
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller);
+/**
- stm32_firewall_populate_bus - Populate device tree nodes that have a correct firewall
configuration. This is used at boot-time only, as a sanity check
between device tree and firewalls hardware configurations to
prevent a kernel crash when a device driver is not granted access
- @firewall_controller Firewall controller which nodes will be populated or not
- */
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller);
+#endif /* _STM32_FIREWALL_H */ diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h new file mode 100644 index 000000000000..ccaecea7fc6c --- /dev/null +++ b/include/linux/bus/stm32_firewall_device.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef STM32_FIREWALL_DEVICE_H +#define STM32_FIREWALL_DEVICE_H
+#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#define STM32_FIREWALL_MAX_EXTRA_ARGS 5
+/* Opaque reference to stm32_firewall_controller */ +struct stm32_firewall_controller;
+/**
- stm32_firewall - Information on a device's firewall. Each device can have more than one firewall.
- @firewall_ctrl Pointer referencing a firewall controller of the device. It is
opaque so a device cannot manipulate the controller's ops or access
the controller's data
- @extra_args Extra arguments that are implementation dependent
- @extra_args_size Number of extra arguments
- @firewall_id Firewall ID associated the device for this firewall controller
- */
+struct stm32_firewall {
- struct stm32_firewall_controller *firewall_ctrl;
- u32 extra_args[STM32_FIREWALL_MAX_EXTRA_ARGS];
- size_t extra_args_size;
- u32 firewall_id;
+};
+#if IS_ENABLED(CONFIG_STM32_FIREWALL) +/**
- stm32_firewall_get_firewall - Get the firewall(s) associated to given device.
The firewall controller reference is always the first argument
of the feature-domains property.
The firewall ID is always the second argument of the
feature-domains property.
- @np Device node to parse
- @firewall Resulting firewall reference(s)
- Returns 0 on success, -ENODEV if there's no match with a firewall controller or appropriate errno
- code if error occurred.
- */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access - Request firewall access rights and grant access.
- @firewall Firewall reference containing the ID to check against its firewall
controller
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_release_access - Release access granted from a call to
stm32_firewall_grant_access().
- @firewall Firewall reference containing the ID to check against its firewall
controller- */
+void stm32_firewall_release_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access_by_id - Request firewall access rights of a given device
based on a specific firewall ID
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+/**
- stm32_firewall_release_access_by_id - Release access granted from a call to
stm32_firewall_grant_access_by_id().
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- */
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+#else /* CONFIG_STM32_FIREWALL */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ +}
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ +}
+#endif /* CONFIG_STM32_FIREWALL */
+#endif /* STM32_FIREWALL_DEVICE_H */
2.25.1
On Fri, Jul 07, 2023 at 03:43:15PM +0200, Gatien CHEVALLIER wrote:
On 7/6/23 17:09, Rob Herring wrote:
On Wed, Jul 05, 2023 at 07:27:54PM +0200, Gatien Chevallier wrote:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
How do resource firewalls work? Access to registers for some clocks in a clock controller are disabled? Or something gates off clocks/resets to a block?
To take a practical example:
A clock controller can be firewall-aware and have its own firewall registers to configure. To access a clock/reset that is handled this way, a device would need to check this "resource firewall". I thought that for these kinds of hardware blocks, having a common API would help.
We already have the concept of 'protected clocks' which are ones controlled by secure mode which limits what Linux can do with them. I think you should extend this mechanism if needed and use the existing clock/reset APIs for managing resources.
It might make more sense for "resource" accesses to be managed within those resource APIs (i.e. the clock and reset frameworks) and leave this framework to bus accesses.
Okay, I'll drop this for V2 if you find that the above explaination do not justify this.
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
initcall ordering hacks should not be needed. We have both deferred probe and fw_devlinks to avoid that problem.
Greg also doubts this.
Drivers like reset/clock controllers drivers (core_initcall level) will have a dependency on the firewall controllers in order to initialize their resources. I was not sure how to manage these dependencies.
Now, looking at init/main.c, I've realized that core_initcall() level comes before arch_initcall() level...
If managed by fw_devlink, the feature-domains property should be supported as well I suppose? I'm not sure how to handle this properly. I'd welcome your suggestion.
DT parent/child child dependencies are already handled which might be enough for you. Otherwise, adding a new provider/consumer binding is a couple of lines to add the property names. See drivers/of/property.c.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++
Why something stm32 specific? We know there are multiple platforms wanting something in this area. Wasn't the last attempt common?
For a common binding, I'm not eager to accept anything new with only 1 user.
Last attempt was common for the feature-domain bindings. The system-bus driver was ST-specific. I don't know if other platforms needs this kind of framework. Are you suggesting that this framework should be generic? Or that this framework should have a st-specific property?
Ah right, the posting for SCMI device permissions was the binding only. The binding should be generic and support more than 1 user. That somewhat implies a generic framework, but not necessarily.
I've oriented this firewall framework to serve ST purpose. There may be a need for other platforms but I'm not sure that this framework serves them well. One can argue that it is quite minimalist and covers basic purposes of a hardware firewall but I would need more feedback from other vendors to submit it as a generic one.
We already know there are at least 2 users. Why would we make the 2nd user refactor your driver into a common framework?
[...]
+int stm32_firewall_get_firewall(struct device_node *np,
struct stm32_firewall *firewall)+{
- struct stm32_firewall_controller *ctrl;
- struct of_phandle_args args;
- u32 controller_phandle;
- bool match = false;
- size_t i;
- int err;
- if (!firewall)
return -EINVAL;- /* The controller phandle is always the first argument of the feature-domains property. */
- err = of_property_read_u32(np, "feature-domains", &controller_phandle);
Why do you need to parse the property twice?
The first parsing is to have the first argument, which is the controller phandle. The second parsing is here to get the firewall arguments based on the number of arguments defined by #feature-domain-cells. Maybe using of_property_read_u32_array() would be better.
No. It's not a u32 array. It's a phandle+args property, so you should only use phandle+args APIs.
I did not want to close the door for supporting several feature domain controllers, hence multiple phandles. of_parse_phandle_with_args() seemed fine for this purpose but the phandle is parsed out.
There's an iterator for handling multiple phandle+args cases.
Rob
Hello Rob,
On 7/7/23 17:07, Rob Herring wrote:
On Fri, Jul 07, 2023 at 03:43:15PM +0200, Gatien CHEVALLIER wrote:
On 7/6/23 17:09, Rob Herring wrote:
On Wed, Jul 05, 2023 at 07:27:54PM +0200, Gatien Chevallier wrote:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
How do resource firewalls work? Access to registers for some clocks in a clock controller are disabled? Or something gates off clocks/resets to a block?
To take a practical example:
A clock controller can be firewall-aware and have its own firewall registers to configure. To access a clock/reset that is handled this way, a device would need to check this "resource firewall". I thought that for these kinds of hardware blocks, having a common API would help.
We already have the concept of 'protected clocks' which are ones controlled by secure mode which limits what Linux can do with them. I think you should extend this mechanism if needed and use the existing clock/reset APIs for managing resources.
Ok, thank you for the input. I'll remove this type of firewall for V2 as I no longer have a use case.
It might make more sense for "resource" accesses to be managed within those resource APIs (i.e. the clock and reset frameworks) and leave this framework to bus accesses.
Okay, I'll drop this for V2 if you find that the above explaination do not justify this.
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
initcall ordering hacks should not be needed. We have both deferred probe and fw_devlinks to avoid that problem.
Greg also doubts this.
Drivers like reset/clock controllers drivers (core_initcall level) will have a dependency on the firewall controllers in order to initialize their resources. I was not sure how to manage these dependencies.
Now, looking at init/main.c, I've realized that core_initcall() level comes before arch_initcall() level...
If managed by fw_devlink, the feature-domains property should be supported as well I suppose? I'm not sure how to handle this properly. I'd welcome your suggestion.
DT parent/child child dependencies are already handled which might be enough for you. Otherwise, adding a new provider/consumer binding is a couple of lines to add the property names. See drivers/of/property.c.
Ok, I'll try with a modification of drivers/of/property.c as the parent/child dependency won't be enough. Thanks for pointing this out.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++
Why something stm32 specific? We know there are multiple platforms wanting something in this area. Wasn't the last attempt common?
For a common binding, I'm not eager to accept anything new with only 1 user.
Last attempt was common for the feature-domain bindings. The system-bus driver was ST-specific. I don't know if other platforms needs this kind of framework. Are you suggesting that this framework should be generic? Or that this framework should have a st-specific property?
Ah right, the posting for SCMI device permissions was the binding only. The binding should be generic and support more than 1 user. That somewhat implies a generic framework, but not necessarily.
I've oriented this firewall framework to serve ST purpose. There may be a need for other platforms but I'm not sure that this framework serves them well. One can argue that it is quite minimalist and covers basic purposes of a hardware firewall but I would need more feedback from other vendors to submit it as a generic one.
We already know there are at least 2 users. Why would we make the 2nd user refactor your driver into a common framework?
[...]
If one thinks this framework is generic enough so it can be of use for them, so yes, I can submit it as a common framework. I'm not that sure Oleksii finds a use case with it. He seemed interested by the bindings. Maybe I'm wrong Oleksii?
For V2, I'd rather submit it again as an ST-specific framework again to address the generic comments. This way, other people have time to manifest themselves.
+int stm32_firewall_get_firewall(struct device_node *np,
struct stm32_firewall *firewall)+{
- struct stm32_firewall_controller *ctrl;
- struct of_phandle_args args;
- u32 controller_phandle;
- bool match = false;
- size_t i;
- int err;
- if (!firewall)
return -EINVAL;- /* The controller phandle is always the first argument of the feature-domains property. */
- err = of_property_read_u32(np, "feature-domains", &controller_phandle);
Why do you need to parse the property twice?
The first parsing is to have the first argument, which is the controller phandle. The second parsing is here to get the firewall arguments based on the number of arguments defined by #feature-domain-cells. Maybe using of_property_read_u32_array() would be better.
No. It's not a u32 array. It's a phandle+args property, so you should only use phandle+args APIs.
I did not want to close the door for supporting several feature domain controllers, hence multiple phandles. of_parse_phandle_with_args() seemed fine for this purpose but the phandle is parsed out.
There's an iterator for handling multiple phandle+args cases.
Rob
Ok, will look into that for V2.
Best regards, Gatien
Hello Gatien,
Gatien CHEVALLIER gatien.chevallier@foss.st.com writes:
Hello Rob,
On 7/7/23 17:07, Rob Herring wrote:
On Fri, Jul 07, 2023 at 03:43:15PM +0200, Gatien CHEVALLIER wrote:
On 7/6/23 17:09, Rob Herring wrote:
On Wed, Jul 05, 2023 at 07:27:54PM +0200, Gatien Chevallier wrote:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
How do resource firewalls work? Access to registers for some clocks in a clock controller are disabled? Or something gates off clocks/resets to a block?
To take a practical example:
A clock controller can be firewall-aware and have its own firewall registers to configure. To access a clock/reset that is handled this way, a device would need to check this "resource firewall". I thought that for these kinds of hardware blocks, having a common API would help.
We already have the concept of 'protected clocks' which are ones controlled by secure mode which limits what Linux can do with them. I think you should extend this mechanism if needed and use the existing clock/reset APIs for managing resources.
Ok, thank you for the input. I'll remove this type of firewall for V2 as I no longer have a use case.
It might make more sense for "resource" accesses to be managed within those resource APIs (i.e. the clock and reset frameworks) and leave this framework to bus accesses.
Okay, I'll drop this for V2 if you find that the above explaination do not justify this.
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
initcall ordering hacks should not be needed. We have both deferred probe and fw_devlinks to avoid that problem.
Greg also doubts this.
Drivers like reset/clock controllers drivers (core_initcall level) will have a dependency on the firewall controllers in order to initialize their resources. I was not sure how to manage these dependencies.
Now, looking at init/main.c, I've realized that core_initcall() level comes before arch_initcall() level...
If managed by fw_devlink, the feature-domains property should be supported as well I suppose? I'm not sure how to handle this properly. I'd welcome your suggestion.
DT parent/child child dependencies are already handled which might be enough for you. Otherwise, adding a new provider/consumer binding is a couple of lines to add the property names. See drivers/of/property.c.
Ok, I'll try with a modification of drivers/of/property.c as the parent/child dependency won't be enough. Thanks for pointing this out.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++
Why something stm32 specific? We know there are multiple platforms wanting something in this area. Wasn't the last attempt common?
For a common binding, I'm not eager to accept anything new with only 1 user.
Last attempt was common for the feature-domain bindings. The system-bus driver was ST-specific. I don't know if other platforms needs this kind of framework. Are you suggesting that this framework should be generic? Or that this framework should have a st-specific property?
Ah right, the posting for SCMI device permissions was the binding only. The binding should be generic and support more than 1 user. That somewhat implies a generic framework, but not necessarily.
I've oriented this firewall framework to serve ST purpose. There may be a need for other platforms but I'm not sure that this framework serves them well. One can argue that it is quite minimalist and covers basic purposes of a hardware firewall but I would need more feedback from other vendors to submit it as a generic one.
We already know there are at least 2 users. Why would we make the 2nd user refactor your driver into a common framework? [...]
If one thinks this framework is generic enough so it can be of use for them, so yes, I can submit it as a common framework. I'm not that sure Oleksii finds a use case with it. He seemed interested by the bindings. Maybe I'm wrong Oleksii?
Correct. I'm interested only in bindings which should be processed by the hypervisor and removed from the OS DT the Kernel running in VM wouldn't know it exists.
For V2, I'd rather submit it again as an ST-specific framework again to address the generic comments. This way, other people have time to manifest themselves.
+int stm32_firewall_get_firewall(struct device_node *np,
[snip]
Best regards, Gatien
On Wed, Jul 05, 2023 at 07:27:54PM +0200, Gatien Chevallier wrote:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
But you aren't defining a "generic" api here, you are defining a specific one for your specific hardware.
Or am I missing something?
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
Why must it happen at arch_initcall? So it can never be a module? That feels wrong.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++ include/linux/bus/stm32_firewall_device.h | 134 ++++++++++++ 7 files changed, 486 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h
diff --git a/MAINTAINERS b/MAINTAINERS index 41385f01fa98..fabf95ba9b86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20123,6 +20123,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c
+ST STM32 FIREWALL +M: Gatien Chevallier gatien.chevallier@foss.st.com +S: Maintained +F: drivers/bus/stm32_firewall.c
ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET pierre-yves.mordret@foss.st.com M: Alain Volmat alain.volmat@foss.st.com diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..5a46e90f1e4e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -293,6 +293,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI
- select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including:
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fcfa280df98a..4d54a7ea52b2 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above.
+config STM32_FIREWALL
- bool "STM32 Firewall framework"
- depends on ARCH_STM32
Why this dependency?
- default MACH_STM32MP157 || MACH_STM32MP13 || MACH_STM32MP25
- help
Say y to enable firewall framework and its services. Firewallcontrollers will be able to register to the framework. Firewallcontrollers must be initialized and register to the firewall frameworkat arch_initcall level.
This needs better wording saying it is only for stm32 devices.
config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64 diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..510db5bc6eaf --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-or-later
Are you _SURE_ this needs to be "or later"? Sorry, I have to ask.
thanks,
greg k-h
Hello Greg,
On 7/7/23 12:37, Greg KH wrote:
On Wed, Jul 05, 2023 at 07:27:54PM +0200, Gatien Chevallier wrote:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
But you aren't defining a "generic" api here, you are defining a specific one for your specific hardware.
Or am I missing something?
This framework is indeed ST-oriented, I should have specified : "...offers a generic API for STM32 firewall controllers that is defined in their drivers...". Will change in V2
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
Why must it happen at arch_initcall? So it can never be a module? That feels wrong.
Rob asked the same question.
I responded under his comment, I'm not quite sure how to handle it with fw_devlink for dependencies with drivers that are probed at early init levels.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++ include/linux/bus/stm32_firewall_device.h | 134 ++++++++++++ 7 files changed, 486 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h
diff --git a/MAINTAINERS b/MAINTAINERS index 41385f01fa98..fabf95ba9b86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20123,6 +20123,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c
+ST STM32 FIREWALL +M: Gatien Chevallier gatien.chevallier@foss.st.com +S: Maintained +F: drivers/bus/stm32_firewall.c
- ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET pierre-yves.mordret@foss.st.com M: Alain Volmat alain.volmat@foss.st.com
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..5a46e90f1e4e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -293,6 +293,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI
- select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including:
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fcfa280df98a..4d54a7ea52b2 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above.
+config STM32_FIREWALL
- bool "STM32 Firewall framework"
- depends on ARCH_STM32
Why this dependency?
- default MACH_STM32MP157 || MACH_STM32MP13 || MACH_STM32MP25
- help
Say y to enable firewall framework and its services. Firewallcontrollers will be able to register to the framework. Firewallcontrollers must be initialized and register to the firewall frameworkat arch_initcall level.This needs better wording saying it is only for stm32 devices.
Ack, will change in V2.
- config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..510db5bc6eaf --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-or-later
Are you _SURE_ this needs to be "or later"? Sorry, I have to ask.
thanks,
greg k-h
I'll change to (GPL-2.0-only OR BSD-3-Clause) :)
Best regards, Gatien
On Fri, Jul 07, 2023 at 04:00:23PM +0200, Gatien CHEVALLIER wrote:
I'll change to (GPL-2.0-only OR BSD-3-Clause) :)
If you do that, I'll require a lawyer to sign off on it to verify that you all know EXACTLY the work involved in dealing with dual-licensed kernel code. Sorry, licenses aren't jokes.
thanks,
greg k-h
On 7/7/23 17:10, Greg KH wrote:
On Fri, Jul 07, 2023 at 04:00:23PM +0200, Gatien CHEVALLIER wrote:
I'll change to (GPL-2.0-only OR BSD-3-Clause) :)
If you do that, I'll require a lawyer to sign off on it to verify that you all know EXACTLY the work involved in dealing with dual-licensed kernel code. Sorry, licenses aren't jokes.
I was worried about the interactions with software running on BSD license, hence my (poorly written) proposal. Looking back at it there's no good reason to use a dual-license here. GPL-2.0-only is fine.
thanks,
greg k-h
Gatien Chevallier gatien.chevallier@foss.st.com writes:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++ include/linux/bus/stm32_firewall_device.h | 134 ++++++++++++ 7 files changed, 486 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h
diff --git a/MAINTAINERS b/MAINTAINERS index 41385f01fa98..fabf95ba9b86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20123,6 +20123,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c
+ST STM32 FIREWALL +M: Gatien Chevallier gatien.chevallier@foss.st.com +S: Maintained +F: drivers/bus/stm32_firewall.c
ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET pierre-yves.mordret@foss.st.com M: Alain Volmat alain.volmat@foss.st.com diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..5a46e90f1e4e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -293,6 +293,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI
- select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including:
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fcfa280df98a..4d54a7ea52b2 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above.
+config STM32_FIREWALL
- bool "STM32 Firewall framework"
- depends on ARCH_STM32
- default MACH_STM32MP157 || MACH_STM32MP13 || MACH_STM32MP25
- help
Say y to enable firewall framework and its services. Firewallcontrollers will be able to register to the framework. Firewallcontrollers must be initialized and register to the firewall frameworkat arch_initcall level.config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64 diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..510db5bc6eaf --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/bus/stm32_firewall_device.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#include "stm32_firewall.h"
+/* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall controller reference + firewall ID */ +#define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 2)
+static LIST_HEAD(firewall_controller_list); +static DEFINE_MUTEX(firewall_controller_list_lock);
+static int stm32_firewall_get_id(struct device_node *np, u32 *id) +{
- u32 feature_domain_cell[2];
- /* Get property from device node */
- if (of_property_read_u32_array(np, "feature-domains",
feature_domain_cell,ARRAY_SIZE(feature_domain_cell))) {pr_err("Unable to find get firewall ID property\n");return -ENODEV;- }
- *id = feature_domain_cell[1];
- return 0;
+}
+/* Firewall device API */
+int stm32_firewall_get_firewall(struct device_node *np,
struct stm32_firewall *firewall)+{
- struct stm32_firewall_controller *ctrl;
- struct of_phandle_args args;
- u32 controller_phandle;
- bool match = false;
- size_t i;
- int err;
- if (!firewall)
return -EINVAL;- /* The controller phandle is always the first argument of the feature-domains property. */
- err = of_property_read_u32(np, "feature-domains", &controller_phandle);
- if (err) {
pr_err("Unable to get feature-domains property for node %s\n", np->full_name);return err;- }
- /* Parse property with phandle parsed out */
- err = of_parse_phandle_with_args(np, "feature-domains", "#feature-domain-cells", 0, &args);
- if (err) {
pr_err("Unable to read feature-domains arguments for node %s\n", np->full_name);return err;- }
- /* The phandle is parsed out */
- if (args.args_count > STM32_FIREWALL_MAX_ARGS - 1)
return -EINVAL;- of_node_put(np);
- /* Check if the parsed phandle corresponds to a registered firewall controller */
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry(ctrl, &firewall_controller_list, entry) {
if (ctrl->dev->of_node->phandle == controller_phandle) {match = true;firewall->firewall_ctrl = ctrl;break;}- }
- mutex_unlock(&firewall_controller_list_lock);
- if (!match) {
firewall->firewall_ctrl = NULL;pr_err("No firewall controller registered for %s\n", np->full_name);return -ENODEV;- }
- /*
* The firewall ID is always the second argument of the feature-domains property.* The first argument is already parsed out, so args.args[0] is the second argument.*/- firewall->firewall_id = args.args[0];
- /* Extra args start at the third argument */
- for (i = 0; i < args.args_count; i++)
firewall->extra_args[i] = args.args[i + 1];- /* Remove the firewall ID arg that is not an extra argument */
- if (args.args_count >= 1)
firewall->extra_args_size = args.args_count - 1;
As I can see you support some extra args, that can be provided in the feature-domain property. But in the binding description I see maxItems: 2. I beliewe this should be highlighted in bindings description.
- return 0;
+} +EXPORT_SYMBOL_GPL(stm32_firewall_get_firewall);
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access);
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access_by_id);
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access);
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id);
+/* Firewall controller API */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller) +{
- pr_info("Registering firewall controller %s", dev_name(firewall_controller->dev));
- if (!firewall_controller)
return -ENODEV;- mutex_lock(&firewall_controller_list_lock);
- list_add_tail(&firewall_controller->entry, &firewall_controller_list);
- mutex_unlock(&firewall_controller_list_lock);
- return 0;
+}
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller) +{
- struct stm32_firewall_controller *ctrl, *tmp;
- bool controller_removed = false;
- if (!firewall_controller) {
pr_debug("Null reference while unregistering firewall controller");return;- }
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry_safe(ctrl, tmp, &firewall_controller_list, entry) {
if (ctrl == firewall_controller) {controller_removed = true;list_del_init(&ctrl->entry);break;}- }
IIUC list_for_each_entry_safe protects you from removing node during loop. But all list operations are done under firewall_controller_list_lock mutex. I beliewe there is no need for _safe call under the mutex because removing node during loop is impossible. I think it worth investigation if it's safe to use list_for_each_entry_safe without lock.
- mutex_unlock(&firewall_controller_list_lock);
- if (!controller_removed)
pr_debug("There was no firewall controller named %s to unregister",dev_name(firewall_controller->dev));+}
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller) +{
- struct device_node *child;
- struct device *parent;
- u32 firewall_id;
- int err;
- parent = firewall_controller->dev;
- dev_dbg(parent, "Populating %s system bus\n", dev_name(firewall_controller->dev));
- for_each_available_child_of_node(dev_of_node(parent), child) {
err = stm32_firewall_get_id(child, &firewall_id);if (err < 0 ||firewall_controller->grant_access(firewall_controller, firewall_id)) {/** Peripheral access not allowed or not defined.* Mark the node as populated so platform bus won't probe it*/of_node_set_flag(child, OF_POPULATED);dev_err(parent, "%s: Device driver will not be probed\n",child->full_name);}- }
+} diff --git a/drivers/bus/stm32_firewall.h b/drivers/bus/stm32_firewall.h new file mode 100644 index 000000000000..8d92e8c1ab77 --- /dev/null +++ b/drivers/bus/stm32_firewall.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef _STM32_FIREWALL_H +#define _STM32_FIREWALL_H
+#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+/**
- STM32_PERIPHERAL_FIREWALL: This type of firewall protects peripherals
Intendation
- STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory
zones
- STM32_RESOURCE_FIREWALL: This type of firewall protects internal resources
- STM32_NOTYPE_FIREWALL: Undefined firewall type
- */
+#define STM32_PERIPHERAL_FIREWALL BIT(1)
Intendation
+#define STM32_MEMORY_FIREWALL BIT(2) +#define STM32_RESOURCE_FIREWALL BIT(3) +#define STM32_NOTYPE_FIREWALL BIT(4)
+/**
- struct stm32_firewall_controller - Information on firewall controller supplying services
- @name Name of the firewall controller
- @dev Device reference of the firewall controller
Intendation
- @mmio Base address of the firewall controller
- @entry List entry of the firewall controller list
- @type Type of firewall
- @max_entries Number of entries covered by the firewall
Intendation
- @grant_access Callback used to grant access for a device access against a
firewall controller
- @release_access Callback used to release resources taken by a device when access was
granted
- @grant_memory_range_access Callback used to grant access for a device to a given memory region
- */
+struct stm32_firewall_controller {
- const char *name;
- struct device *dev;
- void __iomem *mmio;
- struct list_head entry;
- unsigned int type;
- unsigned int max_entries;
- int (*grant_access)(struct stm32_firewall_controller *ctrl, u32 id);
- void (*release_access)(struct stm32_firewall_controller *ctrl, u32 id);
- int (*grant_memory_range_access)(struct stm32_firewall_controller *ctrl, phys_addr_t paddr,
size_t size);+};
+/**
- int stm32_firewall_controller_register - Register a firewall controller to the STM32 firewall
framework
- @firewall_controller Firewall controller to register
- Returns 0 in case of success or -ENODEV if no controller was given.
- */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller);
+/**
- int stm32_firewall_controller_unregister - Unregister a firewall controller from the STM32
firewall framework
- @firewall_controller Firewall controller to unregister
- */
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller);
+/**
- stm32_firewall_populate_bus - Populate device tree nodes that have a correct firewall
configuration. This is used at boot-time only, as a sanity check
between device tree and firewalls hardware configurations to
prevent a kernel crash when a device driver is not granted access
- @firewall_controller Firewall controller which nodes will be populated or not
- */
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller);
+#endif /* _STM32_FIREWALL_H */ diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h new file mode 100644 index 000000000000..ccaecea7fc6c --- /dev/null +++ b/include/linux/bus/stm32_firewall_device.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef STM32_FIREWALL_DEVICE_H +#define STM32_FIREWALL_DEVICE_H
+#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#define STM32_FIREWALL_MAX_EXTRA_ARGS 5
It's not clear to me why it's 5. Comment above sais this is implementation defined. Maybe this parameter can be configurable?
+/* Opaque reference to stm32_firewall_controller */ +struct stm32_firewall_controller;
+/**
- stm32_firewall - Information on a device's firewall. Each device can have more than one firewall.
- @firewall_ctrl Pointer referencing a firewall controller of the device. It is
opaque so a device cannot manipulate the controller's ops or access
the controller's data
- @extra_args Extra arguments that are implementation dependent
- @extra_args_size Number of extra arguments
- @firewall_id Firewall ID associated the device for this firewall controller
- */
+struct stm32_firewall {
- struct stm32_firewall_controller *firewall_ctrl;
- u32 extra_args[STM32_FIREWALL_MAX_EXTRA_ARGS];
- size_t extra_args_size;
- u32 firewall_id;
+};
+#if IS_ENABLED(CONFIG_STM32_FIREWALL) +/**
- stm32_firewall_get_firewall - Get the firewall(s) associated to given device.
The firewall controller reference is always the first argument
of the feature-domains property.
The firewall ID is always the second argument of the
feature-domains property.
- @np Device node to parse
Intendation
- @firewall Resulting firewall reference(s)
- Returns 0 on success, -ENODEV if there's no match with a firewall controller or appropriate errno
- code if error occurred.
- */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access - Request firewall access rights and grant access.
- @firewall Firewall reference containing the ID to check against its firewall
controller
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_release_access - Release access granted from a call to
stm32_firewall_grant_access().
- @firewall Firewall reference containing the ID to check against its firewall
controller- */
+void stm32_firewall_release_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access_by_id - Request firewall access rights of a given device
based on a specific firewall ID
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
Can we store all registered IDs that were found by populate_bus functio, or is it expected when this function was called before populate_bus call?
+/**
- stm32_firewall_release_access_by_id - Release access granted from a call to
stm32_firewall_grant_access_by_id().
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- */
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+#else /* CONFIG_STM32_FIREWALL */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ +}
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ +}
+#endif /* CONFIG_STM32_FIREWALL */ +#endif /* STM32_FIREWALL_DEVICE_H */
Hello Oleksii,
On 7/7/23 15:50, Oleksii Moisieiev wrote:
Gatien Chevallier gatien.chevallier@foss.st.com writes:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++ include/linux/bus/stm32_firewall_device.h | 134 ++++++++++++ 7 files changed, 486 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h
diff --git a/MAINTAINERS b/MAINTAINERS index 41385f01fa98..fabf95ba9b86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20123,6 +20123,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c
+ST STM32 FIREWALL +M: Gatien Chevallier gatien.chevallier@foss.st.com +S: Maintained +F: drivers/bus/stm32_firewall.c
- ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET pierre-yves.mordret@foss.st.com M: Alain Volmat alain.volmat@foss.st.com
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..5a46e90f1e4e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -293,6 +293,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI
- select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including:
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fcfa280df98a..4d54a7ea52b2 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above.
+config STM32_FIREWALL
- bool "STM32 Firewall framework"
- depends on ARCH_STM32
- default MACH_STM32MP157 || MACH_STM32MP13 || MACH_STM32MP25
- help
Say y to enable firewall framework and its services. Firewallcontrollers will be able to register to the framework. Firewallcontrollers must be initialized and register to the firewall frameworkat arch_initcall level.- config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..510db5bc6eaf --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/bus/stm32_firewall_device.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#include "stm32_firewall.h"
+/* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall controller reference + firewall ID */ +#define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 2)
+static LIST_HEAD(firewall_controller_list); +static DEFINE_MUTEX(firewall_controller_list_lock);
+static int stm32_firewall_get_id(struct device_node *np, u32 *id) +{
- u32 feature_domain_cell[2];
- /* Get property from device node */
- if (of_property_read_u32_array(np, "feature-domains",
feature_domain_cell,ARRAY_SIZE(feature_domain_cell))) {pr_err("Unable to find get firewall ID property\n");return -ENODEV;- }
- *id = feature_domain_cell[1];
- return 0;
+}
+/* Firewall device API */
+int stm32_firewall_get_firewall(struct device_node *np,
struct stm32_firewall *firewall)+{
- struct stm32_firewall_controller *ctrl;
- struct of_phandle_args args;
- u32 controller_phandle;
- bool match = false;
- size_t i;
- int err;
- if (!firewall)
return -EINVAL;- /* The controller phandle is always the first argument of the feature-domains property. */
- err = of_property_read_u32(np, "feature-domains", &controller_phandle);
- if (err) {
pr_err("Unable to get feature-domains property for node %s\n", np->full_name);return err;- }
- /* Parse property with phandle parsed out */
- err = of_parse_phandle_with_args(np, "feature-domains", "#feature-domain-cells", 0, &args);
- if (err) {
pr_err("Unable to read feature-domains arguments for node %s\n", np->full_name);return err;- }
- /* The phandle is parsed out */
- if (args.args_count > STM32_FIREWALL_MAX_ARGS - 1)
return -EINVAL;- of_node_put(np);
- /* Check if the parsed phandle corresponds to a registered firewall controller */
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry(ctrl, &firewall_controller_list, entry) {
if (ctrl->dev->of_node->phandle == controller_phandle) {match = true;firewall->firewall_ctrl = ctrl;break;}- }
- mutex_unlock(&firewall_controller_list_lock);
- if (!match) {
firewall->firewall_ctrl = NULL;pr_err("No firewall controller registered for %s\n", np->full_name);return -ENODEV;- }
- /*
* The firewall ID is always the second argument of the feature-domains property.* The first argument is already parsed out, so args.args[0] is the second argument.*/- firewall->firewall_id = args.args[0];
- /* Extra args start at the third argument */
- for (i = 0; i < args.args_count; i++)
firewall->extra_args[i] = args.args[i + 1];- /* Remove the firewall ID arg that is not an extra argument */
- if (args.args_count >= 1)
firewall->extra_args_size = args.args_count - 1;As I can see you support some extra args, that can be provided in the feature-domain property. But in the binding description I see maxItems: 2. I beliewe this should be highlighted in bindings description.
Good point, maybe it would be better to define a high maxItem value in the binding description that is aligned with STM32_FIREWALL_MAX_ARGS.
- return 0;
+} +EXPORT_SYMBOL_GPL(stm32_firewall_get_firewall);
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access);
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access_by_id);
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access);
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id);
+/* Firewall controller API */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller) +{
- pr_info("Registering firewall controller %s", dev_name(firewall_controller->dev));
- if (!firewall_controller)
return -ENODEV;- mutex_lock(&firewall_controller_list_lock);
- list_add_tail(&firewall_controller->entry, &firewall_controller_list);
- mutex_unlock(&firewall_controller_list_lock);
- return 0;
+}
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller) +{
- struct stm32_firewall_controller *ctrl, *tmp;
- bool controller_removed = false;
- if (!firewall_controller) {
pr_debug("Null reference while unregistering firewall controller");return;- }
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry_safe(ctrl, tmp, &firewall_controller_list, entry) {
if (ctrl == firewall_controller) {controller_removed = true;list_del_init(&ctrl->entry);break;}- }
IIUC list_for_each_entry_safe protects you from removing node during loop. But all list operations are done under firewall_controller_list_lock mutex. I beliewe there is no need for _safe call under the mutex because removing node during loop is impossible. I think it worth investigation if it's safe to use list_for_each_entry_safe without lock.
AFAICT, list_for_each_entry_safe() does not protect against concurrent accesses, so I'll keep the mutex lock.
Deleting while iterating will cause trouble if not using the safe version. I think it is fine as it is.
- mutex_unlock(&firewall_controller_list_lock);
- if (!controller_removed)
pr_debug("There was no firewall controller named %s to unregister",dev_name(firewall_controller->dev));+}
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller) +{
- struct device_node *child;
- struct device *parent;
- u32 firewall_id;
- int err;
- parent = firewall_controller->dev;
- dev_dbg(parent, "Populating %s system bus\n", dev_name(firewall_controller->dev));
- for_each_available_child_of_node(dev_of_node(parent), child) {
err = stm32_firewall_get_id(child, &firewall_id);if (err < 0 ||firewall_controller->grant_access(firewall_controller, firewall_id)) {/** Peripheral access not allowed or not defined.* Mark the node as populated so platform bus won't probe it*/of_node_set_flag(child, OF_POPULATED);dev_err(parent, "%s: Device driver will not be probed\n",child->full_name);}- }
+} diff --git a/drivers/bus/stm32_firewall.h b/drivers/bus/stm32_firewall.h new file mode 100644 index 000000000000..8d92e8c1ab77 --- /dev/null +++ b/drivers/bus/stm32_firewall.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef _STM32_FIREWALL_H +#define _STM32_FIREWALL_H
+#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+/**
- STM32_PERIPHERAL_FIREWALL: This type of firewall protects peripherals
Intendation
- STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory
zones
- STM32_RESOURCE_FIREWALL: This type of firewall protects internal resources
- STM32_NOTYPE_FIREWALL: Undefined firewall type
- */
+#define STM32_PERIPHERAL_FIREWALL BIT(1)
Intendation
I'm sorry but I don't understand. I indent with tabs, maybe this is why it appears strange here. The indentation is fine, same for others below.
+#define STM32_MEMORY_FIREWALL BIT(2) +#define STM32_RESOURCE_FIREWALL BIT(3) +#define STM32_NOTYPE_FIREWALL BIT(4)
+/**
- struct stm32_firewall_controller - Information on firewall controller supplying services
- @name Name of the firewall controller
- @dev Device reference of the firewall controller
Intendation
- @mmio Base address of the firewall controller
- @entry List entry of the firewall controller list
- @type Type of firewall
- @max_entries Number of entries covered by the firewall
Intendation
- @grant_access Callback used to grant access for a device access against a
firewall controller
- @release_access Callback used to release resources taken by a device when access was
granted
- @grant_memory_range_access Callback used to grant access for a device to a given memory region
- */
+struct stm32_firewall_controller {
- const char *name;
- struct device *dev;
- void __iomem *mmio;
- struct list_head entry;
- unsigned int type;
- unsigned int max_entries;
- int (*grant_access)(struct stm32_firewall_controller *ctrl, u32 id);
- void (*release_access)(struct stm32_firewall_controller *ctrl, u32 id);
- int (*grant_memory_range_access)(struct stm32_firewall_controller *ctrl, phys_addr_t paddr,
size_t size);+};
+/**
- int stm32_firewall_controller_register - Register a firewall controller to the STM32 firewall
framework
- @firewall_controller Firewall controller to register
- Returns 0 in case of success or -ENODEV if no controller was given.
- */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller);
+/**
- int stm32_firewall_controller_unregister - Unregister a firewall controller from the STM32
firewall framework
- @firewall_controller Firewall controller to unregister
- */
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller);
+/**
- stm32_firewall_populate_bus - Populate device tree nodes that have a correct firewall
configuration. This is used at boot-time only, as a sanity check
between device tree and firewalls hardware configurations to
prevent a kernel crash when a device driver is not granted access
- @firewall_controller Firewall controller which nodes will be populated or not
- */
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller);
+#endif /* _STM32_FIREWALL_H */ diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h new file mode 100644 index 000000000000..ccaecea7fc6c --- /dev/null +++ b/include/linux/bus/stm32_firewall_device.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef STM32_FIREWALL_DEVICE_H +#define STM32_FIREWALL_DEVICE_H
+#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#define STM32_FIREWALL_MAX_EXTRA_ARGS 5
It's not clear to me why it's 5. Comment above sais this is implementation defined. Maybe this parameter can be configurable?
Maybe it should be part of compat_data of firewall controllers :)
+/* Opaque reference to stm32_firewall_controller */ +struct stm32_firewall_controller;
+/**
- stm32_firewall - Information on a device's firewall. Each device can have more than one firewall.
- @firewall_ctrl Pointer referencing a firewall controller of the device. It is
opaque so a device cannot manipulate the controller's ops or access
the controller's data
- @extra_args Extra arguments that are implementation dependent
- @extra_args_size Number of extra arguments
- @firewall_id Firewall ID associated the device for this firewall controller
- */
+struct stm32_firewall {
- struct stm32_firewall_controller *firewall_ctrl;
- u32 extra_args[STM32_FIREWALL_MAX_EXTRA_ARGS];
- size_t extra_args_size;
- u32 firewall_id;
+};
+#if IS_ENABLED(CONFIG_STM32_FIREWALL) +/**
- stm32_firewall_get_firewall - Get the firewall(s) associated to given device.
The firewall controller reference is always the first argument
of the feature-domains property.
The firewall ID is always the second argument of the
feature-domains property.
- @np Device node to parse
Intendation
- @firewall Resulting firewall reference(s)
- Returns 0 on success, -ENODEV if there's no match with a firewall controller or appropriate errno
- code if error occurred.
- */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access - Request firewall access rights and grant access.
- @firewall Firewall reference containing the ID to check against its firewall
controller
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_release_access - Release access granted from a call to
stm32_firewall_grant_access().
- @firewall Firewall reference containing the ID to check against its firewall
controller- */
+void stm32_firewall_release_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access_by_id - Request firewall access rights of a given device
based on a specific firewall ID
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
Can we store all registered IDs that were found by populate_bus functio, or is it expected when this function was called before populate_bus call?
This function is intended to be used by devices that needs to check specific ID. Maybe IDs of peripherals that do not have a driver in Linux / driver isn't probed / ...
About storing all IDs found when populating the bus, do you have some use in mind? :) Else I'd prefer to save some memory.
Best regards, Gatien
+/**
- stm32_firewall_release_access_by_id - Release access granted from a call to
stm32_firewall_grant_access_by_id().
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- */
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+#else /* CONFIG_STM32_FIREWALL */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ +}
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ +}
+#endif /* CONFIG_STM32_FIREWALL */ +#endif /* STM32_FIREWALL_DEVICE_H */
Gatien CHEVALLIER gatien.chevallier@foss.st.com writes:
Hello Gatien,
Hello Oleksii,
On 7/7/23 15:50, Oleksii Moisieiev wrote:
Gatien Chevallier gatien.chevallier@foss.st.com writes:
Introduce a firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s).
The firewall framework offers a generic API that is defined in firewall controllers drivers to best fit the specificity of each firewall.
There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -Resource firewalls that filter accesses to internal resources such as reset and clock controllers
A firewall controller must be probed at arch_initcall level and register to the framework so that consumers can use their services.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
MAINTAINERS | 5 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 252 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 +++++++ include/linux/bus/stm32_firewall_device.h | 134 ++++++++++++ 7 files changed, 486 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h
diff --git a/MAINTAINERS b/MAINTAINERS index 41385f01fa98..fabf95ba9b86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20123,6 +20123,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c +ST STM32 FIREWALL +M: Gatien Chevallier gatien.chevallier@foss.st.com +S: Maintained +F: drivers/bus/stm32_firewall.c
- ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET pierre-yves.mordret@foss.st.com M: Alain Volmat alain.volmat@foss.st.com
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..5a46e90f1e4e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -293,6 +293,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI
- select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including:
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fcfa280df98a..4d54a7ea52b2 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above. +config STM32_FIREWALL
- bool "STM32 Firewall framework"
- depends on ARCH_STM32
- default MACH_STM32MP157 || MACH_STM32MP13 || MACH_STM32MP25
- help
Say y to enable firewall framework and its services. Firewallcontrollers will be able to register to the framework. Firewallcontrollers must be initialized and register to the firewall frameworkat arch_initcall level.- config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..510db5bc6eaf --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/bus/stm32_firewall_device.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#include "stm32_firewall.h"
+/* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall controller reference + firewall ID */ +#define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 2)
+static LIST_HEAD(firewall_controller_list); +static DEFINE_MUTEX(firewall_controller_list_lock);
+static int stm32_firewall_get_id(struct device_node *np, u32 *id) +{
- u32 feature_domain_cell[2];
- /* Get property from device node */
- if (of_property_read_u32_array(np, "feature-domains",
feature_domain_cell,ARRAY_SIZE(feature_domain_cell))) {pr_err("Unable to find get firewall ID property\n");return -ENODEV;- }
- *id = feature_domain_cell[1];
- return 0;
+}
+/* Firewall device API */
+int stm32_firewall_get_firewall(struct device_node *np,
struct stm32_firewall *firewall)+{
- struct stm32_firewall_controller *ctrl;
- struct of_phandle_args args;
- u32 controller_phandle;
- bool match = false;
- size_t i;
- int err;
- if (!firewall)
return -EINVAL;- /* The controller phandle is always the first argument of the feature-domains property. */
- err = of_property_read_u32(np, "feature-domains", &controller_phandle);
- if (err) {
pr_err("Unable to get feature-domains property for node %s\n", np->full_name);return err;- }
- /* Parse property with phandle parsed out */
- err = of_parse_phandle_with_args(np, "feature-domains", "#feature-domain-cells", 0, &args);
- if (err) {
pr_err("Unable to read feature-domains arguments for node %s\n", np->full_name);return err;- }
- /* The phandle is parsed out */
- if (args.args_count > STM32_FIREWALL_MAX_ARGS - 1)
return -EINVAL;- of_node_put(np);
- /* Check if the parsed phandle corresponds to a registered firewall controller */
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry(ctrl, &firewall_controller_list, entry) {
if (ctrl->dev->of_node->phandle == controller_phandle) {match = true;firewall->firewall_ctrl = ctrl;break;}- }
- mutex_unlock(&firewall_controller_list_lock);
- if (!match) {
firewall->firewall_ctrl = NULL;pr_err("No firewall controller registered for %s\n", np->full_name);return -ENODEV;- }
- /*
* The firewall ID is always the second argument of the feature-domains property.* The first argument is already parsed out, so args.args[0] is the second argument.*/- firewall->firewall_id = args.args[0];
- /* Extra args start at the third argument */
- for (i = 0; i < args.args_count; i++)
firewall->extra_args[i] = args.args[i + 1];- /* Remove the firewall ID arg that is not an extra argument */
- if (args.args_count >= 1)
firewall->extra_args_size = args.args_count - 1;As I can see you support some extra args, that can be provided in the feature-domain property. But in the binding description I see maxItems: 2. I beliewe this should be highlighted in bindings description.
Good point, maybe it would be better to define a high maxItem value in the binding description that is aligned with STM32_FIREWALL_MAX_ARGS.
- return 0;
+} +EXPORT_SYMBOL_GPL(stm32_firewall_get_firewall);
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access);
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX)
return -EINVAL;- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller)
return -ENODEV;- return firewall_controller->grant_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access_by_id);
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, firewall->firewall_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access);
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- struct stm32_firewall_controller *firewall_controller;
- if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) {
pr_err("Incorrect arguments when releasing a firewall access");return;- }
- firewall_controller = firewall->firewall_ctrl;
- if (!firewall_controller) {
pr_debug("No firewall controller to release");return;- }
- firewall_controller->release_access(firewall_controller, subsystem_id);
+} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id);
+/* Firewall controller API */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller) +{
- pr_info("Registering firewall controller %s", dev_name(firewall_controller->dev));
- if (!firewall_controller)
return -ENODEV;- mutex_lock(&firewall_controller_list_lock);
- list_add_tail(&firewall_controller->entry, &firewall_controller_list);
- mutex_unlock(&firewall_controller_list_lock);
- return 0;
+}
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller) +{
- struct stm32_firewall_controller *ctrl, *tmp;
- bool controller_removed = false;
- if (!firewall_controller) {
pr_debug("Null reference while unregistering firewall controller");return;- }
- mutex_lock(&firewall_controller_list_lock);
- list_for_each_entry_safe(ctrl, tmp, &firewall_controller_list, entry) {
if (ctrl == firewall_controller) {controller_removed = true;list_del_init(&ctrl->entry);break;}- }
IIUC list_for_each_entry_safe protects you from removing node during loop. But all list operations are done under firewall_controller_list_lock mutex. I beliewe there is no need for _safe call under the mutex because removing node during loop is impossible. I think it worth investigation if it's safe to use list_for_each_entry_safe without lock.
AFAICT, list_for_each_entry_safe() does not protect against concurrent accesses, so I'll keep the mutex lock.
Deleting while iterating will cause trouble if not using the safe version. I think it is fine as it is.
Ok, in that case I whould rather drop _safe, because for your case it is impossible to remove entry while iterating the list. This will save a couple of CPU instructions.
- mutex_unlock(&firewall_controller_list_lock);
- if (!controller_removed)
pr_debug("There was no firewall controller named %s to unregister",dev_name(firewall_controller->dev));+}
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller) +{
- struct device_node *child;
- struct device *parent;
- u32 firewall_id;
- int err;
- parent = firewall_controller->dev;
- dev_dbg(parent, "Populating %s system bus\n", dev_name(firewall_controller->dev));
- for_each_available_child_of_node(dev_of_node(parent), child) {
err = stm32_firewall_get_id(child, &firewall_id);if (err < 0 ||firewall_controller->grant_access(firewall_controller, firewall_id)) {/** Peripheral access not allowed or not defined.* Mark the node as populated so platform bus won't probe it*/of_node_set_flag(child, OF_POPULATED);dev_err(parent, "%s: Device driver will not be probed\n",child->full_name);}- }
+} diff --git a/drivers/bus/stm32_firewall.h b/drivers/bus/stm32_firewall.h new file mode 100644 index 000000000000..8d92e8c1ab77 --- /dev/null +++ b/drivers/bus/stm32_firewall.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef _STM32_FIREWALL_H +#define _STM32_FIREWALL_H
+#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+/**
- STM32_PERIPHERAL_FIREWALL: This type of firewall protects peripherals
Intendation
- STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory
zones
- STM32_RESOURCE_FIREWALL: This type of firewall protects internal resources
- STM32_NOTYPE_FIREWALL: Undefined firewall type
- */
+#define STM32_PERIPHERAL_FIREWALL BIT(1)
Intendation
I'm sorry but I don't understand. I indent with tabs, maybe this is why it appears strange here. The indentation is fine, same for others below.
Nevermind, Just looks strange in patch.
+#define STM32_MEMORY_FIREWALL BIT(2) +#define STM32_RESOURCE_FIREWALL BIT(3) +#define STM32_NOTYPE_FIREWALL BIT(4)
+/**
- struct stm32_firewall_controller - Information on firewall controller supplying services
- @name Name of the firewall controller
- @dev Device reference of the firewall controller
Intendation
- @mmio Base address of the firewall controller
- @entry List entry of the firewall controller list
- @type Type of firewall
- @max_entries Number of entries covered by the firewall
Intendation
- @grant_access Callback used to grant access for a device access against a
firewall controller
- @release_access Callback used to release resources taken by a device when access was
granted
- @grant_memory_range_access Callback used to grant access for a device to a given memory region
- */
+struct stm32_firewall_controller {
- const char *name;
- struct device *dev;
- void __iomem *mmio;
- struct list_head entry;
- unsigned int type;
- unsigned int max_entries;
- int (*grant_access)(struct stm32_firewall_controller *ctrl, u32 id);
- void (*release_access)(struct stm32_firewall_controller *ctrl, u32 id);
- int (*grant_memory_range_access)(struct stm32_firewall_controller *ctrl, phys_addr_t paddr,
size_t size);+};
+/**
- int stm32_firewall_controller_register - Register a firewall controller to the STM32 firewall
framework
- @firewall_controller Firewall controller to register
- Returns 0 in case of success or -ENODEV if no controller was given.
- */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller);
+/**
- int stm32_firewall_controller_unregister - Unregister a firewall controller from the STM32
firewall framework
- @firewall_controller Firewall controller to unregister
- */
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller);
+/**
- stm32_firewall_populate_bus - Populate device tree nodes that have a correct firewall
configuration. This is used at boot-time only, as a sanity check
between device tree and firewalls hardware configurations to
prevent a kernel crash when a device driver is not granted access
- @firewall_controller Firewall controller which nodes will be populated or not
- */
+void stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller);
+#endif /* _STM32_FIREWALL_H */ diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h new file mode 100644 index 000000000000..ccaecea7fc6c --- /dev/null +++ b/include/linux/bus/stm32_firewall_device.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- */
+#ifndef STM32_FIREWALL_DEVICE_H +#define STM32_FIREWALL_DEVICE_H
+#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h>
+#define STM32_FIREWALL_MAX_EXTRA_ARGS 5
It's not clear to me why it's 5. Comment above sais this is implementation defined. Maybe this parameter can be configurable?
Maybe it should be part of compat_data of firewall controllers :)
+/* Opaque reference to stm32_firewall_controller */ +struct stm32_firewall_controller;
+/**
- stm32_firewall - Information on a device's firewall. Each device can have more than one firewall.
- @firewall_ctrl Pointer referencing a firewall controller of the device. It is
opaque so a device cannot manipulate the controller's ops or access
the controller's data
- @extra_args Extra arguments that are implementation dependent
- @extra_args_size Number of extra arguments
- @firewall_id Firewall ID associated the device for this firewall controller
- */
+struct stm32_firewall {
- struct stm32_firewall_controller *firewall_ctrl;
- u32 extra_args[STM32_FIREWALL_MAX_EXTRA_ARGS];
- size_t extra_args_size;
- u32 firewall_id;
+};
+#if IS_ENABLED(CONFIG_STM32_FIREWALL) +/**
- stm32_firewall_get_firewall - Get the firewall(s) associated to given device.
The firewall controller reference is always the first argument
of the feature-domains property.
The firewall ID is always the second argument of the
feature-domains property.
- @np Device node to parse
Intendation
- @firewall Resulting firewall reference(s)
- Returns 0 on success, -ENODEV if there's no match with a firewall controller or appropriate errno
- code if error occurred.
- */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access - Request firewall access rights and grant access.
- @firewall Firewall reference containing the ID to check against its firewall
controller
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_release_access - Release access granted from a call to
stm32_firewall_grant_access().
- @firewall Firewall reference containing the ID to check against its firewall
controller- */
+void stm32_firewall_release_access(struct stm32_firewall *firewall);
+/**
- stm32_firewall_grant_access_by_id - Request firewall access rights of a given device
based on a specific firewall ID
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
- appropriate errno code if error occurred
- */
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
Can we store all registered IDs that were found by populate_bus functio, or is it expected when this function was called before populate_bus call?
This function is intended to be used by devices that needs to check specific ID. Maybe IDs of peripherals that do not have a driver in Linux / driver isn't probed / ...
About storing all IDs found when populating the bus, do you have some use in mind? :) Else I'd prefer to save some memory.
Best regards, Gatien
Then I think it worth mentioning in Warnings comment. What bothered me is that you've said that there is no way to check ID while I was seeing possible implementation.
+/**
- stm32_firewall_release_access_by_id - Release access granted from a call to
stm32_firewall_grant_access_by_id().
- Warnings:
- There is no way to ensure that the given ID will correspond to the firewall referenced in the
- device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
- function must be used with caution.
- This function should be used for subsystem resources that do not have the same firewall ID
- as their parent.
- U32_MAX is an invalid ID.
- @firewall Firewall reference containing the firewall controller
- @subsystem_id Firewall ID of the subsystem resource
- */
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+#else /* CONFIG_STM32_FIREWALL */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ +}
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{
- return -ENODEV;
+}
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ +}
+#endif /* CONFIG_STM32_FIREWALL */ +#endif /* STM32_FIREWALL_DEVICE_H */
RIFSC is a peripheral firewall controller that filter accesses based on Arm TrustZone secure state, Arm CPU privilege execution level and Compartment IDentification of the STM32 SoC subsystems.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com --- MAINTAINERS | 1 + drivers/bus/Makefile | 2 +- drivers/bus/stm32_rifsc.c | 248 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 250 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/stm32_rifsc.c
diff --git a/MAINTAINERS b/MAINTAINERS index fabf95ba9b86..1ea2f9f60b43 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20127,6 +20127,7 @@ ST STM32 FIREWALL M: Gatien Chevallier gatien.chevallier@foss.st.com S: Maintained F: drivers/bus/stm32_firewall.c +F: drivers/bus/stm32_rifsc.c
ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET pierre-yves.mordret@foss.st.com diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index fc0511450ec2..e50d18e1d141 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o -obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_rifsc.c b/drivers/bus/stm32_rifsc.c new file mode 100644 index 000000000000..f591fd3d4392 --- /dev/null +++ b/drivers/bus/stm32_rifsc.c @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/types.h> + +#include "stm32_firewall.h" + +/* + * RIFSC offset register + */ +#define RIFSC_RISC_SECCFGR0 0x10 +#define RIFSC_RISC_PRIVCFGR0 0x30 +#define RIFSC_RISC_PER0_CIDCFGR 0x100 +#define RIFSC_RISC_PER0_SEMCR 0x104 +#define RIFSC_RISC_HWCFGR2 0xFEC + +/* + * SEMCR register + */ +#define SEMCR_MUTEX BIT(0) + +/* + * HWCFGR2 register + */ +#define HWCFGR2_CONF1_MASK GENMASK(15, 0) +#define HWCFGR2_CONF2_MASK GENMASK(23, 16) +#define HWCFGR2_CONF3_MASK GENMASK(31, 24) + +/* + * RIFSC miscellaneous + */ +#define RIFSC_RISC_CFEN_MASK BIT(0) +#define RIFSC_RISC_SEM_EN_MASK BIT(1) +#define RIFSC_RISC_SCID_MASK GENMASK(6, 4) +#define RIFSC_RISC_SEML_SHIFT 16 +#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16) +#define RIFSC_RISC_PER_ID_MASK GENMASK(31, 24) + +#define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CFEN_MASK | \ + RIFSC_RISC_SEM_EN_MASK | \ + RIFSC_RISC_SCID_MASK | \ + RIFSC_RISC_SEMWL_MASK) + +#define IDS_PER_RISC_SEC_PRIV_REGS 32 + +/* RIF miscellaneous */ +/* + * CIDCFGR register fields + */ +#define CIDCFGR_CFEN BIT(0) +#define CIDCFGR_SEMEN BIT(1) +#define CIDCFGR_SEMWL(x) BIT(RIFSC_RISC_SEML_SHIFT + (x)) + +#define SEMWL_SHIFT 16 + +/* Compartiment IDs */ +#define RIF_CID0 0x0 +#define RIF_CID1 0x1 + +static bool stm32_rifsc_is_semaphore_available(void __iomem *addr) +{ + return !(readl(addr) & SEMCR_MUTEX); +} + +static int stm32_rif_acquire_semaphore(struct stm32_firewall_controller *stm32_firewall_controller, + int id) +{ + void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; + + __set_bit(SEMCR_MUTEX, addr); + + /* Check that CID1 has the semaphore */ + if (stm32_rifsc_is_semaphore_available(addr) || + FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) != RIF_CID1) + return -EACCES; + + return 0; +} + +static void stm32_rif_release_semaphore(struct stm32_firewall_controller *stm32_firewall_controller, + int id) +{ + void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; + + if (stm32_rifsc_is_semaphore_available(addr)) + return; + + writel(SEMCR_MUTEX, addr); + + /* Ok if another compartment takes the semaphore before the check */ + WARN_ON(!stm32_rifsc_is_semaphore_available(addr) && + FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) == RIF_CID1); +} + +static int stm32_rifsc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + struct stm32_firewall_controller *rifsc_controller = ctrl; + u32 reg_offset, reg_id, sec_reg_value, cid_reg_value; + int rc; + + if (firewall_id >= rifsc_controller->max_entries) { + dev_err(rifsc_controller->dev, "Invalid sys bus ID %u", firewall_id); + return -EINVAL; + } + + /* + * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for + * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register + * per peripheral + */ + reg_id = firewall_id / IDS_PER_RISC_SEC_PRIV_REGS; + reg_offset = firewall_id % IDS_PER_RISC_SEC_PRIV_REGS; + sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); + cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id); + + /* First check conditions for semaphore mode, which doesn't take into account static CID. */ + if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) { + if (cid_reg_value & BIT(RIF_CID1 + SEMWL_SHIFT)) { + /* Static CID is irrelevant if semaphore mode */ + goto skip_cid_check; + } else { + dev_dbg(rifsc_controller->dev, + "Invalid bus semaphore configuration: index %d\n", firewall_id); + return -EACCES; + } + } + + /* + * Skip CID check if CID filtering isn't enabled or filtering is enabled on CID0, which + * corresponds to whatever CID. + */ + if (!(cid_reg_value & CIDCFGR_CFEN) || + FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0) + goto skip_cid_check; + + /* Coherency check with the CID configuration */ + if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) { + dev_dbg(rifsc_controller->dev, "Invalid CID configuration for peripheral: %d\n", + firewall_id); + return -EACCES; + } + +skip_cid_check: + /* Check security configuration */ + if (sec_reg_value & BIT(reg_offset)) { + dev_dbg(rifsc_controller->dev, + "Invalid security configuration for peripheral: %d\n", firewall_id); + return -EACCES; + } + + /* + * If the peripheral is in semaphore mode, take the semaphore so that + * the CID1 has the ownership. + */ + if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) { + rc = stm32_rif_acquire_semaphore(rifsc_controller, firewall_id); + if (rc) { + dev_err(rifsc_controller->dev, + "Couldn't acquire semaphore for peripheral: %d\n", firewall_id); + return rc; + } + } + + return 0; +} + +static void stm32_rifsc_release_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + stm32_rif_release_semaphore(ctrl, firewall_id); +} + +static int stm32_rifsc_probe(struct platform_device *pdev) +{ + struct stm32_firewall_controller *rifsc_controller; + struct device_node *np = pdev->dev.of_node; + u32 nb_risup, nb_rimu, nb_risal; + struct resource *res; + void __iomem *mmio; + int rc; + + rifsc_controller = devm_kzalloc(&pdev->dev, sizeof(*rifsc_controller), GFP_KERNEL); + if (!rifsc_controller) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mmio = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + rifsc_controller->dev = &pdev->dev; + rifsc_controller->mmio = mmio; + rifsc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL; + rifsc_controller->grant_access = stm32_rifsc_grant_access; + rifsc_controller->release_access = stm32_rifsc_release_access; + + /* Get number of RIFSC entries*/ + nb_risup = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF1_MASK; + nb_rimu = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF2_MASK; + nb_risal = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF3_MASK; + rifsc_controller->max_entries = nb_risup + nb_rimu + nb_risal; + + platform_set_drvdata(pdev, rifsc_controller); + + rc = stm32_firewall_controller_register(rifsc_controller); + if (rc) { + dev_err(rifsc_controller->dev, "Couldn't register as a firewall controller: %d", + rc); + return rc; + } + + stm32_firewall_populate_bus(rifsc_controller); + + /* Populate all allowed nodes */ + return of_platform_populate(np, NULL, NULL, &pdev->dev); +} + +static const struct of_device_id stm32_rifsc_of_match[] = { + { .compatible = "st,stm32mp25-rifsc" }, + {} +}; +MODULE_DEVICE_TABLE(of, stm32_rifsc_of_match); + +static struct platform_driver stm32_rifsc_driver = { + .probe = stm32_rifsc_probe, + .driver = { + .name = "stm32-rifsc", + .of_match_table = stm32_rifsc_of_match, + }, +}; + +static int __init stm32_rifsc_init(void) +{ + return platform_driver_register(&stm32_rifsc_driver); +} +arch_initcall(stm32_rifsc_init);
RIFSC is a firewall controller. Change its compatible so that is matches the documentation and reference RIFSC as a feature-domain-controller.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5268a4321841..62101084cab8 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -106,17 +106,20 @@ soc@0 { ranges = <0x0 0x0 0x0 0x80000000>;
rifsc: rifsc-bus@42080000 { - compatible = "simple-bus"; + compatible = "st,stm32mp25-rifsc"; reg = <0x42080000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges; + feature-domain-controller; + #feature-domain-cells = <1>;
usart2: serial@400e0000 { compatible = "st,stm32h7-uart"; reg = <0x400e0000 0x400>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ck_flexgen_08>; + feature-domains = <&rifsc 32>; status = "disabled"; }; };
Hi Gatien
On 7/5/23 19:27, Gatien Chevallier wrote:
RIFSC is a firewall controller. Change its compatible so that is matches the documentation and reference RIFSC as a feature-domain-controller.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
arch/arm64/boot/dts/st/stm32mp251.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5268a4321841..62101084cab8 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -106,17 +106,20 @@ soc@0 { ranges = <0x0 0x0 0x0 0x80000000>;
rifsc: rifsc-bus@42080000 {
compatible = "simple-bus";
compatible = "st,stm32mp25-rifsc";
You could keep "simple-bus" compatible (in second position). In case of the RIFSC is not probed, the platform will be able to boot. If you agree you can use the same for ETZPC.
Cheers Alex
reg = <0x42080000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges;
feature-domain-controller;#feature-domain-cells = <1>; usart2: serial@400e0000 { compatible = "st,stm32h7-uart"; reg = <0x400e0000 0x400>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ck_flexgen_08>;feature-domains = <&rifsc 32>; status = "disabled"; };};
Hi Alex,
On 7/6/23 11:25, Alexandre TORGUE wrote:
Hi Gatien
On 7/5/23 19:27, Gatien Chevallier wrote:
RIFSC is a firewall controller. Change its compatible so that is matches the documentation and reference RIFSC as a feature-domain-controller.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
arch/arm64/boot/dts/st/stm32mp251.dtsi | 5 ++++- Â 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5268a4321841..62101084cab8 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -106,17 +106,20 @@ soc@0 { Â Â Â Â Â Â Â Â Â ranges = <0x0 0x0 0x0 0x80000000>; Â Â Â Â Â Â Â Â Â rifsc: rifsc-bus@42080000 { -Â Â Â Â Â Â Â Â Â Â Â compatible = "simple-bus"; +Â Â Â Â Â Â Â Â Â Â Â compatible = "st,stm32mp25-rifsc";
You could keep "simple-bus" compatible (in second position). In case of the RIFSC is not probed, the platform will be able to boot. If you agree you can use the same for ETZPC.
Cheers Alex
Sure, good point.
I'll change that in V2
Best regards, Gatien
reg = <0x42080000 0x1000>; Â Â Â Â Â Â Â Â Â Â Â Â Â #address-cells = <1>; Â Â Â Â Â Â Â Â Â Â Â Â Â #size-cells = <1>; Â Â Â Â Â Â Â Â Â Â Â Â Â ranges; +Â Â Â Â Â Â Â Â Â Â Â feature-domain-controller; +Â Â Â Â Â Â Â Â Â Â Â #feature-domain-cells = <1>; Â Â Â Â Â Â Â Â Â Â Â Â Â usart2: serial@400e0000 { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â compatible = "st,stm32h7-uart"; Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â reg = <0x400e0000 0x400>; Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â clocks = <&ck_flexgen_08>; +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â feature-domains = <&rifsc 32>; Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â status = "disabled"; Â Â Â Â Â Â Â Â Â Â Â Â Â }; Â Â Â Â Â Â Â Â Â };
Hi Alex,
On 7/6/23 11:30, Gatien CHEVALLIER wrote:
Hi Alex,
On 7/6/23 11:25, Alexandre TORGUE wrote:
Hi Gatien
On 7/5/23 19:27, Gatien Chevallier wrote:
RIFSC is a firewall controller. Change its compatible so that is matches the documentation and reference RIFSC as a feature-domain-controller.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com
arch/arm64/boot/dts/st/stm32mp251.dtsi | 5 ++++- Â 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5268a4321841..62101084cab8 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -106,17 +106,20 @@ soc@0 { Â Â Â Â Â Â Â Â Â ranges = <0x0 0x0 0x0 0x80000000>; Â Â Â Â Â Â Â Â Â rifsc: rifsc-bus@42080000 { -Â Â Â Â Â Â Â Â Â Â Â compatible = "simple-bus"; +Â Â Â Â Â Â Â Â Â Â Â compatible = "st,stm32mp25-rifsc";
You could keep "simple-bus" compatible (in second position). In case of the RIFSC is not probed, the platform will be able to boot. If you agree you can use the same for ETZPC.
Cheers Alex
Sure, good point.
I'll change that in V2
Best regards, Gatien
Actually, it would be a bad idea to keep "simple-bus" as a compatible.
Practical example: 1) Firewall controller forbids a device probe by marking the device's node as populated (OF_POPULATED flag). 2) The simple-bus, which is simple, populates all the devices from the device tree data, overriding what the firewall bus has done. 3)=>Forbidden device's driver will be probed.
I think it's best to keep one compatible. If someone wants these drivers as external modules, then it'll be best to handle this differently. I'll resubmit with a single compatible for V2, please do not hesitate to comment on the V2 if you're not okay with this.
Best regards, Gatien
reg = <0x42080000 0x1000>; Â Â Â Â Â Â Â Â Â Â Â Â Â #address-cells = <1>; Â Â Â Â Â Â Â Â Â Â Â Â Â #size-cells = <1>; Â Â Â Â Â Â Â Â Â Â Â Â Â ranges; +Â Â Â Â Â Â Â Â Â Â Â feature-domain-controller; +Â Â Â Â Â Â Â Â Â Â Â #feature-domain-cells = <1>; Â Â Â Â Â Â Â Â Â Â Â Â Â usart2: serial@400e0000 { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â compatible = "st,stm32h7-uart"; Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â reg = <0x400e0000 0x400>; Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â clocks = <&ck_flexgen_08>; +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â feature-domains = <&rifsc 32>; Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â status = "disabled"; Â Â Â Â Â Â Â Â Â Â Â Â Â }; Â Â Â Â Â Â Â Â Â };
ETZPC is a peripheral and memory firewall controller that filter accesses based on Arm TrustZone secure state and Arm CPU privilege execution level. It handles MCU isolation as well.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com --- MAINTAINERS | 1 + drivers/bus/Makefile | 2 +- drivers/bus/stm32_etzpc.c | 137 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 139 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/stm32_etzpc.c
diff --git a/MAINTAINERS b/MAINTAINERS index 1ea2f9f60b43..51f5bced7b9b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20126,6 +20126,7 @@ F: drivers/media/i2c/st-mipid02.c ST STM32 FIREWALL M: Gatien Chevallier gatien.chevallier@foss.st.com S: Maintained +F: drivers/bus/stm32_etzpc.c F: drivers/bus/stm32_firewall.c F: drivers/bus/stm32_rifsc.c
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index e50d18e1d141..cddd4984d6af 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o -obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o stm32_etzpc.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_etzpc.c b/drivers/bus/stm32_etzpc.c new file mode 100644 index 000000000000..2ef5ab738f87 --- /dev/null +++ b/drivers/bus/stm32_etzpc.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/types.h> + +#include "stm32_firewall.h" + +/* + * ETZPC registers + */ +#define ETZPC_DECPROT 0x10 +#define ETZPC_HWCFGR 0x3F0 + +/* + * HWCFGR register + */ +#define ETZPC_HWCFGR_NUM_TZMA GENMASK(7, 0) +#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8) +#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16) +#define ETZPC_HWCFGR_CHUNKS1N4 GENMASK(31, 24) + +/* + * ETZPC miscellaneous + */ +#define ETZPC_PROT_MASK GENMASK(1, 0) +#define ETZPC_PROT_A7NS 0x3 +#define ETZPC_DECPROT_SHIFT 1 + +#define IDS_PER_DECPROT_REGS 16 + +static int stm32_etzpc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + u32 offset, reg_offset, sec_val; + + if (firewall_id >= ctrl->max_entries) { + dev_err(ctrl->dev, "Invalid sys bus ID %u", firewall_id); + return -EINVAL; + } + + /* Check access configuration, 16 peripherals per register */ + reg_offset = ETZPC_DECPROT + 0x4 * (firewall_id / IDS_PER_DECPROT_REGS); + offset = (firewall_id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT; + + /* Verify peripheral is non-secure and attributed to cortex A7 */ + sec_val = (readl(ctrl->mmio + reg_offset) >> offset) & ETZPC_PROT_MASK; + if (sec_val != ETZPC_PROT_A7NS) { + dev_dbg(ctrl->dev, "Invalid bus configuration: reg_offset %#x, value %d\n", + reg_offset, sec_val); + return -EACCES; + } + + return 0; +} + +static void stm32_etzpc_release_access(struct stm32_firewall_controller *ctrl __maybe_unused, + u32 firewall_id __maybe_unused) +{ +} + +static int stm32_etzpc_probe(struct platform_device *pdev) +{ + struct stm32_firewall_controller *etzpc_controller; + struct device_node *np = pdev->dev.of_node; + u32 nb_per, nb_master; + struct resource *res; + void __iomem *mmio; + int rc; + + etzpc_controller = devm_kzalloc(&pdev->dev, sizeof(*etzpc_controller), GFP_KERNEL); + if (!etzpc_controller) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mmio = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + etzpc_controller->dev = &pdev->dev; + etzpc_controller->mmio = mmio; + etzpc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL; + etzpc_controller->grant_access = stm32_etzpc_grant_access; + etzpc_controller->release_access = stm32_etzpc_release_access; + + /* Get number of etzpc entries*/ + nb_per = FIELD_GET(ETZPC_HWCFGR_NUM_PER_SEC, + readl(etzpc_controller->mmio + ETZPC_HWCFGR)); + nb_master = FIELD_GET(ETZPC_HWCFGR_NUM_AHB_SEC, + readl(etzpc_controller->mmio + ETZPC_HWCFGR)); + etzpc_controller->max_entries = nb_per + nb_master; + + platform_set_drvdata(pdev, etzpc_controller); + + rc = stm32_firewall_controller_register(etzpc_controller); + if (rc) { + dev_err(etzpc_controller->dev, "Couldn't register as a firewall controller: %d", + rc); + return rc; + } + + stm32_firewall_populate_bus(etzpc_controller); + + /* Populate all allowed nodes */ + return of_platform_populate(np, NULL, NULL, &pdev->dev); +} + +static const struct of_device_id stm32_etzpc_of_match[] = { + { .compatible = "st,stm32-etzpc" }, + {} +}; +MODULE_DEVICE_TABLE(of, stm32_etzpc_of_match); + +static struct platform_driver stm32_etzpc_driver = { + .probe = stm32_etzpc_probe, + .driver = { + .name = "stm32-etzpc", + .of_match_table = stm32_etzpc_of_match, + }, +}; + +static int __init stm32_etzpc_init(void) +{ + return platform_driver_register(&stm32_etzpc_driver); +} +arch_initcall(stm32_etzpc_init);
ETZPC is a firewall controller. Put all peripherals filtered by the ETZPC as ETZPC subnodes and reference ETZPC as a feature-domain-controller.
For more information on which peripheral is securable or supports MCU isolation, please read the STM32MP15 reference manual.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com --- arch/arm/boot/dts/st/stm32mp151.dtsi | 2757 +++++++++++++------------ arch/arm/boot/dts/st/stm32mp153.dtsi | 52 +- arch/arm/boot/dts/st/stm32mp15xc.dtsi | 19 +- 3 files changed, 1451 insertions(+), 1377 deletions(-)
diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index 61508917521c..764e3fc60521 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -122,1543 +122,1616 @@ soc { interrupt-parent = <&intc>; ranges;
- timers2: timer@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM2_K>; - clock-names = "int"; - dmas = <&dmamux1 18 0x400 0x1>, - <&dmamux1 19 0x400 0x1>, - <&dmamux1 20 0x400 0x1>, - <&dmamux1 21 0x400 0x1>, - <&dmamux1 22 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + ipcc: mailbox@4c001000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = + <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + clocks = <&rcc IPCC>; + wakeup-source; status = "disabled"; + };
- pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32h7-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; + rcc: rcc@50000000 { + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; };
- timers3: timer@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM3_K>; - clock-names = "int"; - dmas = <&dmamux1 23 0x400 0x1>, - <&dmamux1 24 0x400 0x1>, - <&dmamux1 25 0x400 0x1>, - <&dmamux1 26 0x400 0x1>, - <&dmamux1 27 0x400 0x1>, - <&dmamux1 28 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; + pwr_regulators: pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>;
- pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; };
- timer@2 { - compatible = "st,stm32h7-timer-trigger"; - reg = <2>; - status = "disabled"; + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; };
- counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; };
- timers4: timer@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM4_K>; - clock-names = "int"; - dmas = <&dmamux1 29 0x400 0x1>, - <&dmamux1 30 0x400 0x1>, - <&dmamux1 31 0x400 0x1>, - <&dmamux1 32 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; + pwr_mcu: pwr_mcu@50001014 { + compatible = "st,stm32mp151-pwr-mcu", "syscon"; + reg = <0x50001014 0x4>; + };
- timer@3 { - compatible = "st,stm32h7-timer-trigger"; - reg = <3>; - status = "disabled"; - }; + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + };
- counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; };
- timers5: timer@40003000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40003000 0x400>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM5_K>; - clock-names = "int"; - dmas = <&dmamux1 55 0x400 0x1>, - <&dmamux1 56 0x400 0x1>, - <&dmamux1 57 0x400 0x1>, - <&dmamux1 58 0x400 0x1>, - <&dmamux1 59 0x400 0x1>, - <&dmamux1 60 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc TMPSENS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; status = "disabled"; + };
- pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32h7-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; + mdma1: dma-controller@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc MDMA>; + resets = <&rcc MDMA_R>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; };
- timers6: timer@40004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40004000 0x400>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM6_K>; - clock-names = "int"; - dmas = <&dmamux1 69 0x400 0x1>; - dma-names = "up"; + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x58005000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; status = "disabled"; - - timer@5 { - compatible = "st,stm32h7-timer-trigger"; - reg = <5>; - status = "disabled"; - }; };
- timers7: timer@40005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40005000 0x400>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM7_K>; - clock-names = "int"; - dmas = <&dmamux1 70 0x400 0x1>; - dma-names = "up"; + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x58007000 0x1000>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; status = "disabled"; - - timer@6 { - compatible = "st,stm32h7-timer-trigger"; - reg = <6>; - status = "disabled"; - }; };
- timers12: timer@40006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40006000 0x400>; - interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM12_K>; - clock-names = "int"; + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; };
- timers13: timer@40007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40007000 0x400>; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM13_K>; - clock-names = "int"; + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; };
- timers14: timer@40008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40008000 0x400>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM14_K>; - clock-names = "int"; + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + companion = <&usbh_ohci>; status = "disabled"; + };
- pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; + ltdc: display-controller@5a001000 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&rcc LTDC_R>; + status = "disabled"; + };
- timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; };
- lptimer1: timer@40009000 { + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40009000 0x400>; - interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM1_K>; - clock-names = "mux"; - wakeup-source; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; status = "disabled";
- pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; reg = <0>; - status = "disabled"; };
- counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; }; };
- spi2: spi@4000b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - dmas = <&dmamux1 39 0x400 0x05>, - <&dmamux1 40 0x400 0x05>; - dma-names = "rx", "tx"; + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + clocks = <&rcc RTCAPB>, <&rcc RTC>; + clock-names = "pclk", "rtc_ck"; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; };
- i2s2: audio-controller@4000b000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000b000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; + bsec: efuse@5c005000 { + compatible = "st,stm32mp15-bsec"; + reg = <0x5c005000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + part_number_otp: part-number-otp@4 { + reg = <0x4 0x1>; + }; + vrefint: vrefin-cal@52 { + reg = <0x52 0x2>; + }; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; };
- spi3: spi@4000c000 { + etzpc: bus@5c007000 { + compatible = "st,stm32-etzpc"; + reg = <0x5c007000 0x400>; #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000c000 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI3_K>; - resets = <&rcc SPI3_R>; - dmas = <&dmamux1 61 0x400 0x05>, - <&dmamux1 62 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + feature-domain-controller; + #feature-domain-cells = <1>; + ranges;
- i2s3: audio-controller@4000c000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000c000 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + feature-domains = <&etzpc 16>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + };
- spdifrx: audio-controller@4000d000 { - compatible = "st,stm32h7-spdifrx"; - #sound-dai-cells = <0>; - reg = <0x4000d000 0x400>; - clocks = <&rcc SPDIF_K>; - clock-names = "kclk"; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 93 0x400 0x01>, - <&dmamux1 94 0x400 0x01>; - dma-names = "rx", "rx-ctrl"; - status = "disabled"; - }; + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + };
- usart2: serial@4000e000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000e000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x15>, - <&dmamux1 44 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + };
- usart3: serial@4000f000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000f000 0x400>; - interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART3_K>; - wakeup-source; - dmas = <&dmamux1 45 0x400 0x15>, - <&dmamux1 46 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + feature-domains = <&etzpc 17>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + };
- uart4: serial@40010000 { - compatible = "st,stm32h7-uart"; - reg = <0x40010000 0x400>; - interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART4_K>; - wakeup-source; - dmas = <&dmamux1 63 0x400 0x15>, - <&dmamux1 64 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + };
- uart5: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART5_K>; - wakeup-source; - dmas = <&dmamux1 65 0x400 0x15>, - <&dmamux1 66 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + };
- i2c1: i2c@40012000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40012000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C1_K>; - resets = <&rcc I2C1_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x1>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; + feature-domains = <&etzpc 18>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + };
- i2c2: i2c@40013000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40013000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C2_K>; - resets = <&rcc I2C2_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x2>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + };
- i2c3: i2c@40014000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40014000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + };
- i2c5: i2c@40015000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40015000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + feature-domains = <&etzpc 19>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + };
- cec: cec@40016000 { - compatible = "st,stm32-cec"; - reg = <0x40016000 0x400>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CEC_K>, <&rcc CEC>; - clock-names = "cec", "hdmi-cec"; - status = "disabled"; - }; + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + };
- dac: dac@40017000 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40017000 0x400>; - clocks = <&rcc DAC12>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + };
- dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <1>; - status = "disabled"; + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; + feature-domains = <&etzpc 20>; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; };
- dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <2>; - status = "disabled"; + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; + feature-domains = <&etzpc 21>; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; }; - };
- uart7: serial@40018000 { - compatible = "st,stm32h7-uart"; - reg = <0x40018000 0x400>; - interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART7_K>; - wakeup-source; - dmas = <&dmamux1 79 0x400 0x15>, - <&dmamux1 80 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + timers12: timer@40006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40006000 0x400>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + feature-domains = <&etzpc 22>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + };
- uart8: serial@40019000 { - compatible = "st,stm32h7-uart"; - reg = <0x40019000 0x400>; - interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART8_K>; - wakeup-source; - dmas = <&dmamux1 81 0x400 0x15>, - <&dmamux1 82 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + };
- timers1: timer@44000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44000000 0x400>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM1_K>; - clock-names = "int"; - dmas = <&dmamux1 11 0x400 0x1>, - <&dmamux1 12 0x400 0x1>, - <&dmamux1 13 0x400 0x1>, - <&dmamux1 14 0x400 0x1>, - <&dmamux1 15 0x400 0x1>, - <&dmamux1 16 0x400 0x1>, - <&dmamux1 17 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; + timers13: timer@40007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40007000 0x400>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + feature-domains = <&etzpc 23>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + };
- pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; };
- timer@0 { - compatible = "st,stm32h7-timer-trigger"; - reg = <0>; - status = "disabled"; - }; + timers14: timer@40008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40008000 0x400>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + feature-domains = <&etzpc 24>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + };
- counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; }; - };
- timers8: timer@44001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44001000 0x400>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM8_K>; - clock-names = "int"; - dmas = <&dmamux1 47 0x400 0x1>, - <&dmamux1 48 0x400 0x1>, - <&dmamux1 49 0x400 0x1>, - <&dmamux1 50 0x400 0x1>, - <&dmamux1 51 0x400 0x1>, - <&dmamux1 52 0x400 0x1>, - <&dmamux1 53 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; + feature-domains = <&etzpc 25>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + };
- pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; };
- timer@7 { - compatible = "st,stm32h7-timer-trigger"; - reg = <7>; + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 27>; status = "disabled"; };
- counter { - compatible = "st,stm32-timer-counter"; + spi2: spi@4000b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + dmas = <&dmamux1 39 0x400 0x05>, + <&dmamux1 40 0x400 0x05>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 27>; status = "disabled"; }; - }; - - usart6: serial@44003000 { - compatible = "st,stm32h7-uart"; - reg = <0x44003000 0x400>; - interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART6_K>; - wakeup-source; - dmas = <&dmamux1 71 0x400 0x15>, - <&dmamux1 72 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi1: spi@44004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44004000 0x400>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI1_K>; - resets = <&rcc SPI1_R>; - dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: audio-controller@44004000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x44004000 0x400>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - };
- spi4: spi@44005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44005000 0x400>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - dmas = <&dmamux1 83 0x400 0x05>, - <&dmamux1 84 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers15: timer@44006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44006000 0x400>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000c000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 28>; status = "disabled"; };
- timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; + spi3: spi@4000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + dmas = <&dmamux1 61 0x400 0x05>, + <&dmamux1 62 0x400 0x05>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 28>; status = "disabled"; }; - }; - - timers16: timer@44007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44007000 0x400>; - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled";
- pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; + reg = <0x4000d000 0x400>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + feature-domains = <&etzpc 29>; + status = "disabled"; + }; + + usart2: serial@4000e000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000e000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 30>; + status = "disabled"; + }; + + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 31>; + status = "disabled"; + }; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART4_K>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 32>; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 33>; + status = "disabled"; + }; + + i2c1: i2c@40012000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + wakeup-source; + i2c-analog-filter; + feature-domains = <&etzpc 34>; status = "disabled"; }; - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; + + i2c2: i2c@40013000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; + i2c-analog-filter; + feature-domains = <&etzpc 35>; status = "disabled"; }; - };
- timers17: timer@44008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44008000 0x400>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; + i2c3: i2c@40014000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40014000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; + i2c-analog-filter; + feature-domains = <&etzpc 36>; + status = "disabled"; + };
- pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; + i2c5: i2c@40015000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40015000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; + i2c-analog-filter; + feature-domains = <&etzpc 37>; status = "disabled"; };
- timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; + cec: cec@40016000 { + compatible = "st,stm32-cec"; + reg = <0x40016000 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CEC_K>, <&rcc CEC>; + clock-names = "cec", "hdmi-cec"; + feature-domains = <&etzpc 38>; status = "disabled"; }; - };
- spi5: spi@44009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44009000 0x400>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - dmas = <&dmamux1 85 0x400 0x05>, - <&dmamux1 86 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + dac: dac@40017000 { + compatible = "st,stm32h7-dac-core"; + reg = <0x40017000 0x400>; + clocks = <&rcc DAC12>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + feature-domains = <&etzpc 39>; + status = "disabled";
- sai1: sai@4400a000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400a000 0x400>; - reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI1_R>; - status = "disabled"; + dac1: dac@1 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <1>; + status = "disabled"; + };
- sai1a: audio-controller@4400a004 { - #sound-dai-cells = <0>; + dac2: dac@2 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <2>; + status = "disabled"; + }; + };
- compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 87 0x400 0x01>; + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 40>; status = "disabled"; };
- sai1b: audio-controller@4400a024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 88 0x400 0x01>; + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 41>; status = "disabled"; }; - };
- sai2: sai@4400b000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400b000 0x400>; - reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI2_R>; - status = "disabled"; + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + feature-domains = <&etzpc 48>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + };
- sai2a: audio-controller@4400b004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 89 0x400 0x01>; - status = "disabled"; - }; + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + };
- sai2b: audio-controller@4400b024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 90 0x400 0x01>; - status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; }; - };
- sai3: sai@4400c000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400c000 0x400>; - reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI3_R>; - status = "disabled"; + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + feature-domains = <&etzpc 49>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + };
- sai3a: audio-controller@4400c004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 113 0x400 0x01>; + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 51>; status = "disabled"; };
- sai3b: audio-controller@4400c024 { + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 114 0x400 0x01>; + reg = <0x44004000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 52>; status = "disabled"; }; - }; - - dfsdm: dfsdm@4400d000 { - compatible = "st,stm32mp1-dfsdm"; - reg = <0x4400d000 0x800>; - clocks = <&rcc DFSDM_K>; - clock-names = "dfsdm"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled";
- dfsdm0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <0>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 101 0x400 0x01>; - dma-names = "rx"; + spi1: spi@44004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 52>; status = "disabled"; };
- dfsdm1: filter@1 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <1>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 102 0x400 0x01>; - dma-names = "rx"; + spi4: spi@44005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44005000 0x400>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + dmas = <&dmamux1 83 0x400 0x05>, + <&dmamux1 84 0x400 0x05>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 53>; status = "disabled"; };
- dfsdm2: filter@2 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <2>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 103 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; + timers15: timer@44006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44006000 0x400>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + feature-domains = <&etzpc 54>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; };
- dfsdm3: filter@3 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <3>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 104 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; + timers16: timer@44007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44007000 0x400>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + feature-domains = <&etzpc 55>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; };
- dfsdm4: filter@4 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <4>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 91 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; + timers17: timer@44008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44008000 0x400>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + feature-domains = <&etzpc 56>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; };
- dfsdm5: filter@5 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <5>; - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 92 0x400 0x01>; - dma-names = "rx"; + spi5: spi@44009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44009000 0x400>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + dmas = <&dmamux1 85 0x400 0x05>, + <&dmamux1 86 0x400 0x05>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 57>; status = "disabled"; }; - };
- dma1: dma-controller@48000000 { - compatible = "st,stm32-dma"; - reg = <0x48000000 0x400>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc DMA1>; - resets = <&rcc DMA1_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400a000 0x400>; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI1_R>; + feature-domains = <&etzpc 58>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + #sound-dai-cells = <0>; + + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + };
- dma2: dma-controller@48001000 { - compatible = "st,stm32-dma"; - reg = <0x48001000 0x400>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc DMA2>; - resets = <&rcc DMA2_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; + sai1b: audio-controller@4400a024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + };
- dmamux1: dma-router@48002000 { - compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x40>; - #dma-cells = <3>; - dma-requests = <128>; - dma-masters = <&dma1 &dma2>; - dma-channels = <16>; - clocks = <&rcc DMAMUX>; - resets = <&rcc DMAMUX_R>; - }; + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400b000 0x400>; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI2_R>; + feature-domains = <&etzpc 59>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + };
- adc: adc@48003000 { - compatible = "st,stm32mp1-adc-core"; - reg = <0x48003000 0x400>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc ADC12>, <&rcc ADC12_K>; - clock-names = "bus", "adc"; - interrupt-controller; - st,syscfg = <&syscfg>; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + sai2b: audio-controller@4400b024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + };
- adc1: adc@0 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; + sai3: sai@4400c000 { + compatible = "st,stm32h7-sai"; #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; + #size-cells = <1>; + ranges = <0 0x4400c000 0x400>; + reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI3_R>; + feature-domains = <&etzpc 60>; + status = "disabled"; + + sai3a: audio-controller@4400c004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 113 0x400 0x01>; + status = "disabled"; + }; + + sai3b: audio-controller@4400c024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 114 0x400 0x01>; + status = "disabled"; + }; };
- adc2: adc@100 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; #address-cells = <1>; #size-cells = <0>; - reg = <0x100>; - interrupt-parent = <&adc>; - interrupts = <1>; - dmas = <&dmamux1 10 0x400 0x01>; - dma-names = "rx"; - nvmem-cells = <&vrefint>; - nvmem-cell-names = "vrefint"; - status = "disabled"; - channel@13 { - reg = <13>; - label = "vrefint"; + feature-domains = <&etzpc 61>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <0>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; }; - channel@14 { - reg = <14>; - label = "vddcore"; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <1>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; }; - }; - };
- sdmmc3: mmc@48004000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x48004000 0x400>; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC3_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC3_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; + dfsdm2: filter@2 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <2>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 103 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + };
- usbotg_hs: usb-otg@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>, <&usbphyc>; - clock-names = "otg", "utmi"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&usb33>; - status = "disabled"; - }; - - ipcc: mailbox@4c001000 { - compatible = "st,stm32mp1-ipcc"; - #mbox-cells = <1>; - reg = <0x4c001000 0x400>; - st,proc-id = <0>; - interrupts-extended = - <&exti 61 1>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "rx", "tx"; - clocks = <&rcc IPCC>; - wakeup-source; - status = "disabled"; - }; - - dcmi: dcmi@4c006000 { - compatible = "st,stm32-dcmi"; - reg = <0x4c006000 0x400>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc CAMITF_R>; - clocks = <&rcc DCMI>; - clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x01>; - dma-names = "tx"; - status = "disabled"; - }; - - rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; + dfsdm3: filter@3 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <3>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 104 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + };
- pwr_regulators: pwr@50001000 { - compatible = "st,stm32mp1,pwr-reg"; - reg = <0x50001000 0x10>; + dfsdm4: filter@4 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <4>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 91 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + };
- reg11: reg11 { - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; + dfsdm5: filter@5 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <5>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 92 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; };
- reg18: reg18 { - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + feature-domains = <&etzpc 88>; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + feature-domains = <&etzpc 89>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + #dma-cells = <3>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + dma-channels = <16>; + clocks = <&rcc DMAMUX>; + resets = <&rcc DMAMUX_R>; + feature-domains = <&etzpc 90>; + }; + + adc: adc@48003000 { + compatible = "st,stm32mp1-adc-core"; + reg = <0x48003000 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC12>, <&rcc ADC12_K>; + clock-names = "bus", "adc"; + interrupt-controller; + st,syscfg = <&syscfg>; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + feature-domains = <&etzpc 72>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + };
- usb33: usb33 { - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + adc2: adc@100 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100>; + interrupt-parent = <&adc>; + interrupts = <1>; + dmas = <&dmamux1 10 0x400 0x01>; + dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; + status = "disabled"; + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + }; }; - };
- pwr_mcu: pwr_mcu@50001014 { - compatible = "st,stm32mp151-pwr-mcu", "syscon"; - reg = <0x50001014 0x4>; - }; + sdmmc3: mmc@48004000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x48004000 0x400>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SDMMC3_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC3_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + feature-domains = <&etzpc 86>; + status = "disabled"; + }; + + usbotg_hs: usb-otg@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>, <&usbphyc>; + clock-names = "otg", "utmi"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + feature-domains = <&etzpc 85>; + status = "disabled"; + }; + + dcmi: dcmi@4c006000 { + compatible = "st,stm32-dcmi"; + reg = <0x4c006000 0x400>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc CAMITF_R>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; + dmas = <&dmamux1 75 0x400 0x01>; + dma-names = "tx"; + feature-domains = <&etzpc 70>; + status = "disabled"; + }; + + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + feature-domains = <&etzpc 64>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + };
- exti: interrupt-controller@5000d000 { - compatible = "st,stm32mp1-exti", "syscon"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000d000 0x400>; - }; + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + };
- syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - clocks = <&rcc SYSCFG>; - }; + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + };
- lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + feature-domains = <&etzpc 65>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + };
- pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; };
- trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; + feature-domains = <&etzpc 66>; status = "disabled"; - };
- counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled";
- pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; + feature-domains = <&etzpc 67>; status = "disabled"; - };
- trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; }; - }; - - lptimer4: timer@50023000 { - compatible = "st,stm32-lptimer"; - reg = <0x50023000 0x400>; - interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM4_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled";
- pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; + vrefbuf: vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; + feature-domains = <&etzpc 69>; status = "disabled"; }; - };
- lptimer5: timer@50024000 { - compatible = "st,stm32-lptimer"; - reg = <0x50024000 0x400>; - interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM5_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; + sai4: sai@50027000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50027000 0x400>; + reg = <0x50027000 0x4>, <0x500273f0 0x10>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI4_R>; + feature-domains = <&etzpc 68>; + status = "disabled"; + + sai4a: audio-controller@50027004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 99 0x400 0x01>; + status = "disabled"; + };
- pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; + sai4b: audio-controller@50027024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 100 0x400 0x01>; + status = "disabled"; + }; }; - };
- vrefbuf: vrefbuf@50025000 { - compatible = "st,stm32-vrefbuf"; - reg = <0x50025000 0x8>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - clocks = <&rcc VREF>; - status = "disabled"; - }; - - sai4: sai@50027000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50027000 0x400>; - reg = <0x50027000 0x4>, <0x500273f0 0x10>; - interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI4_R>; - status = "disabled"; + hash1: hash@54002000 { + compatible = "st,stm32f756-hash"; + reg = <0x54002000 0x400>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; + dma-names = "in"; + dma-maxburst = <2>; + feature-domains = <&etzpc 8>; + status = "disabled"; + }; + + rng1: rng@54003000 { + compatible = "st,stm32-rng"; + reg = <0x54003000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + feature-domains = <&etzpc 7>; + status = "okay"; + }; + + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + feature-domains = <&etzpc 91>; + status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, + <&mdma1 20 0x2 0x12000a08 0x0 0x0>, + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + };
- sai4a: audio-controller@50027004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 99 0x400 0x01>; - status = "disabled"; + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, + <&mdma1 22 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + #address-cells = <1>; + #size-cells = <0>; + feature-domains = <&etzpc 92>; + status = "disabled"; + }; + + ethernet0: ethernet@5800a000 { + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; + st,syscon = <&syscfg 0x4>; + snps,mixed-burst; + snps,pbl = <2>; + snps,en-tx-lpi-clockgating; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; + feature-domains = <&etzpc 94>; + status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; };
- sai4b: audio-controller@50027024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 100 0x400 0x01>; + usart1: serial@5c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x5c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + wakeup-source; + feature-domains = <&etzpc 3>; status = "disabled"; }; - }; - - dts: thermal@50028000 { - compatible = "st,stm32-thermal"; - reg = <0x50028000 0x100>; - interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc TMPSENS>; - clock-names = "pclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - hash1: hash@54002000 { - compatible = "st,stm32f756-hash"; - reg = <0x54002000 0x400>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; - dma-names = "in"; - dma-maxburst = <2>; - status = "disabled"; - }; - - rng1: rng@54003000 { - compatible = "st,stm32-rng"; - reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; - status = "disabled"; - };
- mdma1: dma-controller@58000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x58000000 0x1000>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc MDMA>; - resets = <&rcc MDMA_R>; - #dma-cells = <5>; - dma-channels = <32>; - dma-requests = <48>; - }; - - fmc: memory-controller@58002000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ - - nand-controller@4,0 { + spi6: spi@5c001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x5c001000 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; + dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, + <&mdma1 35 0x0 0x40002 0x0 0x0>; + feature-domains = <&etzpc 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c4: i2c@5c002000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x5c002000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; #address-cells = <1>; #size-cells = <0>; - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, - <&mdma1 20 0x2 0x12000a08 0x0 0x0>, - <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; + i2c-analog-filter; + feature-domains = <&etzpc 5>; status = "disabled"; }; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, - <&mdma1 22 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x58005000 0x1000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x58007000 0x1000>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - crc1: crc@58009000 { - compatible = "st,stm32f7-crc"; - reg = <0x58009000 0x400>; - clocks = <&rcc CRC1>; - status = "disabled"; - }; - - ethernet0: ethernet@5800a000 { - compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; - reg = <0x5800a000 0x2000>; - reg-names = "stmmaceth"; - interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", - "mac-clk-tx", - "mac-clk-rx", - "eth-ck", - "ptp_ref", - "ethstp"; - clocks = <&rcc ETHMAC>, - <&rcc ETHTX>, - <&rcc ETHRX>, - <&rcc ETHCK_K>, - <&rcc ETHPTP_K>, - <&rcc ETHSTP>; - st,syscon = <&syscfg 0x4>; - snps,mixed-burst; - snps,pbl = <2>; - snps,en-tx-lpi-clockgating; - snps,axi-config = <&stmmac_axi_config_0>; - snps,tso; - status = "disabled"; - - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - }; - - usbh_ohci: usb@5800c000 { - compatible = "generic-ohci"; - reg = <0x5800c000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - };
- usbh_ehci: usb@5800d000 { - compatible = "generic-ehci"; - reg = <0x5800d000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - companion = <&usbh_ohci>; - status = "disabled"; - }; - - ltdc: display-controller@5a001000 { - compatible = "st,stm32-ltdc"; - reg = <0x5a001000 0x400>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LTDC_PX>; - clock-names = "lcd"; - resets = <&rcc LTDC_R>; - status = "disabled"; - }; - - iwdg2: watchdog@5a002000 { - compatible = "st,stm32mp1-iwdg"; - reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; - clock-names = "pclk", "lsi"; - status = "disabled"; - }; - - usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; - - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; - }; - }; - - usart1: serial@5c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x5c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - wakeup-source; - status = "disabled"; - }; - - spi6: spi@5c001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x5c001000 0x400>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; - dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, - <&mdma1 35 0x0 0x40002 0x0 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@5c002000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c002000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - rtc: rtc@5c004000 { - compatible = "st,stm32mp1-rtc"; - reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; - clock-names = "pclk", "rtc_ck"; - interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - bsec: efuse@5c005000 { - compatible = "st,stm32mp15-bsec"; - reg = <0x5c005000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - part_number_otp: part-number-otp@4 { - reg = <0x4 0x1>; - }; - vrefint: vrefin-cal@52 { - reg = <0x52 0x2>; - }; - ts_cal1: calib@5c { - reg = <0x5c 0x2>; - }; - ts_cal2: calib@5e { - reg = <0x5e 0x2>; + i2c6: i2c@5c009000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x5c009000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C6_K>; + resets = <&rcc I2C6_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x20>; + wakeup-source; + i2c-analog-filter; + feature-domains = <&etzpc 12>; + status = "disabled"; }; };
- i2c6: i2c@5c009000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c009000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x20>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - tamp: tamp@5c00a000 { compatible = "st,stm32-tamp", "syscon", "simple-mfd"; reg = <0x5c00a000 0x400>; diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi index 486084e0b80b..82073dd85f18 100644 --- a/arch/arm/boot/dts/st/stm32mp153.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -28,32 +28,34 @@ timer { <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; +};
- soc { - m_can1: can@4400e000 { - compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x1400>; - reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; - status = "disabled"; - }; +&etzpc { + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + feature-domains = <&etzpc 62>; + status = "disabled"; + };
- m_can2: can@4400f000 { - compatible = "bosch,m_can"; - reg = <0x4400f000 0x400>, <0x44011000 0x2800>; - reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; - status = "disabled"; - }; + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + feature-domains = <&etzpc 62>; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/stm32mp15xc.dtsi index b06a55a2fa18..55524a8d3093 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi @@ -4,15 +4,14 @@ * Author: Alexandre Torgue alexandre.torgue@st.com for STMicroelectronics. */
-/ { - soc { - cryp1: cryp@54001000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54001000 0x400>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; +&etzpc { + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + feature-domains = <&etzpc 9>; + status = "disabled"; }; };
ETZPC is a firewall controller. Put all peripherals filtered by the ETZPC as ETZPC subnodes and reference ETZPC as a feature-domain-controller.
For more information on which peripheral is securable or supports MCU isolation, please read the STM32MP13 reference manual.
Signed-off-by: Gatien Chevallier gatien.chevallier@foss.st.com --- arch/arm/boot/dts/st/stm32mp131.dtsi | 1027 +++++++++++++------------ arch/arm/boot/dts/st/stm32mp133.dtsi | 51 +- arch/arm/boot/dts/st/stm32mp13xc.dtsi | 19 +- arch/arm/boot/dts/st/stm32mp13xf.dtsi | 19 +- 4 files changed, 576 insertions(+), 540 deletions(-)
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index d163c267e34c..0bd9494cafa2 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -757,340 +757,6 @@ dmamux1: dma-router@48002000 { dma-channels = <16>; };
- adc_2: adc@48004000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48004000 0x400>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc ADC2>, <&rcc ADC2_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc2: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_2>; - interrupts = <0>; - dmas = <&dmamux1 10 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@13 { - reg = <13>; - label = "vrefint"; - }; - channel@14 { - reg = <14>; - label = "vddcore"; - }; - channel@16 { - reg = <16>; - label = "vddcpu"; - }; - channel@17 { - reg = <17>; - label = "vddq_ddr"; - }; - }; - }; - - usbotg_hs: usb@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x40000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&usb33>; - status = "disabled"; - }; - - usart1: serial@4c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - resets = <&rcc USART1_R>; - wakeup-source; - dmas = <&dmamux1 41 0x400 0x5>, - <&dmamux1 42 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usart2: serial@4c001000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c001000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - resets = <&rcc USART2_R>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x5>, - <&dmamux1 44 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s4: audio-controller@4c002000 { - compatible = "st,stm32h7-i2s"; - reg = <0x4c002000 0x400>; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@4c002000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c002000 0x400>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi5: spi@4c003000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c003000 0x400>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 85 0x400 0x01>, - <&dmamux1 86 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c3: i2c@4c004000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c004000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 73 0x400 0x1>, - <&dmamux1 74 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c4: i2c@4c005000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c005000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 75 0x400 0x1>, - <&dmamux1 76 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c5: i2c@4c006000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c006000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 115 0x400 0x1>, - <&dmamux1 116 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - i2c-analog-filter; - status = "disabled"; - }; - - timers12: timer@4c007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c007000 0x400>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM12_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timer@4c008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c008000 0x400>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; - }; - - timers14: timer@4c009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c009000 0x400>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM14_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; - }; - - timers15: timer@4c00a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00a000 0x400>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; - status = "disabled"; - }; - }; - - timers16: timer@4c00b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00b000 0x400>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; - status = "disabled"; - }; - }; - - timers17: timer@4c00c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00c000 0x400>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; - status = "disabled"; - }; - }; - rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -1117,69 +783,6 @@ syscfg: syscon@50020000 { clocks = <&rcc SYSCFG>; };
- lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - lptimer4: timer@50023000 { compatible = "st,stm32-lptimer"; reg = <0x50023000 0x400>; @@ -1232,82 +835,6 @@ mdma: dma-controller@58000000 { dma-requests = <48>; };
- fmc: memory-controller@58002000 { - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ - #address-cells = <2>; - #size-cells = <1>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - - nand-controller@4,0 { - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, - <&mdma 24 0x2 0x12000a08 0x0 0x0>, - <&mdma 25 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; - status = "disabled"; - }; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, - <&mdma 26 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - status = "disabled"; - }; - - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58005000 0x1000>, <0x58006000 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58007000 0x1000>, <0x58008000 0x1000>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; @@ -1335,29 +862,6 @@ iwdg2: watchdog@5a002000 { status = "disabled"; };
- usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; - - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; - }; - }; - rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; @@ -1386,6 +890,536 @@ ts_cal2: calib@5e { }; };
+ etzpc: bus@5c007000 { + compatible = "st,stm32-etzpc"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + feature-domain-controller; + #feature-domain-cells = <1>; + ranges; + + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + feature-domains = <&etzpc 33>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + + usbotg_hs: usb@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + feature-domains = <&etzpc 34>; + status = "disabled"; + }; + + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + wakeup-source; + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 16>; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 17>; + status = "disabled"; + }; + + i2s4: audio-controller@4c002000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4c002000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 13>; + status = "disabled"; + }; + + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 18>; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc 19>; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + feature-domains = <&etzpc 20>; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + feature-domains = <&etzpc 21>; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + feature-domains = <&etzpc 22>; + status = "disabled"; + }; + + timers12: timer@4c007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c007000 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + feature-domains = <&etzpc 23>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@4c008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c008000 0x400>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + feature-domains = <&etzpc 24>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@4c009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c009000 0x400>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + feature-domains = <&etzpc 25>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + timers15: timer@4c00a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00a000 0x400>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + feature-domains = <&etzpc 26>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@4c00b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00b000 0x400>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + feature-domains = <&etzpc 27>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@4c00c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00c000 0x400>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + feature-domains = <&etzpc 28>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + feature-domains = <&etzpc 1>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + feature-domains = <&etzpc 2>; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + fmc: memory-controller@58002000 { + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + #address-cells = <2>; + #size-cells = <1>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + feature-domains = <&etzpc 54>; + status = "disabled"; + + nand-controller@4,0 { + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, + <&mdma 24 0x2 0x12000a08 0x0 0x0>, + <&mdma 25 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + }; + + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, + <&mdma 26 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + feature-domains = <&etzpc 55>; + status = "disabled"; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + feature-domains = <&etzpc 50>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + feature-domains = <&etzpc 51>; + status = "disabled"; + }; + + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + feature-domains = <&etzpc 5>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + + }; + /* * Break node order to solve dependency probe issue between * pinctrl and exti. @@ -1397,6 +1431,7 @@ pinctrl: pinctrl@50002000 { ranges = <0 0x50002000 0x8400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + pins-are-numbered;
gpioa: gpio@50002000 { gpio-controller; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index df451c3c2a26..be6061552683 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -33,35 +33,38 @@ m_can2: can@4400f000 { bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; + }; +};
- adc_1: adc@48003000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48003000 0x400>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc ADC1>, <&rcc ADC1_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; +&etzpc { + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + feature-domains = <&etzpc 32>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; #address-cells = <1>; #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; status = "disabled";
- adc1: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_1>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@18 { - reg = <18>; - label = "vrefint"; - }; + channel@18 { + reg = <18>; + label = "vrefint"; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xc.dtsi b/arch/arm/boot/dts/st/stm32mp13xc.dtsi index 4d00e7592882..a1a7a40c2a3e 100644 --- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi @@ -4,15 +4,14 @@ * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. */
-/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; +&etzpc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + feature-domains = <&etzpc 42>; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xf.dtsi b/arch/arm/boot/dts/st/stm32mp13xf.dtsi index 4d00e7592882..a1a7a40c2a3e 100644 --- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi @@ -4,15 +4,14 @@ * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. */
-/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; +&etzpc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + feature-domains = <&etzpc 42>; + status = "disabled"; }; };
participants (6)
-
Alexandre TORGUE -
Gatien Chevallier -
Greg KH -
Krzysztof Kozlowski -
Oleksii Moisieiev -
Rob Herring