[alsa-devel] [PATCH] ASoC: fsl_spdif: don't change the root clock rate of spdif in driver
The spdif root clock may be used by other module or defined with CLK_SET_RATE_GATE, so we can't change the clock rate in driver. In this patch remove the clk_set_rate and clk_round_rate to protect the clock.
Signed-off-by: Shengjiu Wang shengjiu.wang@freescale.com --- sound/soc/fsl/fsl_spdif.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-)
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index 70acfe4..f2e4595 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -377,7 +377,6 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream, unsigned long csfs = 0; u32 stc, mask, rate; u8 clk, txclk_df, sysclk_df; - int ret;
switch (sample_rate) { case 32000: @@ -419,21 +418,6 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
sysclk_df = spdif_priv->sysclk_df[rate];
- /* Don't mess up the clocks from other modules */ - if (clk != STC_TXCLK_SPDIF_ROOT) - goto clk_set_bypass; - - /* - * The S/PDIF block needs a clock of 64 * fs * txclk_df. - * So request 64 * fs * (txclk_df + 1) to get rounded. - */ - ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (txclk_df + 1)); - if (ret) { - dev_err(&pdev->dev, "failed to set tx clock rate\n"); - return ret; - } - -clk_set_bypass: dev_dbg(&pdev->dev, "expected clock rate = %d\n", (64 * sample_rate * txclk_df * sysclk_df)); dev_dbg(&pdev->dev, "actual clock rate = %ld\n", @@ -1056,7 +1040,7 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, { const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; bool is_sysclk = clk == spdif_priv->sysclk; - u64 rate_ideal, rate_actual, sub; + u64 rate_actual, sub; u32 sysclk_dfmin, sysclk_dfmax; u32 txclk_df, sysclk_df, arate;
@@ -1066,11 +1050,7 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { for (txclk_df = 1; txclk_df <= 128; txclk_df++) { - rate_ideal = rate[index] * (txclk_df + 1) * 64; - if (round) - rate_actual = clk_round_rate(clk, rate_ideal); - else - rate_actual = clk_get_rate(clk); + rate_actual = clk_get_rate(clk);
arate = rate_actual / 64; arate /= txclk_df * sysclk_df;
On Tue, Sep 16, 2014 at 07:46:34PM +0800, Shengjiu Wang wrote:
The spdif root clock may be used by other module or defined with CLK_SET_RATE_GATE, so we can't change the clock rate in driver. In this patch remove the clk_set_rate and clk_round_rate to protect the clock.
It's a quite convenient and conservative way to remove the clock dealing code in the driver, however, it may result less flexible functionalities.
The reason why I left the clk_set_rate() in the driver is to hope we may find a better way to tackle those tough situations. For IP itself, it doesn't matter if the clock the SoC provides to it is being shared by other modules or not.
So I think, if it's a shared clock, we should not define it as a rate-changeable one in the SoC level, as we might still have some SoCs provide a dedicated clock to S/PDIF so as to get the maximum range of clock support for users.
@Shawn Sorry to involve you in this topic. I'm not so sure if we can do this in the clock driver so that the clock rate would be fixed even if the driver is trying to change it. If we can, I think we may use a better solution here instead.
Thank you Nicolin
On Tue, Sep 16, 2014 at 11:19:28AM -0700, Nicolin Chen wrote:
So I think, if it's a shared clock, we should not define it as a rate-changeable one in the SoC level, as we might still have some SoCs provide a dedicated clock to S/PDIF so as to get the maximum range of clock support for users.
@Shawn Sorry to involve you in this topic. I'm not so sure if we can do this in the clock driver so that the clock rate would be fixed even if the driver is trying to change it. If we can, I think we may use a better solution here instead.
I tend to agree here. My first thought here is that we should have support in the clock API for constraining clocks in the clock API so we can still set the clock where there's a possibility to do that. Not trivail to implement though.
On Tue, Sep 16, 2014 at 11:19:28AM -0700, Nicolin Chen wrote:
On Tue, Sep 16, 2014 at 07:46:34PM +0800, Shengjiu Wang wrote:
The spdif root clock may be used by other module or defined with CLK_SET_RATE_GATE, so we can't change the clock rate in driver. In this patch remove the clk_set_rate and clk_round_rate to protect the clock.
It's a quite convenient and conservative way to remove the clock dealing code in the driver, however, it may result less flexible functionalities.
The reason why I left the clk_set_rate() in the driver is to hope we may find a better way to tackle those tough situations. For IP itself, it doesn't matter if the clock the SoC provides to it is being shared by other modules or not.
So I think, if it's a shared clock, we should not define it as a rate-changeable one in the SoC level, as we might still have some SoCs provide a dedicated clock to S/PDIF so as to get the maximum range of clock support for users.
@Shawn Sorry to involve you in this topic. I'm not so sure if we can do this in the clock driver so that the clock rate would be fixed even if the driver is trying to change it. If we can, I think we may use a better solution here instead.
No, we do not have anything like that today.
Shawn
On Wed, Sep 17, 2014 at 09:32:52AM +0800, Shawn Guo wrote:
On Tue, Sep 16, 2014 at 11:19:28AM -0700, Nicolin Chen wrote:
On Tue, Sep 16, 2014 at 07:46:34PM +0800, Shengjiu Wang wrote:
The spdif root clock may be used by other module or defined with CLK_SET_RATE_GATE, so we can't change the clock rate in driver. In this patch remove the clk_set_rate and clk_round_rate to protect the clock.
It's a quite convenient and conservative way to remove the clock dealing code in the driver, however, it may result less flexible functionalities.
The reason why I left the clk_set_rate() in the driver is to hope we may find a better way to tackle those tough situations. For IP itself, it doesn't matter if the clock the SoC provides to it is being shared by other modules or not.
So I think, if it's a shared clock, we should not define it as a rate-changeable one in the SoC level, as we might still have some SoCs provide a dedicated clock to S/PDIF so as to get the maximum range of clock support for users.
@Shawn Sorry to involve you in this topic. I'm not so sure if we can do this in the clock driver so that the clock rate would be fixed even if the driver is trying to change it. If we can, I think we may use a better solution here instead.
No, we do not have anything like that today.
It's not supported in the clock API or just not implemented in our code? Can we just register a clock without CLK_SET_RATE_PARENT to achieve the purpose? (We are just trying to fix those PRED and PODF dividers when the driver calls set_rate to their GATE clock.)
Thank you Nicolin
On Tue, Sep 16, 2014 at 07:24:40PM -0700, Nicolin Chen wrote:
It's not supported in the clock API or just not implemented in our code? Can we just register a clock without CLK_SET_RATE_PARENT to achieve the purpose? (We are just trying to fix those PRED and PODF dividers when the driver calls set_rate to their GATE clock.)
It seems I misunderstood your question. Yes, if we drop flag CLK_SET_RATE_PARENT for the gate clock in question, the rate change request will not be propagated to upstream dividers.
Shawn
On Wed, Sep 17, 2014 at 10:31:28AM +0800, Shawn Guo wrote:
On Tue, Sep 16, 2014 at 07:24:40PM -0700, Nicolin Chen wrote:
It's not supported in the clock API or just not implemented in our code? Can we just register a clock without CLK_SET_RATE_PARENT to achieve the purpose? (We are just trying to fix those PRED and PODF dividers when the driver calls set_rate to their GATE clock.)
It seems I misunderstood your question. Yes, if we drop flag CLK_SET_RATE_PARENT for the gate clock in question, the rate change request will not be propagated to upstream dividers.
Okay. Since there's a solution that allows us to handle it better, problem solved then.
@Shengjiu Would you please take a look at the clock driver to implement a new clock register function? And make sure to register the GATE clock only without the flag CLK_SET_RATE_PARENT, as we may still need to set a reasonable rate for the clock by setting its PODF clock node instead.
Thank you both Nicolin
participants (4)
-
Mark Brown -
Nicolin Chen -
Shawn Guo -
Shengjiu Wang