[PATCH v6 0/8] Add SC7280 audioreach device tree nodes
Add SC7280 audioreach device tree nodes and extract audio specific dtsi nodes and add them in new file.
This patch series depends on: -- https://patchwork.kernel.org/project/linux-clk/list/?series=717985 Corresponding dt-bindings not mainlined yet. -- https://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git/commit/...
Changes Since v5: -- Re-arrange the patch list, driver changes should come after binding. -- Remove incorrect dai cells property in "Add sound node for crd-rev3 board" patch. -- Remove newlines in "Add LPASS PIL node" patch. -- Update the commit message in "Update VA/RX/TX macro clock nodes" patch. -- Update the commit message in "Update lpass_tlmm node" patch. Changes Since v4: -- Modify lpasscc clock controller node name. -- Disable lpass_core node. -- Modify Model name in sound node in "Add sound node for crd-rev3 board" patch. -- Remove protection domain property in "Add LPASS PIL node". Changes Since v3: -- Remove deleting digital codecs in crd-rev3 board specific dtsi and upadate them using phandle. -- Update commit message in "Update lpass_tlmm node" patch. -- Change the position of status property in LPASS PIL node. -- Update commit message in "Add sound node" patch. Changes Since v2: -- Remove Patch related to Add CGCR reset property. -- Remove Patch related to Disable legacy path clock nodes. -- Add dt-bindings for missing properties. -- Change the order of nodes. -- Move digictal codec macro nodes to root node from soc node. -- Add adsp-pil-mode property in required clock nodes. Changes Since v1: -- Move remoteproc node to soc dtsi file. -- Add qcom, adsp-pil-mode reg property in lpasscc node. -- Fix typo errors. -- Remove redundant status properties.
Srinivasa Rao Mandadapu (8): arm64: dts: qcom: sc7280: Modify lpasscc node name dt-bindings: remoteproc: qcom: sc7280-adsp-pil: Add missing properties arm64: dts: qcom: sc7280: Extract audio nodes from common idp dtsi file arm64: dts: qcom: sc7280: Add sound node for crd-rev3 board arm64: dts: qcom: sc7280: Add LPASS PIL node arm64: dts: qcom: sc7280: Modify VA/RX/TX macro clock nodes for audioreach solution arm64: dts: qcom: sc7280: Modify LPASS_MCC reg region size in the lpass_tlmm node arm64: dts: qcom: sc7280: Add qcom,adsp-pil-mode property in clock nodes
.../remoteproc/qcom,sc7280-adsp-pil.yaml | 30 ++- .../arm64/boot/dts/qcom/sc7280-audio-idp.dtsi | 131 +++++++++ arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 1 + .../sc7280-herobrine-audioreach-wcd9385.dtsi | 253 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 122 --------- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 +- 6 files changed, 413 insertions(+), 128 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
From: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com
Modify lpasscc clock controller node name to generic name, that is from lpasscc to clock-controller.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Signed-off-by: Mohammad Rafi Shaik quic_mohs@quicinc.com Reviewed-by: Stephen Boyd swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 31728f461422..270618521638 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2237,7 +2237,7 @@ tcsr_2: syscon@1fc0000 { reg = <0 0x01fc0000 0 0x30000>; };
- lpasscc: lpasscc@3000000 { + lpasscc: clock-controller@3000000 { compatible = "qcom,sc7280-lpasscc"; reg = <0 0x03000000 0 0x40>, <0 0x03c04000 0 0x4>;
From: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com
Add reg-names and power-domain-names for remoteproc ADSP peripheral loader. Add firmware-name property to distinguish and load different firmware binaries of various vendors. Change qcom,halt-regs property phandle to tcsr_1 from tcsr_mutex. Also add required-opps property and change power domain from LCX to CX, which is actual PD to be controlled, for setting appropriate performance state. This is to make compatible with remoteproc ADSP PIL driver and latest device tree changes.
Fixes: 8490a99586ab ("dt-bindings: remoteproc: qcom: Add SC7280 ADSP support") Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Signed-off-by: Mohammad Rafi Shaik quic_mohs@quicinc.com Reviewed-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- .../remoteproc/qcom,sc7280-adsp-pil.yaml | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml index 94ca7a0cc203..7addc7de64c0 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml @@ -23,6 +23,11 @@ properties: - description: qdsp6ss register - description: efuse q6ss register
+ reg-names: + items: + - const: qdsp6ss_base + - const: lpass_efuse + iommus: items: - description: Phandle to apps_smmu node with sid mask @@ -57,7 +62,11 @@ properties:
power-domains: items: - - description: LCX power domain + - description: CX power domain + + power-domain-names: + items: + - const: cx
resets: items: @@ -73,6 +82,12 @@ properties: maxItems: 1 description: Reference to the reserved-memory for the Hexagon core
+ firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + The name of the firmware which should be loaded for this remote + processor. + qcom,halt-regs: $ref: /schemas/types.yaml#/definitions/phandle-array description: @@ -80,7 +95,7 @@ properties: four offsets within syscon for q6, modem, nc and qv6 halt registers. items: - items: - - description: phandle to TCSR_MUTEX registers + - description: phandle to TCSR_1 registers - description: offset to the Q6 halt register - description: offset to the modem halt register - description: offset to the nc halt register @@ -100,6 +115,10 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM.
+ required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + glink-edge: $ref: qcom,glink-edge.yaml# type: object @@ -167,13 +186,16 @@ examples: <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "xo", "gcc_cfg_noc_lpass";
- power-domains = <&rpmhpd SC7280_LCX>; + power-domains = <&rpmhpd SC7280_CX>; + power-domain-names = "cx"; + + required-opps = <&rpmhpd_opp_nom>;
resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>, <&aoss_reset AOSS_CC_LPASS_RESTART>; reset-names = "pdc_sync", "cc_lpass";
- qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; + qcom,halt-regs = <&tcsr_1 0x23000 0x25000 0x28000 0x33000>;
memory-region = <&adsp_mem>;
From: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com
Split common idp dtsi file into audio specific dtsi and common idp dtsi file.
It is required to isolate idp and crd-rev3 platform device tree nodes and convert crd-rev3 platform device tree nodes into audioreach specific device tree nodes.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Signed-off-by: Mohammad Rafi Shaik quic_mohs@quicinc.com Reviewed-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- .../arm64/boot/dts/qcom/sc7280-audio-idp.dtsi | 131 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 122 ---------------- 3 files changed, 132 insertions(+), 122 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi new file mode 100644 index 000000000000..994a13325477 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 Audio IDP board device tree source (common between SKU1 and SKU2) + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +/{ + /* BOARD-SPECIFIC TOP LEVEL NODES */ + sound: sound { + compatible = "google,sc7280-herobrine"; + model = "sc7280-wcd938x-max98360a-1mic"; + + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; + + #address-cells = <1>; + #size-cells = <0>; + + dai-link@0 { + link-name = "MAX98360A"; + reg = <0>; + + cpu { + sound-dai = <&lpass_cpu MI2S_SECONDARY>; + }; + + codec { + sound-dai = <&max98360a>; + }; + }; + + dai-link@1 { + link-name = "DisplayPort"; + reg = <1>; + + cpu { + sound-dai = <&lpass_cpu LPASS_DP_RX>; + }; + + codec { + sound-dai = <&mdss_dp>; + }; + }; + + dai-link@2 { + link-name = "WCD9385 Playback"; + reg = <2>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>; + }; + + codec { + sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + }; + + dai-link@3 { + link-name = "WCD9385 Capture"; + reg = <3>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>; + }; + + codec { + sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + }; + + dai-link@4 { + link-name = "DMIC"; + reg = <4>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>; + }; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + }; + }; +}; + +&lpass_cpu { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; + + dai-link@1 { + reg = <MI2S_SECONDARY>; + qcom,playback-sd-lines = <0>; + }; + + dai-link@5 { + reg = <LPASS_DP_RX>; + }; + + dai-link@6 { + reg = <LPASS_CDC_DMA_RX0>; + }; + + dai-link@19 { + reg = <LPASS_CDC_DMA_TX3>; + }; + + dai-link@25 { + reg = <LPASS_CDC_DMA_VA_TX0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index afae7f46b050..15f7f26b80cd 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -8,6 +8,7 @@ /dts-v1/;
#include "sc7280-idp.dtsi" +#include "sc7280-audio-idp.dtsi" #include "sc7280-idp-ec-h1.dtsi"
/ { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index c6dc200c00ce..c09ee1b93511 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -87,100 +87,6 @@ nvme_3v3_regulator: nvme-3v3-regulator { pinctrl-names = "default"; pinctrl-0 = <&nvme_pwren>; }; - - sound: sound { - compatible = "google,sc7280-herobrine"; - model = "sc7280-wcd938x-max98360a-1mic"; - - audio-routing = - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC1", "MIC BIAS1", - "AMIC2", "MIC BIAS2", - "VA DMIC0", "MIC BIAS3", - "VA DMIC1", "MIC BIAS3", - "VA DMIC2", "MIC BIAS1", - "VA DMIC3", "MIC BIAS1", - "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC1", "ADC2_OUTPUT", - "TX SWR_ADC2", "ADC3_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT"; - - #address-cells = <1>; - #size-cells = <0>; - - dai-link@0 { - link-name = "MAX98360A"; - reg = <0>; - - cpu { - sound-dai = <&lpass_cpu MI2S_SECONDARY>; - }; - - codec { - sound-dai = <&max98360a>; - }; - }; - - dai-link@1 { - link-name = "DisplayPort"; - reg = <1>; - - cpu { - sound-dai = <&lpass_cpu LPASS_DP_RX>; - }; - - codec { - sound-dai = <&mdss_dp>; - }; - }; - - dai-link@2 { - link-name = "WCD9385 Playback"; - reg = <2>; - - cpu { - sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>; - }; - - codec { - sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>; - }; - }; - - dai-link@3 { - link-name = "WCD9385 Capture"; - reg = <3>; - - cpu { - sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>; - }; - - codec { - sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>; - }; - }; - - dai-link@4 { - link-name = "DMIC"; - reg = <4>; - - cpu { - sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>; - }; - - codec { - sound-dai = <&lpass_va_macro 0>; - }; - }; - }; };
&apps_rsc { @@ -373,34 +279,6 @@ &gpi_dma1 { status = "okay"; };
-&lpass_cpu { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; - - dai-link@1 { - reg = <MI2S_SECONDARY>; - qcom,playback-sd-lines = <0>; - }; - - dai-link@5 { - reg = <LPASS_DP_RX>; - }; - - dai-link@6 { - reg = <LPASS_CDC_DMA_RX0>; - }; - - dai-link@19 { - reg = <LPASS_CDC_DMA_TX3>; - }; - - dai-link@25 { - reg = <LPASS_CDC_DMA_VA_TX0>; - }; -}; - &lpass_rx_macro { status = "okay"; };
From: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com
Add sound node for sc7280 ADSP based audioreach platforms such as crd-rev3 board.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Signed-off-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- .../sc7280-herobrine-audioreach-wcd9385.dtsi | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi new file mode 100644 index 000000000000..95d3aa08ebde --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 device tree source for boards using Max98360 and wcd9385 codec + * along with ADSP + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/sound/qcom,q6afe.h> + +/{ + /* BOARD-SPECIFIC TOP LEVEL NODES */ + sound: sound { + compatible = "google,sc7280-herobrine"; + model = "AR-wcd938x-max98360a-1mic"; + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "VA DMIC3", "MIC BIAS3", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; + + #address-cells = <1>; + #size-cells = <0>; + + dai-link@0 { + link-name = "WCD9385 Playback"; + reg = <0>; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dai-link@1 { + link-name = "WCD9385 Capture"; + reg = <1>; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dai-link@2 { + link-name = "Amplifier Playback"; + reg = <2>; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_RX>; + }; + + codec { + sound-dai = <&max98360a>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dai-link@3 { + link-name = "DMIC"; + reg = <3>; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; +};
From: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com
Add LPASS PIL node for sc7280 based audioreach platforms.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Signed-off-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- .../sc7280-herobrine-audioreach-wcd9385.dtsi | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi index 95d3aa08ebde..9daea1b25656 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -7,6 +7,8 @@ */
#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/clock/qcom,lpass-sc7280.h> +#include <dt-bindings/soc/qcom,gpr.h>
/{ /* BOARD-SPECIFIC TOP LEVEL NODES */ @@ -105,4 +107,92 @@ platform { }; }; }; + + remoteproc_adsp: remoteproc@3000000 { + compatible = "qcom,sc7280-adsp-pil"; + reg = <0 0x03000000 0 0x5000>, <0 0x0355b000 0 0x10>; + reg-names = "qdsp6ss_base", "lpass_efuse"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + qcom,qmp = <&aoss_qmp>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "xo", "gcc_cfg_noc_lpass"; + + iommus = <&apps_smmu 0x1800 0x0>; + + power-domains = <&rpmhpd SC7280_CX>; + power-domain-names = "cx"; + + required-opps = <&rpmhpd_opp_nom>; + + resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>, + <&aoss_reset AOSS_CC_LPASS_RESTART>; + reset-names = "pdc_sync", "cc_lpass"; + + qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; };
From: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com
Modify VA, RX and TX macro and lpass_tlmm clock properties and enable them. For audioreach solution mclk, npl and fsgen clocks are enabled through the q6prm clock driver.
Delete the power domain properties from VA, RX and TX macro, for audioreach solution the macro, dcodec power domains enabled through the q6prm clock driver.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Signed-off-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- .../sc7280-herobrine-audioreach-wcd9385.dtsi | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi index 9daea1b25656..c02ca393378f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -196,3 +196,46 @@ q6prmcc: clock-controller { }; }; }; + +&lpass_rx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + + status = "okay"; +}; + +&lpass_tlmm { + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; +}; + +&lpass_tx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + + status = "okay"; +}; + +&lpass_va_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec"; + + status = "okay"; +};
From: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com
Modify LPASS_MCC register region size in "lpass_tlmm" node. The pincntl driver requires access until slew-rate register region and remaining register region related to the lpass_efuse register is not required in pincntl driver as lpass_efuse register region is required in adsp remoteproc driver.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Signed-off-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 270618521638..08afabbd0778 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2488,7 +2488,7 @@ lpass_ag_noc: interconnect@3c40000 { lpass_tlmm: pinctrl@33c0000 { compatible = "qcom,sc7280-lpass-lpi-pinctrl"; reg = <0 0x033c0000 0x0 0x20000>, - <0 0x03550000 0x0 0x10000>; + <0 0x03550000 0x0 0xa100>; qcom,adsp-bypass-mode; gpio-controller; #gpio-cells = <2>;
From: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com
Add "qcom,adsp-pil-mode" property in clock nodes for herobrine crd revision 3 board specific device tree. This is to register clocks conditionally by differentiating ADSP based platforms and legacy path platforms. Also disable lpass_core clock, as it is creating conflict with ADSP clocks and it is not required for ADSP based platforms.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Signed-off-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi index c02ca393378f..876a29178d46 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -197,6 +197,14 @@ q6prmcc: clock-controller { }; };
+&lpass_aon { + qcom,adsp-pil-mode; +}; + +&lpass_core { + status = "disabled"; +}; + &lpass_rx_macro { /delete-property/ power-domains; /delete-property/ power-domain-names; @@ -239,3 +247,7 @@ &lpass_va_macro {
status = "okay"; }; + +&lpasscc { + qcom,adsp-pil-mode; +};
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Mohammad Rafi Shaik