On 29 January 2018 at 02:50, Chen-Yu Tsai wens@csie.org wrote:

On Wed, Jan 24, 2018 at 10:10 PM, codekipper@gmail.com wrote:

...

From: Marcus Cooper codekipper@gmail.com

Some codecs require a different amount of a bit clocks per frame than what is calculated by the sample width. Use the tdm slot bindings to provide this mechanism.

Signed-off-by: Marcus Cooper codekipper@gmail.com

sound/soc/sunxi/sun4i-i2s.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index dca1143c1150..d7a9141514cf 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -96,6 +96,7 @@ #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)

+#define SUN8I_I2S_FMT0_LRCK_MAX_PERIOD (GENMASK(17, 8) >> 8) #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)

@@ -193,6 +194,9 @@ struct sun4i_i2s { struct regmap_field *field_rxchansel;

    const struct sun4i_i2s_quirks   *variant;

•   unsigned int    tdm_slots;
  

•   unsigned int    slot_width;
  

};

struct sun4i_i2s_clk_div { @@ -344,7 +348,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, if (i2s->variant->has_fmt_set_lrck_period) regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,

•                              SUN8I_I2S_FMT0_LRCK_PERIOD(32));
  

•                              SUN8I_I2S_FMT0_LRCK_PERIOD(word_size));
  
    return 0;
  

} @@ -418,7 +422,8 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, sr + i2s->variant->fmt_offset);

    return sun4i_i2s_set_clk_rate(dai, params_rate(params),

•                                 params_width(params));
  

•                                 i2s->tdm_slots ?
  

•                                 i2s->slot_width : params_width(params));
  

}

static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) @@ -691,6 +696,19 @@ static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, return 0; }

+static int sun4i_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,

•   unsigned int tx_mask, unsigned int rx_mask,
  

•   int slots, int width)
  

+{

•   struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  

•   i2s->tdm_slots = slots;
  

•   i2s->slot_width = width;
  

•   return 0;
  

+}

IIRC some of the DAI controllers actually support TDM. Would this change conflict with that in the future?

Hi Wens, I'm not sure..I was looking for a clean example of being able to override the number of bclks in the lrclk width and some other devices(Rpi) were doing it this way. I open to suggestions, BR, CK

Thanks ChenYu

...

static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { .hw_params = sun4i_i2s_hw_params, .set_fmt = sun4i_i2s_set_fmt, @@ -698,6 +716,7 @@ static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { .shutdown = sun4i_i2s_shutdown, .startup = sun4i_i2s_startup, .trigger = sun4i_i2s_trigger,

•   .set_tdm_slot   = sun4i_i2s_set_dai_tdm_slot,
  

};

static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)

2.16.0

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On 29 January 2018 at 08:38, Chen-Yu Tsai wens@csie.org wrote:

On Mon, Jan 29, 2018 at 3:34 PM, Code Kipper codekipper@gmail.com wrote:

...

On 29 January 2018 at 02:50, Chen-Yu Tsai wens@csie.org wrote:

...

On Wed, Jan 24, 2018 at 10:10 PM, codekipper@gmail.com wrote:

...

From: Marcus Cooper codekipper@gmail.com

Some codecs require a different amount of a bit clocks per frame than what is calculated by the sample width. Use the tdm slot bindings to provide this mechanism.

Signed-off-by: Marcus Cooper codekipper@gmail.com

sound/soc/sunxi/sun4i-i2s.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index dca1143c1150..d7a9141514cf 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -96,6 +96,7 @@ #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)

+#define SUN8I_I2S_FMT0_LRCK_MAX_PERIOD (GENMASK(17, 8) >> 8) #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)

@@ -193,6 +194,9 @@ struct sun4i_i2s { struct regmap_field *field_rxchansel;

    const struct sun4i_i2s_quirks   *variant;

•   unsigned int    tdm_slots;
  

•   unsigned int    slot_width;
  

};

struct sun4i_i2s_clk_div { @@ -344,7 +348,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, if (i2s->variant->has_fmt_set_lrck_period) regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,

•                              SUN8I_I2S_FMT0_LRCK_PERIOD(32));
  

•                              SUN8I_I2S_FMT0_LRCK_PERIOD(word_size));
  
    return 0;
  

} @@ -418,7 +422,8 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, sr + i2s->variant->fmt_offset);

    return sun4i_i2s_set_clk_rate(dai, params_rate(params),

•                                 params_width(params));
  

•                                 i2s->tdm_slots ?
  

•                                 i2s->slot_width : params_width(params));
  

}

static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) @@ -691,6 +696,19 @@ static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, return 0; }

+static int sun4i_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,

•   unsigned int tx_mask, unsigned int rx_mask,
  

•   int slots, int width)
  

+{

•   struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  

•   i2s->tdm_slots = slots;
  

•   i2s->slot_width = width;
  

•   return 0;
  

+}

IIRC some of the DAI controllers actually support TDM. Would this change conflict with that in the future?

Hi Wens, I'm not sure..I was looking for a clean example of being able to override the number of bclks in the lrclk width and some other devices(Rpi) were doing it this way. I open to suggestions,

I'm not familiar with the issue either. If Mark doesn't have any objections, we could merge it for now, and fix it later if there are any complications.

BTW, you didn't provide a device tree example (if any) for how to use this.

Hi Wens,

here is an example that I use for the Pine64 audio hat. https://github.com/codekipper/linux-sunxi/commit/faa9dfba955bf71ca23b089b1cb...

I've done the same on the A64 for HDMI and analog audio which both use the i2s and seem to require 32bit LRCK width.

BR, CK

ChenYu

...

BR, CK

...

Thanks ChenYu

...

static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { .hw_params = sun4i_i2s_hw_params, .set_fmt = sun4i_i2s_set_fmt, @@ -698,6 +716,7 @@ static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { .shutdown = sun4i_i2s_shutdown, .startup = sun4i_i2s_startup, .trigger = sun4i_i2s_trigger,

•   .set_tdm_slot   = sun4i_i2s_set_dai_tdm_slot,
  

};

static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)

2.16.0

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On Wed, Jan 24, 2018 at 10:11 PM, codekipper@gmail.com wrote:

From: Marcus Cooper codekipper@gmail.com

Subject is slightly hard to read.

ASoC: sun4i-i2s: Do not divide clocks when acting as slave

would be easier to understand.

There is no need to set the clock and calculate the division of the audio pll for the bclk and sync signals when they are not required.

Signed-off-by: Marcus Cooper codekipper@gmail.com

sound/soc/sunxi/sun4i-i2s.c | 116 ++++++++++++++++++++++++-------------------- 1 file changed, 64 insertions(+), 52 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index d7a9141514cf..626679057d0f 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -195,6 +195,8 @@ struct sun4i_i2s {

    const struct sun4i_i2s_quirks   *variant;

•   bool bit_clk_master;
  

•   unsigned int    tdm_slots;
    unsigned int    slot_width;
  

}; @@ -282,67 +284,73 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, int bclk_div, mclk_div; int ret;

•   switch (rate) {
  

•   case 176400:
  

•   case 88200:
  

•   case 44100:
  

•   case 22050:
  

•   case 11025:
  

•           clk_rate = 22579200;
  

•           break;
  

•   if (i2s->bit_clk_master) {
  

•           switch (rate) {
  

•           case 176400:
  

•           case 88200:
  

•           case 44100:
  

•           case 22050:
  

•           case 11025:
  

•                   clk_rate = 22579200;
  

•                   break;
  
  

•   case 192000:
  

•   case 128000:
  

•   case 96000:
  

•   case 64000:
  

•   case 48000:
  

•   case 32000:
  

•   case 24000:
  

•   case 16000:
  

•   case 12000:
  

•   case 8000:
  

•           clk_rate = 24576000;
  

•           break;
  

•           case 192000:
  

•           case 128000:
  

•           case 96000:
  

•           case 64000:
  

•           case 48000:
  

•           case 32000:
  

•           case 24000:
  

•           case 16000:
  

•           case 12000:
  

•           case 8000:
  

•                   clk_rate = 24576000;
  

•                   break;
  
  

•   default:
  

•           dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
  

•           return -EINVAL;
  

•   }
  

•           default:
  

•                   dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
  

•                   return -EINVAL;
  

•           }
  
  

•   ret = clk_set_rate(i2s->mod_clk, clk_rate);
  

•   if (ret)
  

•           return ret;
  

•           ret = clk_set_rate(i2s->mod_clk, clk_rate);
  

•           if (ret) {
  

•                   dev_err(dai->dev, "Unable to set clock\n");
  

•                   return ret;
  

•           }
  
  

•   oversample_rate = i2s->mclk_freq / rate;
  

•   if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
  

•           dev_err(dai->dev, "Unsupported oversample rate: %d\n",
  

•                   oversample_rate);
  

•           return -EINVAL;
  

•   }
  

•           oversample_rate = i2s->mclk_freq / rate;
  

•           if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
  

•                   dev_err(dai->dev, "Unsupported oversample rate: %d\n",
  

•                           oversample_rate);
  

•                   return -EINVAL;
  

•           }
  
  

•   bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
  

•                                     word_size);
  

•   if (bclk_div < 0) {
  

•           dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
  

•           return -EINVAL;
  

•   }
  

•           bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
  

•                                             word_size);
  

•           if (bclk_div < 0) {
  

•                   dev_err(dai->dev, "Unsupported BCLK divider: %d\n",
  

•                           bclk_div);
  

•                   return -EINVAL;
  

•           }
  
  

•   mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
  

•                                     clk_rate, rate);
  

•   if (mclk_div < 0) {
  

•           dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
  

•           return -EINVAL;
  

•   }
  

•           mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
  

•                                             clk_rate, rate);
  

•           if (mclk_div < 0) {
  

•                   dev_err(dai->dev, "Unsupported MCLK divider: %d\n",
  

•                           mclk_div);
  

•                   return -EINVAL;
  

•           }
  
  

•   /* Adjust the clock division values if needed */
  

•   bclk_div += i2s->variant->bclk_offset;
  

•   mclk_div += i2s->variant->mclk_offset;
  

•           /* Adjust the clock division values if needed */
  

•           bclk_div += i2s->variant->bclk_offset;
  

•           mclk_div += i2s->variant->mclk_offset;
  
  

•   regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
  

•                SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
  

•                SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
  

•           regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
  

•                        SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
  

•                        SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
  
  

•   regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
  

•           regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
  

•   }
  

The changed block is so long that it seems better to split it out into a helper function that doesn't get called when the controller isn't the BCLK master. Or you could move the last "Set sync period" block up top, and do an early return if it's not the master. Either way I think it's better than having a large indented block.

On the other hand, do the settings need to be cleared if it's the slave?

ChenYu

    /* Set sync period */
    if (i2s->variant->has_fmt_set_lrck_period)

@@ -501,10 +509,12 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) case SND_SOC_DAIFMT_CBS_CFS: /* BCLK and LRCLK master */ val = SUN4I_I2S_CTRL_MODE_MASTER;

•                   i2s->bit_clk_master = true;
                    break;
            case SND_SOC_DAIFMT_CBM_CFM:
                    /* BCLK and LRCLK slave */
                    val = SUN4I_I2S_CTRL_MODE_SLAVE;
  

•                   i2s->bit_clk_master = false;
                    break;
            default:
                    dev_err(dai->dev, "Unsupported slave setting: %d\n",
  

@@ -525,10 +535,12 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) /* BCLK and LRCLK master */ val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;

•                   i2s->bit_clk_master = true;
                    break;
            case SND_SOC_DAIFMT_CBM_CFM:
                    /* BCLK and LRCLK slave */
                    val = 0;
  

•                   i2s->bit_clk_master = false;
                    break;
            default:
                    dev_err(dai->dev, "Unsupported slave setting: %d\n",
  

-- 2.16.0

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On 24 January 2018 at 15:11, codekipper@gmail.com wrote:

From: Marcus Cooper codekipper@gmail.com

On the newer SoCs this is set by default to transfer a 0 after each sample in each slot. Add the regmap field to configure this and set it so that it pads the sample with 0s.

Signed-off-by: Marcus Cooper codekipper@gmail.com

NACK missing regmap field from A83t. CK

---

sound/soc/sunxi/sun4i-i2s.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 626679057d0f..9fda1240b717 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -139,6 +139,7 @@

• @field_fmt_bclk: regmap field to set clk polarity.
• @field_fmt_lrclk: regmap field to set frame polarity.
• @field_fmt_mode: regmap field to set the operational mode.

• • @field_fmt_sext: regmap field to set the sign extension.
  • @field_txchanmap: location of the tx channel mapping register.
  • @field_rxchanmap: location of the rx channel mapping register.
  • @field_txchansel: location of the tx channel select bit fields.

@@ -164,6 +165,7 @@ struct sun4i_i2s_quirks { struct reg_field field_fmt_bclk; struct reg_field field_fmt_lrclk; struct reg_field field_fmt_mode;

•   struct reg_field                field_fmt_sext;
    struct reg_field                field_txchanmap;
    struct reg_field                field_rxchanmap;
    struct reg_field                field_txchansel;
  

@@ -188,6 +190,7 @@ struct sun4i_i2s { struct regmap_field *field_fmt_bclk; struct regmap_field *field_fmt_lrclk; struct regmap_field *field_fmt_mode;

•   struct regmap_field     *field_fmt_sext;
    struct regmap_field     *field_txchanmap;
    struct regmap_field     *field_rxchanmap;
    struct regmap_field     *field_txchansel;
  

@@ -358,6 +361,9 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, SUN8I_I2S_FMT0_LRCK_PERIOD(word_size));

•   /* Set sign extension to pad out LSB with 0 */
  

•   regmap_field_write(i2s->field_fmt_sext, 0);
  

•   return 0;
  

}

@@ -929,6 +935,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), .has_slave_select_bit = true, .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),

•   .field_fmt_sext         = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
    .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
    .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
    .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
  

@@ -946,6 +953,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), .has_slave_select_bit = true, .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),

•   .field_fmt_sext         = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
    .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
    .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
    .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
  

@@ -986,6 +994,7 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),

•   .field_fmt_sext         = REG_FIELD(SUN4I_I2S_FMT1_REG, 4, 5),
    .field_txchanmap        = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
    .field_rxchanmap        = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
    .field_txchansel        = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
  

@@ -1031,6 +1040,12 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, if (IS_ERR(i2s->field_fmt_mode)) return PTR_ERR(i2s->field_fmt_mode);

•   i2s->field_fmt_sext =
  

•                   devm_regmap_field_alloc(dev, i2s->regmap,
  

•                                           i2s->variant->field_fmt_sext);
  

•   if (IS_ERR(i2s->field_fmt_sext))
  

•           return PTR_ERR(i2s->field_fmt_sext);
  

•   i2s->field_txchanmap =
                    devm_regmap_field_alloc(dev, i2s->regmap,
                                            i2s->variant->field_txchanmap);
  

-- 2.16.0

On 25 January 2018 at 09:41, Maxime Ripard maxime.ripard@free-electrons.com wrote:

Hi,

On Wed, Jan 24, 2018 at 03:11:01PM +0100, codekipper@gmail.com wrote:

...

From: Marcus Cooper codekipper@gmail.com

On the newer SoCs this is set by default to transfer a 0 after each sample in each slot. Add the regmap field to configure this and set it so that it pads the sample with 0s.

Signed-off-by: Marcus Cooper codekipper@gmail.com

sound/soc/sunxi/sun4i-i2s.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 626679057d0f..9fda1240b717 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -139,6 +139,7 @@

• @field_fmt_bclk: regmap field to set clk polarity.
• @field_fmt_lrclk: regmap field to set frame polarity.
• @field_fmt_mode: regmap field to set the operational mode.

• • @field_fmt_sext: regmap field to set the sign extension.
  • @field_txchanmap: location of the tx channel mapping register.
  • @field_rxchanmap: location of the rx channel mapping register.
  • @field_txchansel: location of the tx channel select bit fields.

@@ -164,6 +165,7 @@ struct sun4i_i2s_quirks { struct reg_field field_fmt_bclk; struct reg_field field_fmt_lrclk; struct reg_field field_fmt_mode;

• struct reg_field                field_fmt_sext;
  struct reg_field                field_txchanmap;
  struct reg_field                field_rxchanmap;
  struct reg_field                field_txchansel;
  

@@ -188,6 +190,7 @@ struct sun4i_i2s { struct regmap_field *field_fmt_bclk; struct regmap_field *field_fmt_lrclk; struct regmap_field *field_fmt_mode;

• struct regmap_field     *field_fmt_sext;
  struct regmap_field     *field_txchanmap;
  struct regmap_field     *field_rxchanmap;
  struct regmap_field     *field_txchansel;
  

@@ -358,6 +361,9 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, SUN8I_I2S_FMT0_LRCK_PERIOD(word_size));

• /* Set sign extension to pad out LSB with 0 */
  

• regmap_field_write(i2s->field_fmt_sext, 0);
  

Your commit log seems to suggest that it's only relevant for the newer SoCs (which ones?), yet you enable it for all the supported ones. Either the code or the commit log should be adjusted to be consistent with the other.

ACK Thanks, CK

Maxime

-- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com