[PATCH v7 0/2] Add support for SoundWire1.6 audio cgcr register control
This patch series is to add v1.6.0 compatible name for qcom soundwire driver and corresponding dt bindings.
Changes Since V6: -- Update commit message -- Update Example with reset control in dt bindings. Changes Since V5: -- Constify static struct qcom_swrm_data global variables. -- Remove redundant swrm_v1_6_data variable. Changes Since V4: -- Dropped audio cgcr control patch due to dependency on clock patches. -- Update dt-bindings as per new reset control properties. Changes Since V3: -- Add v1.6.0 compatible name and soundwire data structure. -- Change macro define name properly. -- Update bindings for new property. -- Change commit message description. -- Change signedoff by sequence. Changes since v2: -- Update error check after ioremap. Changes since v1: -- Add const name to mask value. Srinivasa Rao Mandadapu (2): soundwire: qcom: Add compatible name for v1.6.0 dt-bindings: soundwire: qcom: Add bindings for audio clock reset control property
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 14 ++++++++++++++ drivers/soundwire/qcom.c | 1 + 2 files changed, 15 insertions(+)
Update compatible string and master data information in soundwire driver to support v1.6.0 in lpass sc7280 based platform.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Co-developed-by: Venkata Prasad Potturu quic_potturu@quicinc.com Signed-off-by: Venkata Prasad Potturu quic_potturu@quicinc.com --- drivers/soundwire/qcom.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 4337761..2d955ca 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -1348,6 +1348,7 @@ static int qcom_swrm_remove(struct platform_device *pdev) static const struct of_device_id qcom_swrm_of_match[] = { { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, + { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_5_data }, {/* sentinel */}, };
Quoting Srinivasa Rao Mandadapu (2022-03-03 06:02:07)
Update compatible string and master data information in soundwire driver to support v1.6.0 in lpass sc7280 based platform.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Co-developed-by: Venkata Prasad Potturu quic_potturu@quicinc.com Signed-off-by: Venkata Prasad Potturu quic_potturu@quicinc.com
Reviewed-by: Stephen Boyd swboyd@chromium.org
Update description for audio clock reset control property, which is required for latest chipsets, to allow rx, tx and wsa bus clock enabling in software control mode by configuring dynamic clock gating control registers.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Co-developed-by: Venkata Prasad Potturu quic_potturu@quicinc.com Signed-off-by: Venkata Prasad Potturu quic_potturu@quicinc.com --- Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt index b93a2b3..32e156d 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt +++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt @@ -150,6 +150,18 @@ board specific bus parameters. or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications.
+- reset: + Usage: optional + Value type: <prop-encoded-array> + Definition: Should specify the SoundWire audio CSR reset controller interface, + which is required for SoundWire version 1.6.0 and above. + +- reset-names: + Usage: optional + Value type: <stringlist> + Definition: should be "swr_audio_cgcr" for SoundWire audio CSR reset + controller interface. + Note: More Information on detail of encoding of these fields can be found in MIPI Alliance SoundWire 1.0 Specifications. @@ -168,6 +180,8 @@ soundwire: soundwire@c85 { interrupts = <20 IRQ_TYPE_EDGE_RISING>; clocks = <&wcc>; clock-names = "iface"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; #sound-dai-cells = <1>; qcom,dports-type = <0>; qcom,dout-ports = <6>;
On Thu, 03 Mar 2022 19:32:08 +0530, Srinivasa Rao Mandadapu wrote:
Update description for audio clock reset control property, which is required for latest chipsets, to allow rx, tx and wsa bus clock enabling in software control mode by configuring dynamic clock gating control registers.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Co-developed-by: Venkata Prasad Potturu quic_potturu@quicinc.com Signed-off-by: Venkata Prasad Potturu quic_potturu@quicinc.com
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
Acked-by: Rob Herring robh@kernel.org
Quoting Srinivasa Rao Mandadapu (2022-03-03 06:02:08)
Update description for audio clock reset control property, which is required for latest chipsets, to allow rx, tx and wsa bus clock enabling in software control mode by configuring dynamic clock gating control registers.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Co-developed-by: Venkata Prasad Potturu quic_potturu@quicinc.com Signed-off-by: Venkata Prasad Potturu quic_potturu@quicinc.com
Reviewed-by: Stephen Boyd swboyd@chromium.org
participants (3)
-
Rob Herring -
Srinivasa Rao Mandadapu -
Stephen Boyd