Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively.

Signed-off-by: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com Acked-by: Heiko Stuebner heiko@sntech.de # Rockchip drivers Reviewed-by: Michal Simek michal.simek@amd.com Reviewed-by: Cédric Le Goater clg@kaod.org # Aspeed driver Reviewed-by: Dhruva Gole d-gole@ti.com # SPI Cadence QSPI Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com # spi-stm32-qspi Acked-by: William Zhang william.zhang@broadcom.com # bcm63xx-hsspi driver Reviewed-by: Serge Semin fancer.lancer@gmail.com # DW SSI part --- drivers/spi/spi-altera-core.c | 2 +- drivers/spi/spi-amd.c | 4 ++-- drivers/spi/spi-ar934x.c | 2 +- drivers/spi/spi-armada-3700.c | 4 ++-- drivers/spi/spi-aspeed-smc.c | 13 +++++++------ drivers/spi/spi-at91-usart.c | 2 +- drivers/spi/spi-ath79.c | 4 ++-- drivers/spi/spi-atmel.c | 26 +++++++++++++------------- drivers/spi/spi-au1550.c | 4 ++-- drivers/spi/spi-axi-spi-engine.c | 2 +- drivers/spi/spi-bcm-qspi.c | 10 +++++----- drivers/spi/spi-bcm2835.c | 19 ++++++++++--------- drivers/spi/spi-bcm2835aux.c | 4 ++-- drivers/spi/spi-bcm63xx-hsspi.c | 30 +++++++++++++++--------------- drivers/spi/spi-bcm63xx.c | 2 +- drivers/spi/spi-bcmbca-hsspi.c | 30 +++++++++++++++--------------- drivers/spi/spi-cadence-quadspi.c | 5 +++-- drivers/spi/spi-cadence-xspi.c | 4 ++-- drivers/spi/spi-cadence.c | 4 ++-- drivers/spi/spi-cavium.c | 8 ++++---- drivers/spi/spi-coldfire-qspi.c | 8 ++++---- drivers/spi/spi-davinci.c | 18 +++++++++--------- drivers/spi/spi-dln2.c | 6 +++--- drivers/spi/spi-dw-core.c | 2 +- drivers/spi/spi-dw-mmio.c | 4 ++-- drivers/spi/spi-falcon.c | 2 +- drivers/spi/spi-fsi.c | 2 +- drivers/spi/spi-fsl-dspi.c | 16 ++++++++-------- drivers/spi/spi-fsl-espi.c | 6 +++--- drivers/spi/spi-fsl-lpspi.c | 2 +- drivers/spi/spi-fsl-qspi.c | 6 +++--- drivers/spi/spi-fsl-spi.c | 2 +- drivers/spi/spi-geni-qcom.c | 6 +++--- drivers/spi/spi-gpio.c | 4 ++-- drivers/spi/spi-gxp.c | 4 ++-- drivers/spi/spi-hisi-sfc-v3xx.c | 2 +- drivers/spi/spi-img-spfi.c | 14 +++++++------- drivers/spi/spi-imx.c | 30 +++++++++++++++--------------- drivers/spi/spi-ingenic.c | 4 ++-- drivers/spi/spi-intel.c | 2 +- drivers/spi/spi-jcore.c | 4 ++-- drivers/spi/spi-lantiq-ssc.c | 6 +++--- drivers/spi/spi-mem.c | 4 ++-- drivers/spi/spi-meson-spicc.c | 2 +- drivers/spi/spi-microchip-core.c | 6 +++--- drivers/spi/spi-mpc512x-psc.c | 8 ++++---- drivers/spi/spi-mpc52xx.c | 2 +- drivers/spi/spi-mt65xx.c | 6 +++--- drivers/spi/spi-mt7621.c | 2 +- drivers/spi/spi-mux.c | 8 ++++---- drivers/spi/spi-mxic.c | 10 +++++----- drivers/spi/spi-mxs.c | 2 +- drivers/spi/spi-npcm-fiu.c | 20 ++++++++++---------- drivers/spi/spi-nxp-fspi.c | 10 +++++----- drivers/spi/spi-omap-uwire.c | 8 ++++---- drivers/spi/spi-omap2-mcspi.c | 24 ++++++++++++------------ drivers/spi/spi-orion.c | 4 ++-- drivers/spi/spi-pci1xxxx.c | 4 ++-- drivers/spi/spi-pic32-sqi.c | 2 +- drivers/spi/spi-pic32.c | 4 ++-- drivers/spi/spi-pl022.c | 4 ++-- drivers/spi/spi-pxa2xx.c | 6 +++--- drivers/spi/spi-qcom-qspi.c | 2 +- drivers/spi/spi-rb4xx.c | 2 +- drivers/spi/spi-rockchip-sfc.c | 2 +- drivers/spi/spi-rockchip.c | 26 ++++++++++++++------------ drivers/spi/spi-rspi.c | 10 +++++----- drivers/spi/spi-s3c64xx.c | 2 +- drivers/spi/spi-sc18is602.c | 4 ++-- drivers/spi/spi-sh-msiof.c | 6 +++--- drivers/spi/spi-sh-sci.c | 2 +- drivers/spi/spi-sifive.c | 6 +++--- drivers/spi/spi-sn-f-ospi.c | 2 +- drivers/spi/spi-st-ssc4.c | 2 +- drivers/spi/spi-stm32-qspi.c | 12 ++++++------ drivers/spi/spi-sun4i.c | 2 +- drivers/spi/spi-sun6i.c | 2 +- drivers/spi/spi-synquacer.c | 6 +++--- drivers/spi/spi-tegra114.c | 28 ++++++++++++++-------------- drivers/spi/spi-tegra20-sflash.c | 2 +- drivers/spi/spi-tegra20-slink.c | 6 +++--- drivers/spi/spi-tegra210-quad.c | 8 ++++---- drivers/spi/spi-ti-qspi.c | 16 ++++++++-------- drivers/spi/spi-topcliff-pch.c | 4 ++-- drivers/spi/spi-wpcm-fiu.c | 12 ++++++------ drivers/spi/spi-xcomm.c | 2 +- drivers/spi/spi-xilinx.c | 6 +++--- drivers/spi/spi-xlp.c | 4 ++-- drivers/spi/spi-zynq-qspi.c | 2 +- drivers/spi/spi-zynqmp-gqspi.c | 2 +- drivers/spi/spidev.c | 6 +++--- include/trace/events/spi.h | 10 +++++----- 92 files changed, 333 insertions(+), 328 deletions(-)

diff --git a/drivers/spi/spi-altera-core.c b/drivers/spi/spi-altera-core.c index 94fe6bf1b9a6..87e37f48f196 100644 --- a/drivers/spi/spi-altera-core.c +++ b/drivers/spi/spi-altera-core.c @@ -80,7 +80,7 @@ static void altera_spi_set_cs(struct spi_device *spi, bool is_high) altr_spi_writel(hw, ALTERA_SPI_TARGET_SEL, 0); } else { altr_spi_writel(hw, ALTERA_SPI_TARGET_SEL, - BIT(spi->chip_select)); + BIT(spi_get_chipselect(spi, 0))); hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK; altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr); } diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index bfc3ab5f39ea..fecead757a3c 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -347,7 +347,7 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, case AMD_SPI_V1: break; case AMD_SPI_V2: - amd_spi_clear_chip(amd_spi, message->spi->chip_select); + amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0)); break; default: return -ENODEV; @@ -364,7 +364,7 @@ static int amd_spi_master_transfer(struct spi_master *master, struct amd_spi *amd_spi = spi_master_get_devdata(master); struct spi_device *spi = msg->spi;

- amd_spi_select_chip(amd_spi, spi->chip_select); + amd_spi_select_chip(amd_spi, spi_get_chipselect(spi, 0));

/* * Extract spi_transfers from the spi message and diff --git a/drivers/spi/spi-ar934x.c b/drivers/spi/spi-ar934x.c index c71c8348eeaa..9dcada8c4cb9 100644 --- a/drivers/spi/spi-ar934x.c +++ b/drivers/spi/spi-ar934x.c @@ -125,7 +125,7 @@ static int ar934x_spi_transfer_one_message(struct spi_controller *ctlr, iowrite32(reg, sp->base + AR934X_SPI_DATAOUT); }

- reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term, + reg = AR934X_SPI_SHIFT_VAL(spi_get_chipselect(spi, 0), term, trx_cur * 8); iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL); stat = readl_poll_timeout( diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c index 6a7e605f73bf..a7fb7c94e70e 100644 --- a/drivers/spi/spi-armada-3700.c +++ b/drivers/spi/spi-armada-3700.c @@ -437,9 +437,9 @@ static void a3700_spi_set_cs(struct spi_device *spi, bool enable) struct a3700_spi *a3700_spi = spi_controller_get_devdata(spi->controller);

if (!enable) - a3700_spi_activate_cs(a3700_spi, spi->chip_select); + a3700_spi_activate_cs(a3700_spi, spi_get_chipselect(spi, 0)); else - a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); + a3700_spi_deactivate_cs(a3700_spi, spi_get_chipselect(spi, 0)); }

static void a3700_spi_header_set(struct a3700_spi *a3700_spi) diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 3f2548860317..e75b0d51f06a 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -296,7 +296,7 @@ static const struct aspeed_spi_data ast2400_spi_data; static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master); - struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select]; + struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(mem->spi, 0)]; u32 addr_mode, addr_mode_backup; u32 ctl_val; int ret = 0; @@ -377,7 +377,8 @@ static const char *aspeed_spi_get_name(struct spi_mem *mem) struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master); struct device *dev = aspi->dev;

- return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); + return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), + spi_get_chipselect(mem->spi, 0)); }

struct aspeed_spi_window { @@ -553,7 +554,7 @@ static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip); static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) { struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master); - struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select]; + struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)]; struct spi_mem_op *op = &desc->info.op_tmpl; u32 ctl_val; int ret = 0; @@ -620,7 +621,7 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offset, size_t len, void *buf) { struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master); - struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select]; + struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];

/* Switch to USER command mode if mapping window is too small */ if (chip->ahb_window_size < offset + len) { @@ -670,7 +671,7 @@ static int aspeed_spi_setup(struct spi_device *spi) { struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master); const struct aspeed_spi_data *data = aspi->data; - unsigned int cs = spi->chip_select; + unsigned int cs = spi_get_chipselect(spi, 0); struct aspeed_spi_chip *chip = &aspi->chips[cs];

chip->aspi = aspi; @@ -697,7 +698,7 @@ static int aspeed_spi_setup(struct spi_device *spi) static void aspeed_spi_cleanup(struct spi_device *spi) { struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master); - unsigned int cs = spi->chip_select; + unsigned int cs = spi_get_chipselect(spi, 0);

aspeed_spi_chip_enable(aspi, cs, false);

diff --git a/drivers/spi/spi-at91-usart.c b/drivers/spi/spi-at91-usart.c index 4fb3653b5941..7854d9790fe9 100644 --- a/drivers/spi/spi-at91-usart.c +++ b/drivers/spi/spi-at91-usart.c @@ -390,7 +390,7 @@ static int at91_usart_spi_setup(struct spi_device *spi)

dev_dbg(&spi->dev, "setup: bpw %u mode 0x%x -> mr %d %08x\n", - spi->bits_per_word, spi->mode, spi->chip_select, mr); + spi->bits_per_word, spi->mode, spi_get_chipselect(spi, 0), mr);

return 0; } diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c index b4d25b3bee19..d3dd21386f12 100644 --- a/drivers/spi/spi-ath79.c +++ b/drivers/spi/spi-ath79.c @@ -71,7 +71,7 @@ static void ath79_spi_chipselect(struct spi_device *spi, int is_active) { struct ath79_spi *sp = ath79_spidev_to_sp(spi); int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; - u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); + u32 cs_bit = AR71XX_SPI_IOC_CS(spi_get_chipselect(spi, 0));

if (cs_high) sp->ioc_base |= cs_bit; @@ -140,7 +140,7 @@ static int ath79_exec_mem_op(struct spi_mem *mem, struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);

/* Ensures that reading is performed on device connected to hardware cs0 */ - if (mem->spi->chip_select || mem->spi->cs_gpiod) + if (spi_get_chipselect(mem->spi, 0) || spi_get_csgpiod(mem->spi, 0)) return -ENOTSUPP;

/* Only use for fast-read op. */ diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 73f80c8ac2ff..7f06305e16cb 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -327,10 +327,10 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi) int chip_select; u32 mr;

- if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) chip_select = as->native_cs_for_gpio; else - chip_select = spi->chip_select; + chip_select = spi_get_chipselect(spi, 0);

if (atmel_spi_is_v2(as)) { spi_writel(as, CSR0 + 4 * chip_select, asd->csr); @@ -378,10 +378,10 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) int chip_select; u32 mr;

- if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) chip_select = as->native_cs_for_gpio; else - chip_select = spi->chip_select; + chip_select = spi_get_chipselect(spi, 0);

/* only deactivate *this* device; sometimes transfers to * another device may be active when this routine is called. @@ -394,7 +394,7 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)

dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);

- if (!spi->cs_gpiod) + if (!spi_get_csgpiod(spi, 0)) spi_writel(as, CR, SPI_BIT(LASTXFER)); }

@@ -800,10 +800,10 @@ static int atmel_spi_set_xfer_speed(struct atmel_spi *as, unsigned long bus_hz; int chip_select;

- if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) chip_select = as->native_cs_for_gpio; else - chip_select = spi->chip_select; + chip_select = spi_get_chipselect(spi, 0);

/* v1 chips start out at half the peripheral bus speed. */ bus_hz = as->spi_clk; @@ -1189,7 +1189,7 @@ static int atmel_spi_setup(struct spi_device *spi) as = spi_controller_get_devdata(spi->controller);

/* see notes above re chipselect */ - if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) { + if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH)) { dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); return -EINVAL; } @@ -1201,16 +1201,16 @@ static int atmel_spi_setup(struct spi_device *spi) */ initialize_native_cs_for_gpio(as);

- if (spi->cs_gpiod && as->native_cs_free) { + if (spi_get_csgpiod(spi, 0) && as->native_cs_free) { dev_err(&spi->dev, "No native CS available to support this GPIO CS\n"); return -EBUSY; }

- if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) chip_select = as->native_cs_for_gpio; else - chip_select = spi->chip_select; + chip_select = spi_get_chipselect(spi, 0);

csr = SPI_BF(BITS, bits - 8); if (spi->mode & SPI_CPOL) @@ -1218,7 +1218,7 @@ static int atmel_spi_setup(struct spi_device *spi) if (!(spi->mode & SPI_CPHA)) csr |= SPI_BIT(NCPHA);

- if (!spi->cs_gpiod) + if (!spi_get_csgpiod(spi, 0)) csr |= SPI_BIT(CSAAT); csr |= SPI_BF(DLYBS, 0);

@@ -1244,7 +1244,7 @@ static int atmel_spi_setup(struct spi_device *spi)

dev_dbg(&spi->dev, "setup: bpw %u mode 0x%x -> csr%d %08x\n", - bits, spi->mode, spi->chip_select, csr); + bits, spi->mode, spi_get_chipselect(spi, 0), csr);

if (!atmel_spi_is_v2(as)) spi_writel(as, CSR0 + 4 * chip_select, csr); diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c index 8151bed8a117..0b57e6afce0f 100644 --- a/drivers/spi/spi-au1550.c +++ b/drivers/spi/spi-au1550.c @@ -166,7 +166,7 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value) switch (value) { case BITBANG_CS_INACTIVE: if (hw->pdata->deactivate_cs) - hw->pdata->deactivate_cs(hw->pdata, spi->chip_select, + hw->pdata->deactivate_cs(hw->pdata, spi_get_chipselect(spi, 0), cspol); break;

@@ -211,7 +211,7 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value) } while ((stat & PSC_SPISTAT_DR) == 0);

if (hw->pdata->activate_cs) - hw->pdata->activate_cs(hw->pdata, spi->chip_select, + hw->pdata->activate_cs(hw->pdata, spi_get_chipselect(spi, 0), cspol); break; } diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-engine.c index c5a3a3189164..89661f3b0d44 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -193,7 +193,7 @@ static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry, unsigned int mask = 0xff;

if (assert) - mask ^= BIT(spi->chip_select); + mask ^= BIT(spi_get_chipselect(spi, 0));

spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask)); } diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 0eee574d3e1f..7c2f1d1fb3f7 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -986,7 +986,7 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) if (has_bspi(qspi)) mspi_cdram &= ~1; else - mspi_cdram |= (~(1 << spi->chip_select) & + mspi_cdram |= (~(1 << spi_get_chipselect(spi, 0)) & MSPI_CDRAM_PCS);

write_cdram_slot(qspi, slot, mspi_cdram); @@ -1046,8 +1046,8 @@ static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi, return -EIO;

from = op->addr.val; - if (!spi->cs_gpiod) - bcm_qspi_chip_select(qspi, spi->chip_select); + if (!spi_get_csgpiod(spi, 0)) + bcm_qspi_chip_select(qspi, spi_get_chipselect(spi, 0)); bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);

/* @@ -1126,8 +1126,8 @@ static int bcm_qspi_transfer_one(struct spi_master *master, int slots; unsigned long timeo = msecs_to_jiffies(100);

- if (!spi->cs_gpiod) - bcm_qspi_chip_select(qspi, spi->chip_select); + if (!spi_get_csgpiod(spi, 0)) + bcm_qspi_chip_select(qspi, spi_get_chipselect(spi, 0)); qspi->trans_pos.trans = trans; qspi->trans_pos.byte = 0;

diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c index 747e03228c48..6b7a3fa93fdf 100644 --- a/drivers/spi/spi-bcm2835.c +++ b/drivers/spi/spi-bcm2835.c @@ -1274,9 +1274,9 @@ static int bcm2835_spi_setup(struct spi_device *spi) * The SPI core has successfully requested the CS GPIO line from the * device tree, so we are done. */ - if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) return 0; - if (spi->chip_select > 1) { + if (spi_get_chipselect(spi, 0) > 1) { /* error in the case of native CS requested with CS > 1 * officially there is a CS2, but it is not documented * which GPIO is connected with that... @@ -1301,18 +1301,19 @@ static int bcm2835_spi_setup(struct spi_device *spi) if (!chip) return 0;

- spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select, - DRV_NAME, - GPIO_LOOKUP_FLAGS_DEFAULT, - GPIOD_OUT_LOW); - if (IS_ERR(spi->cs_gpiod)) { - ret = PTR_ERR(spi->cs_gpiod); + spi_set_csgpiod(spi, 0, gpiochip_request_own_desc(chip, + 8 - (spi_get_chipselect(spi, 0)), + DRV_NAME, + GPIO_LOOKUP_FLAGS_DEFAULT, + GPIOD_OUT_LOW)); + if (IS_ERR(spi_get_csgpiod(spi, 0))) { + ret = PTR_ERR(spi_get_csgpiod(spi, 0)); goto err_cleanup; }

/* and set up the "mode" and level */ dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n", - spi->chip_select); + spi_get_chipselect(spi, 0));

return 0;

diff --git a/drivers/spi/spi-bcm2835aux.c b/drivers/spi/spi-bcm2835aux.c index 7f2546fd900a..288f7b994b36 100644 --- a/drivers/spi/spi-bcm2835aux.c +++ b/drivers/spi/spi-bcm2835aux.c @@ -448,7 +448,7 @@ static int bcm2835aux_spi_setup(struct spi_device *spi) if (spi->mode & SPI_NO_CS) return 0;

- if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) return 0;

/* for dt-backwards compatibility: only support native on CS0 @@ -465,7 +465,7 @@ static int bcm2835aux_spi_setup(struct spi_device *spi) dev_warn(&spi->dev, "Native CS is not supported - please configure cs-gpio in device-tree\n");

- if (spi->chip_select == 0) + if (spi_get_chipselect(spi, 0) == 0) return 0;

dev_warn(&spi->dev, "Native CS is not working for cs > 0\n"); diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index f2708caa2f33..ee2528dad02d 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -349,7 +349,7 @@ static int bcm63xx_hsspi_do_prepend_txrx(struct spi_device *spi, struct spi_transfer *t) { struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); - unsigned int chip_select = spi->chip_select; + unsigned int chip_select = spi_get_chipselect(spi, 0); u16 opcode = 0, val; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; @@ -441,7 +441,7 @@ static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs, static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, struct spi_device *spi, int hz) { - unsigned int profile = spi->chip_select; + unsigned int profile = spi_get_chipselect(spi, 0); u32 reg;

reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); @@ -468,7 +468,7 @@ static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) { struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); - unsigned int chip_select = spi->chip_select; + unsigned int chip_select = spi_get_chipselect(spi, 0); u16 opcode = 0, val; int pending = t->len; int step_size = HSSPI_BUFFER_LEN; @@ -478,7 +478,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)

bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); if (!t->cs_off) - bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); + bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);

if (tx && rx) opcode = HSSPI_OP_READ_WRITE; @@ -545,14 +545,14 @@ static int bcm63xx_hsspi_setup(struct spi_device *spi) u32 reg;

reg = __raw_readl(bs->regs + - HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); + HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0))); reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING); if (spi->mode & SPI_CPHA) reg |= SIGNAL_CTRL_LAUNCH_RISING; else reg |= SIGNAL_CTRL_LATCH_RISING; __raw_writel(reg, bs->regs + - HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); + HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));

mutex_lock(&bs->bus_mutex); reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); @@ -560,16 +560,16 @@ static int bcm63xx_hsspi_setup(struct spi_device *spi) /* only change actual polarities if there is no transfer */ if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) { if (spi->mode & SPI_CS_HIGH) - reg |= BIT(spi->chip_select); + reg |= BIT(spi_get_chipselect(spi, 0)); else - reg &= ~BIT(spi->chip_select); + reg &= ~BIT(spi_get_chipselect(spi, 0)); __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); }

if (spi->mode & SPI_CS_HIGH) - bs->cs_polarity |= BIT(spi->chip_select); + bs->cs_polarity |= BIT(spi_get_chipselect(spi, 0)); else - bs->cs_polarity &= ~BIT(spi->chip_select); + bs->cs_polarity &= ~BIT(spi_get_chipselect(spi, 0));

mutex_unlock(&bs->bus_mutex);

@@ -600,7 +600,7 @@ static int bcm63xx_hsspi_do_dummy_cs_txrx(struct spi_device *spi, * e. At the end restore the polarities again to their default values. */

- dummy_cs = !spi->chip_select; + dummy_cs = !spi_get_chipselect(spi, 0); bcm63xx_hsspi_set_cs(bs, dummy_cs, true);

list_for_each_entry(t, &msg->transfers, transfer_list) { @@ -633,22 +633,22 @@ static int bcm63xx_hsspi_do_dummy_cs_txrx(struct spi_device *spi, keep_cs = true; } else { if (!t->cs_off) - bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); + bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);

spi_transfer_cs_change_delay_exec(msg, t);

if (!list_next_entry(t, transfer_list)->cs_off) - bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); + bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true); } } else if (!list_is_last(&t->transfer_list, &msg->transfers) && t->cs_off != list_next_entry(t, transfer_list)->cs_off) { - bcm63xx_hsspi_set_cs(bs, spi->chip_select, t->cs_off); + bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), t->cs_off); } }

bcm63xx_hsspi_set_cs(bs, dummy_cs, false); if (status || !keep_cs) - bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); + bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);

return status; } diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c index 77b8328c8a6d..96633a0051b1 100644 --- a/drivers/spi/spi-bcm63xx.c +++ b/drivers/spi/spi-bcm63xx.c @@ -282,7 +282,7 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, /* Issue the transfer */ cmd = SPI_CMD_START_IMMEDIATE; cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); - cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); + cmd |= (spi_get_chipselect(spi, 0) << SPI_CMD_DEVICE_ID_SHIFT); bcm_spi_writew(bs, cmd, SPI_CMD);

/* Enable the CMD_DONE interrupt */ diff --git a/drivers/spi/spi-bcmbca-hsspi.c b/drivers/spi/spi-bcmbca-hsspi.c index c7a44832bc9c..8cbd01619789 100644 --- a/drivers/spi/spi-bcmbca-hsspi.c +++ b/drivers/spi/spi-bcmbca-hsspi.c @@ -193,7 +193,7 @@ static void bcmbca_hsspi_set_cs(struct bcmbca_hsspi *bs, unsigned int cs, static void bcmbca_hsspi_set_clk(struct bcmbca_hsspi *bs, struct spi_device *spi, int hz) { - unsigned int profile = spi->chip_select; + unsigned int profile = spi_get_chipselect(spi, 0); u32 reg;

reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); @@ -251,7 +251,7 @@ static int bcmbca_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t, struct spi_message *msg) { struct bcmbca_hsspi *bs = spi_master_get_devdata(spi->master); - unsigned int chip_select = spi->chip_select; + unsigned int chip_select = spi_get_chipselect(spi, 0); u16 opcode = 0, val; int pending = t->len; int step_size = HSSPI_BUFFER_LEN; @@ -312,7 +312,7 @@ static int bcmbca_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t, PINGPONG_COMMAND_START_NOW; __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));

- if (bcmbca_hsspi_wait_cmd(bs, spi->chip_select)) + if (bcmbca_hsspi_wait_cmd(bs, spi_get_chipselect(spi, 0))) return -ETIMEDOUT;

pending -= curr_step; @@ -332,33 +332,33 @@ static int bcmbca_hsspi_setup(struct spi_device *spi) u32 reg;

reg = __raw_readl(bs->regs + - HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); + HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0))); reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING); if (spi->mode & SPI_CPHA) reg |= SIGNAL_CTRL_LAUNCH_RISING; else reg |= SIGNAL_CTRL_LATCH_RISING; __raw_writel(reg, bs->regs + - HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); + HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));

mutex_lock(&bs->bus_mutex); reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);

if (spi->mode & SPI_CS_HIGH) - reg |= BIT(spi->chip_select); + reg |= BIT(spi_get_chipselect(spi, 0)); else - reg &= ~BIT(spi->chip_select); + reg &= ~BIT(spi_get_chipselect(spi, 0)); __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);

if (spi->mode & SPI_CS_HIGH) - bs->cs_polarity |= BIT(spi->chip_select); + bs->cs_polarity |= BIT(spi_get_chipselect(spi, 0)); else - bs->cs_polarity &= ~BIT(spi->chip_select); + bs->cs_polarity &= ~BIT(spi_get_chipselect(spi, 0));

reg = __raw_readl(bs->spim_ctrl); - reg &= ~BIT(spi->chip_select + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); + reg &= ~BIT(spi_get_chipselect(spi, 0) + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); if (spi->mode & SPI_CS_HIGH) - reg |= BIT(spi->chip_select + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); + reg |= BIT(spi_get_chipselect(spi, 0) + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); __raw_writel(reg, bs->spim_ctrl);

mutex_unlock(&bs->bus_mutex); @@ -388,16 +388,16 @@ static int bcmbca_hsspi_transfer_one(struct spi_master *master, keep_cs = true; } else { if (!t->cs_off) - bcmbca_hsspi_set_cs(bs, spi->chip_select, false); + bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);

spi_transfer_cs_change_delay_exec(msg, t);

if (!list_next_entry(t, transfer_list)->cs_off) - bcmbca_hsspi_set_cs(bs, spi->chip_select, true); + bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true); } } else if (!list_is_last(&t->transfer_list, &msg->transfers) && t->cs_off != list_next_entry(t, transfer_list)->cs_off) { - bcmbca_hsspi_set_cs(bs, spi->chip_select, t->cs_off); + bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), t->cs_off); }

msg->actual_length += t->len; @@ -406,7 +406,7 @@ static int bcmbca_hsspi_transfer_one(struct spi_master *master, mutex_unlock(&bs->msg_mutex);

if (status || !keep_cs) - bcmbca_hsspi_set_cs(bs, spi->chip_select, false); + bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);

msg->status = status; spi_finalize_current_message(master); diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 463fd49f4f80..79ab7e309644 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1355,7 +1355,7 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); struct cqspi_flash_pdata *f_pdata;

- f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; + f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; cqspi_configure(f_pdata, mem->spi->max_speed_hz);

if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { @@ -1561,7 +1561,8 @@ static const char *cqspi_get_name(struct spi_mem *mem) struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); struct device *dev = &cqspi->pdev->dev;

- return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); + return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), + spi_get_chipselect(mem->spi, 0)); }

static const struct spi_controller_mem_ops cqspi_mem_ops = { diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index 91db3c973167..ce4a3145f065 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -409,8 +409,8 @@ static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi, { enum spi_mem_data_dir dir = op->data.dir;

- if (cdns_xspi->cur_cs != mem->spi->chip_select) - cdns_xspi->cur_cs = mem->spi->chip_select; + if (cdns_xspi->cur_cs != spi_get_chipselect(mem->spi, 0)) + cdns_xspi->cur_cs = spi_get_chipselect(mem->spi, 0);

return cdns_xspi_send_stig_command(cdns_xspi, op, (dir != SPI_MEM_NO_DATA)); diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index 1ad86e5d2b2f..49936237e583 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -185,11 +185,11 @@ static void cdns_spi_chipselect(struct spi_device *spi, bool is_high) /* Select the slave */ ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; if (!(xspi->is_decoded_cs)) - ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << + ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) << CDNS_SPI_SS_SHIFT) & CDNS_SPI_CR_SSCTRL; else - ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & + ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) & CDNS_SPI_CR_SSCTRL; }

diff --git a/drivers/spi/spi-cavium.c b/drivers/spi/spi-cavium.c index 6854c3ce423b..dfe224defd6e 100644 --- a/drivers/spi/spi-cavium.c +++ b/drivers/spi/spi-cavium.c @@ -57,8 +57,8 @@ static int octeon_spi_do_transfer(struct octeon_spi *p, mpi_cfg.s.cslate = cpha ? 1 : 0; mpi_cfg.s.enable = 1;

- if (spi->chip_select < 4) - p->cs_enax |= 1ull << (12 + spi->chip_select); + if (spi_get_chipselect(spi, 0) < 4) + p->cs_enax |= 1ull << (12 + spi_get_chipselect(spi, 0)); mpi_cfg.u64 |= p->cs_enax;

if (mpi_cfg.u64 != p->last_cfg) { @@ -78,7 +78,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p, writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); } mpi_tx.u64 = 0; - mpi_tx.s.csid = spi->chip_select; + mpi_tx.s.csid = spi_get_chipselect(spi, 0); mpi_tx.s.leavecs = 1; mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0; mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES; @@ -103,7 +103,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p, }

mpi_tx.u64 = 0; - mpi_tx.s.csid = spi->chip_select; + mpi_tx.s.csid = spi_get_chipselect(spi, 0); if (last_xfer) mpi_tx.s.leavecs = xfer->cs_change; else diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c index d98e74c6e4b2..b1bd8a6b5bf9 100644 --- a/drivers/spi/spi-coldfire-qspi.c +++ b/drivers/spi/spi-coldfire-qspi.c @@ -290,9 +290,9 @@ static void mcfqspi_set_cs(struct spi_device *spi, bool enable) bool cs_high = spi->mode & SPI_CS_HIGH;

if (enable) - mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); + mcfqspi_cs_select(mcfqspi, spi_get_chipselect(spi, 0), cs_high); else - mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high); + mcfqspi_cs_deselect(mcfqspi, spi_get_chipselect(spi, 0), cs_high); }

static int mcfqspi_transfer_one(struct spi_master *master, @@ -324,11 +324,11 @@ static int mcfqspi_transfer_one(struct spi_master *master, static int mcfqspi_setup(struct spi_device *spi) { mcfqspi_cs_deselect(spi_master_get_devdata(spi->master), - spi->chip_select, spi->mode & SPI_CS_HIGH); + spi_get_chipselect(spi, 0), spi->mode & SPI_CS_HIGH);

dev_dbg(&spi->dev, "bits per word %d, chip select %d, speed %d KHz\n", - spi->bits_per_word, spi->chip_select, + spi->bits_per_word, spi_get_chipselect(spi, 0), (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz)) / 1000);

diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index add1e198a439..b04811c911e2 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -199,7 +199,7 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) { struct davinci_spi *dspi; struct davinci_spi_config *spicfg = spi->controller_data; - u8 chip_sel = spi->chip_select; + u8 chip_sel = spi_get_chipselect(spi, 0); u16 spidat1 = CS_DEFAULT;

dspi = spi_master_get_devdata(spi->master); @@ -212,11 +212,11 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) * Board specific chip select logic decides the polarity and cs * line for the controller */ - if (spi->cs_gpiod) { + if (spi_get_csgpiod(spi, 0)) { if (value == BITBANG_CS_ACTIVE) - gpiod_set_value(spi->cs_gpiod, 1); + gpiod_set_value(spi_get_csgpiod(spi, 0), 1); else - gpiod_set_value(spi->cs_gpiod, 0); + gpiod_set_value(spi_get_csgpiod(spi, 0), 0); } else { if (value == BITBANG_CS_ACTIVE) { if (!(spi->mode & SPI_CS_WORD)) @@ -293,11 +293,11 @@ static int davinci_spi_setup_transfer(struct spi_device *spi, if (bits_per_word <= 8) { dspi->get_rx = davinci_spi_rx_buf_u8; dspi->get_tx = davinci_spi_tx_buf_u8; - dspi->bytes_per_word[spi->chip_select] = 1; + dspi->bytes_per_word[spi_get_chipselect(spi, 0)] = 1; } else { dspi->get_rx = davinci_spi_rx_buf_u16; dspi->get_tx = davinci_spi_tx_buf_u16; - dspi->bytes_per_word[spi->chip_select] = 2; + dspi->bytes_per_word[spi_get_chipselect(spi, 0)] = 2; }

if (!hz) @@ -415,11 +415,11 @@ static int davinci_spi_setup(struct spi_device *spi) dspi = spi_master_get_devdata(spi->master);

if (!(spi->mode & SPI_NO_CS)) { - if (np && spi->cs_gpiod) + if (np && spi_get_csgpiod(spi, 0)) internal_cs = false;

if (internal_cs) - set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); + set_io_bits(dspi->base + SPIPC0, 1 << spi_get_chipselect(spi, 0)); }

if (spi->mode & SPI_READY) @@ -579,7 +579,7 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) spicfg = &davinci_spi_default_cfg;

/* convert len to words based on bits_per_word */ - data_type = dspi->bytes_per_word[spi->chip_select]; + data_type = dspi->bytes_per_word[spi_get_chipselect(spi, 0)];

dspi->tx = t->tx_buf; dspi->rx = t->rx_buf; diff --git a/drivers/spi/spi-dln2.c b/drivers/spi/spi-dln2.c index 821bfc6b0dd6..6bd93c47853c 100644 --- a/drivers/spi/spi-dln2.c +++ b/drivers/spi/spi-dln2.c @@ -596,12 +596,12 @@ static int dln2_spi_prepare_message(struct spi_master *master, struct dln2_spi *dln2 = spi_master_get_devdata(master); struct spi_device *spi = message->spi;

- if (dln2->cs != spi->chip_select) { - ret = dln2_spi_cs_set_one(dln2, spi->chip_select); + if (dln2->cs != spi_get_chipselect(spi, 0)) { + ret = dln2_spi_cs_set_one(dln2, spi_get_chipselect(spi, 0)); if (ret < 0) return ret;

- dln2->cs = spi->chip_select; + dln2->cs = spi_get_chipselect(spi, 0); }

return 0; diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index c3bfb6c84cab..ae3108c70f50 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -103,7 +103,7 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable) * support active-high or active-low CS level. */ if (cs_high == enable) - dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); + dw_writel(dws, DW_SPI_SER, BIT(spi_get_chipselect(spi, 0))); else dw_writel(dws, DW_SPI_SER, 0); } diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 6ae124c30969..328541b5fb52 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -65,7 +65,7 @@ static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable) struct dw_spi *dws = spi_master_get_devdata(spi->master); struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); struct dw_spi_mscc *dwsmscc = dwsmmio->priv; - u32 cs = spi->chip_select; + u32 cs = spi_get_chipselect(spi, 0);

if (cs < 4) { u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE; @@ -138,7 +138,7 @@ static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable) struct dw_spi *dws = spi_master_get_devdata(spi->master); struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); struct dw_spi_mscc *dwsmscc = dwsmmio->priv; - u8 cs = spi->chip_select; + u8 cs = spi_get_chipselect(spi, 0);

if (!enable) { /* CS override drive enable */ diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c index a7d4dffac66b..4c103dff0d44 100644 --- a/drivers/spi/spi-falcon.c +++ b/drivers/spi/spi-falcon.c @@ -131,7 +131,7 @@ int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t, * especially alen and dumlen. */

- priv->sfcmd = ((spi->chip_select + priv->sfcmd = ((spi_get_chipselect(spi, 0) << SFCMD_CS_OFFSET) & SFCMD_CS_MASK); priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED; diff --git a/drivers/spi/spi-fsi.c b/drivers/spi/spi-fsi.c index cf1e4f9ebd72..ba3b17d7c9ec 100644 --- a/drivers/spi/spi-fsi.c +++ b/drivers/spi/spi-fsi.c @@ -425,7 +425,7 @@ static int fsi_spi_transfer_one_message(struct spi_controller *ctlr, struct spi_message *mesg) { int rc; - u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1); + u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(spi_get_chipselect(mesg->spi, 0) + 1); unsigned int len; struct spi_transfer *transfer; struct fsi_spi *ctx = spi_controller_get_devdata(ctlr); diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 49df00f52ea4..ee42285b5c52 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -902,19 +902,19 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)

static void dspi_assert_cs(struct spi_device *spi, bool *cs) { - if (!spi->cs_gpiod || *cs) + if (!spi_get_csgpiod(spi, 0) || *cs) return;

- gpiod_set_value_cansleep(spi->cs_gpiod, true); + gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), true); *cs = true; }

static void dspi_deassert_cs(struct spi_device *spi, bool *cs) { - if (!spi->cs_gpiod || !*cs) + if (!spi_get_csgpiod(spi, 0) || !*cs) return;

- gpiod_set_value_cansleep(spi->cs_gpiod, false); + gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), false); *cs = false; }

@@ -938,8 +938,8 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr,

/* Prepare command word for CMD FIFO */ dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0); - if (!spi->cs_gpiod) - dspi->tx_cmd |= SPI_PUSHR_CMD_PCS(spi->chip_select); + if (!spi_get_csgpiod(spi, 0)) + dspi->tx_cmd |= SPI_PUSHR_CMD_PCS(spi_get_chipselect(spi, 0));

if (list_is_last(&dspi->cur_transfer->transfer_list, &dspi->cur_msg->transfers)) { @@ -1058,7 +1058,7 @@ static int dspi_setup(struct spi_device *spi) chip->ctar_val |= SPI_CTAR_LSBFE; }

- gpiod_direction_output(spi->cs_gpiod, false); + gpiod_direction_output(spi_get_csgpiod(spi, 0), false); dspi_deassert_cs(spi, &cs);

spi_set_ctldata(spi, chip); @@ -1071,7 +1071,7 @@ static void dspi_cleanup(struct spi_device *spi) struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);

dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", - spi->controller->bus_num, spi->chip_select); + spi->controller->bus_num, spi_get_chipselect(spi, 0));

kfree(chip); } diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c index 42a3ed79e7dc..b3d2d3db5850 100644 --- a/drivers/spi/spi-fsl-espi.c +++ b/drivers/spi/spi-fsl-espi.c @@ -345,7 +345,7 @@ static void fsl_espi_setup_transfer(struct spi_device *spi,

/* don't write the mode register if the mode doesn't change */ if (cs->hw_mode != hw_mode_old) - fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select), + fsl_espi_write_reg(espi, ESPI_SPMODEx(spi_get_chipselect(spi, 0)), cs->hw_mode); }

@@ -359,7 +359,7 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) reinit_completion(&espi->done);

/* Set SPCOM[CS] and SPCOM[TRANLEN] field */ - spcom = SPCOM_CS(spi->chip_select); + spcom = SPCOM_CS(spi_get_chipselect(spi, 0)); spcom |= SPCOM_TRANLEN(t->len - 1);

/* configure RXSKIP mode */ @@ -492,7 +492,7 @@ static int fsl_espi_setup(struct spi_device *spi)

pm_runtime_get_sync(espi->dev);

- cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select)); + cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi_get_chipselect(spi, 0))); /* mask out bits we are going to set */ cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | CSMODE_REV); diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index b9e8b7b241a4..f2341ab99556 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -425,7 +425,7 @@ static int fsl_lpspi_setup_transfer(struct spi_controller *controller, if (fsl_lpspi->is_only_cs1) fsl_lpspi->config.chip_select = 1; else - fsl_lpspi->config.chip_select = spi->chip_select; + fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);

if (!fsl_lpspi->config.speed_hz) fsl_lpspi->config.speed_hz = spi->max_speed_hz; diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index bacc54836959..8ade61e5ebc0 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -528,7 +528,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi) unsigned long rate = spi->max_speed_hz; int ret;

- if (q->selected == spi->chip_select) + if (q->selected == spi_get_chipselect(spi, 0)) return;

if (needs_4x_clock(q)) @@ -544,7 +544,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi) if (ret) return;

- q->selected = spi->chip_select; + q->selected = spi_get_chipselect(spi, 0);

fsl_qspi_invalidate(q); } @@ -823,7 +823,7 @@ static const char *fsl_qspi_get_name(struct spi_mem *mem)

name = devm_kasprintf(dev, GFP_KERNEL, "%s-%d", dev_name(q->dev), - mem->spi->chip_select); + spi_get_chipselect(mem->spi, 0));

if (!name) { dev_err(dev, "failed to get memory for custom flash name\n"); diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index 725d043488a1..702756c25aa7 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -503,7 +503,7 @@ static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; u32 slvsel; - u16 cs = spi->chip_select; + u16 cs = spi_get_chipselect(spi, 0);

if (cs < mpc8xxx_spi->native_chipselects) { slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel); diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index f80635532b4d..ba7be505ec4e 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -391,9 +391,9 @@ static int setup_fifo_params(struct spi_device *spi_slv, cpha = CPHA;

if (spi_slv->mode & SPI_CS_HIGH) - demux_output_inv = BIT(spi_slv->chip_select); + demux_output_inv = BIT(spi_get_chipselect(spi_slv, 0));

- demux_sel = spi_slv->chip_select; + demux_sel = spi_get_chipselect(spi_slv, 0); mas->cur_bits_per_word = spi_slv->bits_per_word;

spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); @@ -469,7 +469,7 @@ static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); - peripheral.cs = spi_slv->chip_select; + peripheral.cs = spi_get_chipselect(spi_slv, 0); peripheral.pack_en = true; peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN;

diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c index 9c8c7948044e..092afc7679d4 100644 --- a/drivers/spi/spi-gpio.c +++ b/drivers/spi/spi-gpio.c @@ -230,7 +230,7 @@ static void spi_gpio_chipselect(struct spi_device *spi, int is_active)

/* Drive chip select line, if we have one */ if (spi_gpio->cs_gpios) { - struct gpio_desc *cs = spi_gpio->cs_gpios[spi->chip_select]; + struct gpio_desc *cs = spi_gpio->cs_gpios[spi_get_chipselect(spi, 0)];

/* SPI chip selects are normally active-low */ gpiod_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active); @@ -248,7 +248,7 @@ static int spi_gpio_setup(struct spi_device *spi) * initialized from the descriptor lookup. */ if (spi_gpio->cs_gpios) { - cs = spi_gpio->cs_gpios[spi->chip_select]; + cs = spi_gpio->cs_gpios[spi_get_chipselect(spi, 0)]; if (!spi->controller_state && cs) status = gpiod_direction_output(cs, !(spi->mode & SPI_CS_HIGH)); diff --git a/drivers/spi/spi-gxp.c b/drivers/spi/spi-gxp.c index c900c2f39b57..684d63f402f3 100644 --- a/drivers/spi/spi-gxp.c +++ b/drivers/spi/spi-gxp.c @@ -201,7 +201,7 @@ static ssize_t gxp_spi_write(struct gxp_spi_chip *chip, const struct spi_mem_op static int do_gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct gxp_spi *spifi = spi_controller_get_devdata(mem->spi->master); - struct gxp_spi_chip *chip = &spifi->chips[mem->spi->chip_select]; + struct gxp_spi_chip *chip = &spifi->chips[spi_get_chipselect(mem->spi, 0)]; int ret;

if (op->data.dir == SPI_MEM_DATA_IN) { @@ -237,7 +237,7 @@ static const struct spi_controller_mem_ops gxp_spi_mem_ops = { static int gxp_spi_setup(struct spi_device *spi) { struct gxp_spi *spifi = spi_controller_get_devdata(spi->master); - unsigned int cs = spi->chip_select; + unsigned int cs = spi_get_chipselect(spi, 0); struct gxp_spi_chip *chip = &spifi->chips[cs];

chip->spifi = spifi; diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c index f07d1045a30a..7cbcb065bb44 100644 --- a/drivers/spi/spi-hisi-sfc-v3xx.c +++ b/drivers/spi/spi-hisi-sfc-v3xx.c @@ -361,7 +361,7 @@ static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem, { struct hisi_sfc_v3xx_host *host; struct spi_device *spi = mem->spi; - u8 chip_select = spi->chip_select; + u8 chip_select = spi_get_chipselect(spi, 0);

host = spi_controller_get_devdata(spi->master);

diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index c64e4fd3fdf0..d775f87770e3 100644 --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c @@ -413,15 +413,15 @@ static int img_spfi_prepare(struct spi_master *master, struct spi_message *msg) val = spfi_readl(spfi, SPFI_PORT_STATE); val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << SPFI_PORT_STATE_DEV_SEL_SHIFT); - val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT; + val |= spi_get_chipselect(msg->spi, 0) << SPFI_PORT_STATE_DEV_SEL_SHIFT; if (msg->spi->mode & SPI_CPHA) - val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); + val |= SPFI_PORT_STATE_CK_PHASE(spi_get_chipselect(msg->spi, 0)); else - val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); + val &= ~SPFI_PORT_STATE_CK_PHASE(spi_get_chipselect(msg->spi, 0)); if (msg->spi->mode & SPI_CPOL) - val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); + val |= SPFI_PORT_STATE_CK_POL(spi_get_chipselect(msg->spi, 0)); else - val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); + val &= ~SPFI_PORT_STATE_CK_POL(spi_get_chipselect(msg->spi, 0)); spfi_writel(spfi, val, SPFI_PORT_STATE);

return 0; @@ -450,11 +450,11 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi, div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz); div = clamp(512 / (1 << get_count_order(div)), 1, 128);

- val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); + val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi_get_chipselect(spi, 0))); val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT); val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; - spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); + spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi_get_chipselect(spi, 0)));

spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT, SPFI_TRANSACTION); diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index e4ccd0c329d0..620bce96b1f9 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -528,7 +528,7 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);

/* set chip select to use */ - ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); + ctrl |= MX51_ECSPI_CTRL_CS(spi_get_chipselect(spi, 0));

/* * The ctrl register must be written first, with the EN bit set other @@ -549,22 +549,22 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, * BURST_LENGTH + 1 bits are received */ if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) - cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi_get_chipselect(spi, 0)); else - cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi_get_chipselect(spi, 0));

if (spi->mode & SPI_CPOL) { - cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); - cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi_get_chipselect(spi, 0)); + cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi_get_chipselect(spi, 0)); } else { - cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); - cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi_get_chipselect(spi, 0)); + cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi_get_chipselect(spi, 0)); }

if (spi->mode & SPI_CS_HIGH) - cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi_get_chipselect(spi, 0)); else - cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi_get_chipselect(spi, 0));

if (cfg == current_cfg) return 0; @@ -614,9 +614,9 @@ static void mx51_configure_cpha(struct spi_imx_data *spi_imx, cpha ^= flip_cpha;

if (cpha) - cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi_get_chipselect(spi, 0)); else - cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi_get_chipselect(spi, 0));

writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); } @@ -768,8 +768,8 @@ static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, reg |= MX31_CSPICTRL_POL; if (spi->mode & SPI_CS_HIGH) reg |= MX31_CSPICTRL_SSPOL; - if (!spi->cs_gpiod) - reg |= (spi->chip_select) << + if (!spi_get_csgpiod(spi, 0)) + reg |= (spi_get_chipselect(spi, 0)) << (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : MX31_CSPICTRL_CS_SHIFT);

@@ -868,8 +868,8 @@ static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, reg |= MX21_CSPICTRL_POL; if (spi->mode & SPI_CS_HIGH) reg |= MX21_CSPICTRL_SSPOL; - if (!spi->cs_gpiod) - reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; + if (!spi_get_csgpiod(spi, 0)) + reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT;

writel(reg, spi_imx->base + MXC_CSPICTRL);

diff --git a/drivers/spi/spi-ingenic.c b/drivers/spi/spi-ingenic.c index 713a238bee63..7d4b515a160d 100644 --- a/drivers/spi/spi-ingenic.c +++ b/drivers/spi/spi-ingenic.c @@ -263,7 +263,7 @@ static int spi_ingenic_prepare_message(struct spi_controller *ctlr, { struct ingenic_spi *priv = spi_controller_get_devdata(ctlr); struct spi_device *spi = message->spi; - unsigned int cs = REG_SSICR1_FRMHL << spi->chip_select; + unsigned int cs = REG_SSICR1_FRMHL << spi_get_chipselect(spi, 0); unsigned int ssicr0_mask = REG_SSICR0_LOOP | REG_SSICR0_FSEL; unsigned int ssicr1_mask = REG_SSICR1_PHA | REG_SSICR1_POL | cs; unsigned int ssicr0 = 0, ssicr1 = 0; @@ -282,7 +282,7 @@ static int spi_ingenic_prepare_message(struct spi_controller *ctlr,

if (spi->mode & SPI_LOOP) ssicr0 |= REG_SSICR0_LOOP; - if (spi->chip_select) + if (spi_get_chipselect(spi, 0)) ssicr0 |= REG_SSICR0_FSEL;

if (spi->mode & SPI_CPHA) diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index f4679868c49f..bc6d22149e7e 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -451,7 +451,7 @@ static u32 intel_spi_chip_addr(const struct intel_spi *ispi, /* Pick up the correct start address */ if (!mem) return 0; - return mem->spi->chip_select == 1 ? ispi->chip0_size : 0; + return (spi_get_chipselect(mem->spi, 0) == 1) ? ispi->chip0_size : 0; }

static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem, diff --git a/drivers/spi/spi-jcore.c b/drivers/spi/spi-jcore.c index 74c8319c29f1..c42a3358e8c9 100644 --- a/drivers/spi/spi-jcore.c +++ b/drivers/spi/spi-jcore.c @@ -68,9 +68,9 @@ static void jcore_spi_program(struct jcore_spi *hw) static void jcore_spi_chipsel(struct spi_device *spi, bool value) { struct jcore_spi *hw = spi_master_get_devdata(spi->master); - u32 csbit = 1U << (2 * spi->chip_select); + u32 csbit = 1U << (2 * spi_get_chipselect(spi, 0));

- dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select); + dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi_get_chipselect(spi, 0));

if (value) hw->cs_reg |= csbit; diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c index 76cf2a66f874..8d6ecc5d6f70 100644 --- a/drivers/spi/spi-lantiq-ssc.c +++ b/drivers/spi/spi-lantiq-ssc.c @@ -388,11 +388,11 @@ static int lantiq_ssc_setup(struct spi_device *spidev) { struct spi_master *master = spidev->master; struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); - unsigned int cs = spidev->chip_select; + unsigned int cs = spi_get_chipselect(spidev, 0); u32 gpocon;

/* GPIOs are used for CS */ - if (spidev->cs_gpiod) + if (spi_get_csgpiod(spidev, 0)) return 0;

dev_dbg(spi->dev, "using internal chipselect %u\n", cs); @@ -796,7 +796,7 @@ static void lantiq_ssc_handle_err(struct spi_master *master, static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable) { struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master); - unsigned int cs = spidev->chip_select; + unsigned int cs = spi_get_chipselect(spidev, 0); u32 fgpo;

if (!!(spidev->mode & SPI_CS_HIGH) == enable) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 701838b6f0c4..edd7430d4c05 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -325,7 +325,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) if (!spi_mem_internal_supports_op(mem, op)) return -ENOTSUPP;

- if (ctlr->mem_ops && ctlr->mem_ops->exec_op && !mem->spi->cs_gpiod) { + if (ctlr->mem_ops && ctlr->mem_ops->exec_op && !spi_get_csgpiod(mem->spi, 0)) { ret = spi_mem_access_start(mem); if (ret) return ret; @@ -808,7 +808,7 @@ int spi_mem_poll_status(struct spi_mem *mem, op->data.dir != SPI_MEM_DATA_IN) return -EINVAL;

- if (ctlr->mem_ops && ctlr->mem_ops->poll_status && !mem->spi->cs_gpiod) { + if (ctlr->mem_ops && ctlr->mem_ops->poll_status && !spi_get_csgpiod(mem->spi, 0)) { ret = spi_mem_access_start(mem); if (ret) return ret; diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index b9f812837cd6..141562c882f1 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -505,7 +505,7 @@ static int meson_spicc_prepare_message(struct spi_master *master, conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);

/* Select CS */ - conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select); + conf |= FIELD_PREP(SPICC_CS_MASK, spi_get_chipselect(spi, 0));

/* Default 8bit word */ conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1); diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index e6cf6ff08061..b59e8a0c5b97 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -247,8 +247,8 @@ static void mchp_corespi_set_cs(struct spi_device *spi, bool disable) struct mchp_corespi *corespi = spi_master_get_devdata(spi->master);

reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT); - reg &= ~BIT(spi->chip_select); - reg |= !disable << spi->chip_select; + reg &= ~BIT(spi_get_chipselect(spi, 0)); + reg |= !disable << spi_get_chipselect(spi, 0);

mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg); } @@ -265,7 +265,7 @@ static int mchp_corespi_setup(struct spi_device *spi) */ if (spi->mode & SPI_CS_HIGH) { reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT); - reg |= BIT(spi->chip_select); + reg |= BIT(spi_get_chipselect(spi, 0)); mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg); } return 0; diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c index 0b86f1804682..99aeef28a477 100644 --- a/drivers/spi/spi-mpc512x-psc.c +++ b/drivers/spi/spi-mpc512x-psc.c @@ -121,17 +121,17 @@ static void mpc512x_psc_spi_activate_cs(struct spi_device *spi) out_be32(psc_addr(mps, ccr), ccr); mps->bits_per_word = cs->bits_per_word;

- if (spi->cs_gpiod) { + if (spi_get_csgpiod(spi, 0)) { /* gpiolib will deal with the inversion */ - gpiod_set_value(spi->cs_gpiod, 1); + gpiod_set_value(spi_get_csgpiod(spi, 0), 1); } }

static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi) { - if (spi->cs_gpiod) { + if (spi_get_csgpiod(spi, 0)) { /* gpiolib will deal with the inversion */ - gpiod_set_value(spi->cs_gpiod, 0); + gpiod_set_value(spi_get_csgpiod(spi, 0), 0); } }

diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c index b652fb196622..ab7df5f64342 100644 --- a/drivers/spi/spi-mpc52xx.c +++ b/drivers/spi/spi-mpc52xx.c @@ -101,7 +101,7 @@ static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value) int cs;

if (ms->gpio_cs_count > 0) { - cs = ms->message->spi->chip_select; + cs = spi_get_chipselect(ms->message->spi, 0); gpiod_set_value(ms->gpio_cs[cs], value); } else { out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08); diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 9eab6c20dbc5..21c321f43766 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -421,7 +421,7 @@ static int mtk_spi_hw_init(struct spi_master *master,

/* pad select */ if (mdata->dev_comp->need_pad_sel) - writel(mdata->pad_sel[spi->chip_select], + writel(mdata->pad_sel[spi_get_chipselect(spi, 0)], mdata->base + SPI_PAD_SEL_REG);

/* tick delay */ @@ -735,9 +735,9 @@ static int mtk_spi_setup(struct spi_device *spi) if (!spi->controller_data) spi->controller_data = (void *)&mtk_default_chip_info;

- if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) + if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0)) /* CS de-asserted, gpiolib will handle inversion */ - gpiod_direction_output(spi->cs_gpiod, 0); + gpiod_direction_output(spi_get_csgpiod(spi, 0), 0);

return 0; } diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c index c4cc8e2f85e2..3e9d396b33bd 100644 --- a/drivers/spi/spi-mt7621.c +++ b/drivers/spi/spi-mt7621.c @@ -76,7 +76,7 @@ static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val) static void mt7621_spi_set_cs(struct spi_device *spi, int enable) { struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); - int cs = spi->chip_select; + int cs = spi_get_chipselect(spi, 0); u32 polar = 0; u32 master;

diff --git a/drivers/spi/spi-mux.c b/drivers/spi/spi-mux.c index 0709e987bd5a..fa8c1f740c70 100644 --- a/drivers/spi/spi-mux.c +++ b/drivers/spi/spi-mux.c @@ -51,22 +51,22 @@ static int spi_mux_select(struct spi_device *spi) struct spi_mux_priv *priv = spi_controller_get_devdata(spi->controller); int ret;

- ret = mux_control_select(priv->mux, spi->chip_select); + ret = mux_control_select(priv->mux, spi_get_chipselect(spi, 0)); if (ret) return ret;

- if (priv->current_cs == spi->chip_select) + if (priv->current_cs == spi_get_chipselect(spi, 0)) return 0;

dev_dbg(&priv->spi->dev, "setting up the mux for cs %d\n", - spi->chip_select); + spi_get_chipselect(spi, 0));

/* copy the child device's settings except for the cs */ priv->spi->max_speed_hz = spi->max_speed_hz; priv->spi->mode = spi->mode; priv->spi->bits_per_word = spi->bits_per_word;

- priv->current_cs = spi->chip_select; + priv->current_cs = spi_get_chipselect(spi, 0);

return 0; } diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 10727ea53043..00617fd4b2c3 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -306,8 +306,8 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) nio = 2;

return flags | HC_CFG_NIO(nio) | - HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) | - HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1); + HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) | + HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1); }

static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op, @@ -405,7 +405,7 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, len = min_t(size_t, len, mxic->linear.size); writel(len, mxic->regs + LRD_RANGE); writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) | - LMODE_SLV_ACT(desc->mem->spi->chip_select) | + LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) | LMODE_EN, mxic->regs + LRD_CTRL);

@@ -449,7 +449,7 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, len = min_t(size_t, len, mxic->linear.size); writel(len, mxic->regs + LWR_RANGE); writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) | - LMODE_SLV_ACT(desc->mem->spi->chip_select) | + LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) | LMODE_EN, mxic->regs + LWR_CTRL);

@@ -524,7 +524,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, writel(HC_EN_BIT, mxic->regs + HC_EN);

writel(mxic_spi_mem_prep_op_cfg(op, op->data.nbytes), - mxic->regs + SS_CTRL(mem->spi->chip_select)); + mxic->regs + SS_CTRL(spi_get_chipselect(mem->spi, 0)));

writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, mxic->regs + HC_CFG); diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c index 10fb31a5e409..963a53dd680b 100644 --- a/drivers/spi/spi-mxs.c +++ b/drivers/spi/spi-mxs.c @@ -369,7 +369,7 @@ static int mxs_spi_transfer_one(struct spi_master *master, /* Program CS register bits here, it will be used for all transfers. */ writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); - writel(mxs_spi_cs_to_reg(m->spi->chip_select), + writel(mxs_spi_cs_to_reg(spi_get_chipselect(m->spi, 0)), ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

list_for_each_entry(t, &m->transfers, transfer_list) { diff --git a/drivers/spi/spi-npcm-fiu.c b/drivers/spi/spi-npcm-fiu.c index 8d7698d167ef..eb353561509a 100644 --- a/drivers/spi/spi-npcm-fiu.c +++ b/drivers/spi/spi-npcm-fiu.c @@ -288,7 +288,7 @@ static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, { struct npcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->master); - struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; + struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)]; void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr + offs); u8 *buf_rx = buf; @@ -315,7 +315,7 @@ static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc, { struct npcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->master); - struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; + struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)]; void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr + offs); const u8 *buf_tx = buf; @@ -344,7 +344,7 @@ static int npcm_fiu_uma_read(struct spi_mem *mem,

regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, NPCM_FIU_UMA_CTS_DEV_NUM, - (mem->spi->chip_select << + (spi_get_chipselect(mem->spi, 0) << NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode); @@ -398,7 +398,7 @@ static int npcm_fiu_uma_write(struct spi_mem *mem,

regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, NPCM_FIU_UMA_CTS_DEV_NUM, - (mem->spi->chip_select << + (spi_get_chipselect(mem->spi, 0) << NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));

regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, @@ -451,7 +451,7 @@ static int npcm_fiu_manualwrite(struct spi_mem *mem,

regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, NPCM_FIU_UMA_CTS_DEV_NUM, - (mem->spi->chip_select << + (spi_get_chipselect(mem->spi, 0) << NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, NPCM_FIU_UMA_CTS_SW_CS, 0); @@ -545,7 +545,7 @@ static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct npcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->master); - struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select]; + struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(mem->spi, 0)]; int ret = 0; u8 *buf;

@@ -605,7 +605,7 @@ static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) { struct npcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->master); - struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; + struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)]; struct regmap *gcr_regmap;

if (!fiu->res_mem) { @@ -624,7 +624,7 @@ static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) chip->flash_region_mapped_ptr = devm_ioremap(fiu->dev, (fiu->res_mem->start + (fiu->info->max_map_size * - desc->mem->spi->chip_select)), + spi_get_chipselect(desc->mem->spi, 0))), (u32)desc->info.length); if (!chip->flash_region_mapped_ptr) { dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n"); @@ -669,9 +669,9 @@ static int npcm_fiu_setup(struct spi_device *spi) struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl); struct npcm_fiu_chip *chip;

- chip = &fiu->chip[spi->chip_select]; + chip = &fiu->chip[spi_get_chipselect(spi, 0)]; chip->fiu = fiu; - chip->chipselect = spi->chip_select; + chip->chipselect = spi_get_chipselect(spi, 0); chip->clkrate = spi->max_speed_hz;

fiu->clkrate = clk_get_rate(fiu->clk); diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 71be1ec3fbde..76168cc1e00d 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -663,7 +663,7 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) * Return, if previously selected slave device is same as current * requested slave device. */ - if (f->selected == spi->chip_select) + if (f->selected == spi_get_chipselect(spi, 0)) return;

/* Reset FLSHxxCR0 registers */ @@ -676,9 +676,9 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);

fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + - 4 * spi->chip_select); + 4 * spi_get_chipselect(spi, 0));

- dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select); + dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi_get_chipselect(spi, 0));

nxp_fspi_clk_disable_unprep(f);

@@ -690,7 +690,7 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) if (ret) return;

- f->selected = spi->chip_select; + f->selected = spi_get_chipselect(spi, 0); }

static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) @@ -1055,7 +1055,7 @@ static const char *nxp_fspi_get_name(struct spi_mem *mem)

name = devm_kasprintf(dev, GFP_KERNEL, "%s-%d", dev_name(f->dev), - mem->spi->chip_select); + spi_get_chipselect(mem->spi, 0));

if (!name) { dev_err(dev, "failed to get memory for custom flash name\n"); diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c index 6da77de19e2b..902d2e0c1f2f 100644 --- a/drivers/spi/spi-omap-uwire.c +++ b/drivers/spi/spi-omap-uwire.c @@ -179,7 +179,7 @@ static void uwire_chipselect(struct spi_device *spi, int value)

w = uwire_read_reg(UWIRE_CSR); old_cs = (w >> 10) & 0x03; - if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) { + if (value == BITBANG_CS_INACTIVE || old_cs != spi_get_chipselect(spi, 0)) { /* Deselect this CS, or the previous CS */ w &= ~CS_CMD; uwire_write_reg(UWIRE_CSR, w); @@ -193,7 +193,7 @@ static void uwire_chipselect(struct spi_device *spi, int value) else uwire_write_reg(UWIRE_SR4, 0);

- w = spi->chip_select << 10; + w = spi_get_chipselect(spi, 0) << 10; w |= CS_CMD; uwire_write_reg(UWIRE_CSR, w); } @@ -210,7 +210,7 @@ static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t) if (!t->tx_buf && !t->rx_buf) return 0;

- w = spi->chip_select << 10; + w = spi_get_chipselect(spi, 0) << 10; w |= CS_CMD;

if (t->tx_buf) { @@ -408,7 +408,7 @@ static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t) rate /= 8; break; } - omap_uwire_configure_mode(spi->chip_select, flags); + omap_uwire_configure_mode(spi_get_chipselect(spi, 0), flags); pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n", __func__, flags, clk_get_rate(uwire->ck) / 1000, diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c index ce3cdd540420..1a967930f4e5 100644 --- a/drivers/spi/spi-omap2-mcspi.c +++ b/drivers/spi/spi-omap2-mcspi.c @@ -379,7 +379,7 @@ static void omap2_mcspi_rx_callback(void *data) { struct spi_device *spi = data; struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); - struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; + struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];

/* We must disable the DMA RX request */ omap2_mcspi_set_dma_req(spi, 1, 0); @@ -391,7 +391,7 @@ static void omap2_mcspi_tx_callback(void *data) { struct spi_device *spi = data; struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); - struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; + struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];

/* We must disable the DMA TX request */ omap2_mcspi_set_dma_req(spi, 0, 0); @@ -408,7 +408,7 @@ static void omap2_mcspi_tx_dma(struct spi_device *spi, struct dma_async_tx_descriptor *tx;

mcspi = spi_master_get_devdata(spi->master); - mcspi_dma = &mcspi->dma_channels[spi->chip_select]; + mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];

dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);

@@ -446,7 +446,7 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, struct dma_async_tx_descriptor *tx;

mcspi = spi_master_get_devdata(spi->master); - mcspi_dma = &mcspi->dma_channels[spi->chip_select]; + mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; count = xfer->len;

/* @@ -591,7 +591,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) int wait_res;

mcspi = spi_master_get_devdata(spi->master); - mcspi_dma = &mcspi->dma_channels[spi->chip_select]; + mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];

if (cs->word_len <= 8) { width = DMA_SLAVE_BUSWIDTH_1_BYTE; @@ -1062,8 +1062,8 @@ static int omap2_mcspi_setup(struct spi_device *spi) cs = kzalloc(sizeof(*cs), GFP_KERNEL); if (!cs) return -ENOMEM; - cs->base = mcspi->base + spi->chip_select * 0x14; - cs->phys = mcspi->phys + spi->chip_select * 0x14; + cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14; + cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14; cs->mode = 0; cs->chconf0 = 0; cs->chctrl0 = 0; @@ -1142,7 +1142,7 @@ static int omap2_mcspi_transfer_one(struct spi_master *master, u32 chconf;

mcspi = spi_master_get_devdata(master); - mcspi_dma = mcspi->dma_channels + spi->chip_select; + mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0); cs = spi->controller_state; cd = spi->controller_data;

@@ -1158,7 +1158,7 @@ static int omap2_mcspi_transfer_one(struct spi_master *master,

omap2_mcspi_set_enable(spi, 0);

- if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);

if (par_override || @@ -1247,7 +1247,7 @@ static int omap2_mcspi_transfer_one(struct spi_master *master,

omap2_mcspi_set_enable(spi, 0);

- if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));

if (mcspi->fifo_depth > 0 && t) @@ -1289,7 +1289,7 @@ static bool omap2_mcspi_can_dma(struct spi_master *master, { struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); struct omap2_mcspi_dma *mcspi_dma = - &mcspi->dma_channels[spi->chip_select]; + &mcspi->dma_channels[spi_get_chipselect(spi, 0)];

if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) return false; @@ -1307,7 +1307,7 @@ static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi) { struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); struct omap2_mcspi_dma *mcspi_dma = - &mcspi->dma_channels[spi->chip_select]; + &mcspi->dma_channels[spi_get_chipselect(spi, 0)];

if (mcspi->max_xfer_len && mcspi_dma->dma_rx) return mcspi->max_xfer_len; diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c index e79d1fe0bca4..bb244b596143 100644 --- a/drivers/spi/spi-orion.c +++ b/drivers/spi/spi-orion.c @@ -346,7 +346,7 @@ static void orion_spi_set_cs(struct spi_device *spi, bool enable) * as it is handled by a GPIO, but that doesn't matter. What we need * is to deassert the old chip select and assert some other chip select. */ - val |= ORION_SPI_CS(spi->chip_select); + val |= ORION_SPI_CS(spi_get_chipselect(spi, 0));

/* * Chip select logic is inverted from spi_set_cs(). For lines using a @@ -470,7 +470,7 @@ orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) unsigned int count; int word_len; struct orion_spi *orion_spi; - int cs = spi->chip_select; + int cs = spi_get_chipselect(spi, 0); void __iomem *vaddr;

word_len = spi->bits_per_word; diff --git a/drivers/spi/spi-pci1xxxx.c b/drivers/spi/spi-pci1xxxx.c index a31c3b612a43..1c5731641a04 100644 --- a/drivers/spi/spi-pci1xxxx.c +++ b/drivers/spi/spi-pci1xxxx.c @@ -116,11 +116,11 @@ static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable) regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); if (enable) { regval &= ~SPI_MST_CTL_DEVSEL_MASK; - regval |= (spi->chip_select << 25); + regval |= (spi_get_chipselect(spi, 0) << 25); writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); } else { - regval &= ~(spi->chip_select << 25); + regval &= ~(spi_get_chipselect(spi, 0) << 25); writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));

diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c index 4c8493f34fca..51dfb49523f3 100644 --- a/drivers/spi/spi-pic32-sqi.c +++ b/drivers/spi/spi-pic32-sqi.c @@ -267,7 +267,7 @@ static int pic32_sqi_one_transfer(struct pic32_sqi *sqi, u32 nbits;

/* Device selection */ - bd_ctrl = spi->chip_select << BD_DEVSEL_SHIFT; + bd_ctrl = spi_get_chipselect(spi, 0) << BD_DEVSEL_SHIFT;

/* half-duplex: select transfer buffer, direction and lane */ if (xfer->rx_buf) { diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c index 5a64ad0c94fe..8a02073a354d 100644 --- a/drivers/spi/spi-pic32.c +++ b/drivers/spi/spi-pic32.c @@ -591,7 +591,7 @@ static int pic32_spi_setup(struct spi_device *spi) * unreliable/erroneous SPI transactions. * To avoid that we will always handle /CS by toggling GPIO. */ - if (!spi->cs_gpiod) + if (!spi_get_csgpiod(spi, 0)) return -EINVAL;

return 0; @@ -600,7 +600,7 @@ static int pic32_spi_setup(struct spi_device *spi) static void pic32_spi_cleanup(struct spi_device *spi) { /* de-activate cs-gpio, gpiolib will handle inversion */ - gpiod_direction_output(spi->cs_gpiod, 0); + gpiod_direction_output(spi_get_csgpiod(spi, 0), 0); }

static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev) diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index a17ff839117f..982407bc5d9f 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -1587,9 +1587,9 @@ static int pl022_transfer_one_message(struct spi_master *master,

/* Setup the SPI using the per chip configuration */ pl022->cur_chip = spi_get_ctldata(msg->spi); - pl022->cur_cs = msg->spi->chip_select; + pl022->cur_cs = spi_get_chipselect(msg->spi, 0); /* This is always available but may be set to -ENOENT */ - pl022->cur_gpiod = msg->spi->cs_gpiod; + pl022->cur_gpiod = spi_get_csgpiod(msg->spi, 0);

restore_state(pl022); flush(pl022); diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index a75ba2993f3c..d04e8cb987e9 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -368,7 +368,7 @@ static void lpss_ssp_select_cs(struct spi_device *spi,

value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);

- cs = spi->chip_select; + cs = spi_get_chipselect(spi, 0); cs <<= config->cs_sel_shift; if (cs != (value & config->cs_sel_mask)) { /* @@ -429,7 +429,7 @@ static void cs_assert(struct spi_device *spi) spi_controller_get_devdata(spi->controller);

if (drv_data->ssp_type == CE4100_SSP) { - pxa2xx_spi_write(drv_data, SSSR, spi->chip_select); + pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0)); return; }

@@ -1217,7 +1217,7 @@ static int setup(struct spi_device *spi) return -ENOMEM;

if (drv_data->ssp_type == CE4100_SSP) { - if (spi->chip_select > 4) { + if (spi_get_chipselect(spi, 0) > 4) { dev_err(&spi->dev, "failed setup: cs number must not be > 4.\n"); kfree(chip); diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index 15c4e21cd562..aa91a6c9ab55 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -311,7 +311,7 @@ static int qcom_qspi_prepare_message(struct spi_master *master,

mstr_cfg = readl(ctrl->base + MSTR_CONFIG); mstr_cfg &= ~CHIP_SELECT_NUM; - if (message->spi->chip_select) + if (spi_get_chipselect(message->spi, 0)) mstr_cfg |= CHIP_SELECT_NUM;

mstr_cfg |= FB_CLK_EN | PIN_WPN | PIN_HOLDN | SBL_EN | FULL_CYCLE_MODE; diff --git a/drivers/spi/spi-rb4xx.c b/drivers/spi/spi-rb4xx.c index e312b30b733b..5073736d3d1f 100644 --- a/drivers/spi/spi-rb4xx.c +++ b/drivers/spi/spi-rb4xx.c @@ -107,7 +107,7 @@ static int rb4xx_transfer_one(struct spi_master *master, * command set was designed to almost not clash with that of the * boot flash. */ - if (spi->chip_select == 2) + if (spi_get_chipselect(spi, 0) == 2) /* MMC */ spi_ioc = AR71XX_SPI_IOC_CS0; else diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c index 80e1ee110d31..4fabd2e0439f 100644 --- a/drivers/spi/spi-rockchip-sfc.c +++ b/drivers/spi/spi-rockchip-sfc.c @@ -346,7 +346,7 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,

/* set the Controller */ ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; - cmd |= mem->spi->chip_select << SFC_CMD_CS_SHIFT; + cmd |= spi_get_chipselect(mem->spi, 0) << SFC_CMD_CS_SHIFT;

dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", op->addr.nbytes, op->addr.buswidth, diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index a66fff0ee20e..143ede958ac1 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -246,28 +246,30 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;

/* Return immediately for no-op */ - if (cs_asserted == rs->cs_asserted[spi->chip_select]) + if (cs_asserted == rs->cs_asserted[spi_get_chipselect(spi, 0)]) return;

if (cs_asserted) { /* Keep things powered as long as CS is asserted */ pm_runtime_get_sync(rs->dev);

- if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); else - ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select)); + ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, + BIT(spi_get_chipselect(spi, 0))); } else { - if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); else - ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select)); + ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, + BIT(spi_get_chipselect(spi, 0)));

/* Drop reference from when we first asserted CS */ pm_runtime_put(rs->dev); }

- rs->cs_asserted[spi->chip_select] = cs_asserted; + rs->cs_asserted[spi_get_chipselect(spi, 0)] = cs_asserted; }

static void rockchip_spi_handle_err(struct spi_controller *ctlr, @@ -541,7 +543,7 @@ static int rockchip_spi_config(struct rockchip_spi *rs, if (spi->mode & SPI_LSB_FIRST) cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; if (spi->mode & SPI_CS_HIGH) - cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET; + cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET;

if (xfer->rx_buf && xfer->tx_buf) cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; @@ -724,7 +726,7 @@ static int rockchip_spi_setup(struct spi_device *spi) struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller); u32 cr0;

- if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) { + if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) { dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); return -EINVAL; } @@ -735,10 +737,10 @@ static int rockchip_spi_setup(struct spi_device *spi)

cr0 &= ~(0x3 << CR0_SCPH_OFFSET); cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET); - if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1) - cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET; - else if (spi->chip_select <= 1) - cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET); + if (spi->mode & SPI_CS_HIGH && spi_get_chipselect(spi, 0) <= 1) + cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET; + else if (spi_get_chipselect(spi, 0) <= 1) + cr0 &= ~(BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET);

writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);

diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index f494c86bafea..f50a39efaf96 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -950,7 +950,7 @@ static int rspi_setup(struct spi_device *spi) struct rspi_data *rspi = spi_controller_get_devdata(spi->controller); u8 sslp;

- if (spi->cs_gpiod) + if (spi_get_csgpiod(spi, 0)) return 0;

pm_runtime_get_sync(&rspi->pdev->dev); @@ -958,9 +958,9 @@ static int rspi_setup(struct spi_device *spi)

sslp = rspi_read8(rspi, RSPI_SSLP); if (spi->mode & SPI_CS_HIGH) - sslp |= SSLP_SSLP(spi->chip_select); + sslp |= SSLP_SSLP(spi_get_chipselect(spi, 0)); else - sslp &= ~SSLP_SSLP(spi->chip_select); + sslp &= ~SSLP_SSLP(spi_get_chipselect(spi, 0)); rspi_write8(rspi, sslp, RSPI_SSLP);

spin_unlock_irq(&rspi->lock); @@ -1001,8 +1001,8 @@ static int rspi_prepare_message(struct spi_controller *ctlr, rspi->spcmd |= SPCMD_LSBF;

/* Configure slave signal to assert */ - rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs - : spi->chip_select); + rspi->spcmd |= SPCMD_SSLA(spi_get_csgpiod(spi, 0) ? rspi->ctlr->unused_native_cs + : spi_get_chipselect(spi, 0));

/* CMOS output mode and MOSI signal from previous transfer */ rspi->sppcr = 0; diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index cc69f8ffdbdc..7ac17f0d18a9 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -891,7 +891,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi)

/* NULL is fine, we just avoid using the FB delay (=0) */ if (IS_ERR(cs)) { - dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); + dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0)); return -ENODEV; }

diff --git a/drivers/spi/spi-sc18is602.c b/drivers/spi/spi-sc18is602.c index 983b3621bc2a..a12adc68731b 100644 --- a/drivers/spi/spi-sc18is602.c +++ b/drivers/spi/spi-sc18is602.c @@ -70,7 +70,7 @@ static int sc18is602_txrx(struct sc18is602 *hw, struct spi_message *msg,

if (hw->tlen == 0) { /* First byte (I2C command) is chip select */ - hw->buffer[0] = 1 << msg->spi->chip_select; + hw->buffer[0] = 1 << spi_get_chipselect(msg->spi, 0); hw->tlen = 1; hw->rindex = 0; } @@ -229,7 +229,7 @@ static int sc18is602_setup(struct spi_device *spi) struct sc18is602 *hw = spi_master_get_devdata(spi->master);

/* SC18IS602 does not support CS2 */ - if (hw->id == sc18is602 && spi->chip_select == 2) + if (hw->id == sc18is602 && (spi_get_chipselect(spi, 0) == 2)) return -ENXIO;

return 0; diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index d828a3b370b8..50498c4eb661 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -554,7 +554,7 @@ static int sh_msiof_spi_setup(struct spi_device *spi) spi_controller_get_devdata(spi->controller); u32 clr, set, tmp;

- if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr)) + if (spi_get_csgpiod(spi, 0) || spi_controller_is_slave(p->ctlr)) return 0;

if (p->native_cs_inited && @@ -587,11 +587,11 @@ static int sh_msiof_prepare_message(struct spi_controller *ctlr, u32 ss, cs_high;

/* Configure pins before asserting CS */ - if (spi->cs_gpiod) { + if (spi_get_csgpiod((struct spi_device *)spi, 0)) { ss = ctlr->unused_native_cs; cs_high = p->native_cs_high; } else { - ss = spi->chip_select; + ss = spi_get_chipselect((struct spi_device *)spi, 0); cs_high = !!(spi->mode & SPI_CS_HIGH); } sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL), diff --git a/drivers/spi/spi-sh-sci.c b/drivers/spi/spi-sh-sci.c index 0fdfec2de47a..92ca3f2d61ba 100644 --- a/drivers/spi/spi-sh-sci.c +++ b/drivers/spi/spi-sh-sci.c @@ -108,7 +108,7 @@ static void sh_sci_spi_chipselect(struct spi_device *dev, int value) struct sh_sci_spi *sp = spi_master_get_devdata(dev->master);

if (sp->info->chip_select) - (sp->info->chip_select)(sp->info, dev->chip_select, value); + (sp->info->chip_select)(sp->info, spi_get_chipselect(dev, 0), value); }

static int sh_sci_spi_probe(struct platform_device *dev) diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 055de44e0d22..dae9e097c333 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -135,13 +135,13 @@ sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg)

/* Update the chip select polarity */ if (device->mode & SPI_CS_HIGH) - spi->cs_inactive &= ~BIT(device->chip_select); + spi->cs_inactive &= ~BIT(spi_get_chipselect(device, 0)); else - spi->cs_inactive |= BIT(device->chip_select); + spi->cs_inactive |= BIT(spi_get_chipselect(device, 0)); sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);

/* Select the correct device */ - sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select); + sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, spi_get_chipselect(device, 0));

/* Set clock mode */ sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE, diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c index 644ae34f623b..d64100f88181 100644 --- a/drivers/spi/spi-sn-f-ospi.c +++ b/drivers/spi/spi-sn-f-ospi.c @@ -267,7 +267,7 @@ static void f_ospi_config_indir_protocol(struct f_ospi *ospi, int unit;

/* Set one chip select */ - writel(BIT(spi->chip_select), ospi->base + OSPI_SSEL); + writel(BIT(spi_get_chipselect(spi, 0)), ospi->base + OSPI_SSEL);

mode = f_ospi_get_mode(ospi, op->cmd.buswidth, 1); prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode); diff --git a/drivers/spi/spi-st-ssc4.c b/drivers/spi/spi-st-ssc4.c index 9141f19c7f8e..7fcff9c539e2 100644 --- a/drivers/spi/spi-st-ssc4.c +++ b/drivers/spi/spi-st-ssc4.c @@ -183,7 +183,7 @@ static int spi_st_setup(struct spi_device *spi) return -EINVAL; }

- if (!spi->cs_gpiod) { + if (!spi_get_csgpiod(spi, 0)) { dev_err(&spi->dev, "no valid gpio assigned\n"); return -EINVAL; } diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index 29125af0afdb..2b6804aa6901 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -359,7 +359,7 @@ static int stm32_qspi_get_mode(u8 buswidth) static int stm32_qspi_send(struct spi_device *spi, const struct spi_mem_op *op) { struct stm32_qspi *qspi = spi_controller_get_devdata(spi->master); - struct stm32_qspi_flash *flash = &qspi->flash[spi->chip_select]; + struct stm32_qspi_flash *flash = &qspi->flash[spi_get_chipselect(spi, 0)]; u32 ccr, cr; int timeout, err = 0, err_poll_status = 0;

@@ -564,7 +564,7 @@ static int stm32_qspi_transfer_one_message(struct spi_controller *ctrl, struct spi_mem_op op; int ret = 0;

- if (!spi->cs_gpiod) + if (!spi_get_csgpiod(spi, 0)) return -EOPNOTSUPP;

ret = pm_runtime_resume_and_get(qspi->dev); @@ -573,7 +573,7 @@ static int stm32_qspi_transfer_one_message(struct spi_controller *ctrl,

mutex_lock(&qspi->lock);

- gpiod_set_value_cansleep(spi->cs_gpiod, true); + gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), true);

list_for_each_entry(transfer, &msg->transfers, transfer_list) { u8 dummy_bytes = 0; @@ -626,7 +626,7 @@ static int stm32_qspi_transfer_one_message(struct spi_controller *ctrl, }

end_of_transfer: - gpiod_set_value_cansleep(spi->cs_gpiod, false); + gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), false);

mutex_unlock(&qspi->lock);

@@ -669,8 +669,8 @@ static int stm32_qspi_setup(struct spi_device *spi)

presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;

- flash = &qspi->flash[spi->chip_select]; - flash->cs = spi->chip_select; + flash = &qspi->flash[spi_get_chipselect(spi, 0)]; + flash->cs = spi_get_chipselect(spi, 0); flash->presc = presc;

mutex_lock(&qspi->lock); diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c index 994d0fb50e68..b8947265d329 100644 --- a/drivers/spi/spi-sun4i.c +++ b/drivers/spi/spi-sun4i.c @@ -167,7 +167,7 @@ static void sun4i_spi_set_cs(struct spi_device *spi, bool enable) reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);

reg &= ~SUN4I_CTL_CS_MASK; - reg |= SUN4I_CTL_CS(spi->chip_select); + reg |= SUN4I_CTL_CS(spi_get_chipselect(spi, 0));

/* We want to control the chip select manually */ reg |= SUN4I_CTL_CS_MANUAL; diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 43c29afea6bb..7532c85a352c 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -174,7 +174,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)

reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); reg &= ~SUN6I_TFR_CTL_CS_MASK; - reg |= SUN6I_TFR_CTL_CS(spi->chip_select); + reg |= SUN6I_TFR_CTL_CS(spi_get_chipselect(spi, 0));

if (enable) reg |= SUN6I_TFR_CTL_CS_LEVEL; diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 3a92f722a6c5..aeaf7db022f0 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -250,7 +250,7 @@ static int synquacer_spi_config(struct spi_master *master, }

mode = spi->mode; - cs = spi->chip_select; + cs = spi_get_chipselect(spi, 0); speed = xfer->speed_hz; bpw = xfer->bits_per_word;

@@ -344,7 +344,7 @@ static int synquacer_spi_config(struct spi_master *master, sspi->bpw = bpw; sspi->mode = mode; sspi->speed = speed; - sspi->cs = spi->chip_select; + sspi->cs = spi_get_chipselect(spi, 0); sspi->bus_width = bus_width;

return 0; @@ -488,7 +488,7 @@ static void synquacer_spi_set_cs(struct spi_device *spi, bool enable) val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); val &= ~(SYNQUACER_HSSPI_DMPSEL_CS_MASK << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT); - val |= spi->chip_select << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT; + val |= spi_get_chipselect(spi, 0) << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT;

if (!enable) val |= SYNQUACER_HSSPI_DMSTOP_STOP; diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index b6bee922a92c..9e7d762d0ee6 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -747,7 +747,7 @@ static int tegra_spi_set_hw_cs_timing(struct spi_device *spi) if (setup_dly && hold_dly) { setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1); spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1, - spi->chip_select, + spi_get_chipselect(spi, 0), setup_hold); if (tspi->spi_cs_timing1 != spi_cs_timing) { tspi->spi_cs_timing1 = spi_cs_timing; @@ -760,9 +760,9 @@ static int tegra_spi_set_hw_cs_timing(struct spi_device *spi) inactive_cycles--; cs_state = inactive_cycles ? 0 : 1; spi_cs_timing = tspi->spi_cs_timing2; - SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select, + SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0), cs_state); - SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select, + SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0), inactive_cycles); if (tspi->spi_cs_timing2 != spi_cs_timing) { tspi->spi_cs_timing2 = spi_cs_timing; @@ -831,8 +831,8 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, tegra_spi_writel(tspi, command1, SPI_COMMAND1);

/* GPIO based chip select control */ - if (spi->cs_gpiod) - gpiod_set_value(spi->cs_gpiod, 1); + if (spi_get_csgpiod(spi, 0)) + gpiod_set_value(spi_get_csgpiod(spi, 0), 1);

if (is_single_xfer && !(t->cs_change)) { tspi->use_hw_based_cs = true; @@ -846,7 +846,7 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, command1 &= ~SPI_CS_SW_VAL; }

- if (tspi->last_used_cs != spi->chip_select) { + if (tspi->last_used_cs != spi_get_chipselect(spi, 0)) { if (cdata && cdata->tx_clk_tap_delay) tx_tap = cdata->tx_clk_tap_delay; if (cdata && cdata->rx_clk_tap_delay) @@ -855,7 +855,7 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, SPI_RX_TAP_DELAY(rx_tap); if (command2 != tspi->def_command2_reg) tegra_spi_writel(tspi, command2, SPI_COMMAND2); - tspi->last_used_cs = spi->chip_select; + tspi->last_used_cs = spi_get_chipselect(spi, 0); }

} else { @@ -896,7 +896,7 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi, command1 |= SPI_TX_EN; tspi->cur_direction |= DATA_DIR_TX; } - command1 |= SPI_CS_SEL(spi->chip_select); + command1 |= SPI_CS_SEL(spi_get_chipselect(spi, 0)); tegra_spi_writel(tspi, command1, SPI_COMMAND1); tspi->command1_reg = command1;

@@ -980,14 +980,14 @@ static int tegra_spi_setup(struct spi_device *spi)

spin_lock_irqsave(&tspi->lock, flags); /* GPIO based chip select control */ - if (spi->cs_gpiod) - gpiod_set_value(spi->cs_gpiod, 0); + if (spi_get_csgpiod(spi, 0)) + gpiod_set_value(spi_get_csgpiod(spi, 0), 0);

val = tspi->def_command1_reg; if (spi->mode & SPI_CS_HIGH) - val &= ~SPI_CS_POL_INACTIVE(spi->chip_select); + val &= ~SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0)); else - val |= SPI_CS_POL_INACTIVE(spi->chip_select); + val |= SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0)); tspi->def_command1_reg = val; tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); spin_unlock_irqrestore(&tspi->lock, flags); @@ -1002,8 +1002,8 @@ static void tegra_spi_transfer_end(struct spi_device *spi) int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;

/* GPIO based chip select control */ - if (spi->cs_gpiod) - gpiod_set_value(spi->cs_gpiod, 0); + if (spi_get_csgpiod(spi, 0)) + gpiod_set_value(spi_get_csgpiod(spi, 0), 0);

if (!tspi->use_hw_based_cs) { if (cs_val) diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c index ed82530ea64b..4286310628a2 100644 --- a/drivers/spi/spi-tegra20-sflash.c +++ b/drivers/spi/spi-tegra20-sflash.c @@ -280,7 +280,7 @@ static int tegra_sflash_start_transfer_one(struct spi_device *spi, command |= SPI_ACTIVE_SCLK_DRIVE_HIGH; else command |= SPI_ACTIVE_SCLK_DRIVE_LOW; - command |= SPI_CS0_EN << spi->chip_select; + command |= SPI_CS0_EN << spi_get_chipselect(spi, 0); } else { command = tsd->command_reg; command &= ~SPI_BIT_LENGTH(~0); diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index ac7933bc03e2..c2915f7672cc 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c @@ -758,9 +758,9 @@ static int tegra_slink_setup(struct spi_device *spi) spin_lock_irqsave(&tspi->lock, flags); val = tspi->def_command_reg; if (spi->mode & SPI_CS_HIGH) - val |= cs_pol_bit[spi->chip_select]; + val |= cs_pol_bit[spi_get_chipselect(spi, 0)]; else - val &= ~cs_pol_bit[spi->chip_select]; + val &= ~cs_pol_bit[spi_get_chipselect(spi, 0)]; tspi->def_command_reg = val; tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); spin_unlock_irqrestore(&tspi->lock, flags); @@ -781,7 +781,7 @@ static int tegra_slink_prepare_message(struct spi_master *master, tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;

tspi->command2_reg = tspi->def_command2_reg; - tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select); + tspi->command2_reg |= SLINK_SS_EN_CS(spi_get_chipselect(spi, 0));

tspi->command_reg &= ~SLINK_MODES; if (spi->mode & SPI_CPHA) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index fd0d532364e2..325b4427491c 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -829,7 +829,7 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran tegra_qspi_mask_clear_irq(tqspi);

command1 = tqspi->def_command1_reg; - command1 |= QSPI_CS_SEL(spi->chip_select); + command1 |= QSPI_CS_SEL(spi_get_chipselect(spi, 0)); command1 |= QSPI_BIT_LENGTH(bits_per_word - 1);

command1 &= ~QSPI_CONTROL_MODE_MASK; @@ -960,11 +960,11 @@ static int tegra_qspi_setup(struct spi_device *spi)

/* keep default cs state to inactive */ val = tqspi->def_command1_reg; - val |= QSPI_CS_SEL(spi->chip_select); + val |= QSPI_CS_SEL(spi_get_chipselect(spi, 0)); if (spi->mode & SPI_CS_HIGH) - val &= ~QSPI_CS_POL_INACTIVE(spi->chip_select); + val &= ~QSPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0)); else - val |= QSPI_CS_POL_INACTIVE(spi->chip_select); + val |= QSPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));

tqspi->def_command1_reg = val; tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 60086869bcae..5914335ff63d 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -533,10 +533,10 @@ static void ti_qspi_enable_memory_map(struct spi_device *spi) if (qspi->ctrl_base) { regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, MEM_CS_MASK, - MEM_CS_EN(spi->chip_select)); + MEM_CS_EN(spi_get_chipselect(spi, 0))); } qspi->mmap_enabled = true; - qspi->current_cs = spi->chip_select; + qspi->current_cs = spi_get_chipselect(spi, 0); }

static void ti_qspi_disable_memory_map(struct spi_device *spi) @@ -572,7 +572,7 @@ static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode, memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT | dummy_bytes << QSPI_SETUP_DUMMY_SHIFT); ti_qspi_write(qspi, memval, - QSPI_SPI_SETUP_REG(spi->chip_select)); + QSPI_SPI_SETUP_REG(spi_get_chipselect(spi, 0))); }

static int ti_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) @@ -623,7 +623,7 @@ static int ti_qspi_exec_mem_op(struct spi_mem *mem,

mutex_lock(&qspi->list_lock);

- if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select) { + if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) { ti_qspi_setup_clk(qspi, mem->spi->max_speed_hz); ti_qspi_enable_memory_map(mem->spi); } @@ -673,11 +673,11 @@ static int ti_qspi_start_transfer_one(struct spi_master *master, qspi->dc = 0;

if (spi->mode & SPI_CPHA) - qspi->dc |= QSPI_CKPHA(spi->chip_select); + qspi->dc |= QSPI_CKPHA(spi_get_chipselect(spi, 0)); if (spi->mode & SPI_CPOL) - qspi->dc |= QSPI_CKPOL(spi->chip_select); + qspi->dc |= QSPI_CKPOL(spi_get_chipselect(spi, 0)); if (spi->mode & SPI_CS_HIGH) - qspi->dc |= QSPI_CSPOL(spi->chip_select); + qspi->dc |= QSPI_CSPOL(spi_get_chipselect(spi, 0));

frame_len_words = 0; list_for_each_entry(t, &m->transfers, transfer_list) @@ -686,7 +686,7 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,

/* setup command reg */ qspi->cmd = 0; - qspi->cmd |= QSPI_EN_CS(spi->chip_select); + qspi->cmd |= QSPI_EN_CS(spi_get_chipselect(spi, 0)); qspi->cmd |= QSPI_FLEN(frame_len_words);

ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c index 1679a0ba3d62..af5846cfe5e9 100644 --- a/drivers/spi/spi-topcliff-pch.c +++ b/drivers/spi/spi-topcliff-pch.c @@ -499,7 +499,7 @@ static inline void pch_spi_select_chip(struct pch_spi_data *data, struct spi_device *pspi) { if (data->current_chip != NULL) { - if (pspi->chip_select != data->n_curnt_chip) { + if (spi_get_chipselect(pspi, 0) != data->n_curnt_chip) { dev_dbg(&pspi->dev, "%s : different slave\n", __func__); data->current_chip = NULL; } @@ -507,7 +507,7 @@ static inline void pch_spi_select_chip(struct pch_spi_data *data,

data->current_chip = pspi;

- data->n_curnt_chip = data->current_chip->chip_select; + data->n_curnt_chip = spi_get_chipselect(data->current_chip, 0);

dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__); pch_spi_setup_transfer(pspi); diff --git a/drivers/spi/spi-wpcm-fiu.c b/drivers/spi/spi-wpcm-fiu.c index ab33710d50ac..f15312fdcdaf 100644 --- a/drivers/spi/spi-wpcm-fiu.c +++ b/drivers/spi/spi-wpcm-fiu.c @@ -158,7 +158,7 @@ static int wpcm_fiu_normal_exec(struct spi_mem *mem, const struct spi_mem_op *op if (op->data.dir == SPI_MEM_DATA_OUT) wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes);

- ret = wpcm_fiu_do_uma(fiu, mem->spi->chip_select, op->addr.nbytes == 3, + ret = wpcm_fiu_do_uma(fiu, spi_get_chipselect(mem->spi, 0), op->addr.nbytes == 3, op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes);

if (op->data.dir == SPI_MEM_DATA_IN) @@ -196,7 +196,7 @@ static bool wpcm_fiu_4ba_match(const struct spi_mem_op *op) static int wpcm_fiu_4ba_exec(struct spi_mem *mem, const struct spi_mem_op *op) { struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); - int cs = mem->spi->chip_select; + int cs = spi_get_chipselect(mem->spi, 0);

wpcm_fiu_ects_assert(fiu, cs);

@@ -241,7 +241,7 @@ static bool wpcm_fiu_rdid_match(const struct spi_mem_op *op) static int wpcm_fiu_rdid_exec(struct spi_mem *mem, const struct spi_mem_op *op) { struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); - int cs = mem->spi->chip_select; + int cs = spi_get_chipselect(mem->spi, 0);

/* First transfer */ wpcm_fiu_set_opcode(fiu, op->cmd.opcode); @@ -278,7 +278,7 @@ static bool wpcm_fiu_dummy_match(const struct spi_mem_op *op) static int wpcm_fiu_dummy_exec(struct spi_mem *mem, const struct spi_mem_op *op) { struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); - int cs = mem->spi->chip_select; + int cs = spi_get_chipselect(mem->spi, 0);

wpcm_fiu_ects_assert(fiu, cs);

@@ -376,7 +376,7 @@ static int wpcm_fiu_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) { struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller); - int cs = desc->mem->spi->chip_select; + int cs = spi_get_chipselect(desc->mem->spi, 0);

if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN) return -ENOTSUPP; @@ -400,7 +400,7 @@ static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) static ssize_t wpcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) { struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller); - int cs = desc->mem->spi->chip_select; + int cs = spi_get_chipselect(desc->mem->spi, 0);

if (offs >= MAX_MEMORY_SIZE_PER_CS) return -ENOTSUPP; diff --git a/drivers/spi/spi-xcomm.c b/drivers/spi/spi-xcomm.c index 8628241ec99e..5d23411f2a3e 100644 --- a/drivers/spi/spi-xcomm.c +++ b/drivers/spi/spi-xcomm.c @@ -58,7 +58,7 @@ static int spi_xcomm_sync_config(struct spi_xcomm *spi_xcomm, unsigned int len) static void spi_xcomm_chipselect(struct spi_xcomm *spi_xcomm, struct spi_device *spi, int is_active) { - unsigned long cs = spi->chip_select; + unsigned long cs = spi_get_chipselect(spi, 0); uint16_t chipselect = spi_xcomm->chipselect;

if (is_active) diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c index d2f9eea5e093..5dd3d1901412 100644 --- a/drivers/spi/spi-xilinx.c +++ b/drivers/spi/spi-xilinx.c @@ -213,7 +213,7 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) */

cs = xspi->cs_inactive; - cs ^= BIT(spi->chip_select); + cs ^= BIT(spi_get_chipselect(spi, 0));

/* Activate the chip select */ xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); @@ -228,9 +228,9 @@ static int xilinx_spi_setup_transfer(struct spi_device *spi, struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);

if (spi->mode & SPI_CS_HIGH) - xspi->cs_inactive &= ~BIT(spi->chip_select); + xspi->cs_inactive &= ~BIT(spi_get_chipselect(spi, 0)); else - xspi->cs_inactive |= BIT(spi->chip_select); + xspi->cs_inactive |= BIT(spi_get_chipselect(spi, 0));

return 0; } diff --git a/drivers/spi/spi-xlp.c b/drivers/spi/spi-xlp.c index e5707fe5c8f1..3b91cdd5ae21 100644 --- a/drivers/spi/spi-xlp.c +++ b/drivers/spi/spi-xlp.c @@ -139,7 +139,7 @@ static int xlp_spi_setup(struct spi_device *spi) int cs;

xspi = spi_master_get_devdata(spi->master); - cs = spi->chip_select; + cs = spi_get_chipselect(spi, 0); /* * The value of fdiv must be between 4 and 65535. */ @@ -350,7 +350,7 @@ static int xlp_spi_transfer_one(struct spi_master *master, struct xlp_spi_priv *xspi = spi_master_get_devdata(master); int ret = 0;

- xspi->cs = spi->chip_select; + xspi->cs = spi_get_chipselect(spi, 0); xspi->dev = spi->dev;

if (spi_transfer_is_last(master, t)) diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c index 8558c0fe3775..ee1995b91287 100644 --- a/drivers/spi/spi-zynq-qspi.c +++ b/drivers/spi/spi-zynq-qspi.c @@ -296,7 +296,7 @@ static void zynq_qspi_chipselect(struct spi_device *spi, bool assert) /* Select the lower (CS0) or upper (CS1) memory */ if (ctlr->num_chipselect > 1) { config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET); - if (!spi->chip_select) + if (!spi_get_chipselect(spi, 0)) config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE; else config_reg |= ZYNQ_QSPI_LCFG_U_PAGE; diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 270d28a3f8eb..fb2ca9b90eab 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -468,7 +468,7 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) genfifoentry |= GQSPI_GENFIFO_MODE_SPI;

if (!is_high) { - if (!qspi->chip_select) { + if (!spi_get_chipselect(qspi, 0)) { xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER; } else { diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 5a038c667401..a399c617ca25 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -393,7 +393,7 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) struct spi_controller *ctlr = spi->controller;

if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods && - ctlr->cs_gpiods[spi->chip_select]) + ctlr->cs_gpiods[spi_get_chipselect(spi, 0)]) tmp &= ~SPI_CS_HIGH; }

@@ -432,7 +432,7 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) }

if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods && - ctlr->cs_gpiods[spi->chip_select]) + ctlr->cs_gpiods[spi_get_chipselect(spi, 0)]) tmp |= SPI_CS_HIGH;

tmp |= spi->mode & ~SPI_MODE_MASK; @@ -805,7 +805,7 @@ static int spidev_probe(struct spi_device *spi) spidev->devt = MKDEV(SPIDEV_MAJOR, minor); dev = device_create(spidev_class, &spi->dev, spidev->devt, spidev, "spidev%d.%d", - spi->master->bus_num, spi->chip_select); + spi->master->bus_num, spi_get_chipselect(spi, 0)); status = PTR_ERR_OR_ZERO(dev); } else { dev_dbg(&spi->dev, "no minor number available!\n"); diff --git a/include/trace/events/spi.h b/include/trace/events/spi.h index c0d9844befd7..c0248a8fa79c 100644 --- a/include/trace/events/spi.h +++ b/include/trace/events/spi.h @@ -57,7 +57,7 @@ TRACE_EVENT(spi_setup,

TP_fast_assign( __entry->bus_num = spi->controller->bus_num; - __entry->chip_select = spi->chip_select; + __entry->chip_select = spi_get_chipselect(spi, 0); __entry->mode = spi->mode; __entry->bits_per_word = spi->bits_per_word; __entry->max_speed_hz = spi->max_speed_hz; @@ -88,7 +88,7 @@ TRACE_EVENT(spi_set_cs,

TP_fast_assign( __entry->bus_num = spi->controller->bus_num; - __entry->chip_select = spi->chip_select; + __entry->chip_select = spi_get_chipselect(spi, 0); __entry->mode = spi->mode; __entry->enable = enable; ), @@ -113,7 +113,7 @@ DECLARE_EVENT_CLASS(spi_message,

TP_fast_assign( __entry->bus_num = msg->spi->controller->bus_num; - __entry->chip_select = msg->spi->chip_select; + __entry->chip_select = spi_get_chipselect(msg->spi, 0); __entry->msg = msg; ),

@@ -154,7 +154,7 @@ TRACE_EVENT(spi_message_done,

TP_fast_assign( __entry->bus_num = msg->spi->controller->bus_num; - __entry->chip_select = msg->spi->chip_select; + __entry->chip_select = spi_get_chipselect(msg->spi, 0); __entry->msg = msg; __entry->frame = msg->frame_length; __entry->actual = msg->actual_length; @@ -197,7 +197,7 @@ DECLARE_EVENT_CLASS(spi_transfer,

TP_fast_assign( __entry->bus_num = msg->spi->controller->bus_num; - __entry->chip_select = msg->spi->chip_select; + __entry->chip_select = spi_get_chipselect(msg->spi, 0); __entry->xfer = xfer; __entry->len = xfer->len;

Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively.

Signed-off-by: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com Acked-by: Jonathan Cameron Jonathan.Cameron@huawei.com Reviewed-by: Michal Simek michal.simek@amd.com --- drivers/iio/imu/adis16400.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/imu/adis16400.c b/drivers/iio/imu/adis16400.c index c02fc35dceb4..3eda32e12a53 100644 --- a/drivers/iio/imu/adis16400.c +++ b/drivers/iio/imu/adis16400.c @@ -466,7 +466,7 @@ static int adis16400_initial_setup(struct iio_dev *indio_dev)

dev_info(&indio_dev->dev, "%s: prod_id 0x%04x at CS%d (irq %d)\n", indio_dev->name, prod_id, - st->adis.spi->chip_select, st->adis.spi->irq); + spi_get_chipselect(st->adis.spi, 0), st->adis.spi->irq); } /* use high spi speed if possible */ if (st->variant->flags & ADIS16400_HAS_SLOW_MODE) {

Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively.

Signed-off-by: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com Reviewed-by: Greg Kroah-Hartman gregkh@linuxfoundation.org Reviewed-by: Michal Simek michal.simek@amd.com --- drivers/staging/fbtft/fbtft-core.c | 2 +- drivers/staging/greybus/spilib.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/fbtft/fbtft-core.c b/drivers/staging/fbtft/fbtft-core.c index afaba94d1d1c..3a4abf3bae40 100644 --- a/drivers/staging/fbtft/fbtft-core.c +++ b/drivers/staging/fbtft/fbtft-core.c @@ -840,7 +840,7 @@ int fbtft_register_framebuffer(struct fb_info *fb_info) sprintf(text1, ", %zu KiB buffer memory", par->txbuf.len >> 10); if (spi) sprintf(text2, ", spi%d.%d at %d MHz", spi->master->bus_num, - spi->chip_select, spi->max_speed_hz / 1000000); + spi_get_chipselect(spi, 0), spi->max_speed_hz / 1000000); dev_info(fb_info->dev, "%s frame buffer, %dx%d, %d KiB video memory%s, fps=%lu%s\n", fb_info->fix.id, fb_info->var.xres, fb_info->var.yres, diff --git a/drivers/staging/greybus/spilib.c b/drivers/staging/greybus/spilib.c index ad0700a0bb81..efb3bec58e15 100644 --- a/drivers/staging/greybus/spilib.c +++ b/drivers/staging/greybus/spilib.c @@ -237,7 +237,7 @@ static struct gb_operation *gb_spi_operation_create(struct gb_spilib *spi, request = operation->request->payload; request->count = cpu_to_le16(count); request->mode = dev->mode; - request->chip_select = dev->chip_select; + request->chip_select = spi_get_chipselect(dev, 0);

gb_xfer = &request->transfers[0]; tx_data = gb_xfer + count; /* place tx data after last gb_xfer */

Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively.

Signed-off-by: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com --- arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c index caa96edf0e72..4ab1d48cd229 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c @@ -144,7 +144,7 @@ static int __init fsl_spi_init(struct spi_board_info *board_infos,

static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on) { - pr_debug("%s %d %d\n", __func__, spi->chip_select, on); + pr_debug("%s %d %d\n", __func__, spi_get_chipselect(spi, 0), on); par_io_data_set(3, 13, on); }

For supporting multiple CS the SPI device need to be aware of all the CS values. So, the "chip_select" member in the spi_device structure is now an array that holds all the CS values.

spi_device structure now has a "cs_index_mask" member. This acts as an index to the chip_select array. If nth bit of spi->cs_index_mask is set then the driver would assert spi->chip_select[n].

In parallel mode all the chip selects are asserted/de-asserted simultaneously and each byte of data is stored in both devices, the even bits in one, the odd bits in the other. The split is automatically handled by the GQSPI controller. The GQSPI controller supports a maximum of two flashes connected in parallel mode. A "multi-cs-cap" flag is added in the spi controntroller data, through ctlr->multi-cs-cap the spi core will make sure that the controller is capable of handling multiple chip selects at once.

For supporting multiple CS via GPIO the cs_gpiod member of the spi_device structure is now an array that holds the gpio descriptor for each chipselect.

Multi CS support using GPIO is not tested due to unavailability of necessary hardware setup.

Signed-off-by: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com --- drivers/spi/spi.c | 225 +++++++++++++++++++++++++++------------- include/linux/spi/spi.h | 34 ++++-- 2 files changed, 182 insertions(+), 77 deletions(-)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index c725b4bab7af..742bd688381c 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -612,10 +612,17 @@ static int spi_dev_check(struct device *dev, void *data) { struct spi_device *spi = to_spi_device(dev); struct spi_device *new_spi = data; - - if (spi->controller == new_spi->controller && - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0)) - return -EBUSY; + int idx, nw_idx; + + if (spi->controller == new_spi->controller) { + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) { + if (spi_get_chipselect(spi, idx) == + spi_get_chipselect(new_spi, nw_idx)) + return -EBUSY; + } + } + } return 0; }

@@ -629,7 +636,7 @@ static int __spi_add_device(struct spi_device *spi) { struct spi_controller *ctlr = spi->controller; struct device *dev = ctlr->dev.parent; - int status; + int status, idx;

/* * We need to make sure there's no other device with this @@ -638,8 +645,7 @@ static int __spi_add_device(struct spi_device *spi) */ status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check); if (status) { - dev_err(dev, "chipselect %d already in use\n", - spi_get_chipselect(spi, 0)); + dev_err(dev, "chipselect %d already in use\n", spi_get_chipselect(spi, 0)); return status; }

@@ -649,8 +655,10 @@ static int __spi_add_device(struct spi_device *spi) return -ENODEV; }

- if (ctlr->cs_gpiods) - spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi, 0)]); + if (ctlr->cs_gpiods) { + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) + spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]); + }

/* * Drivers may modify this initial i/o setup, but will @@ -690,13 +698,15 @@ int spi_add_device(struct spi_device *spi) { struct spi_controller *ctlr = spi->controller; struct device *dev = ctlr->dev.parent; - int status; + int status, idx;

- /* Chipselects are numbered 0..max; validate. */ - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) { - dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0), - ctlr->num_chipselect); - return -EINVAL; + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { + /* Chipselects are numbered 0..max; validate. */ + if (spi_get_chipselect(spi, idx) >= ctlr->num_chipselect) { + dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, idx), + ctlr->num_chipselect); + return -EINVAL; + } }

/* Set the bus ID string */ @@ -713,12 +723,15 @@ static int spi_add_device_locked(struct spi_device *spi) { struct spi_controller *ctlr = spi->controller; struct device *dev = ctlr->dev.parent; + int idx;

- /* Chipselects are numbered 0..max; validate. */ - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) { - dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0), - ctlr->num_chipselect); - return -EINVAL; + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { + /* Chipselects are numbered 0..max; validate. */ + if (spi_get_chipselect(spi, idx) >= ctlr->num_chipselect) { + dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, idx), + ctlr->num_chipselect); + return -EINVAL; + } }

/* Set the bus ID string */ @@ -966,58 +979,119 @@ static void spi_res_release(struct spi_controller *ctlr, struct spi_message *mes static void spi_set_cs(struct spi_device *spi, bool enable, bool force) { bool activate = enable; + u32 cs_num = __ffs(spi->cs_index_mask); + int idx;

/* - * Avoid calling into the driver (or doing delays) if the chip select - * isn't actually changing from the last time this was called. + * In parallel mode all the chip selects are asserted/de-asserted + * at once */ - if (!force && ((enable && spi->controller->last_cs == spi_get_chipselect(spi, 0)) || - (!enable && spi->controller->last_cs != spi_get_chipselect(spi, 0))) && - (spi->controller->last_cs_mode_high == (spi->mode & SPI_CS_HIGH))) - return; - - trace_spi_set_cs(spi, activate); - - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1; - spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH; - - if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) && !activate) - spi_delay_exec(&spi->cs_hold, NULL); - - if (spi->mode & SPI_CS_HIGH) - enable = !enable; + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) == SPI_PARALLEL_CS_MASK) { + spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH; + + if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) && !activate) + spi_delay_exec(&spi->cs_hold, NULL); + + if (spi->mode & SPI_CS_HIGH) + enable = !enable; + + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi, 1)) { + if (!(spi->mode & SPI_NO_CS)) { + /* + * Historically ACPI has no means of the GPIO polarity and + * thus the SPISerialBus() resource defines it on the per-chip + * basis. In order to avoid a chain of negations, the GPIO + * polarity is considered being Active High. Even for the cases + * when _DSD() is involved (in the updated versions of ACPI) + * the GPIO CS polarity must be defined Active High to avoid + * ambiguity. That's why we use enable, that takes SPI_CS_HIGH + * into account. + */ + if (has_acpi_companion(&spi->dev)) { + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) + gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx), + !enable); + } else { + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) + /* Polarity handled by GPIO library */ + gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx), + activate); + } + } + /* Some SPI masters need both GPIO CS & slave_select */ + if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && + spi->controller->set_cs) + spi->controller->set_cs(spi, !enable); + else if (spi->controller->set_cs) + spi->controller->set_cs(spi, !enable); + }

- if (spi_get_csgpiod(spi, 0)) { - if (!(spi->mode & SPI_NO_CS)) { - /* - * Historically ACPI has no means of the GPIO polarity and - * thus the SPISerialBus() resource defines it on the per-chip - * basis. In order to avoid a chain of negations, the GPIO - * polarity is considered being Active High. Even for the cases - * when _DSD() is involved (in the updated versions of ACPI) - * the GPIO CS polarity must be defined Active High to avoid - * ambiguity. That's why we use enable, that takes SPI_CS_HIGH - * into account. - */ - if (has_acpi_companion(&spi->dev)) - gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable); - else - /* Polarity handled by GPIO library */ - gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate); + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { + if (spi_get_csgpiod(spi, idx) || !spi->controller->set_cs_timing) { + if (activate) + spi_delay_exec(&spi->cs_setup, NULL); + else + spi_delay_exec(&spi->cs_inactive, NULL); + } } - /* Some SPI masters need both GPIO CS & slave_select */ - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && - spi->controller->set_cs) + } else { + /* + * Avoid calling into the driver (or doing delays) if the chip select + * isn't actually changing from the last time this was called. + */ + if (!force && ((enable && spi->controller->last_cs == + spi_get_chipselect(spi, cs_num)) || + (!enable && spi->controller->last_cs != + spi_get_chipselect(spi, cs_num))) && + (spi->controller->last_cs_mode_high == + (spi->mode & SPI_CS_HIGH))) + return; + + trace_spi_set_cs(spi, activate); + + spi->controller->last_cs = enable ? spi_get_chipselect(spi, cs_num) : -1; + spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH; + + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller->set_cs_timing) && !activate) + spi_delay_exec(&spi->cs_hold, NULL); + + if (spi->mode & SPI_CS_HIGH) + enable = !enable; + + if (spi_get_csgpiod(spi, cs_num)) { + if (!(spi->mode & SPI_NO_CS)) { + /* + * Historically ACPI has no means of the GPIO polarity and + * thus the SPISerialBus() resource defines it on the per-chip + * basis. In order to avoid a chain of negations, the GPIO + * polarity is considered being Active High. Even for the cases + * when _DSD() is involved (in the updated versions of ACPI) + * the GPIO CS polarity must be defined Active High to avoid + * ambiguity. That's why we use enable, that takes SPI_CS_HIGH + * into account. + */ + if (has_acpi_companion(&spi->dev)) + gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num), + !enable); + else + /* Polarity handled by GPIO library */ + gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num), + activate); + } + /* Some SPI masters need both GPIO CS & slave_select */ + if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && + spi->controller->set_cs) + spi->controller->set_cs(spi, !enable); + } else if (spi->controller->set_cs) { spi->controller->set_cs(spi, !enable); - } else if (spi->controller->set_cs) { - spi->controller->set_cs(spi, !enable); - } + }

- if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) { - if (activate) - spi_delay_exec(&spi->cs_setup, NULL); - else - spi_delay_exec(&spi->cs_inactive, NULL); + if (spi_get_csgpiod(spi, cs_num) || !spi->controller->set_cs_timing) { + if (activate) + spi_delay_exec(&spi->cs_setup, NULL); + else + spi_delay_exec(&spi->cs_inactive, NULL); + } } }

@@ -2246,8 +2320,8 @@ static void of_spi_parse_dt_cs_delay(struct device_node *nc, static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, struct device_node *nc) { - u32 value; - int rc; + u32 value, cs[SPI_CS_CNT_MAX] = {0}; + int rc, idx;

/* Mode (clock phase/polarity/etc.) */ if (of_property_read_bool(nc, "spi-cpha")) @@ -2320,13 +2394,21 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, }

/* Device address */ - rc = of_property_read_u32(nc, "reg", &value); - if (rc) { + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1, + SPI_CS_CNT_MAX); + if (rc < 0 || rc > ctlr->num_chipselect) { dev_err(&ctlr->dev, "%pOF has no valid 'reg' property (%d)\n", nc, rc); return rc; + } else if ((of_property_read_bool(nc, "parallel-memories")) && + (!ctlr->multi_cs_cap)) { + dev_err(&ctlr->dev, "SPI controller doesn't support multi CS\n"); + return -EINVAL; } - spi_set_chipselect(spi, 0, value); + for (idx = 0; idx < rc; idx++) + spi_set_chipselect(spi, idx, cs[idx]); + /* By default set the spi->cs_index_mask as 1 */ + spi->cs_index_mask = 0x01;

/* Device speed */ if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@ -3846,6 +3928,7 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) struct spi_controller *ctlr = spi->controller; struct spi_transfer *xfer; int w_size; + u32 cs_num = __ffs(spi->cs_index_mask);

if (list_empty(&message->transfers)) return -EINVAL; @@ -3858,7 +3941,7 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) * cs_change is set for each transfer. */ if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits & SPI_CS_WORD) || - spi_get_csgpiod(spi, 0))) { + spi_get_csgpiod(spi, cs_num))) { size_t maxsize; int ret;

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index bdb35a91b4bf..452682aa1a39 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -19,6 +19,11 @@ #include <linux/acpi.h> #include <linux/u64_stats_sync.h>

+/* Max no. of CS supported per spi device */ +#define SPI_CS_CNT_MAX 2 + +/* chip select mask */ +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1)) struct dma_chan; struct software_node; struct ptp_system_timestamp; @@ -166,6 +171,7 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, * deasserted. If @cs_change_delay is used from @spi_transfer, then the * two delays will be added up. * @pcpu_statistics: statistics for the spi_device + * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array * * A @spi_device is used to interchange data between an SPI slave * (usually a discrete chip) and CPU memory. @@ -181,7 +187,7 @@ struct spi_device { struct spi_controller *controller; struct spi_controller *master; /* Compatibility layer */ u32 max_speed_hz; - u8 chip_select; + u8 chip_select[SPI_CS_CNT_MAX]; u8 bits_per_word; bool rt; #define SPI_NO_TX BIT(31) /* No transmit wire */ @@ -202,7 +208,7 @@ struct spi_device { void *controller_data; char modalias[SPI_NAME_SIZE]; const char *driver_override; - struct gpio_desc *cs_gpiod; /* Chip select gpio desc */ + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */ struct spi_delay word_delay; /* Inter-word delay */ /* CS delays */ struct spi_delay cs_setup; @@ -212,6 +218,13 @@ struct spi_device { /* The statistics */ struct spi_statistics __percpu *pcpu_statistics;

+ /* Bit mask of the chipselect(s) that the driver need to use from + * the chipselect array.When the controller is capable to handle + * multiple chip selects & memories are connected in parallel + * then more than one bit need to be set in cs_index_mask. + */ + u32 cs_index_mask : 2; + /* * likely need more hooks for more protocol options affecting how * the controller talks to each chip, like: @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(struct spi_device *spi)

static inline u8 spi_get_chipselect(struct spi_device *spi, u8 idx) { - return spi->chip_select; + return spi->chip_select[idx]; }

static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect) { - spi->chip_select = chipselect; + spi->chip_select[idx] = chipselect; }

static inline struct gpio_desc *spi_get_csgpiod(struct spi_device *spi, u8 idx) { - return spi->cs_gpiod; + return spi->cs_gpiod[idx]; }

static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod) { - spi->cs_gpiod = csgpiod; + spi->cs_gpiod[idx] = csgpiod; }

/** @@ -388,6 +401,8 @@ extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 ch * @bus_lock_spinlock: spinlock for SPI bus locking * @bus_lock_mutex: mutex for exclusion of multiple callers * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use + * @multi_cs_cap: indicates that the SPI Controller can assert/de-assert + * more than one chip select at once. * @setup: updates the device mode and clocking records used by a * device's SPI controller; protocol code may call this. This * must fail if an unrecognized or unsupported mode is requested. @@ -585,6 +600,13 @@ struct spi_controller { /* Flag indicating that the SPI bus is locked for exclusive use */ bool bus_lock_flag;

+ /* + * Flag indicating that the spi-controller has multi chip select + * capability and can assert/de-assert more than one chip select + * at once. + */ + bool multi_cs_cap; + /* Setup mode and clock, etc (spi driver may call many times). * * IMPORTANT: this may be called when transfers to another

In further patches the nor->params references in spi_nor_otp_region_len(nor) & spi_nor_otp_n_regions(nor) macros will be replaced with spi_nor_get_params() API. To make the transition smoother, first converting the macros into static inline functions.

Suggested-by: Michal Simek michal.simek@amd.com Signed-off-by: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com --- drivers/mtd/spi-nor/otp.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c index 00ab0d2d6d2f..3d75899de303 100644 --- a/drivers/mtd/spi-nor/otp.c +++ b/drivers/mtd/spi-nor/otp.c @@ -11,8 +11,27 @@

#include "core.h"

-#define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len) -#define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions) +/** + * spi_nor_otp_region_len() - get size of one OTP region in bytes + * @nor: pointer to 'struct spi_nor' + * + * Return: size of one OTP region in bytes + */ +static inline unsigned int spi_nor_otp_region_len(struct spi_nor *nor) +{ + return nor->params->otp.org->len; +} + +/** + * spi_nor_otp_n_regions() - get number of individual OTP regions + * @nor: pointer to 'struct spi_nor' + * + * Return: number of individual OTP regions + */ +static inline unsigned int spi_nor_otp_n_regions(struct spi_nor *nor) +{ + return nor->params->otp.org->n_regions; +}

/** * spi_nor_otp_read_secr() - read security register

Each flash that is connected in stacked mode should have a separate parameter structure. So, the flash parameter member(*params) of the spi_nor structure is changed to an array (*params[2]). The array is used to store the parameters of each flash connected in stacked configuration.

The current implementation assumes that a maximum of two flashes are connected in stacked mode and both the flashes are of same make but can differ in sizes. So, except the sizes all other flash parameters of both the flashes are identical.

SPI-NOR is not aware of the chip_select values, for any incoming request SPI-NOR will decide the flash index with the help of individual flash size and the configuration type (single/stacked). SPI-NOR will pass on the flash index information to the SPI core & SPI driver by setting the appropriate bit in nor->spimem->spi->cs_index_mask. For example, if nth bit of nor->spimem->spi->cs_index_mask is set then the driver would assert/de-assert spi->chip_slect[n].

Signed-off-by: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com --- drivers/mtd/spi-nor/core.c | 282 +++++++++++++++++++++++++++++------- drivers/mtd/spi-nor/core.h | 4 + include/linux/mtd/spi-nor.h | 12 +- 3 files changed, 244 insertions(+), 54 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 66b6934b4465..0bc6b42f276c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1441,13 +1441,18 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); - u32 addr, len; + struct spi_nor_flash_parameter *params; + u32 addr, len, offset, cur_cs_num = 0; uint32_t rem; int ret; + u64 sz;

dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, (long long)instr->len);

+ params = spi_nor_get_params(nor, 0); + sz = params->size; + if (spi_nor_has_uniform_erase(nor)) { div_u64_rem(instr->len, mtd->erasesize, &rem); if (rem) @@ -1465,26 +1470,30 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { unsigned long timeout;

- ret = spi_nor_write_enable(nor); - if (ret) - goto erase_err; + while (cur_cs_num < SNOR_FLASH_CNT_MAX && params) { + nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; + ret = spi_nor_write_enable(nor); + if (ret) + goto erase_err;

- ret = spi_nor_erase_chip(nor); - if (ret) - goto erase_err; + ret = spi_nor_erase_chip(nor); + if (ret) + goto erase_err;

- /* - * Scale the timeout linearly with the size of the flash, with - * a minimum calibrated to an old 2MB flash. We could try to - * pull these from CFI/SFDP, but these values should be good - * enough for now. - */ - timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, - CHIP_ERASE_2MB_READY_WAIT_JIFFIES * - (unsigned long)(mtd->size / SZ_2M)); - ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); - if (ret) - goto erase_err; + /* + * Scale the timeout linearly with the size of the flash, with + * a minimum calibrated to an old 2MB flash. We could try to + * pull these from CFI/SFDP, but these values should be good + * enough for now. + */ + timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, + CHIP_ERASE_2MB_READY_WAIT_JIFFIES * + (unsigned long)(params->size / SZ_2M)); + ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); + if (ret) + goto erase_err; + cur_cs_num++; + }

/* REVISIT in some cases we could speed up erasing large regions * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up @@ -1493,12 +1502,26 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)

/* "sector"-at-a-time erase */ } else if (spi_nor_has_uniform_erase(nor)) { + /* Determine the flash from which the operation need to start */ + while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (addr > sz - 1) && params) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } + while (len) { + nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; ret = spi_nor_write_enable(nor); if (ret) goto erase_err;

- ret = spi_nor_erase_sector(nor, addr); + offset = addr; + if (nor->flags & SNOR_F_HAS_STACKED) { + params = spi_nor_get_params(nor, cur_cs_num); + offset -= (sz - params->size); + } + + ret = spi_nor_erase_sector(nor, offset); if (ret) goto erase_err;

@@ -1508,13 +1531,45 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)

addr += mtd->erasesize; len -= mtd->erasesize; + + /* + * Flash cross over condition in stacked mode. + */ + if ((nor->flags & SNOR_F_HAS_STACKED) && (addr > sz - 1)) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } }

/* erase multiple sectors */ } else { - ret = spi_nor_erase_multi_sectors(nor, addr, len); - if (ret) - goto erase_err; + u64 erase_len = 0; + + /* Determine the flash from which the operation need to start */ + while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (addr > sz - 1) && params) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } + /* perform multi sector erase onec per Flash*/ + while (len) { + erase_len = (len > (sz - addr)) ? (sz - addr) : len; + offset = addr; + nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; + if (nor->flags & SNOR_F_HAS_STACKED) { + params = spi_nor_get_params(nor, cur_cs_num); + offset -= (sz - params->size); + } + ret = spi_nor_erase_multi_sectors(nor, offset, erase_len); + if (ret) + goto erase_err; + len -= erase_len; + addr += erase_len; + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } }

ret = spi_nor_write_disable(nor); @@ -1713,7 +1768,10 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { struct spi_nor *nor = mtd_to_spi_nor(mtd); - ssize_t ret; + struct spi_nor_flash_parameter *params; + ssize_t ret, read_len; + u32 cur_cs_num = 0; + u64 sz;

dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);

@@ -1721,9 +1779,23 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, if (ret) return ret;

+ params = spi_nor_get_params(nor, 0); + sz = params->size; + + /* Determine the flash from which the operation need to start */ + while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (from > sz - 1) && params) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } while (len) { loff_t addr = from;

+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; + read_len = (len > (sz - addr)) ? (sz - addr) : len; + params = spi_nor_get_params(nor, cur_cs_num); + addr -= (sz - params->size); + addr = spi_nor_convert_addr(nor, addr);

ret = spi_nor_read_data(nor, addr, len, buf); @@ -1735,11 +1807,22 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, if (ret < 0) goto read_err;

- WARN_ON(ret > len); + WARN_ON(ret > read_len); *retlen += ret; buf += ret; from += ret; len -= ret; + + /* + * Flash cross over condition in stacked mode. + * + */ + if ((nor->flags & SNOR_F_HAS_STACKED) && (from > sz - 1)) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } + } ret = 0;

@@ -1759,13 +1842,22 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, struct spi_nor *nor = mtd_to_spi_nor(mtd); struct spi_nor_flash_parameter *params; size_t page_offset, page_remain, i; + u32 page_size, cur_cs_num = 0; ssize_t ret; - u32 page_size; + u64 sz;

dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);

params = spi_nor_get_params(nor, 0); page_size = params->page_size; + sz = params->size; + + /* Determine the flash from which the operation need to start */ + while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (to > sz - 1) && params) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + }

ret = spi_nor_lock_and_prep(nor); if (ret) @@ -1790,6 +1882,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, /* the size of data remaining on the first page */ page_remain = min_t(size_t, page_size - page_offset, len - i);

+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; + params = spi_nor_get_params(nor, cur_cs_num); + addr -= (sz - params->size); + addr = spi_nor_convert_addr(nor, addr);

ret = spi_nor_write_enable(nor); @@ -1806,6 +1902,15 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, goto write_err; *retlen += written; i += written; + + /* + * Flash cross over condition in stacked mode. + */ + if ((nor->flags & SNOR_F_HAS_STACKED) && ((to + i) > sz - 1)) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } }

write_err: @@ -1918,8 +2023,6 @@ int spi_nor_hwcaps_pp2cmd(u32 hwcaps) static int spi_nor_spimem_check_op(struct spi_nor *nor, struct spi_mem_op *op) { - struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0); - /* * First test with 4 address bytes. The opcode itself might * be a 3B addressing opcode but we don't care, because @@ -1928,7 +2031,7 @@ static int spi_nor_spimem_check_op(struct spi_nor *nor, */ op->addr.nbytes = 4; if (!spi_mem_supports_op(nor->spimem, op)) { - if (params->size > SZ_16M) + if (nor->mtd.size > SZ_16M) return -EOPNOTSUPP;

/* If flash size <= 16MB, 3 address bytes are sufficient */ @@ -2525,6 +2628,10 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) static void spi_nor_late_init_params(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0); + struct device_node *np = spi_nor_get_flash_node(nor); + u64 flash_size[SNOR_FLASH_CNT_MAX]; + u32 idx = 0, i = 0; + int rc;

if (nor->manufacturer && nor->manufacturer->fixups && nor->manufacturer->fixups->late_init) @@ -2542,6 +2649,36 @@ static void spi_nor_late_init_params(struct spi_nor *nor) */ if (nor->flags & SNOR_F_HAS_LOCK && !params->locking_ops) spi_nor_init_default_locking_ops(nor); + /* + * The flashes that are connected in stacked mode should be of same make. + * Except the flash size all other properties are identical for all the + * flashes connected in stacked mode. + * The flashes that are connected in parallel mode should be identical. + */ + while (i < SNOR_FLASH_CNT_MAX) { + rc = of_property_read_u64_index(np, "stacked-memories", idx, &flash_size[i]); + if (rc == -EINVAL) { + break; + } else if (rc == -EOVERFLOW) { + idx++; + } else { + idx++; + i++; + if (!(nor->flags & SNOR_F_HAS_STACKED)) + nor->flags |= SNOR_F_HAS_STACKED; + } + } + if (nor->flags & SNOR_F_HAS_STACKED) { + for (idx = 1; idx < SNOR_FLASH_CNT_MAX; idx++) { + params = spi_nor_get_params(nor, idx); + params = devm_kzalloc(nor->dev, sizeof(*params), GFP_KERNEL); + if (params) { + memcpy(params, spi_nor_get_params(nor, 0), sizeof(*params)); + params->size = flash_size[idx]; + spi_nor_set_params(nor, idx, params); + } + } + } }

/** @@ -2750,22 +2887,36 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) */ static int spi_nor_quad_enable(struct spi_nor *nor) { - struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0); + struct spi_nor_flash_parameter *params; + int err, idx;

- if (!params->quad_enable) - return 0; + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + params = spi_nor_get_params(nor, idx); + if (params) { + if (!params->quad_enable) + return 0;

- if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || - spi_nor_get_protocol_width(nor->write_proto) == 4)) - return 0; + if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || + spi_nor_get_protocol_width(nor->write_proto) == 4)) + return 0; + /* + * Set the appropriate CS index before + * issuing the command. + */ + nor->spimem->spi->cs_index_mask = 0x01 << idx;

- return params->quad_enable(nor); + err = params->quad_enable(nor); + if (err) + return err; + } + } + return err; }

static int spi_nor_init(struct spi_nor *nor) { - struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0); - int err; + struct spi_nor_flash_parameter *params; + int err, idx;

err = spi_nor_octal_dtr_enable(nor, true); if (err) { @@ -2806,9 +2957,19 @@ static int spi_nor_init(struct spi_nor *nor) */ WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, "enabling reset hack; may not recover from unexpected reboots\n"); - err = params->set_4byte_addr_mode(nor, true); - if (err && err != -ENOTSUPP) - return err; + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + params = spi_nor_get_params(nor, idx); + if (params) { + /* + * Select the appropriate CS index before + * issuing the command. + */ + nor->spimem->spi->cs_index_mask = 0x01 << idx; + err = params->set_4byte_addr_mode(nor, true); + if (err && err != -ENOTSUPP) + return err; + } + } }

return 0; @@ -2924,19 +3085,31 @@ void spi_nor_restore(struct spi_nor *nor) { struct spi_nor_flash_parameter *params; int ret; + int idx;

/* restore the addressing mode */ if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && nor->flags & SNOR_F_BROKEN_RESET) { - params = spi_nor_get_params(nor, 0); - ret = params->set_4byte_addr_mode(nor, false); - if (ret) - /* - * Do not stop the execution in the hope that the flash - * will default to the 3-byte address mode after the - * software reset. - */ - dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret); + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + params = spi_nor_get_params(nor, idx); + if (params) { + /* + * Select the appropriate CS index before + * issuing the command. + */ + nor->spimem->spi->cs_index_mask = 0x01 << idx; + ret = params->set_4byte_addr_mode(nor, false); + if (ret) + /* + * Do not stop the execution in the hope that the flash + * will default to the 3-byte address mode after the + * software reset. + */ + dev_err(nor->dev, + "Failed to exit 4-byte address mode, err = %d\n", + ret); + } + } }

if (nor->flags & SNOR_F_SOFT_RESET) @@ -3004,6 +3177,8 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor) struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0); struct mtd_info *mtd = &nor->mtd; struct device *dev = nor->dev; + u64 total_sz = 0; + int idx;

spi_nor_set_mtd_locking_ops(nor); spi_nor_set_mtd_otp_ops(nor); @@ -3019,7 +3194,12 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor) mtd->_erase = spi_nor_erase; mtd->writesize = params->writesize; mtd->writebufsize = params->page_size; - mtd->size = params->size; + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + params = spi_nor_get_params(nor, idx); + if (params) + total_sz += params->size; + } + mtd->size = total_sz; mtd->_read = spi_nor_read; /* Might be already set by some SST flashes. */ if (!mtd->_write) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 25423225c29d..cff2f9c389b8 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -11,6 +11,9 @@

#define SPI_NOR_MAX_ID_LEN 6

+/* In single configuration enable CS0 */ +#define SPI_NOR_ENABLE_CS0 BIT(0) + /* Standard SPI NOR flash operations. */ #define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \ @@ -130,6 +133,7 @@ enum spi_nor_option_flags { SNOR_F_IO_MODE_EN_VOLATILE = BIT(11), SNOR_F_SOFT_RESET = BIT(12), SNOR_F_SWP_IS_VOLATILE = BIT(13), + SNOR_F_HAS_STACKED = BIT(14), };

struct spi_nor_read_command { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 338b73125131..99f0f2ede444 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -127,6 +127,12 @@ #define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */ #define SR2_QUAD_EN_BIT7 BIT(7)

+/* + * Maximum number of flashes that can be connected + * in stacked/parallel configuration + */ +#define SNOR_FLASH_CNT_MAX 2 + /* Supported SPI protocols */ #define SNOR_PROTO_INST_MASK GENMASK(23, 16) #define SNOR_PROTO_INST_SHIFT 16 @@ -399,7 +405,7 @@ struct spi_nor {

const struct spi_nor_controller_ops *controller_ops;

- struct spi_nor_flash_parameter *params; + struct spi_nor_flash_parameter *params[SNOR_FLASH_CNT_MAX];

struct { struct spi_mem_dirmap_desc *rdesc; @@ -422,13 +428,13 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)

static inline struct spi_nor_flash_parameter *spi_nor_get_params(const struct spi_nor *nor, u8 idx) { - return nor->params; + return nor->params[idx]; }

static inline void spi_nor_set_params(struct spi_nor *nor, u8 idx, struct spi_nor_flash_parameter *params) { - nor->params = params; + nor->params[idx] = params; } /** * spi_nor_scan() - scan the SPI NOR

The current implementation assumes that a maximum of two flashes are connected in parallel mode. The QSPI controller splits the data evenly between both the flashes so, both the flashes that are connected in parallel mode should be identical. During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in nor->spimem->spi->cs_index_mask. The QSPI driver will then assert/de-assert CS0 & CS1. Write operation in parallel mode are performed in page size * 2 chunks as each write operation results in writing both the flashes. For doubling the address space each operation is performed at addr/2 flash offset, where addr is the address specified by the user.

Signed-off-by: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com --- drivers/mtd/spi-nor/core.c | 514 +++++++++++++++++++++++--------- drivers/mtd/spi-nor/core.h | 4 + drivers/mtd/spi-nor/micron-st.c | 5 + 3 files changed, 384 insertions(+), 139 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 0bc6b42f276c..18fc4a1c28d4 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -464,17 +464,29 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) op.data.nbytes = 2; }

+ if (nor->flags & SNOR_F_HAS_PARALLEL) + op.data.nbytes = 2; + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);

ret = spi_mem_exec_op(nor->spimem, &op); } else { - ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr, - 1); + if (nor->flags & SNOR_F_HAS_PARALLEL) + ret = spi_nor_controller_ops_read_reg(nor, + SPINOR_OP_RDSR, + sr, 2); + else + ret = spi_nor_controller_ops_read_reg(nor, + SPINOR_OP_RDSR, + sr, 1); }

if (ret) dev_dbg(nor->dev, "error %d reading SR\n", ret);

+ if (nor->flags & SNOR_F_HAS_PARALLEL) + sr[0] |= sr[1]; + return ret; }

@@ -1466,12 +1478,122 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) if (ret) return ret;

- /* whole-chip erase? */ - if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { - unsigned long timeout; + if (!(nor->flags & SNOR_F_HAS_PARALLEL)) { + /* whole-chip erase? */ + if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { + unsigned long timeout; + + while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && params) { + nor->spimem->spi->cs_index_mask = 1 << cur_cs_num; + ret = spi_nor_write_enable(nor); + if (ret) + goto erase_err; + + ret = spi_nor_erase_chip(nor); + if (ret) + goto erase_err; + + /* + * Scale the timeout linearly with the size of the flash, with + * a minimum calibrated to an old 2MB flash. We could try to + * pull these from CFI/SFDP, but these values should be good + * enough for now. + */ + timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, + CHIP_ERASE_2MB_READY_WAIT_JIFFIES * + (unsigned long)(params->size / + SZ_2M)); + ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); + if (ret) + goto erase_err; + + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + } + + /* REVISIT in some cases we could speed up erasing large regions + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up + * to use "small sector erase", but that's not always optimal. + */ + + /* "sector"-at-a-time erase */ + } else if (spi_nor_has_uniform_erase(nor)) { + /* Determine the flash from which the operation need to start */ + while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && + (addr > sz - 1) && params) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } + while (len) { + nor->spimem->spi->cs_index_mask = 1 << cur_cs_num; + ret = spi_nor_write_enable(nor); + if (ret) + goto erase_err; + + offset = addr; + if (nor->flags & SNOR_F_HAS_STACKED) { + params = spi_nor_get_params(nor, cur_cs_num); + offset -= (sz - params->size); + } + ret = spi_nor_erase_sector(nor, offset); + if (ret) + goto erase_err; + + ret = spi_nor_wait_till_ready(nor); + if (ret) + goto erase_err; + + addr += mtd->erasesize; + len -= mtd->erasesize; + + /* + * Flash cross over condition in stacked mode. + */ + if ((nor->flags & SNOR_F_HAS_STACKED) && (addr > sz - 1)) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } + } + + /* erase multiple sectors */ + } else { + u64 erase_len = 0; + + /* Determine the flash from which the operation need to start */ + while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && + (addr > sz - 1) && params) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } + /* perform multi sector erase onec per Flash*/ + while (len) { + erase_len = (len > (sz - addr)) ? (sz - addr) : len; + offset = addr; + nor->spimem->spi->cs_index_mask = 1 << cur_cs_num; + if (nor->flags & SNOR_F_HAS_STACKED) { + params = spi_nor_get_params(nor, cur_cs_num); + offset -= (sz - params->size); + } + ret = spi_nor_erase_multi_sectors(nor, offset, erase_len); + if (ret) + goto erase_err; + len -= erase_len; + addr += erase_len; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } + } + } else { + nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS; + + /* whole-chip erase? */ + if (len == mtd->size && !(nor->flags & + SNOR_F_NO_OP_CHIP_ERASE)) { + unsigned long timeout;

- while (cur_cs_num < SNOR_FLASH_CNT_MAX && params) { - nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; ret = spi_nor_write_enable(nor); if (ret) goto erase_err; @@ -1488,90 +1610,45 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) */ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, CHIP_ERASE_2MB_READY_WAIT_JIFFIES * - (unsigned long)(params->size / SZ_2M)); + (unsigned long)(mtd->size / SZ_2M)); ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); if (ret) goto erase_err; - cur_cs_num++; - } - - /* REVISIT in some cases we could speed up erasing large regions - * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up - * to use "small sector erase", but that's not always optimal. - */

- /* "sector"-at-a-time erase */ - } else if (spi_nor_has_uniform_erase(nor)) { - /* Determine the flash from which the operation need to start */ - while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (addr > sz - 1) && params) { - cur_cs_num++; - params = spi_nor_get_params(nor, cur_cs_num); - sz += params->size; - } + /* REVISIT in some cases we could speed up erasing large regions + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up + * to use "small sector erase", but that's not always optimal. + */

- while (len) { - nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; - ret = spi_nor_write_enable(nor); - if (ret) - goto erase_err; + /* "sector"-at-a-time erase */ + } else if (spi_nor_has_uniform_erase(nor)) { + while (len) { + ret = spi_nor_write_enable(nor); + if (ret) + goto erase_err;

- offset = addr; - if (nor->flags & SNOR_F_HAS_STACKED) { - params = spi_nor_get_params(nor, cur_cs_num); - offset -= (sz - params->size); - } + offset = addr / 2;

- ret = spi_nor_erase_sector(nor, offset); - if (ret) - goto erase_err; - - ret = spi_nor_wait_till_ready(nor); - if (ret) - goto erase_err; + ret = spi_nor_erase_sector(nor, offset); + if (ret) + goto erase_err;

- addr += mtd->erasesize; - len -= mtd->erasesize; + ret = spi_nor_wait_till_ready(nor); + if (ret) + goto erase_err;

- /* - * Flash cross over condition in stacked mode. - */ - if ((nor->flags & SNOR_F_HAS_STACKED) && (addr > sz - 1)) { - cur_cs_num++; - params = spi_nor_get_params(nor, cur_cs_num); - sz += params->size; + addr += mtd->erasesize; + len -= mtd->erasesize; } - } - - /* erase multiple sectors */ - } else { - u64 erase_len = 0;

- /* Determine the flash from which the operation need to start */ - while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (addr > sz - 1) && params) { - cur_cs_num++; - params = spi_nor_get_params(nor, cur_cs_num); - sz += params->size; - } - /* perform multi sector erase onec per Flash*/ - while (len) { - erase_len = (len > (sz - addr)) ? (sz - addr) : len; - offset = addr; - nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; - if (nor->flags & SNOR_F_HAS_STACKED) { - params = spi_nor_get_params(nor, cur_cs_num); - offset -= (sz - params->size); - } - ret = spi_nor_erase_multi_sectors(nor, offset, erase_len); + /* erase multiple sectors */ + } else { + offset = addr / 2; + ret = spi_nor_erase_multi_sectors(nor, offset, len); if (ret) goto erase_err; - len -= erase_len; - addr += erase_len; - cur_cs_num++; - params = spi_nor_get_params(nor, cur_cs_num); - sz += params->size; } } - ret = spi_nor_write_disable(nor);

erase_err: @@ -1771,34 +1848,59 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, struct spi_nor_flash_parameter *params; ssize_t ret, read_len; u32 cur_cs_num = 0; - u64 sz; + u_char *readbuf; + bool is_ofst_odd = false; + u64 sz = 0;

dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);

- ret = spi_nor_lock_and_prep(nor); - if (ret) - return ret; - params = spi_nor_get_params(nor, 0); sz = params->size;

- /* Determine the flash from which the operation need to start */ - while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (from > sz - 1) && params) { - cur_cs_num++; - params = spi_nor_get_params(nor, cur_cs_num); - sz += params->size; + /* + * Cannot read from odd offset in parallel mode, so read + * len + 1 from offset + 1 and ignore offset[0] data. + */ + if ((nor->flags & SNOR_F_HAS_PARALLEL) && (from & 0x01)) { + from = (loff_t)(from - 1); + len = (size_t)(len + 1); + is_ofst_odd = true; + readbuf = kmalloc(len, GFP_KERNEL); + if (!readbuf) + return -ENOMEM; + } else { + readbuf = buf; + } + + if (!(nor->flags & SNOR_F_HAS_PARALLEL)) { + /* Determine the flash from which the operation need to start */ + while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (from > sz - 1) && params) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } } + ret = spi_nor_lock_and_prep(nor); + if (ret) + return ret; + while (len) { loff_t addr = from;

- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; - read_len = (len > (sz - addr)) ? (sz - addr) : len; - params = spi_nor_get_params(nor, cur_cs_num); - addr -= (sz - params->size); + if (nor->flags & SNOR_F_HAS_PARALLEL) { + nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS; + read_len = len; + addr /= 2; + } else { + nor->spimem->spi->cs_index_mask = 1 << cur_cs_num; + read_len = (len > (sz - addr)) ? (sz - addr) : len; + params = spi_nor_get_params(nor, cur_cs_num); + addr -= (sz - params->size); + }

addr = spi_nor_convert_addr(nor, addr);

- ret = spi_nor_read_data(nor, addr, len, buf); + ret = spi_nor_read_data(nor, addr, read_len, readbuf); if (ret == 0) { /* We shouldn't see 0-length reads */ ret = -EIO; @@ -1808,8 +1910,20 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, goto read_err;

WARN_ON(ret > read_len); - *retlen += ret; + if (is_ofst_odd) { + /* + * Cannot read from odd offset in parallel mode. + * So read len + 1 from offset + 1 from the flash + * and copy len data from readbuf[1]. + */ + memcpy(buf, (readbuf + 1), (len - 1)); + *retlen += (ret - 1); + } else { + *retlen += ret; + } buf += ret; + if (!is_ofst_odd) + readbuf += ret; from += ret; len -= ret;

@@ -1827,6 +1941,9 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, ret = 0;

read_err: + if (is_ofst_odd) + kfree(readbuf); + spi_nor_unlock_and_unprep(nor); return ret; } @@ -1852,13 +1969,38 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, page_size = params->page_size; sz = params->size;

- /* Determine the flash from which the operation need to start */ - while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (to > sz - 1) && params) { - cur_cs_num++; - params = spi_nor_get_params(nor, cur_cs_num); - sz += params->size; - } + if (nor->flags & SNOR_F_HAS_PARALLEL) { + /* + * Cannot write to odd offset in parallel mode, + * so write 2 byte first. + */ + if (to & 0x01) { + u8 two[2] = {0xff, buf[0]}; + size_t written_len; + + ret = spi_nor_write(mtd, to & ~1, 2, &written_len, two); + if (ret < 0) + return ret; + *retlen += 1; /* We've written only one actual byte */ + ++buf; + --len; + ++to; + } + /* + * Write operation are performed in page size chunks and in + * parallel memories both the flashes are written simultaneously, + * hence doubled the page_size. + */ + page_size <<= 1;

+ } else { + /* Determine the flash from which the operation need to start */ + while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (to > sz - 1) && params) { + cur_cs_num++; + params = spi_nor_get_params(nor, cur_cs_num); + sz += params->size; + } + } ret = spi_nor_lock_and_prep(nor); if (ret) return ret; @@ -1882,9 +2024,14 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, /* the size of data remaining on the first page */ page_remain = min_t(size_t, page_size - page_offset, len - i);

- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num; - params = spi_nor_get_params(nor, cur_cs_num); - addr -= (sz - params->size); + if (nor->flags & SNOR_F_HAS_PARALLEL) { + nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS; + addr /= 2; + } else { + nor->spimem->spi->cs_index_mask = 1 << cur_cs_num; + params = spi_nor_get_params(nor, cur_cs_num); + addr -= (sz - params->size); + }

addr = spi_nor_convert_addr(nor, addr);

@@ -2332,7 +2479,15 @@ static int spi_nor_select_erase(struct spi_nor *nor) if (!erase) return -EINVAL; nor->erase_opcode = erase->opcode; - mtd->erasesize = erase->size; + /* + * In parallel-memories the erase operation is + * performed on both the flashes simultaneously + * so, double the erasesize. + */ + if (nor->flags & SNOR_F_HAS_PARALLEL) + mtd->erasesize = erase->size * 2; + else + mtd->erasesize = erase->size; return 0; }

@@ -2350,7 +2505,15 @@ static int spi_nor_select_erase(struct spi_nor *nor) if (!erase) return -EINVAL;

- mtd->erasesize = erase->size; + /* + * In parallel-memories the erase operation is + * performed on both the flashes simultaneously + * so, double the erasesize. + */ + if (nor->flags & SNOR_F_HAS_PARALLEL) + mtd->erasesize = erase->size * 2; + else + mtd->erasesize = erase->size; return 0; }

@@ -2668,7 +2831,22 @@ static void spi_nor_late_init_params(struct spi_nor *nor) nor->flags |= SNOR_F_HAS_STACKED; } } - if (nor->flags & SNOR_F_HAS_STACKED) { + i = 0; + idx = 0; + while (i < SNOR_FLASH_CNT_MAX) { + rc = of_property_read_u64_index(np, "parallel-memories", idx, &flash_size[i]); + if (rc == -EINVAL) { + break; + } else if (rc == -EOVERFLOW) { + idx++; + } else { + idx++; + i++; + if (!(nor->flags & SNOR_F_HAS_PARALLEL)) + nor->flags |= SNOR_F_HAS_PARALLEL; + } + } + if (nor->flags & (SNOR_F_HAS_STACKED | SNOR_F_HAS_PARALLEL)) { for (idx = 1; idx < SNOR_FLASH_CNT_MAX; idx++) { params = spi_nor_get_params(nor, idx); params = devm_kzalloc(nor->dev, sizeof(*params), GFP_KERNEL); @@ -2890,24 +3068,42 @@ static int spi_nor_quad_enable(struct spi_nor *nor) struct spi_nor_flash_parameter *params; int err, idx;

- for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { - params = spi_nor_get_params(nor, idx); - if (params) { - if (!params->quad_enable) - return 0; + if (nor->flags & SNOR_F_HAS_PARALLEL) { + params = spi_nor_get_params(nor, 0); + if (!params->quad_enable) + return 0;

- if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || - spi_nor_get_protocol_width(nor->write_proto) == 4)) - return 0; - /* - * Set the appropriate CS index before - * issuing the command. - */ - nor->spimem->spi->cs_index_mask = 0x01 << idx; + if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || + spi_nor_get_protocol_width(nor->write_proto) == 4)) + return 0; + /* + * In parallel mode both chip selects i.e., CS0 & + * CS1 need to be asserted simulatneously. + */ + nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS; + err = params->quad_enable(nor); + if (err) + return err; + } else { + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + params = spi_nor_get_params(nor, idx); + if (params) { + if (!params->quad_enable) + return 0;

- err = params->quad_enable(nor); - if (err) - return err; + if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || + spi_nor_get_protocol_width(nor->write_proto) == 4)) + return 0; + /* + * Set the appropriate CS index before + * issuing the command. + */ + nor->spimem->spi->cs_index_mask = 1 << idx; + + err = params->quad_enable(nor); + if (err) + return err; + } } } return err; @@ -2957,17 +3153,29 @@ static int spi_nor_init(struct spi_nor *nor) */ WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, "enabling reset hack; may not recover from unexpected reboots\n"); - for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { - params = spi_nor_get_params(nor, idx); - if (params) { - /* - * Select the appropriate CS index before - * issuing the command. - */ - nor->spimem->spi->cs_index_mask = 0x01 << idx; - err = params->set_4byte_addr_mode(nor, true); - if (err && err != -ENOTSUPP) - return err; + if (nor->flags & SNOR_F_HAS_PARALLEL) { + /* + * In parallel mode both chip selects i.e., CS0 & + * CS1 need to be asserted simulatneously. + */ + nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS; + params = spi_nor_get_params(nor, 0); + err = params->set_4byte_addr_mode(nor, true); + if (err && err != -ENOTSUPP) + return err; + } else { + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + params = spi_nor_get_params(nor, idx); + if (params) { + /* + * Select the appropriate CS index before + * issuing the command. + */ + nor->spimem->spi->cs_index_mask = 1 << idx; + err = params->set_4byte_addr_mode(nor, true); + if (err && err != -ENOTSUPP) + return err; + } } } } @@ -3090,20 +3298,39 @@ void spi_nor_restore(struct spi_nor *nor) /* restore the addressing mode */ if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && nor->flags & SNOR_F_BROKEN_RESET) { - for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { - params = spi_nor_get_params(nor, idx); - if (params) { + if (nor->flags & SNOR_F_HAS_PARALLEL) { + /* + * In parallel mode both chip selects i.e., CS0 & + * CS1 need to be asserted simulatneously. + */ + nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS; + params = spi_nor_get_params(nor, 0); + ret = params->set_4byte_addr_mode(nor, false); + if (ret) + /* + * Do not stop the execution in the hope that the flash + * will default to the 3-byte address mode after the + * software reset. + */ + dev_err(nor->dev, + "Failed to exit 4-byte address mode, err = %d\n", + ret); + } else { + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + params = spi_nor_get_params(nor, idx); + if (!params) + break; /* * Select the appropriate CS index before * issuing the command. */ - nor->spimem->spi->cs_index_mask = 0x01 << idx; + nor->spimem->spi->cs_index_mask = 1 << idx; ret = params->set_4byte_addr_mode(nor, false); if (ret) /* - * Do not stop the execution in the hope that the flash - * will default to the 3-byte address mode after the - * software reset. + * Do not stop the execution in the hope that the + * flash will default to the 3-byte address mode + * after the software reset. */ dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", @@ -3193,7 +3420,16 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor) else mtd->_erase = spi_nor_erase; mtd->writesize = params->writesize; - mtd->writebufsize = params->page_size; + /* + * In parallel-memories the write operation is + * performed on both the flashes simultaneously + * one page per flash, so double the writebufsize. + */ + if (nor->flags & SNOR_F_HAS_PARALLEL) + mtd->writebufsize = params->page_size << 1; + else + mtd->writebufsize = params->page_size; + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { params = spi_nor_get_params(nor, idx); if (params) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index cff2f9c389b8..6c6df417a9c6 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -14,6 +14,9 @@ /* In single configuration enable CS0 */ #define SPI_NOR_ENABLE_CS0 BIT(0)

+/* In parallel configuration enable multiple CS */ +#define SPI_NOR_ENABLE_MULTI_CS (BIT(0) | BIT(1)) + /* Standard SPI NOR flash operations. */ #define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \ @@ -134,6 +137,7 @@ enum spi_nor_option_flags { SNOR_F_SOFT_RESET = BIT(12), SNOR_F_SWP_IS_VOLATILE = BIT(13), SNOR_F_HAS_STACKED = BIT(14), + SNOR_F_HAS_PARALLEL = BIT(15), };

struct spi_nor_read_command { diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index b93e16094b6c..9be39f237dfc 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -357,6 +357,9 @@ static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr) op.data.nbytes = 2; }

+ if (nor->flags & SNOR_F_HAS_PARALLEL) + op.data.nbytes = 2; + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);

ret = spi_mem_exec_op(nor->spimem, &op); @@ -368,6 +371,8 @@ static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr) if (ret) dev_dbg(nor->dev, "error %d reading FSR\n", ret);

+ if (nor->flags & SNOR_F_HAS_PARALLEL) + fsr[0] &= fsr[1]; return ret; }