[PATCH v2] ASoC: Intel: sof_rt5682: add 512FS MCLK clock configuration
codec system clock source support 512FS MCLK synchronous directly, so no need to set PLL configuration when MCLK 24.576MHz.
Suggested-by: Shuming Fan shumingf@realtek.com Signed-off-by: Mac Chiang mac.chiang@intel.com --- Changelog:
v2: - apply mclk configuration to both rt5682vd and rt5682vs - Thanks to Brent by suggesting pll_in condition if MCLK or PLL requires. --- sound/soc/intel/boards/sof_rt5682.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c index bd6d2e7dea53..f4e833cbffe1 100644 --- a/sound/soc/intel/boards/sof_rt5682.c +++ b/sound/soc/intel/boards/sof_rt5682.c @@ -369,11 +369,16 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream,
pll_out = params_rate(params) * 512;
- /* Configure pll for codec */ - ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in, - pll_out); - if (ret < 0) - dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret); + /* when MCLK is 512FS, no need to set PLL configuration additionally. */ + if (pll_in == pll_out) + clk_id = RT5682S_SCLK_S_MCLK; + else { + /* Configure pll for codec */ + ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in, + pll_out); + if (ret < 0) + dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret); + }
/* Configure sysclk for codec */ ret = snd_soc_dai_set_sysclk(codec_dai, clk_id,
On 1/19/22 11:40 PM, Mac Chiang wrote:
codec system clock source support 512FS MCLK synchronous directly, so no need to set PLL configuration when MCLK 24.576MHz.
Suggested-by: Shuming Fan shumingf@realtek.com Signed-off-by: Mac Chiang mac.chiang@intel.com
Changelog:
v2:
- apply mclk configuration to both rt5682vd and rt5682vs
- Thanks to Brent by suggesting pll_in condition if MCLK or PLL requires.
Nice simplification, thanks!
Acked-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com
sound/soc/intel/boards/sof_rt5682.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c index bd6d2e7dea53..f4e833cbffe1 100644 --- a/sound/soc/intel/boards/sof_rt5682.c +++ b/sound/soc/intel/boards/sof_rt5682.c @@ -369,11 +369,16 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream,
pll_out = params_rate(params) * 512;
- /* Configure pll for codec */
- ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in,
pll_out);- if (ret < 0)
dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret);
/* when MCLK is 512FS, no need to set PLL configuration additionally. */
if (pll_in == pll_out)
clk_id = RT5682S_SCLK_S_MCLK;else {
/* Configure pll for codec */ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in,pll_out);if (ret < 0)dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret);}
/* Configure sysclk for codec */ ret = snd_soc_dai_set_sysclk(codec_dai, clk_id,
On Thu, 20 Jan 2022 00:40:12 -0500, Mac Chiang wrote:
codec system clock source support 512FS MCLK synchronous directly, so no need to set PLL configuration when MCLK 24.576MHz.
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/1] ASoC: Intel: sof_rt5682: add 512FS MCLK clock configuration commit: dbf2f8e3fecd5b2197f406f26fed26042664044e
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
participants (3)
-
Mac Chiang -
Mark Brown -
Pierre-Louis Bossart