[PATCH 0/3] Add pin control support for lpass sc7280
This patch series is to make lpass variant independent pin control functions common and to add lpass sc7280 pincontrol support. It also includes dt-bindings for lpass sc7280 lpi compatible.
Srinivasa Rao Mandadapu (3): pinctrl: qcom: Update lpass variant independent functions as generic dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl compatible pinctrl: qcom: Add SC7280 lpass pin configuration
.../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 4 +- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 57 +++++++++++++++++++--- 2 files changed, 52 insertions(+), 9 deletions(-)
Update pin control variable names to make common for all lpass varients.
Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 2f19ab4..c0117c5 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -107,7 +107,7 @@ struct lpi_pinctrl { };
/* sm8250 variant specific data */ -static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { +static const struct pinctrl_pin_desc lpass_lpi_pins[] = { PINCTRL_PIN(0, "gpio0"), PINCTRL_PIN(1, "gpio1"), PINCTRL_PIN(2, "gpio2"), @@ -124,7 +124,8 @@ static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { PINCTRL_PIN(13, "gpio13"), };
-enum sm8250_lpi_functions { + +enum lpass_lpi_functions { LPI_MUX_dmic1_clk, LPI_MUX_dmic1_data, LPI_MUX_dmic2_clk, @@ -203,7 +204,7 @@ static const struct lpi_pingroup sm8250_groups[] = { LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), };
-static const struct lpi_function sm8250_functions[] = { +static const struct lpi_function lpass_functions[] = { LPI_FUNCTION(dmic1_clk), LPI_FUNCTION(dmic1_data), LPI_FUNCTION(dmic2_clk), @@ -228,12 +229,12 @@ static const struct lpi_function sm8250_functions[] = { };
static struct lpi_pinctrl_variant_data sm8250_lpi_data = { - .pins = sm8250_lpi_pins, - .npins = ARRAY_SIZE(sm8250_lpi_pins), + .pins = lpass_lpi_pins, + .npins = ARRAY_SIZE(lpass_lpi_pins), .groups = sm8250_groups, .ngroups = ARRAY_SIZE(sm8250_groups), - .functions = sm8250_functions, - .nfunctions = ARRAY_SIZE(sm8250_functions), + .functions = lpass_functions, + .nfunctions = ARRAY_SIZE(lpass_functions), };
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, @@ -615,7 +616,7 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), "Slew resource not provided\n");
- ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); if (ret) return dev_err_probe(dev, ret, "Can't get clocks\n");
Quoting Srinivasa Rao Mandadapu (2021-10-07 06:48:37)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 2f19ab4..c0117c5 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -124,7 +124,8 @@ static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { PINCTRL_PIN(13, "gpio13"), };
-enum sm8250_lpi_functions {
Please drop this extra newline so the diff makes sense.
+enum lpass_lpi_functions { LPI_MUX_dmic1_clk, LPI_MUX_dmic1_data, LPI_MUX_dmic2_clk, @@ -203,7 +204,7 @@ static const struct lpi_pingroup sm8250_groups[] = { LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), };
-static const struct lpi_function sm8250_functions[] = { +static const struct lpi_function lpass_functions[] = {
Why not follow the approach of other qcom pinctrl drivers and make a core driver that each SoC uses as a library?
LPI_FUNCTION(dmic1_clk), LPI_FUNCTION(dmic1_data), LPI_FUNCTION(dmic2_clk),@@ -615,7 +616,7 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), "Slew resource not provided\n");
ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
Please mention in the commit text why this is now optional.
if (ret) return dev_err_probe(dev, ret, "Can't get clocks\n");
On 10/7/2021 11:27 PM, Stephen Boyd wrote: Thanks for Your Time Stephen!!!
Quoting Srinivasa Rao Mandadapu (2021-10-07 06:48:37)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 2f19ab4..c0117c5 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -124,7 +124,8 @@ static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { PINCTRL_PIN(13, "gpio13"), };
-enum sm8250_lpi_functions {
Please drop this extra newline so the diff makes sense.
Okay.
+enum lpass_lpi_functions { LPI_MUX_dmic1_clk, LPI_MUX_dmic1_data, LPI_MUX_dmic2_clk, @@ -203,7 +204,7 @@ static const struct lpi_pingroup sm8250_groups[] = { LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), };
-static const struct lpi_function sm8250_functions[] = { +static const struct lpi_function lpass_functions[] = {
Why not follow the approach of other qcom pinctrl drivers and make a core driver that each SoC uses as a library?
Actually this driver is for lpass LPI pin control purpose. For this only 14 pins are there and mostly fixed for all platforms.
So I feel for now this approach is fine.
LPI_FUNCTION(dmic1_clk), LPI_FUNCTION(dmic1_data), LPI_FUNCTION(dmic2_clk),@@ -615,7 +616,7 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), "Slew resource not provided\n");
ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);Please mention in the commit text why this is now optional.
Okay. will update commit message accordingly.
if (ret) return dev_err_probe(dev, ret, "Can't get clocks\n");
Add device tree binding compatible name for Qualcomm SC7280 LPASS LPI pinctrl driver.
Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org --- Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml index e47ebf9..578b283 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml @@ -16,7 +16,9 @@ description: |
properties: compatible: - const: qcom,sm8250-lpass-lpi-pinctrl + enum: + - qcom,sc7280-lpass-lpi-pinctrl + - qcom,sm8250-lpass-lpi-pinctrl
reg: minItems: 2
Quoting Srinivasa Rao Mandadapu (2021-10-07 06:48:38)
Add device tree binding compatible name for Qualcomm SC7280 LPASS LPI pinctrl driver.
Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml index e47ebf9..578b283 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml @@ -16,7 +16,9 @@ description: |
properties: compatible:
- const: qcom,sm8250-lpass-lpi-pinctrl
- enum:
- qcom,sc7280-lpass-lpi-pinctrl- qcom,sm8250-lpass-lpi-pinctrl
I suspect we need to split the binding because the function list needs to change. Can you make a whole new file that's probably largely a copy of this file and/or extract the common bits into a meta schema and include that in both the files? Then the function list can be different and the clock property can be omitted in the sc7280 file.
On 10/7/2021 11:29 PM, Stephen Boyd wrote:
Quoting Srinivasa Rao Mandadapu (2021-10-07 06:48:38)
Add device tree binding compatible name for Qualcomm SC7280 LPASS LPI pinctrl driver.
Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml index e47ebf9..578b283 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml @@ -16,7 +16,9 @@ description: |
properties: compatible:
- const: qcom,sm8250-lpass-lpi-pinctrl
- enum:
- qcom,sc7280-lpass-lpi-pinctrl- qcom,sm8250-lpass-lpi-pinctrlI suspect we need to split the binding because the function list needs to change. Can you make a whole new file that's probably largely a copy of this file and/or extract the common bits into a meta schema and include that in both the files? Then the function list can be different and the clock property can be omitted in the sc7280 file.
As most are common functions and fixed number of LPASS Lpi pin configuration across platforms,
Only diff is ADSP bypass platforms 2 clocks are optional. Otherwise clock design also same for SC7280 and SM8250 based architecture.
So I feel Keeping common file is better for now.
Quoting Srinivasa Rao Mandadapu (2021-10-27 00:47:52)
On 10/7/2021 11:29 PM, Stephen Boyd wrote:
Quoting Srinivasa Rao Mandadapu (2021-10-07 06:48:38)
Add device tree binding compatible name for Qualcomm SC7280 LPASS LPI pinctrl driver.
Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml index e47ebf9..578b283 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml @@ -16,7 +16,9 @@ description: |
properties: compatible:
- const: qcom,sm8250-lpass-lpi-pinctrl
- enum:
- qcom,sc7280-lpass-lpi-pinctrl- qcom,sm8250-lpass-lpi-pinctrlI suspect we need to split the binding because the function list needs to change. Can you make a whole new file that's probably largely a copy of this file and/or extract the common bits into a meta schema and include that in both the files? Then the function list can be different and the clock property can be omitted in the sc7280 file.
As most are common functions and fixed number of LPASS Lpi pin configuration across platforms,
Only diff is ADSP bypass platforms 2 clocks are optional. Otherwise clock design also same for SC7280 and SM8250 based architecture.
So I feel Keeping common file is better for now.
I don't agree. We want to be very strict about what is exposed. It needs to match exactly what is supported on the SoC, not be a superset of it.
On Thu, 07 Oct 2021 19:18:38 +0530, Srinivasa Rao Mandadapu wrote:
Add device tree binding compatible name for Qualcomm SC7280 LPASS LPI pinctrl driver.
Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1537726
pinctrl@33c0000: dmic01-active-pins: 'clk', 'data' do not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: dmic01-active-pins: 'function' is a required property arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: dmic01-active-pins: 'pins' is a required property arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: dmic01-sleep-pins: 'clk', 'data' do not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: dmic01-sleep-pins: 'function' is a required property arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: dmic01-sleep-pins: 'pins' is a required property arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: wsa-swr-active-pins: 'clk', 'data' do not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: wsa-swr-active-pins: 'function' is a required property arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: wsa-swr-active-pins: 'pins' is a required property arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: wsa-swr-sleep-pins: 'clk', 'data' do not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: wsa-swr-sleep-pins: 'function' is a required property arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
pinctrl@33c0000: wsa-swr-sleep-pins: 'pins' is a required property arch/arm64/boot/dts/qcom/qrb5165-rb5.dt.yaml arch/arm64/boot/dts/qcom/sm8250-hdk.dt.yaml arch/arm64/boot/dts/qcom/sm8250-mtp.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dt.yaml arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dt.yaml
Update pin control support for SC7280 LPASS LPI.
Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index c0117c5..0b68065 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -122,6 +122,7 @@ static const struct pinctrl_pin_desc lpass_lpi_pins[] = { PINCTRL_PIN(11, "gpio11"), PINCTRL_PIN(12, "gpio12"), PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), };
@@ -137,6 +138,7 @@ enum lpass_lpi_functions { LPI_MUX_i2s1_ws, LPI_MUX_i2s2_clk, LPI_MUX_i2s2_data, + LPI_MUX_sc7280_i2s2_data, LPI_MUX_i2s2_ws, LPI_MUX_qua_mi2s_data, LPI_MUX_qua_mi2s_sclk, @@ -145,6 +147,7 @@ enum lpass_lpi_functions { LPI_MUX_swr_rx_data, LPI_MUX_swr_tx_clk, LPI_MUX_swr_tx_data, + LPI_MUX_sc7280_swr_tx_data, LPI_MUX_wsa_swr_clk, LPI_MUX_wsa_swr_data, LPI_MUX_gpio, @@ -165,8 +168,11 @@ static const unsigned int gpio10_pins[] = { 10 }; static const unsigned int gpio11_pins[] = { 11 }; static const unsigned int gpio12_pins[] = { 12 }; static const unsigned int gpio13_pins[] = { 13 }; +static const unsigned int gpio14_pins[] = { 14 }; + static const char * const swr_tx_clk_groups[] = { "gpio0" }; static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; +static const char * const sc7280_swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; static const char * const swr_rx_clk_groups[] = { "gpio3" }; static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; static const char * const dmic1_clk_groups[] = { "gpio6" }; @@ -186,6 +192,7 @@ static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; static const char * const wsa_swr_clk_groups[] = { "gpio10" }; static const char * const wsa_swr_data_groups[] = { "gpio11" }; static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; +static const char * const sc7280_i2s2_data_groups[] = { "gpio12", "gpio13" };
static const struct lpi_pingroup sm8250_groups[] = { LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), @@ -204,6 +211,24 @@ static const struct lpi_pingroup sm8250_groups[] = { LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), };
+static const struct lpi_pingroup sc7280_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _), + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, sc7280_i2s2_data, _, _), + LPI_PINGROUP(13, NO_SLEW, dmic3_data, sc7280_i2s2_data, _, _), + LPI_PINGROUP(14, 6, sc7280_swr_tx_data, _, _, _), +}; + static const struct lpi_function lpass_functions[] = { LPI_FUNCTION(dmic1_clk), LPI_FUNCTION(dmic1_data), @@ -216,6 +241,7 @@ static const struct lpi_function lpass_functions[] = { LPI_FUNCTION(i2s1_ws), LPI_FUNCTION(i2s2_clk), LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(sc7280_i2s2_data), LPI_FUNCTION(i2s2_ws), LPI_FUNCTION(qua_mi2s_data), LPI_FUNCTION(qua_mi2s_sclk), @@ -224,6 +250,7 @@ static const struct lpi_function lpass_functions[] = { LPI_FUNCTION(swr_rx_data), LPI_FUNCTION(swr_tx_clk), LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(sc7280_swr_tx_data), LPI_FUNCTION(wsa_swr_clk), LPI_FUNCTION(wsa_swr_data), }; @@ -237,6 +264,15 @@ static struct lpi_pinctrl_variant_data sm8250_lpi_data = { .nfunctions = ARRAY_SIZE(lpass_functions), };
+static struct lpi_pinctrl_variant_data sc7280_lpi_data = { + .pins = lpass_lpi_pins, + .npins = ARRAY_SIZE(lpass_lpi_pins), + .groups = sc7280_groups, + .ngroups = ARRAY_SIZE(sc7280_groups), + .functions = lpass_functions, + .nfunctions = ARRAY_SIZE(lpass_functions), +}; + static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) { @@ -678,6 +714,10 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { .compatible = "qcom,sm8250-lpass-lpi-pinctrl", .data = &sm8250_lpi_data, }, + { + .compatible = "qcom,sc7280-lpass-lpi-pinctrl", + .data = &sc7280_lpi_data, + }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
Quoting Srinivasa Rao Mandadapu (2021-10-07 06:48:39)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index c0117c5..0b68065 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -237,6 +264,15 @@ static struct lpi_pinctrl_variant_data sm8250_lpi_data = { .nfunctions = ARRAY_SIZE(lpass_functions), };
+static struct lpi_pinctrl_variant_data sc7280_lpi_data = {
Can this variant data be const?
.pins = lpass_lpi_pins,.npins = ARRAY_SIZE(lpass_lpi_pins),.groups = sc7280_groups,.ngroups = ARRAY_SIZE(sc7280_groups),.functions = lpass_functions,.nfunctions = ARRAY_SIZE(lpass_functions),+};
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) {
On 10/7/2021 11:24 PM, Stephen Boyd wrote:
Quoting Srinivasa Rao Mandadapu (2021-10-07 06:48:39)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index c0117c5..0b68065 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -237,6 +264,15 @@ static struct lpi_pinctrl_variant_data sm8250_lpi_data = { .nfunctions = ARRAY_SIZE(lpass_functions), };
+static struct lpi_pinctrl_variant_data sc7280_lpi_data = {
Can this variant data be const?
Okay. Will change accordingly.
.pins = lpass_lpi_pins,.npins = ARRAY_SIZE(lpass_lpi_pins),.groups = sc7280_groups,.ngroups = ARRAY_SIZE(sc7280_groups),.functions = lpass_functions,.nfunctions = ARRAY_SIZE(lpass_functions),+};
- static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) {
participants (3)
-
Rob Herring -
Srinivasa Rao Mandadapu -
Stephen Boyd