[alsa-devel] [PATCH 1/2] ASoC: fsl-spdif: big-endian support
For most platforms, the CPU and SPDIF device is in the same endianess mode. While for the LS1 platform, the CPU is in LE mode and the SPDIF is in BE mode.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com Cc: Nicolin Chen Guangyu.Chen@freescale.com --- Documentation/devicetree/bindings/sound/fsl,spdif.txt | 4 ++++ sound/soc/fsl/fsl_spdif.c | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt index f2ae335..433ad00 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt @@ -29,6 +29,10 @@ Required properties: can also be referred to TxClk_Source bit of register SPDIF_STC.
+ - big-endian : If this property is absent, the native endian mode will + be in use as default, or the big endian mode will be in use for all the + device registers. + Example:
spdif: spdif@02004000 { diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index 8f36f49..2f8ad75 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -83,6 +83,8 @@ struct fsl_spdif_priv { struct snd_dmaengine_dai_dma_data dma_params_tx; struct snd_dmaengine_dai_dma_data dma_params_rx;
+ bool big_endian; + /* The name space will be allocated dynamically */ char name[0]; }; @@ -985,7 +987,7 @@ static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) } }
-static const struct regmap_config fsl_spdif_regmap_config = { +static struct regmap_config fsl_spdif_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -1105,6 +1107,10 @@ static int fsl_spdif_probe(struct platform_device *pdev) memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); spdif_priv->cpu_dai_drv.name = spdif_priv->name;
+ spdif_priv->big_endian = of_property_read_bool(np, "big-endian"); + if (spdif_priv->big_endian) + fsl_spdif_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG; + /* Get the addresses and IRQ */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_ioremap_resource(&pdev->dev, res);
For most platforms, the CPU and ESAI device is in the same endianess mode. While for the LS1 platform, the CPU is in LE mode and the ESAI is in BE mode.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com Cc: Nicolin Chen Guangyu.Chen@freescale.com --- Documentation/devicetree/bindings/sound/fsl,esai.txt | 6 ++++++ sound/soc/fsl/fsl_esai.c | 7 ++++++- 2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt index d7b99fa..c395371 100644 --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt @@ -34,6 +34,11 @@ Required properties: that ESAI would work in the synchronous mode, which means all the settings for Receiving would be duplicated from Transmition related registers.
+ - big-endian : If this property is absent, the native endian mode will + be in use as default, or the big endian mode will be in use for all the + device registers. + + Example:
esai: esai@02024000 { @@ -46,5 +51,6 @@ esai: esai@02024000 { dma-names = "rx", "tx"; fsl,fifo-depth = <128>; fsl,esai-synchronous; + big-endian; status = "disabled"; }; diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c index c84026c..e1f2669 100644 --- a/sound/soc/fsl/fsl_esai.c +++ b/sound/soc/fsl/fsl_esai.c @@ -57,6 +57,7 @@ struct fsl_esai { bool sck_div[2]; bool slave_mode; bool synchronous; + bool big_endian; char name[32]; };
@@ -661,7 +662,7 @@ static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) } }
-static const struct regmap_config fsl_esai_regmap_config = { +static struct regmap_config fsl_esai_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -687,6 +688,10 @@ static int fsl_esai_probe(struct platform_device *pdev) esai_priv->pdev = pdev; strcpy(esai_priv->name, np->name);
+ esai_priv->big_endian = of_property_read_bool(np, "big-endian"); + if (esai_priv->big_endian) + fsl_esai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG; + /* Get the addresses and IRQ */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_ioremap_resource(&pdev->dev, res);
On Tue, Feb 11, 2014 at 01:41:16PM +0800, Xiubo Li wrote:
For most platforms, the CPU and ESAI device is in the same endianess mode. While for the LS1 platform, the CPU is in LE mode and the ESAI is in BE mode.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com Cc: Nicolin Chen Guangyu.Chen@freescale.com
Documentation/devicetree/bindings/sound/fsl,esai.txt | 6 ++++++ sound/soc/fsl/fsl_esai.c | 7 ++++++- 2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt index d7b99fa..c395371 100644 --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt @@ -34,6 +34,11 @@ Required properties: that ESAI would work in the synchronous mode, which means all the settings for Receiving would be duplicated from Transmition related registers.
- big-endian : If this property is absent, the native endian mode will
- be in use as default, or the big endian mode will be in use for all the
- device registers.
Single blank line should be enough here :)
Example:
esai: esai@02024000 { @@ -46,5 +51,6 @@ esai: esai@02024000 { dma-names = "rx", "tx"; fsl,fifo-depth = <128>; fsl,esai-synchronous;
- big-endian; status = "disabled";
}; diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c index c84026c..e1f2669 100644 --- a/sound/soc/fsl/fsl_esai.c +++ b/sound/soc/fsl/fsl_esai.c @@ -57,6 +57,7 @@ struct fsl_esai { bool sck_div[2]; bool slave_mode; bool synchronous;
- bool big_endian; char name[32];
};
@@ -661,7 +662,7 @@ static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) } }
-static const struct regmap_config fsl_esai_regmap_config = { +static struct regmap_config fsl_esai_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -687,6 +688,10 @@ static int fsl_esai_probe(struct platform_device *pdev) esai_priv->pdev = pdev; strcpy(esai_priv->name, np->name);
- esai_priv->big_endian = of_property_read_bool(np, "big-endian");
- if (esai_priv->big_endian)
fsl_esai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
Same comments here. And please wait for Shawn's reply at the other patch before you revise this part to V2.
Thanks.
/* Get the addresses and IRQ */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_ioremap_resource(&pdev->dev, res); -- 1.8.4
- big-endian : If this property is absent, the native endian mode will
- be in use as default, or the big endian mode will be in use for all the
- device registers.
Single blank line should be enough here :)
This will be removed.
@@ -687,6 +688,10 @@ static int fsl_esai_probe(struct platform_device *pdev) esai_priv->pdev = pdev; strcpy(esai_priv->name, np->name);
- esai_priv->big_endian = of_property_read_bool(np, "big-endian");
- if (esai_priv->big_endian)
fsl_esai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;Same comments here. And please wait for Shawn's reply at the other patch before you revise this part to V2.
Okey,
Thanks,
-- Best Regards, Xiubo
On Tue, Feb 11, 2014 at 01:41:15PM +0800, Xiubo Li wrote:
For most platforms, the CPU and SPDIF device is in the same endianess mode. While for the LS1 platform, the CPU is in LE mode and the SPDIF is in BE mode.
Signed-off-by: Xiubo Li Li.Xiubo@freescale.com Cc: Nicolin Chen Guangyu.Chen@freescale.com
Documentation/devicetree/bindings/sound/fsl,spdif.txt | 4 ++++ sound/soc/fsl/fsl_spdif.c | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt index f2ae335..433ad00 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt @@ -29,6 +29,10 @@ Required properties: can also be referred to TxClk_Source bit of register SPDIF_STC.
- big-endian : If this property is absent, the native endian mode will
- be in use as default, or the big endian mode will be in use for all the
- device registers.
@Shawn Does DT have an existing approach to determine if the current SoC this IP uses is BE or LE? I am thinking the scenario that if all drivers support BE/LE while the SoC is big-endian, all the nodes in the DT would have to include a duplicated property (big-endian).
Example:
spdif: spdif@02004000 { diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index 8f36f49..2f8ad75 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -83,6 +83,8 @@ struct fsl_spdif_priv { struct snd_dmaengine_dai_dma_data dma_params_tx; struct snd_dmaengine_dai_dma_data dma_params_rx;
- bool big_endian;
- /* The name space will be allocated dynamically */ char name[0];
}; @@ -985,7 +987,7 @@ static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) } }
-static const struct regmap_config fsl_spdif_regmap_config = { +static struct regmap_config fsl_spdif_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -1105,6 +1107,10 @@ static int fsl_spdif_probe(struct platform_device *pdev) memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); spdif_priv->cpu_dai_drv.name = spdif_priv->name;
- spdif_priv->big_endian = of_property_read_bool(np, "big-endian");
- if (spdif_priv->big_endian)
fsl_spdif_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
Why not just: if (of_property_read_bool(np, "big-endian")) fsl_spdif_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
- /* Get the addresses and IRQ */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_ioremap_resource(&pdev->dev, res);
-- 1.8.4
- spdif_priv->big_endian = of_property_read_bool(np, "big-endian");
- if (spdif_priv->big_endian)
fsl_spdif_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;Why not just: if (of_property_read_bool(np, "big-endian")) fsl_spdif_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
I just think maybe other places of the driver maybe use this. Yes, it could be removed just for now.
See the next version please.
Thanks very much,
-- Best Regards, Xiubo
- big-endian : If this property is absent, the native endian mode will
- be in use as default, or the big endian mode will be in use for all the
- device registers.
@Shawn Does DT have an existing approach to determine if the current SoC this IP uses is BE or LE? I am thinking the scenario that if all drivers support BE/LE while the SoC is big-endian, all the nodes in the DT would have to include a duplicated property (big-endian).
@Nicolin, @Shawn One special scenario likes the LS1 platform, the CPU and a few devices are in LE mode and other devices will be in BE mode.
Thanks,
-- Best Regards, Xiubo
On Tue, Feb 11, 2014 at 03:39:44PM +0800, Xiubo Li-B47053 wrote:
- big-endian : If this property is absent, the native endian mode will
- be in use as default, or the big endian mode will be in use for all the
- device registers.
@Shawn Does DT have an existing approach to determine if the current SoC this IP uses is BE or LE? I am thinking the scenario that if all drivers support BE/LE while the SoC is big-endian, all the nodes in the DT would have to include a duplicated property (big-endian).
@Nicolin, @Shawn One special scenario likes the LS1 platform, the CPU and a few devices are in LE mode and other devices will be in BE mode.
Hmm... a bit strange to me. But I think it then should be fine here if it's plausible as you describe.
Please revise the patch and send it to see if there's any comment from others.
And for both revised patches: Acked-by: Nicolin Chen Guangyu.Chen@freescale.com
Thank you
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