From: Weidong Wang wangweidong.a@awinic.com

The Awinic AW883XX is an I2S/TDM input, high efficiency digital Smart K audio amplifier with an integrated 10.25V smart boost convert

Signed-off-by: Nick Li liweilei@awinic.com Signed-off-by: Bruce zhao zhaolei@awinic.com Signed-off-by: Weidong Wang wangweidong.a@awinic.com --- sound/soc/codecs/aw883xx/aw883xx.c | 1803 ++++++++++++++++++++++++++++ sound/soc/codecs/aw883xx/aw883xx.h | 155 +++ 2 files changed, 1958 insertions(+) create mode 100644 sound/soc/codecs/aw883xx/aw883xx.c create mode 100644 sound/soc/codecs/aw883xx/aw883xx.h

diff --git a/sound/soc/codecs/aw883xx/aw883xx.c b/sound/soc/codecs/aw883xx/aw883xx.c new file mode 100644 index 000000000000..b22ec3419e9e --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx.c @@ -0,0 +1,1803 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/debugfs.h> +#include <linux/firmware.h> +#include <linux/hrtimer.h> +#include <linux/i2c.h> +#include <linux/input.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/regmap.h> +#include <linux/syscalls.h> +#include <linux/timer.h> +#include <linux/uaccess.h> +#include <linux/version.h> +#include <linux/vmalloc.h> +#include <linux/workqueue.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/tlv.h> +#include "aw883xx_pid_2049_reg.h" +#include "aw883xx.h" +#include "aw883xx_bin_parse.h" +#include "aw883xx_device.h" + +/* + * Marco + */ +#define AW883XX_I2C_NAME "aw883xx_smartpa" + +#define AW883XX_RATES (SNDRV_PCM_RATE_8000_48000 | \ + SNDRV_PCM_RATE_96000) +#define AW883XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) +#define AW883XX_ACF_FILE "aw883xx_acf.bin" +#define AW_REQUEST_FW_RETRIES 5 /* 5 times */ +#define AW_SYNC_LOAD + +#define FADE_TIME_MAX 1000000 +#define FADE_TIME_MIN 0 + +static DEFINE_MUTEX(g_aw883xx_lock); + +static const struct regmap_config aw883xx_remap_config = { + .val_bits = 16, + .reg_bits = 8, + .max_register = AW_PID_2049_REG_MAX - 1, +}; + +/* + * aw883xx distinguish between codecs and components by version + */ +static struct aw_componet_codec_ops aw_componet_codec_ops = { + .kcontrol_codec = snd_soc_kcontrol_component, + .codec_get_drvdata = snd_soc_component_get_drvdata, + .add_codec_controls = snd_soc_add_component_controls, + .unregister_codec = snd_soc_unregister_component, + .register_codec = snd_soc_register_component, +}; + +/* + * aw883xx dsp write/read + */ +static int aw883xx_dsp_write_16bit(struct aw883xx *aw883xx, + uint16_t dsp_addr, uint32_t dsp_data) +{ + int ret; + struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc; + + ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, (uint16_t)dsp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + return 0; +} + +static int aw883xx_dsp_write_32bit(struct aw883xx *aw883xx, + uint16_t dsp_addr, uint32_t dsp_data) +{ + int ret; + uint16_t temp_data = 0; + struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc; + + ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + temp_data = dsp_data & AW883XX_DSP_16_DATA_MASK; + ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + temp_data = dsp_data >> 16; + ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + return 0; +} + +/* + * aw883xx clear dsp chip select state + */ +static void aw883xx_clear_dsp_sel_st(struct aw883xx *aw883xx) +{ + unsigned int reg_value; + uint8_t reg = aw883xx->aw_pa->soft_rst.reg; + + regmap_read(aw883xx->regmap, reg, &reg_value); +} + +int aw883xx_dsp_write(struct aw883xx *aw883xx, + uint16_t dsp_addr, uint32_t dsp_data, uint8_t data_type) +{ + int ret = -1; + + mutex_lock(&aw883xx->dsp_lock); + if (data_type == AW_DSP_16_DATA) { + ret = aw883xx_dsp_write_16bit(aw883xx, dsp_addr, dsp_data); + if (ret < 0) + dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 16 bit dsp_data[%04x] failed", + (uint32_t)dsp_addr, dsp_data); + + } else if (data_type == AW_DSP_32_DATA) { + ret = aw883xx_dsp_write_32bit(aw883xx, dsp_addr, dsp_data); + if (ret < 0) + dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 32 bit dsp_data[%08x] failed", + (uint32_t)dsp_addr, dsp_data); + } else { + dev_err(aw883xx->dev, "data type[%d] unsupported", data_type); + ret = -EINVAL; + } + + aw883xx_clear_dsp_sel_st(aw883xx); + mutex_unlock(&aw883xx->dsp_lock); + return ret; +} + +static int aw883xx_dsp_read_16bit(struct aw883xx *aw883xx, + uint16_t dsp_addr, uint32_t *dsp_data) +{ + int ret; + unsigned int temp_data = 0; + struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc; + + ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c write error, ret=%d", ret); + return ret; + } + + ret = regmap_read(aw883xx->regmap, desc->dsp_mdat_reg, &temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c write error, ret=%d", ret); + return ret; + } + + *dsp_data = temp_data; + + return 0; +} + +static int aw883xx_dsp_read_32bit(struct aw883xx *aw883xx, + uint16_t dsp_addr, uint32_t *dsp_data) +{ + int ret; + unsigned int temp_data = 0; + struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc; + + /*write dsp addr*/ + ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c write error, ret=%d", ret); + return ret; + } + + /*get Low 16 bit data*/ + ret = regmap_read(aw883xx->regmap, desc->dsp_mdat_reg, &temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c read error, ret=%d", ret); + return ret; + } + + *dsp_data = temp_data; + + /*get high 16 bit data*/ + ret = regmap_read(aw883xx->regmap, desc->dsp_mdat_reg, &temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c read error, ret=%d", ret); + return ret; + } + *dsp_data |= (temp_data << 16); + + return 0; +} + +int aw883xx_dsp_read(struct aw883xx *aw883xx, + uint16_t dsp_addr, uint32_t *dsp_data, uint8_t data_type) +{ + int ret = -1; + + mutex_lock(&aw883xx->dsp_lock); + if (data_type == AW_DSP_16_DATA) { + ret = aw883xx_dsp_read_16bit(aw883xx, dsp_addr, dsp_data); + if (ret < 0) + dev_err(aw883xx->dev, "read dsp_addr[0x%04x] 16 bit dsp_data[%04x] failed", + (uint32_t)dsp_addr, *dsp_data); + + } else if (data_type == AW_DSP_32_DATA) { + ret = aw883xx_dsp_read_32bit(aw883xx, dsp_addr, dsp_data); + if (ret < 0) + dev_err(aw883xx->dev, "read dsp_addr[0x%04x] 32 bit dsp_data[%08x] failed", + (uint32_t)dsp_addr, *dsp_data); + } else { + dev_err(aw883xx->dev, "data type[%d] unsupported", data_type); + ret = -EINVAL; + } + + aw883xx_clear_dsp_sel_st(aw883xx); + mutex_unlock(&aw883xx->dsp_lock); + return ret; +} + +static void aw883xx_start_pa(struct aw883xx *aw883xx) +{ + int ret, i; + + if (!aw883xx->allow_pw) { + dev_info(aw883xx->dev, "%s:dev can not allow power", __func__); + return; + } + + if (aw883xx->pstream == AW883XX_STREAM_CLOSE) { + dev_info(aw883xx->dev, "%s:pstream is close", __func__); + return; + } + + for (i = 0; i < AW_START_RETRIES; i++) { + ret = aw883xx_device_start(aw883xx->aw_pa); + if (ret) { + dev_err(aw883xx->dev, "aw883xx device start failed. retry = %d", i); + ret = aw883xx_dev_fw_update(aw883xx->aw_pa, AW_DSP_FW_UPDATE_ON, true); + if (ret < 0) { + dev_err(aw883xx->dev, "fw update failed"); + continue; + } + } else { + dev_info(aw883xx->dev, "start success\n"); + break; + } + } +} + +static void aw883xx_startup_work(struct work_struct *work) +{ + struct aw883xx *aw883xx = + container_of(work, struct aw883xx, start_work.work); + + mutex_lock(&aw883xx->lock); + aw883xx_start_pa(aw883xx); + mutex_unlock(&aw883xx->lock); +} + +static void aw883xx_start(struct aw883xx *aw883xx, bool sync_start) +{ + int ret; + int i; + + if (aw883xx->aw_pa->fw_status == AW_DEV_FW_OK) { + if (!aw883xx->allow_pw) { + dev_info(aw883xx->dev, "%s:dev can not allow power", __func__); + return; + } + + if (aw883xx->aw_pa->status == AW_DEV_PW_ON) + return; + + for (i = 0; i < AW_START_RETRIES; i++) { + ret = aw883xx_dev_fw_update(aw883xx->aw_pa, AW_DSP_FW_UPDATE_OFF, + aw883xx->phase_sync); + if (ret < 0) { + dev_err(aw883xx->dev, "fw update failed. retry = %d", i); + continue; + } else { + /*firmware update success*/ + if (sync_start == AW_SYNC_START) + aw883xx_start_pa(aw883xx); + else + queue_delayed_work(aw883xx->work_queue, + &aw883xx->start_work, + AW883XX_START_WORK_DELAY_MS); + + return; + } + } + } +} + +/* + * Digital Audio Interface + */ +static int aw883xx_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *codec = dai->component; + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + + aw883xx->pstream = AW883XX_STREAM_OPEN; + + mutex_lock(&aw883xx->lock); + aw883xx_start(aw883xx, AW_ASYNC_START); + mutex_unlock(&aw883xx->lock); + + return 0; +} + +static void aw883xx_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *codec = dai->component; + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + + aw883xx->pstream = AW883XX_STREAM_CLOSE; + cancel_delayed_work_sync(&aw883xx->start_work); + mutex_lock(&aw883xx->lock); + aw883xx_device_stop(aw883xx->aw_pa); + mutex_unlock(&aw883xx->lock); + +} + +static const struct snd_soc_dai_ops aw883xx_dai_ops = { + .startup = aw883xx_startup, + .shutdown = aw883xx_shutdown, +}; + +static struct snd_soc_dai_driver aw883xx_dai[] = { + { + .name = "aw883xx-aif", + .id = 1, + .playback = { + .stream_name = "Speaker_Playback", + .channels_min = 1, + .channels_max = 2, + .rates = AW883XX_RATES, + .formats = AW883XX_FORMATS, + }, + .capture = { + .stream_name = "Speaker_Capture", + .channels_min = 1, + .channels_max = 2, + .rates = AW883XX_RATES, + .formats = AW883XX_FORMATS, + }, + .ops = &aw883xx_dai_ops, + /*.symmetric_rates = 1,*/ + }, +}; + +static int aw883xx_fade_time_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + /* set kcontrol info */ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1000000; + + return 0; +} + +/* + * codec driver + */ +static int aw883xx_get_fade_in_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int time; + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component); + struct aw_device *aw_dev = aw883xx->aw_pa; + + aw883xx_dev_get_fade_time(&time, true, aw_dev); + ucontrol->value.integer.value[0] = time; + + pr_debug("step time %ld", ucontrol->value.integer.value[0]); + + return 0; + +} + +static int aw883xx_set_fade_in_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component); + struct aw_device *aw_dev = aw883xx->aw_pa; + + if ((ucontrol->value.integer.value[0] > FADE_TIME_MAX) || + (ucontrol->value.integer.value[0] < FADE_TIME_MIN)) { + pr_debug("set val %ld overflow %d or less than :%d", + ucontrol->value.integer.value[0], FADE_TIME_MAX, FADE_TIME_MAX); + return 0; + } + + aw883xx_dev_set_fade_time(ucontrol->value.integer.value[0], true, aw_dev); + + pr_debug("step time %ld", ucontrol->value.integer.value[0]); + return 1; +} + +static int aw883xx_get_fade_out_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int time; + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component); + struct aw_device *aw_dev = aw883xx->aw_pa; + + aw883xx_dev_get_fade_time(&time, false, aw_dev); + ucontrol->value.integer.value[0] = time; + + pr_debug("step time %ld", ucontrol->value.integer.value[0]); + + return 0; +} + +static int aw883xx_set_fade_out_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component); + struct aw_device *aw_dev = aw883xx->aw_pa; + + if ((ucontrol->value.integer.value[0] > FADE_TIME_MAX) || + (ucontrol->value.integer.value[0] < FADE_TIME_MIN)) { + pr_err("set val %ld overflow %d or less than :%d", + ucontrol->value.integer.value[0], FADE_TIME_MAX, FADE_TIME_MIN); + return 0; + } + + aw883xx_dev_set_fade_time(ucontrol->value.integer.value[0], false, aw_dev); + + pr_debug("step time %ld", ucontrol->value.integer.value[0]); + + return 1; +} + +static int aw883xx_profile_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + int count; + char *name = NULL; + const char *prof_name = NULL; + struct snd_soc_component *codec = + aw_componet_codec_ops.kcontrol_codec(kcontrol); + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; + uinfo->count = 1; + + count = aw883xx_dev_get_profile_count(aw883xx->aw_pa); + if (count <= 0) { + uinfo->value.enumerated.items = 0; + dev_err(aw883xx->dev, "get count[%d] failed", count); + return 0; + } + + uinfo->value.enumerated.items = count; + + if (uinfo->value.enumerated.item >= count) + uinfo->value.enumerated.item = count - 1; + + name = uinfo->value.enumerated.name; + count = uinfo->value.enumerated.item; + + prof_name = aw_dev_get_prof_name(aw883xx->aw_pa, count); + if (!prof_name) { + strscpy(uinfo->value.enumerated.name, "null", + strlen("null") + 1); + return 0; + } + + strscpy(name, prof_name, sizeof(uinfo->value.enumerated.name)); + + return 0; +} + +static int aw883xx_profile_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = + aw_componet_codec_ops.kcontrol_codec(kcontrol); + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = aw883xx_dev_get_profile_index(aw883xx->aw_pa); + dev_dbg(codec->dev, "profile index [%d]", + aw883xx_dev_get_profile_index(aw883xx->aw_pa)); + return 0; + +} + +static int aw883xx_profile_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = + aw_componet_codec_ops.kcontrol_codec(kcontrol); + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + int ret; + int cur_index; + + if (!aw883xx->dbg_en_prof) { + dev_info(codec->dev, "profile close"); + return 0; + } + + /* check value valid */ + ret = aw883xx_dev_check_profile_index(aw883xx->aw_pa, ucontrol->value.integer.value[0]); + if (ret) { + dev_warn(codec->dev, "unsupported index %ld", + ucontrol->value.integer.value[0]); + return 0; + } + + /*check cur_index == set value*/ + cur_index = aw883xx_dev_get_profile_index(aw883xx->aw_pa); + if (cur_index == ucontrol->value.integer.value[0]) { + dev_info(codec->dev, "index no change"); + return 0; + } + + /*pa stop or stopping just set profile*/ + mutex_lock(&aw883xx->lock); + aw883xx_dev_set_profile_index(aw883xx->aw_pa, ucontrol->value.integer.value[0]); + + if (aw883xx->pstream) { + aw883xx_device_stop(aw883xx->aw_pa); + aw883xx_start(aw883xx, AW_SYNC_START); + } + + mutex_unlock(&aw883xx->lock); + + dev_dbg(codec->dev, "profile id %ld", ucontrol->value.integer.value[0]); + return 1; +} + +static int aw883xx_switch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = + aw_componet_codec_ops.kcontrol_codec(kcontrol); + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = aw883xx->allow_pw; + + return 0; +} + +static int aw883xx_switch_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = + aw_componet_codec_ops.kcontrol_codec(kcontrol); + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + + dev_dbg(codec->dev, "set value:%ld", ucontrol->value.integer.value[0]); + + if (ucontrol->value.integer.value[0] == aw883xx->allow_pw) { + dev_info(aw883xx->dev, "PA switch not change"); + return 0; + } + + if (aw883xx->pstream) { + if (ucontrol->value.integer.value[0] == 0) { + cancel_delayed_work_sync(&aw883xx->start_work); + mutex_lock(&aw883xx->lock); + aw883xx_device_stop(aw883xx->aw_pa); + aw883xx->allow_pw = false; + mutex_unlock(&aw883xx->lock); + } else { + cancel_delayed_work_sync(&aw883xx->start_work); + mutex_lock(&aw883xx->lock); + aw883xx->allow_pw = true; + aw883xx_start(aw883xx, AW_SYNC_START); + mutex_unlock(&aw883xx->lock); + } + } else { + mutex_lock(&aw883xx->lock); + if (ucontrol->value.integer.value[0] == 0) + aw883xx->allow_pw = false; + else + aw883xx->allow_pw = true; + mutex_unlock(&aw883xx->lock); + } + + return 1; +} + +static int aw883xx_volume_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct snd_soc_component *codec = + aw_componet_codec_ops.kcontrol_codec(kcontrol); + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc; + + /* set kcontrol info */ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = vol_desc->mute_volume; + + return 0; +} + +static int aw883xx_volume_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = + aw_componet_codec_ops.kcontrol_codec(kcontrol); + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc; + + ucontrol->value.integer.value[0] = vol_desc->ctl_volume; + + dev_dbg(aw883xx->dev, "ucontrol->value.integer.value[0]=%d", + vol_desc->ctl_volume); + + return 0; +} + +static int aw883xx_volume_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + uint16_t value = 0; + uint16_t compared_vol = 0; + struct snd_soc_component *codec = + aw_componet_codec_ops.kcontrol_codec(kcontrol); + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(codec); + struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc; + + value = (uint16_t)ucontrol->value.integer.value[0]; + if (value > vol_desc->mute_volume) { + dev_err(aw883xx->dev, "value over range\n"); + return -EINVAL; + } + + dev_dbg(aw883xx->dev, "ucontrol->value.integer.value[0]=%d", value); + + vol_desc->ctl_volume = value; + + /*get smaller dB*/ + compared_vol = AW_GET_MAX_VALUE(vol_desc->ctl_volume, + vol_desc->monitor_volume); + + aw883xx_dev_set_volume(aw883xx->aw_pa, compared_vol); + + return 1; +} + +static int aw883xx_dynamic_create_controls(struct aw883xx *aw883xx) +{ + struct snd_kcontrol_new *aw883xx_dev_control = NULL; + char *kctl_name = NULL; + + aw883xx_dev_control = devm_kzalloc(aw883xx->codec->dev, + sizeof(struct snd_kcontrol_new) * AW_KCONTROL_NUM, GFP_KERNEL); + if (!aw883xx_dev_control) + return -ENOMEM; + + kctl_name = devm_kzalloc(aw883xx->codec->dev, AW_NAME_BUF_MAX, GFP_KERNEL); + if (!kctl_name) + return -ENOMEM; + + snprintf(kctl_name, AW_NAME_BUF_MAX, "aw_dev_%u_prof", + aw883xx->aw_pa->channel); + + aw883xx_dev_control[0].name = kctl_name; + aw883xx_dev_control[0].iface = SNDRV_CTL_ELEM_IFACE_MIXER; + aw883xx_dev_control[0].info = aw883xx_profile_info; + aw883xx_dev_control[0].get = aw883xx_profile_get; + aw883xx_dev_control[0].put = aw883xx_profile_set; + + kctl_name = devm_kzalloc(aw883xx->codec->dev, AW_NAME_BUF_MAX, GFP_KERNEL); + if (!kctl_name) + return -ENOMEM; + + snprintf(kctl_name, AW_NAME_BUF_MAX, "aw_dev_%u_switch", aw883xx->aw_pa->channel); + + aw883xx_dev_control[1].name = kctl_name; + aw883xx_dev_control[1].iface = SNDRV_CTL_ELEM_IFACE_MIXER; + aw883xx_dev_control[1].info = snd_soc_info_bool_ext; + aw883xx_dev_control[1].get = aw883xx_switch_get; + aw883xx_dev_control[1].put = aw883xx_switch_set; + + kctl_name = devm_kzalloc(aw883xx->codec->dev, AW_NAME_BUF_MAX, GFP_KERNEL); + if (!kctl_name) + return -ENOMEM; + + snprintf(kctl_name, AW_NAME_BUF_MAX, "aw_dev_%d_rx_volume", aw883xx->aw_pa->channel); + + aw883xx_dev_control[2].name = kctl_name; + aw883xx_dev_control[2].iface = SNDRV_CTL_ELEM_IFACE_MIXER; + aw883xx_dev_control[2].info = aw883xx_volume_info; + aw883xx_dev_control[2].get = aw883xx_volume_get; + aw883xx_dev_control[2].put = aw883xx_volume_set; + + kctl_name = devm_kzalloc(aw883xx->codec->dev, AW_NAME_BUF_MAX, GFP_KERNEL); + if (!kctl_name) + return -ENOMEM; + + snprintf(kctl_name, AW_NAME_BUF_MAX, "aw_dev_%d_fadeout_us", aw883xx->aw_pa->channel); + + aw883xx_dev_control[3].name = kctl_name; + aw883xx_dev_control[3].iface = SNDRV_CTL_ELEM_IFACE_MIXER; + aw883xx_dev_control[3].info = aw883xx_fade_time_info; + aw883xx_dev_control[3].get = aw883xx_get_fade_out_time; + aw883xx_dev_control[3].put = aw883xx_set_fade_out_time; + + kctl_name = devm_kzalloc(aw883xx->codec->dev, AW_NAME_BUF_MAX, GFP_KERNEL); + if (!kctl_name) + return -ENOMEM; + + snprintf(kctl_name, AW_NAME_BUF_MAX, "aw_dev_%d_fadein_us", aw883xx->aw_pa->channel); + + aw883xx_dev_control[4].name = kctl_name; + aw883xx_dev_control[4].iface = SNDRV_CTL_ELEM_IFACE_MIXER; + aw883xx_dev_control[4].info = aw883xx_fade_time_info; + aw883xx_dev_control[4].get = aw883xx_get_fade_in_time; + aw883xx_dev_control[4].put = aw883xx_set_fade_in_time; + + aw_componet_codec_ops.add_codec_controls(aw883xx->codec, + aw883xx_dev_control, AW_KCONTROL_NUM); + + return 0; +} + +static int aw883xx_request_firmware_file(struct aw883xx *aw883xx) +{ + const struct firmware *cont = NULL; + int ret = -1; + + aw883xx->aw_pa->fw_status = AW_DEV_FW_FAILED; + + ret = request_firmware(&cont, AW883XX_ACF_FILE, aw883xx->dev); + if ((ret < 0) || (!cont)) { + dev_err(aw883xx->dev, "load [%s] failed!", AW883XX_ACF_FILE); + return ret; + } + + dev_info(aw883xx->dev, "loaded %s - size: %zu", + AW883XX_ACF_FILE, cont ? cont->size : 0); + + aw883xx->aw_cfg = vzalloc(cont->size + sizeof(int)); + if (!aw883xx->aw_cfg) { + release_firmware(cont); + return -ENOMEM; + } + aw883xx->aw_cfg->len = (int)cont->size; + memcpy(aw883xx->aw_cfg->data, cont->data, cont->size); + ret = aw883xx_dev_load_acf_check(aw883xx->aw_cfg); + if (ret < 0) { + dev_err(aw883xx->dev, "Load [%s] failed ....!", AW883XX_ACF_FILE); + vfree(aw883xx->aw_cfg); + aw883xx->aw_cfg = NULL; + release_firmware(cont); + return ret; + } + release_firmware(cont); + + mutex_lock(&aw883xx->lock); + /*aw device init*/ + ret = aw883xx_device_init(aw883xx->aw_pa, aw883xx->aw_cfg); + if (ret < 0) { + dev_info(aw883xx->dev, "dev init failed"); + mutex_unlock(&aw883xx->lock); + return ret; + } + + aw883xx_dynamic_create_controls(aw883xx); + + mutex_unlock(&aw883xx->lock); + + return 0; +} + +static void aw883xx_fw_wrok(struct work_struct *work) +{ + struct aw883xx *aw883xx = container_of(work, + struct aw883xx, acf_work.work); + int ret; + + ret = aw883xx_request_firmware_file(aw883xx); + if (ret < 0) + dev_err(aw883xx->dev, "load profile failed"); +} + +static void aw883xx_load_fw(struct aw883xx *aw883xx) +{ +#ifdef AW_SYNC_LOAD + /*sync loading*/ + aw883xx_request_firmware_file(aw883xx); +#else + /*async loading*/ + queue_delayed_work(aw883xx->work_queue, + &aw883xx->acf_work, + msecs_to_jiffies(AW883XX_LOAD_FW_DELAY_TIME)); + +#endif +} + +static const struct snd_soc_dapm_widget aw883xx_dapm_widgets[] = { + /* playback */ + SND_SOC_DAPM_AIF_IN("AIF_RX", "Speaker_Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_OUTPUT("audio_out"), + /* capture */ + SND_SOC_DAPM_AIF_OUT("AIF_TX", "Speaker_Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_INPUT("iv_in"), +}; + +static const struct snd_soc_dapm_route aw883xx_audio_map[] = { + {"audio_out", NULL, "AIF_RX"}, + {"AIF_TX", NULL, "iv_in"}, +}; + +static int aw883xx_add_widgets(struct aw883xx *aw883xx) +{ + struct snd_soc_dapm_widget *aw_widgets = NULL; + struct snd_soc_dapm_route *aw_route = NULL; + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(aw883xx->codec); + + /*add widgets*/ + aw_widgets = devm_kzalloc(aw883xx->dev, + sizeof(struct snd_soc_dapm_widget) * + ARRAY_SIZE(aw883xx_dapm_widgets), + GFP_KERNEL); + if (!aw_widgets) + return -ENOMEM; + + memcpy(aw_widgets, aw883xx_dapm_widgets, + sizeof(struct snd_soc_dapm_widget) * ARRAY_SIZE(aw883xx_dapm_widgets)); + + snd_soc_dapm_new_controls(dapm, aw_widgets, ARRAY_SIZE(aw883xx_dapm_widgets)); + + /*add route*/ + aw_route = devm_kzalloc(aw883xx->dev, + sizeof(struct snd_soc_dapm_route) * ARRAY_SIZE(aw883xx_audio_map), + GFP_KERNEL); + if (!aw_route) + return -ENOMEM; + + memcpy(aw_route, aw883xx_audio_map, + sizeof(struct snd_soc_dapm_route) * ARRAY_SIZE(aw883xx_audio_map)); + + snd_soc_dapm_add_routes(dapm, aw_route, ARRAY_SIZE(aw883xx_audio_map)); + + return 0; +} + +static int aw883xx_codec_probe(struct snd_soc_component *aw_codec) +{ + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(aw_codec); + + /*destroy_workqueue(struct workqueue_struct *wq)*/ + aw883xx->work_queue = create_singlethread_workqueue("aw883xx"); + if (!aw883xx->work_queue) { + dev_err(aw883xx->dev, "create workqueue failed !"); + return -EINVAL; + } + + INIT_DELAYED_WORK(&aw883xx->start_work, aw883xx_startup_work); + + INIT_DELAYED_WORK(&aw883xx->acf_work, aw883xx_fw_wrok); + + aw883xx->codec = aw_codec; + + aw883xx_add_widgets(aw883xx); + + aw883xx_load_fw(aw883xx); + + return 0; +} + +static void aw883xx_codec_remove(struct snd_soc_component *aw_codec) +{ + struct aw883xx *aw883xx = + aw_componet_codec_ops.codec_get_drvdata(aw_codec); + + cancel_delayed_work_sync(&aw883xx->acf_work); + cancel_delayed_work_sync(&aw883xx->start_work); + + if (aw883xx->work_queue) + destroy_workqueue(aw883xx->work_queue); + + aw883xx_dev_deinit(aw883xx->aw_pa); +} + +static const struct snd_soc_component_driver soc_codec_dev_aw883xx = { + .probe = aw883xx_codec_probe, + .remove = aw883xx_codec_remove, +}; + +static int aw883xx_componet_codec_register(struct aw883xx *aw883xx) +{ + struct snd_soc_dai_driver *dai_drv = NULL; + int ret; + + dai_drv = devm_kzalloc(aw883xx->dev, sizeof(aw883xx_dai), GFP_KERNEL); + if (!dai_drv) + return -ENOMEM; + + memcpy(dai_drv, aw883xx_dai, sizeof(aw883xx_dai)); + + ret = aw883xx->codec_ops->register_codec(aw883xx->dev, + &soc_codec_dev_aw883xx, + dai_drv, ARRAY_SIZE(aw883xx_dai)); + if (ret < 0) { + dev_err(aw883xx->dev, "failed to register aw883xx: %d", ret); + return ret; + } + + return 0; +} + +static struct aw883xx *aw883xx_malloc_init(struct i2c_client *i2c) +{ + struct aw883xx *aw883xx = devm_kzalloc(&i2c->dev, + sizeof(struct aw883xx), GFP_KERNEL); + if (!aw883xx) + return NULL; + + aw883xx->dev = &i2c->dev; + aw883xx->i2c = i2c; + aw883xx->aw_pa = NULL; + aw883xx->codec = NULL; + aw883xx->codec_ops = &aw_componet_codec_ops; + aw883xx->dbg_en_prof = true; + aw883xx->allow_pw = true; + aw883xx->work_queue = NULL; + mutex_init(&aw883xx->lock); + mutex_init(&aw883xx->dsp_lock); + + return aw883xx; +} + +static int aw883xx_gpio_request(struct aw883xx *aw883xx) +{ + int ret = 0; + + if (gpio_is_valid(aw883xx->reset_gpio)) { + ret = devm_gpio_request_one(aw883xx->dev, aw883xx->reset_gpio, + GPIOF_OUT_INIT_LOW, "aw883xx_rst"); + if (ret) { + dev_err(aw883xx->dev, "rst request failed"); + return ret; + } + } + + return 0; +} + +/* + * device tree + */ +static int aw883xx_parse_gpio_dt(struct aw883xx *aw883xx) +{ + struct device_node *np = aw883xx->dev->of_node; + + aw883xx->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); + if (aw883xx->reset_gpio < 0) + dev_err(aw883xx->dev, "no reset gpio provided, will not hw reset"); + else + dev_dbg(aw883xx->dev, "reset gpio provided ok"); + + return 0; +} + +static void aw883xx_parse_sync_flag_dt(struct aw883xx *aw883xx) +{ + int ret; + int32_t sync_enable = 0; + struct device_node *np = aw883xx->dev->of_node; + + ret = of_property_read_u32(np, "sync-flag", &sync_enable); + if (ret < 0) { + dev_dbg(aw883xx->dev, + "read sync flag failed,default phase sync off"); + sync_enable = false; + } else { + dev_dbg(aw883xx->dev, + "sync flag is %d", sync_enable); + } + + aw883xx->phase_sync = sync_enable; +} + +static int aw883xx_parse_dt(struct aw883xx *aw883xx) +{ + aw883xx_parse_sync_flag_dt(aw883xx); + return aw883xx_parse_gpio_dt(aw883xx); +} + +static int aw883xx_hw_reset(struct aw883xx *aw883xx) +{ + if (gpio_is_valid(aw883xx->reset_gpio)) { + gpio_set_value_cansleep(aw883xx->reset_gpio, 0); + usleep_range(AW_1000_US, AW_1000_US + 10); + gpio_set_value_cansleep(aw883xx->reset_gpio, 1); + usleep_range(AW_1000_US, AW_1000_US + 10); + } else { + dev_err(aw883xx->dev, "%s failed", __func__); + } + return 0; +} + +static int aw883xx_read_chipid(struct aw883xx *aw883xx) +{ + int ret = -1; + int reg_val = 0; + + ret = regmap_read(aw883xx->regmap, AW883XX_CHIP_ID_REG, &reg_val); + if (ret) + return -EIO; + + dev_info(aw883xx->dev, "chip id = %x\n", reg_val); + aw883xx->chip_id = reg_val; + + return 0; +} + +/* + * sys group attribute: reg + */ +static ssize_t reg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + int reg_num = aw883xx->aw_pa->ops.aw_get_reg_num(); + ssize_t len = 0; + uint8_t i = 0; + unsigned int reg_val = 0; + + for (i = 0; i < reg_num; i++) { + if (aw883xx->aw_pa->ops.aw_check_rd_access(i)) { + regmap_read(aw883xx->regmap, i, &reg_val); + len += snprintf(buf + len, PAGE_SIZE - len, + "reg:0x%02x=0x%04x\n", i, reg_val); + } + } + + return len; +} + +static ssize_t reg_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + unsigned int databuf[2] = { 0 }; + + if (sscanf(buf, "%x %x", &databuf[0], &databuf[1]) == 2) + regmap_write(aw883xx->regmap, databuf[0], databuf[1]); + + return count; +} + +static ssize_t rw_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + unsigned int databuf[2] = { 0 }; + + if (sscanf(buf, "%x %x", &databuf[0], &databuf[1]) == 2) { + aw883xx->reg_addr = (uint8_t)databuf[0]; + if (aw883xx->aw_pa->ops.aw_check_rd_access(databuf[0])) + regmap_write(aw883xx->regmap, databuf[0], databuf[1]); + } else if (sscanf(buf, "%x", &databuf[0]) == 1) { + aw883xx->reg_addr = (uint8_t)databuf[0]; + } + + return count; +} + +static ssize_t rw_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + ssize_t len = 0; + unsigned int reg_val = 0; + + if (aw883xx->aw_pa->ops.aw_check_rd_access(aw883xx->reg_addr)) { + regmap_read(aw883xx->regmap, aw883xx->reg_addr, &reg_val); + len += snprintf(buf + len, PAGE_SIZE - len, + "reg:0x%02x=0x%04x\n", aw883xx->reg_addr, + reg_val); + } + + return len; +} + +static ssize_t dsp_rw_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + ssize_t len = 0; + unsigned int reg_val = 0; + + mutex_lock(&aw883xx->dsp_lock); + regmap_write(aw883xx->regmap, aw883xx->aw_pa->dsp_mem_desc.dsp_madd_reg, aw883xx->dsp_addr); + regmap_read(aw883xx->regmap, aw883xx->aw_pa->dsp_mem_desc.dsp_mdat_reg, &reg_val); + len += snprintf(buf + len, PAGE_SIZE - len, + "dsp:0x%04x=0x%04x\n", aw883xx->dsp_addr, reg_val); + regmap_read(aw883xx->regmap, aw883xx->aw_pa->dsp_mem_desc.dsp_mdat_reg, &reg_val); + len += snprintf(buf + len, PAGE_SIZE - len, + "dsp:0x%04x=0x%04x\n", aw883xx->dsp_addr + 1, reg_val); + aw883xx_clear_dsp_sel_st(aw883xx); + mutex_unlock(&aw883xx->dsp_lock); + + return len; +} + +static ssize_t dsp_rw_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + unsigned int databuf[2] = { 0 }; + + if (sscanf(buf, "%x %x", &databuf[0], &databuf[1]) == 2) { + aw883xx->dsp_addr = (unsigned int)databuf[0]; + aw883xx_dsp_write(aw883xx, databuf[0], databuf[1], AW_DSP_16_DATA); + dev_dbg(aw883xx->dev, "get param: %x %x", + databuf[0], databuf[1]); + } else if (sscanf(buf, "%x", &databuf[0]) == 1) { + aw883xx->dsp_addr = (unsigned int)databuf[0]; + dev_dbg(aw883xx->dev, "get param: %x", + databuf[0]); + } + aw883xx_clear_dsp_sel_st(aw883xx); + + return count; +} + +static int aw883xx_awrw_write(struct aw883xx *aw883xx, const char *buf, size_t count) +{ + int i, ret; + char *data_buf = NULL; + int str_len, data_len, temp_data; + struct aw883xx_i2c_packet *packet = &aw883xx->i2c_packet; + uint32_t dsp_addr_h = 0, dsp_addr_l = 0; + + if (!buf) { + dev_err(aw883xx->dev, "awrw buf is NULL"); + return -EINVAL; + } + + data_len = AWRW_DATA_BYTES * packet->reg_num; + + str_len = count - AWRW_HDR_LEN - 1; + if ((data_len * 5 - 1) > str_len) { + dev_err(aw883xx->dev, "data_str_len [%d], requeset len [%d]", + str_len, (data_len * 5 - 1)); + return -EINVAL; + } + + if (packet->reg_addr == aw883xx->aw_pa->dsp_mem_desc.dsp_madd_reg) { + if (sscanf(buf + AWRW_HDR_LEN + 1, + "0x%02x 0x%02x", &dsp_addr_h, + &dsp_addr_l) == 2) { + packet->dsp_addr = (dsp_addr_h << 8) | dsp_addr_l; + packet->dsp_status = AWRW_DSP_READY; + dev_dbg(aw883xx->dev, "write:reg_addr[0x%02x], dsp_base_addr:[0x%02x]", + packet->reg_addr, packet->dsp_addr); + } else { + dev_err(aw883xx->dev, "get reg 0x%x data failed", packet->reg_addr); + return -EINVAL; + } + return 0; + } + + mutex_lock(&aw883xx->dsp_lock); + if (packet->reg_addr == aw883xx->aw_pa->dsp_mem_desc.dsp_mdat_reg) { + if (packet->dsp_status != AWRW_DSP_READY) { + dev_err(aw883xx->dev, "please write reg[0x40] first"); + ret = -EINVAL; + goto exit; + } + regmap_write(aw883xx->regmap, + aw883xx->aw_pa->dsp_mem_desc.dsp_madd_reg, + packet->dsp_addr); + packet->dsp_status = AWRW_DSP_ST_NONE; + } + + dev_info(aw883xx->dev, "write:reg_addr[0x%02x], reg_num[%d]", + packet->reg_addr, packet->reg_num); + + data_buf = devm_kzalloc(aw883xx->dev, data_len, GFP_KERNEL); + if (!data_buf) { + ret = -ENOMEM; + goto exit; + } + + for (i = 0; i < data_len; i++) { + if (sscanf(buf + AWRW_HDR_LEN + 1 + i * 5, "0x%02x", &temp_data) == 1) + data_buf[i] = temp_data; + } + + ret = regmap_raw_write(aw883xx->regmap, packet->reg_addr, data_buf, data_len); + if (ret < 0) { + dev_err(aw883xx->dev, "write failed"); + devm_kfree(aw883xx->dev, data_buf); + data_buf = NULL; + goto exit; + } + + devm_kfree(aw883xx->dev, data_buf); + data_buf = NULL; +exit: + mutex_unlock(&aw883xx->dsp_lock); + return ret; +} + +static int aw883xx_awrw_data_check(struct aw883xx *aw883xx, int *data) +{ + if ((data[AWRW_HDR_ADDR_BYTES] != AWRW_ADDR_BYTES) || + (data[AWRW_HDR_DATA_BYTES] != AWRW_DATA_BYTES)) { + dev_err(aw883xx->dev, "addr_bytes [%d] or data_bytes [%d] unsupport", + data[AWRW_HDR_ADDR_BYTES], data[AWRW_HDR_DATA_BYTES]); + return -EINVAL; + } + + return 0; +} + +/* flag addr_bytes data_bytes reg_num reg_addr*/ +static int aw883xx_awrw_parse_buf(struct aw883xx *aw883xx, const char *buf, size_t count) +{ + int data[AWRW_HDR_MAX] = { 0 }; + struct aw883xx_i2c_packet *packet = &aw883xx->i2c_packet; + int ret; + + if (sscanf(buf, "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x", + &data[AWRW_HDR_WR_FLAG], &data[AWRW_HDR_ADDR_BYTES], &data[AWRW_HDR_DATA_BYTES], + &data[AWRW_HDR_REG_NUM], &data[AWRW_HDR_REG_ADDR]) == 5) { + + ret = aw883xx_awrw_data_check(aw883xx, data); + if (ret < 0) + return ret; + + packet->reg_addr = data[AWRW_HDR_REG_ADDR]; + packet->reg_num = data[AWRW_HDR_REG_NUM]; + + if (data[AWRW_HDR_WR_FLAG] == AWRW_FLAG_WRITE) { + return aw883xx_awrw_write(aw883xx, buf, count); + } else if (data[AWRW_HDR_WR_FLAG] == AWRW_FLAG_READ) { + packet->i2c_status = AWRW_I2C_ST_READ; + dev_info(aw883xx->dev, "read_cmd:reg_addr[0x%02x], reg_num[%d]", + packet->reg_addr, packet->reg_num); + + } else { + dev_err(aw883xx->dev, + "please check str format, unsupport flag %d", + data[AWRW_HDR_WR_FLAG]); + return -EINVAL; + } + } else { + dev_err(aw883xx->dev, "can not parse string"); + return -EINVAL; + } + + return 0; +} + +static ssize_t awrw_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + int ret; + + if (count < AWRW_HDR_LEN) { + dev_err(dev, "data count too smaller, please check write format"); + dev_err(dev, "string %s", buf); + return -EINVAL; + } + + ret = aw883xx_awrw_parse_buf(aw883xx, buf, count); + if (ret) + return -EINVAL; + + + return count; +} + +static ssize_t awrw_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + struct aw883xx_i2c_packet *packet = &aw883xx->i2c_packet; + int data_len, len = 0; + int ret, i; + char *reg_data = NULL; + + if (packet->i2c_status != AWRW_I2C_ST_READ) { + dev_err(aw883xx->dev, "please write read cmd first"); + return -EINVAL; + } + + mutex_lock(&aw883xx->dsp_lock); + if (packet->reg_addr == aw883xx->aw_pa->dsp_mem_desc.dsp_mdat_reg) { + if (packet->dsp_status != AWRW_DSP_READY) { + dev_err(aw883xx->dev, "please write reg[0x40] first"); + mutex_unlock(&aw883xx->dsp_lock); + return -EINVAL; + } + ret = regmap_write(aw883xx->regmap, + aw883xx->aw_pa->dsp_mem_desc.dsp_madd_reg, + packet->dsp_addr); + if (ret < 0) { + mutex_unlock(&aw883xx->dsp_lock); + return ret; + } + packet->dsp_status = AWRW_DSP_ST_NONE; + } + + data_len = AWRW_DATA_BYTES * packet->reg_num; + reg_data = devm_kzalloc(dev, data_len, GFP_KERNEL); + if (!reg_data) { + ret = -EINVAL; + goto exit; + } + + ret = regmap_raw_read(aw883xx->regmap, packet->reg_addr, (void *)reg_data, data_len); + if (ret < 0) { + ret = -EFAULT; + goto exit; + } + + dev_info(aw883xx->dev, "reg_addr 0x%02x, reg_num %d", + packet->reg_addr, packet->reg_num); + + for (i = 0; i < data_len; i++) { + len += snprintf(buf + len, PAGE_SIZE - len, + "0x%02x,", reg_data[i]); + + } + ret = len; + +exit: + if (reg_data) { + devm_kfree(dev, reg_data); + reg_data = NULL; + } + mutex_unlock(&aw883xx->dsp_lock); + packet->i2c_status = AWRW_I2C_ST_NONE; + return ret; +} + +static ssize_t fade_step_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + unsigned int databuf = 0; + int ret = 0; + + ret = kstrtoint(buf, 0, &databuf); + if (ret == 0) { + if (databuf > (aw883xx->aw_pa->volume_desc.mute_volume)) { + dev_info(aw883xx->dev, "step overflow %d Db", databuf); + return count; + } + aw883xx_dev_set_fade_vol_step(aw883xx->aw_pa, databuf); + } + + dev_info(aw883xx->dev, "set step %d DB Done", databuf); + + return count; +} + +static ssize_t fade_step_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t len = 0; + struct aw883xx *aw883xx = dev_get_drvdata(dev); + + len += snprintf(buf+len, PAGE_SIZE-len, + "step: %d\n", aw883xx_dev_get_fade_vol_step(aw883xx->aw_pa)); + + return len; +} + +static ssize_t dbg_prof_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + unsigned int databuf = 0; + int ret = 0; + + ret = kstrtoint(buf, 0, &databuf); + if (ret == 0) { + if (databuf) + aw883xx->dbg_en_prof = true; + else + aw883xx->dbg_en_prof = false; + } + + dev_info(aw883xx->dev, "en_prof %d Done", databuf); + + return count; +} + +static ssize_t dbg_prof_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + ssize_t len = 0; + + len += snprintf(buf+len, PAGE_SIZE-len, + " %d\n", aw883xx->dbg_en_prof); + + return len; +} + +static ssize_t phase_sync_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + unsigned int flag = 0; + int ret; + + ret = kstrtouint(buf, 0, &flag); + if (ret < 0) + return ret; + + flag = ((flag == false) ? false : true); + + dev_info(aw883xx->dev, "set phase sync flag : [%d]", flag); + + aw883xx->phase_sync = flag; + + return count; +} + +static ssize_t phase_sync_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + ssize_t len = 0; + + len += snprintf(buf + len, PAGE_SIZE - len, + "sync flag : %d\n", aw883xx->phase_sync); + + return len; +} + +static ssize_t fade_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + uint32_t fade_en = 0; + int ret = 0; + + ret = kstrtouint(buf, 0, &fade_en); + if (ret == 0) + aw883xx->aw_pa->fade_en = fade_en; + + dev_info(aw883xx->dev, "set fade_en %d", aw883xx->aw_pa->fade_en); + + return count; +} + +static ssize_t fade_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + ssize_t len = 0; + + len += snprintf(buf+len, PAGE_SIZE-len, + "fade_en: %d\n", aw883xx->aw_pa->fade_en); + + return len; +} + +static int aw883xx_dsp_log_info(struct aw883xx *aw883xx, unsigned int base_addr, + uint32_t data_len, char *format) +{ + unsigned int reg_val = 0; + char *dsp_reg_info = NULL; + ssize_t dsp_info_len = 0; + int i; + + dsp_reg_info = devm_kzalloc(aw883xx->dev, AW_NAME_BUF_MAX, GFP_KERNEL); + if (!dsp_reg_info) + return -ENOMEM; + + mutex_lock(&aw883xx->dsp_lock); + regmap_write(aw883xx->regmap, aw883xx->aw_pa->dsp_mem_desc.dsp_madd_reg, base_addr); + + for (i = 0; i < data_len; i += 2) { + regmap_read(aw883xx->regmap, aw883xx->aw_pa->dsp_mem_desc.dsp_mdat_reg, &reg_val); + dsp_info_len += snprintf(dsp_reg_info + dsp_info_len, + AW_NAME_BUF_MAX - dsp_info_len, + "%02x,%02x,", (reg_val >> 0) & 0xff, + (reg_val >> 8) & 0xff); + if ((i / 2 + 1) % 8 == 0) { + dev_info(aw883xx->dev, "%s: %s", format, dsp_reg_info); + dsp_info_len = 0; + memset(dsp_reg_info, 0, AW_NAME_BUF_MAX); + } + + if (((data_len) % 8 != 0) && + (i == (data_len - 2))) { + dev_info(aw883xx->dev, "%s: %s", format, dsp_reg_info); + dsp_info_len = 0; + memset(dsp_reg_info, 0, AW_NAME_BUF_MAX); + } + } + + dsp_info_len = 0; + memset(dsp_reg_info, 0, AW_NAME_BUF_MAX); + devm_kfree(aw883xx->dev, dsp_reg_info); + dsp_reg_info = NULL; + mutex_unlock(&aw883xx->dsp_lock); + + return 0; +} + +static ssize_t dsp_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + ssize_t len = 0; + int ret = -1; + uint32_t data_len; + + if (aw883xx->aw_pa->dsp_cfg == AW_DEV_DSP_BYPASS) { + len += snprintf((char *)(buf + len), PAGE_SIZE - len, + "%s: dsp bypass\n", __func__); + } else { + len += snprintf((char *)(buf + len), PAGE_SIZE - len, + "%s: dsp working\n", __func__); + ret = aw883xx_dev_get_iis_status(aw883xx->aw_pa); + if (ret < 0) { + len += snprintf((char *)(buf + len), + PAGE_SIZE - len, + "%s: no iis signal\n", + __func__); + dev_err(aw883xx->dev, "no iis signal, dsp show failed"); + return len; + } + + len += snprintf(buf + len, PAGE_SIZE - len, + "dsp firmware and config info is displayed in the kernel log\n"); + + dev_dbg(aw883xx->dev, "dsp_firmware_len:%d", aw883xx->aw_pa->dsp_fw_len); + ret = aw883xx_dsp_log_info(aw883xx, aw883xx->aw_pa->dsp_mem_desc.dsp_fw_base_addr, + aw883xx->aw_pa->dsp_fw_len, "dsp_fw"); + if (ret < 0) { + dev_err(aw883xx->dev, "dsp_fw display failed"); + return len; + } + + dev_dbg(aw883xx->dev, "dsp_config_len:%d", aw883xx->aw_pa->dsp_cfg_len); + ret = aw883xx_dsp_log_info(aw883xx, aw883xx->aw_pa->dsp_mem_desc.dsp_cfg_base_addr, + aw883xx->aw_pa->dsp_cfg_len, "dsp_config"); + if (ret < 0) { + dev_err(aw883xx->dev, "dsp_config display failed"); + return len; + } + + dev_dbg(aw883xx->dev, "dsp_config:0x8180-0x83fc"); + data_len = 2 * (aw883xx->aw_pa->dsp_st_desc.dsp_reg_e1 - + aw883xx->aw_pa->dsp_st_desc.dsp_reg_s1); + ret = aw883xx_dsp_log_info(aw883xx, aw883xx->aw_pa->dsp_st_desc.dsp_reg_s1, + data_len, "dsp_st"); + if (ret < 0) { + dev_err(aw883xx->dev, "dsp_config:0x8180-0x83fc failed"); + return len; + } + + dev_dbg(aw883xx->dev, "dsp_config:0x9c00-0x9c5c"); + data_len = 2 * (aw883xx->aw_pa->dsp_st_desc.dsp_reg_e2 - + aw883xx->aw_pa->dsp_st_desc.dsp_reg_s2); + ret = aw883xx_dsp_log_info(aw883xx, aw883xx->aw_pa->dsp_st_desc.dsp_reg_s2, + data_len, "dsp_st"); + if (ret < 0) { + dev_err(aw883xx->dev, "dsp_config:0x9c00-0x9c5c display failed"); + return len; + } + } + + return len; +} + +static ssize_t re_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct aw883xx *aw883xx = dev_get_drvdata(dev); + unsigned int databuf = 0; + int ret = 0; + + ret = kstrtoint(buf, 0, &databuf); + if (ret == 0) + aw883xx_dev_set_cali_re(aw883xx->aw_pa, databuf); + + dev_info(aw883xx->dev, "set cali_re %d mohm Done", databuf); + + return count; +} + +static ssize_t re_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t len = 0; + struct aw883xx *aw883xx = dev_get_drvdata(dev); + + len += snprintf(buf+len, PAGE_SIZE-len, + "cali_re: %d mohm\n", aw883xx_dev_get_cali_re(aw883xx->aw_pa)); + + return len; +} + +static DEVICE_ATTR_RW(reg); +static DEVICE_ATTR_RW(rw); +static DEVICE_ATTR_RW(dsp_rw); +static DEVICE_ATTR_RW(awrw); +static DEVICE_ATTR_RW(fade_step); +static DEVICE_ATTR_RW(dbg_prof); +static DEVICE_ATTR_RW(phase_sync); +static DEVICE_ATTR_RW(fade_enable); +static DEVICE_ATTR_RO(dsp); +static DEVICE_ATTR_RW(re); + +static struct attribute *aw883xx_attributes[] = { + &dev_attr_reg.attr, + &dev_attr_rw.attr, + &dev_attr_dsp_rw.attr, + &dev_attr_awrw.attr, + &dev_attr_fade_step.attr, + &dev_attr_dbg_prof.attr, + &dev_attr_phase_sync.attr, + &dev_attr_fade_enable.attr, + &dev_attr_dsp.attr, + &dev_attr_re.attr, + NULL +}; + +static struct attribute_group aw883xx_attribute_group = { + .attrs = aw883xx_attributes +}; + +/* + * i2c driver + */ +static int aw883xx_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct aw883xx *aw883xx = NULL; + int ret = -1; + + if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) { + dev_err(&i2c->dev, "check_functionality failed"); + return -EIO; + } + + aw883xx = aw883xx_malloc_init(i2c); + if (!aw883xx) { + dev_err(&i2c->dev, "malloc aw883xx failed"); + return -ENOMEM; + } + i2c_set_clientdata(i2c, aw883xx); + + ret = aw883xx_parse_dt(aw883xx); + if (ret < 0) { + dev_err(&i2c->dev, "parse dts failed"); + return ret; + } + + /*get gpio resource*/ + ret = aw883xx_gpio_request(aw883xx); + if (ret) + return ret; + + /* hardware reset */ + aw883xx_hw_reset(aw883xx); + + aw883xx->regmap = devm_regmap_init_i2c(i2c, &aw883xx_remap_config); + if (IS_ERR(aw883xx->regmap)) { + ret = PTR_ERR(aw883xx->regmap); + dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret); + return ret; + } + + /* aw883xx chip id */ + ret = aw883xx_read_chipid(aw883xx); + if (ret < 0) { + dev_err(&i2c->dev, "aw883xx_read_chipid failed ret=%d", ret); + return ret; + } + + /*aw pa init*/ + ret = aw883xx_init(aw883xx); + if (ret < 0) + return ret; + + ret = aw883xx_componet_codec_register(aw883xx); + if (ret) { + dev_err(&i2c->dev, "codec register failed"); + return ret; + } + + ret = sysfs_create_group(&i2c->dev.kobj, &aw883xx_attribute_group); + if (ret < 0) { + dev_err(&i2c->dev, "error creating sysfs attr files"); + goto err_sysfs; + } + + dev_set_drvdata(&i2c->dev, aw883xx); + + return 0; + +err_sysfs: + aw_componet_codec_ops.unregister_codec(&i2c->dev); + return ret; +} + +static void aw883xx_i2c_remove(struct i2c_client *i2c) +{ + struct aw883xx *aw883xx = i2c_get_clientdata(i2c); + + sysfs_remove_group(&aw883xx->dev->kobj, + &aw883xx_attribute_group); + + /*free device resource */ + aw883xx_device_remove(aw883xx->aw_pa); + + aw_componet_codec_ops.unregister_codec(&i2c->dev); + vfree(aw883xx->aw_cfg); + aw883xx->aw_cfg = NULL; +} + +static const struct i2c_device_id aw883xx_i2c_id[] = { + {AW883XX_I2C_NAME, 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, aw883xx_i2c_id); + +static const struct of_device_id aw883xx_dt_match[] = { + {.compatible = "awinic,aw883xx_smartpa"}, + {}, +}; + +static struct i2c_driver aw883xx_i2c_driver = { + .driver = { + .name = AW883XX_I2C_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(aw883xx_dt_match), + }, + .probe = aw883xx_i2c_probe, + .remove = aw883xx_i2c_remove, + .id_table = aw883xx_i2c_id, +}; +module_i2c_driver(aw883xx_i2c_driver); + +MODULE_DESCRIPTION("ASoC AW883XX Smart PA Driver"); +MODULE_LICENSE("GPL v2"); + diff --git a/sound/soc/codecs/aw883xx/aw883xx.h b/sound/soc/codecs/aw883xx/aw883xx.h new file mode 100644 index 000000000000..f128296767ab --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_H__ +#define __AW883XX_H__ + +#include <linux/version.h> +#include <sound/control.h> +#include <sound/soc.h> +#include "aw883xx_device.h" + +#define AW883XX_CHIP_ID_REG (0x00) + +/* + * i2c transaction on Linux limited to 64k + * (See Linux kernel documentation: Documentation/i2c/writing-clients) + */ +#define MAX_I2C_BUFFER_SIZE (65536) +#define AW883XX_READ_MSG_NUM (2) + +#define AW_I2C_RETRIES (5) +#define AW_I2C_RETRY_DELAY (5)/* 5ms */ + +#define AW_READ_CHIPID_RETRY_DELAY (5)/* 5ms */ +#define AW_START_RETRIES (5) + +#define AW883XX_FLAG_START_ON_MUTE (1 << 0) +#define AW883XX_FLAG_SKIP_INTERRUPTS (1 << 1) + +#define AW883XX_I2S_CHECK_MAX (5) + +#define AW883XX_SYSST_CHECK_MAX (10) + +#define AW883XX_BIN_TYPE_NUM (3) +#define AW883XX_LOAD_FW_DELAY_TIME (3000) +#define AW883XX_START_WORK_DELAY_MS (0) + + +#define AW883XX_DSP_16_DATA_MASK (0x0000ffff) + +#define AW_GET_IV_CNT_MAX (6) +#define AW_KCONTROL_NUM (5) +#define AW_HW_MONITOR_DELAY (1000) + +enum { + AWRW_I2C_ST_NONE = 0, + AWRW_I2C_ST_READ, + AWRW_I2C_ST_WRITE, +}; + +enum { + AWRW_DSP_ST_NONE = 0, + AWRW_DSP_READY, +}; + +enum { + AW_SYNC_START = 0, + AW_ASYNC_START, +}; + + +#define AWRW_ADDR_BYTES (1) +#define AWRW_DATA_BYTES (2) +#define AWRW_HDR_LEN (24) + +enum { + AWRW_FLAG_WRITE = 0, + AWRW_FLAG_READ, +}; + +enum { + AWRW_HDR_WR_FLAG = 0, + AWRW_HDR_ADDR_BYTES, + AWRW_HDR_DATA_BYTES, + AWRW_HDR_REG_NUM, + AWRW_HDR_REG_ADDR, + AWRW_HDR_MAX, +}; + +struct aw883xx_i2c_packet { + unsigned char i2c_status; + unsigned char dsp_status; + unsigned int reg_num; + unsigned int reg_addr; + unsigned int dsp_addr; + char *reg_data; +}; + +enum { + AW883XX_STREAM_CLOSE = 0, + AW883XX_STREAM_OPEN, +}; + +/* + * Compatible with codec and component + */ + +struct aw_componet_codec_ops { + struct snd_soc_component *(*kcontrol_codec)(struct snd_kcontrol *kcontrol); + void *(*codec_get_drvdata)(struct snd_soc_component *codec); + int (*add_codec_controls)(struct snd_soc_component *codec, + const struct snd_kcontrol_new *controls, unsigned int num_controls); + void (*unregister_codec)(struct device *dev); + int (*register_codec)(struct device *dev, + const struct snd_soc_component_driver *codec_drv, + struct snd_soc_dai_driver *dai_drv, + int num_dai); +}; + +struct aw883xx { + struct i2c_client *i2c; + struct device *dev; + struct mutex lock; + struct mutex dsp_lock; + struct snd_soc_component *codec; + struct aw_componet_codec_ops *codec_ops; + struct aw_device *aw_pa; + + int sysclk; + int reset_gpio; + + unsigned char phase_sync; /*phase sync*/ + uint32_t allow_pw; + uint8_t pstream; + unsigned char fw_retry_cnt; + + uint8_t dbg_en_prof; + + struct workqueue_struct *work_queue; + struct delayed_work start_work; + struct delayed_work acf_work; + + uint8_t reg_addr; + uint16_t dsp_addr; + uint16_t chip_id; + struct aw883xx_i2c_packet i2c_packet; + + struct regmap *regmap; + struct aw_container *aw_cfg; +}; + +int aw883xx_init(struct aw883xx *aw883xx); + +int aw883xx_dsp_write(struct aw883xx *aw883xx, + uint16_t dsp_addr, uint32_t dsp_data, uint8_t data_type); +int aw883xx_dsp_read(struct aw883xx *aw883xx, + uint16_t dsp_addr, uint32_t *dsp_data, uint8_t data_type); + +#endif

From: Weidong Wang wangweidong.a@awinic.com

The Awinic AW883XX is an I2S/TDM input, high efficiency digital Smart K audio amplifier with an integrated 10.25V smart boost convert

Signed-off-by: Nick Li liweilei@awinic.com Signed-off-by: Bruce zhao zhaolei@awinic.com Signed-off-by: Weidong Wang wangweidong.a@awinic.com --- sound/soc/codecs/Kconfig | 10 + sound/soc/codecs/Makefile | 7 + sound/soc/codecs/aw883xx/aw883xx_data_type.h | 148 ++ sound/soc/codecs/aw883xx/aw883xx_init.c | 635 +++++ .../soc/codecs/aw883xx/aw883xx_pid_2049_reg.h | 2300 +++++++++++++++++ 5 files changed, 3100 insertions(+) create mode 100644 sound/soc/codecs/aw883xx/aw883xx_data_type.h create mode 100644 sound/soc/codecs/aw883xx/aw883xx_init.c create mode 100644 sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 7022e6286e6c..f14e0a78acd4 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -54,6 +54,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_ALC5623 imply SND_SOC_ALC5632 imply SND_SOC_AW8738 + imply SND_SOC_AW883XX imply SND_SOC_BT_SCO imply SND_SOC_BD28623 imply SND_SOC_CQ0093VC @@ -2161,4 +2162,13 @@ config SND_SOC_LPASS_TX_MACRO select SND_SOC_LPASS_MACRO_COMMON tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)"

+config SND_SOC_AW883XX + tristate "Soc Audio for awinic aw883xx series" + depends on I2C + help + this option enables support for aw883xx series Smart PA. + The Awinic AW883XX is an I2S/TDM input, high efficiency + digital Smart K audio amplifier with an integrated 10V + smart boost convert. + endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9170ee1447dd..858ca24ad398 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -357,6 +357,11 @@ snd-soc-tas2780-objs := tas2780.o # Mux snd-soc-simple-mux-objs := simple-mux.o

+snd_soc_aw883xx-objs := aw883xx/aw883xx.o \ + aw883xx/aw883xx_init.o \ + aw883xx/aw883xx_device.o \ + aw883xx/aw883xx_bin_parse.o \ + obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o @@ -719,3 +724,5 @@ obj-$(CONFIG_SND_SOC_LPASS_TX_MACRO) += snd-soc-lpass-tx-macro.o

# Mux obj-$(CONFIG_SND_SOC_SIMPLE_MUX) += snd-soc-simple-mux.o + +obj-$(CONFIG_SND_SOC_AW883XX) +=snd_soc_aw883xx.o diff --git a/sound/soc/codecs/aw883xx/aw883xx_data_type.h b/sound/soc/codecs/aw883xx/aw883xx_data_type.h new file mode 100644 index 000000000000..a72d2d59025f --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_data_type.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_DATA_TYPE_H__ +#define __AW883XX_DATA_TYPE_H__ + +#define AW_NAME_BUF_MAX (50) + +/* + * aw profile + */ +#define PROJECT_NAME_MAX (24) +#define CUSTOMER_NAME_MAX (16) +#define CFG_VERSION_MAX (4) +#define DEV_NAME_MAX (16) +#define PROFILE_STR_MAX (32) + +#define ACF_FILE_ID (0xa15f908) + +enum aw_cfg_hdr_version { + AW_CFG_HDR_VER_0_0_0_1 = 0x00000001, + AW_CFG_HDR_VER_1_0_0_0 = 0x01000000, +}; + +enum aw_cfg_dde_type { + AW_DEV_NONE_TYPE_ID = 0xFFFFFFFF, + AW_DEV_TYPE_ID = 0x00000000, + AW_SKT_TYPE_ID = 0x00000001, + AW_DEV_DEFAULT_TYPE_ID = 0x00000002, +}; + +enum aw_sec_type { + ACF_SEC_TYPE_REG = 0, + ACF_SEC_TYPE_DSP, + ACF_SEC_TYPE_DSP_CFG, + ACF_SEC_TYPE_DSP_FW, + ACF_SEC_TYPE_HDR_REG, + ACF_SEC_TYPE_HDR_DSP_CFG, + ACF_SEC_TYPE_HDR_DSP_FW, + ACF_SEC_TYPE_MUTLBIN, + ACF_SEC_TYPE_SKT_PROJECT, + ACF_SEC_TYPE_DSP_PROJECT, + ACF_SEC_TYPE_MONITOR, + ACF_SEC_TYPE_MAX, +}; + +enum profile_data_type { + AW_DATA_TYPE_REG = 0, + AW_DATA_TYPE_DSP_CFG, + AW_DATA_TYPE_DSP_FW, + AW_DATA_TYPE_MAX, +}; + +enum aw_prof_type { + AW_PROFILE_MUSIC = 0, + AW_PROFILE_VOICE, + AW_PROFILE_VOIP, + AW_PROFILE_RINGTONE, + AW_PROFILE_RINGTONE_HS, + AW_PROFILE_LOWPOWER, + AW_PROFILE_BYPASS, + AW_PROFILE_MMI, + AW_PROFILE_FM, + AW_PROFILE_NOTIFICATION, + AW_PROFILE_RECEIVER, + AW_PROFILE_MAX, +}; + +enum aw_profile_status { + AW_PROFILE_WAIT = 0, + AW_PROFILE_OK, +}; + +struct aw_cfg_hdr { + uint32_t a_id; /*acf file ID 0xa15f908*/ + char a_project[PROJECT_NAME_MAX]; /*project name*/ + char a_custom[CUSTOMER_NAME_MAX]; /*custom name :huawei xiaomi vivo oppo*/ + char a_version[CFG_VERSION_MAX]; /*author update version*/ + uint32_t a_author_id; /*author id*/ + uint32_t a_ddt_size; /*sub section table entry size*/ + uint32_t a_ddt_num; /*sub section table entry num*/ + uint32_t a_hdr_offset; /*sub section table offset in file*/ + uint32_t a_hdr_version; /*sub section table version*/ + uint32_t reserve[3]; +}; + +struct aw_cfg_dde { + uint32_t type; /*DDE type id*/ + char dev_name[DEV_NAME_MAX]; + uint16_t dev_index; /*dev id*/ + uint16_t dev_bus; /*dev bus id*/ + uint16_t dev_addr; /*dev addr id*/ + uint16_t dev_profile; /*dev profile id*/ + uint32_t data_type; /*data type id*/ + uint32_t data_size; + uint32_t data_offset; + uint32_t data_crc; + uint32_t reserve[5]; +}; + +struct aw_cfg_dde_v_1_0_0_0 { + uint32_t type; /*DDE type id*/ + char dev_name[DEV_NAME_MAX]; + uint16_t dev_index; /*dev id*/ + uint16_t dev_bus; /*dev bus id*/ + uint16_t dev_addr; /*dev addr id*/ + uint16_t dev_profile; /*dev profile id*/ + uint32_t data_type; /*data type id*/ + uint32_t data_size; + uint32_t data_offset; + uint32_t data_crc; + char dev_profile_str[PROFILE_STR_MAX]; + uint32_t chip_id; + uint32_t reserve[4]; +}; + +struct aw_sec_data_desc { + uint32_t len; + unsigned char *data; +}; + +struct aw_prof_desc { + uint32_t id; + uint32_t prof_st; + char *prf_str; + uint32_t fw_ver; + struct aw_sec_data_desc sec_desc[AW_DATA_TYPE_MAX]; +}; + +struct aw_all_prof_info { + struct aw_prof_desc prof_desc[AW_PROFILE_MAX]; +}; + +struct aw_prof_info { + int count; + int prof_type; + char **prof_name_list; + struct aw_prof_desc *prof_desc; +}; + +#endif + diff --git a/sound/soc/codecs/aw883xx/aw883xx_init.c b/sound/soc/codecs/aw883xx/aw883xx_init.c new file mode 100644 index 000000000000..d2de2e199d49 --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_init.c @@ -0,0 +1,635 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/firmware.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/regmap.h> +#include <linux/syscalls.h> +#include <linux/uaccess.h> +#include <linux/version.h> +#include <linux/workqueue.h> +#include <sound/control.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include "aw883xx.h" +#include "aw883xx_bin_parse.h" +#include "aw883xx_pid_2049_reg.h" + +#define AW_FW_CHECK_PART (10) +#define AW_GET_32_DATA(w, x, y, z) \ + ((uint32_t)((((uint8_t)w) << 24) | (((uint8_t)x) << 16) | \ + (((uint8_t)y) << 8) | ((uint8_t)z))) +#define AW_GET_16_DATA(x, y) \ + ((uint16_t)((((uint8_t)x) << 8) | (uint8_t)y)) + +static const unsigned char aw_pid_2049_reg_access[AW_PID_2049_REG_MAX] = { + [AW_PID_2049_ID_REG] = (REG_RD_ACCESS), + [AW_PID_2049_SYSST_REG] = (REG_RD_ACCESS), + [AW_PID_2049_SYSINT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_SYSINTM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SYSCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_MPDCFG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PWMCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DBGCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCST_REG] = (REG_RD_ACCESS), + [AW_PID_2049_VBAT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TEMP_REG] = (REG_RD_ACCESS), + [AW_PID_2049_PVDD_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ISNDAT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_VSNDAT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_I2SINT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_I2SCAPCNT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA1_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA2_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA3_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA4_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TESTDET_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TESTIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_TESTOUT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_DSPMADD_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSPMDAT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_WDT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ACR1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ACR2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ASR1_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ASR2_REG] = (REG_RD_ACCESS), + [AW_PID_2049_DSPCFG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ASR3_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ASR4_REG] = (REG_RD_ACCESS), + [AW_PID_2049_VSNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ISNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PLLCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PLLCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PLLCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_CDACTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_CDACTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SADCCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SADCCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_CPCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG8_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_TESTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_TESTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWM2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWM1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFRH_REG] = (REG_RD_ACCESS), + [AW_PID_2049_EFRM2_REG] = (REG_RD_ACCESS), + [AW_PID_2049_EFRM1_REG] = (REG_RD_ACCESS), + [AW_PID_2049_EFRL_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TM_REG] = (REG_NONE_ACCESS), +}; + +static int aw883xx_dev_dsp_write(struct aw_device *aw_dev, + uint16_t dsp_addr, uint32_t dsp_data, uint8_t data_type) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_dsp_write(aw883xx, dsp_addr, dsp_data, data_type); +} + +static int aw883xx_dev_dsp_read(struct aw_device *aw_dev, + uint16_t dsp_addr, uint32_t *dsp_data, uint8_t data_type) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_dsp_read(aw883xx, dsp_addr, dsp_data, data_type); +} + +/* + * aw883xx i2c write/read + */ +/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB real_value = value * 8 : 0.125db --> 1*/ +static unsigned int aw_pid_2049_reg_val_to_db(unsigned int value) +{ + return (((value >> AW_PID_2049_VOL_6DB_START) * AW_PID_2049_VOLUME_STEP_DB) + + ((value & 0x3f) % AW_PID_2049_VOLUME_STEP_DB)); +} + +/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB reg_value = value / step << 6 + value % step ; step = 6 * 8*/ +static uint16_t aw_pid_2049_db_val_to_reg(uint16_t value) +{ + return (((value / AW_PID_2049_VOLUME_STEP_DB) << AW_PID_2049_VOL_6DB_START) + + (value % AW_PID_2049_VOLUME_STEP_DB)); +} + +static int aw883xx_set_volume(struct aw883xx *aw883xx, uint16_t value) +{ + unsigned int reg_value = 0; + uint16_t real_value = 0; + uint16_t volume = 0; + struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc; + + volume = AW_GET_MIN_VALUE(value, vol_desc->mute_volume); + real_value = aw_pid_2049_db_val_to_reg(volume); + + /* cal real value */ + regmap_read(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, &reg_value); + + dev_dbg(aw883xx->dev, "value 0x%x , reg:0x%x", value, real_value); + + /*[15 : 6] volume*/ + real_value = (real_value << AW_PID_2049_VOL_START_BIT) | (reg_value & AW_PID_2049_VOL_MASK); + + /* write value */ + regmap_write(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, real_value); + + return 0; +} + +static int aw883xx_get_volume(struct aw883xx *aw883xx, uint16_t *value) +{ + unsigned int reg_value = 0; + uint16_t real_value = 0; + + /* read value */ + regmap_read(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, &reg_value); + + /*[15 : 6] volume*/ + real_value = reg_value >> AW_PID_2049_VOL_START_BIT; + + real_value = aw_pid_2049_reg_val_to_db(real_value); + + *value = real_value; + + return 0; +} + +static int aw_pid_2049_set_volume(struct aw_device *aw_dev, uint16_t value) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_set_volume(aw883xx, value); +} + +static int aw_pid_2049_get_volume(struct aw_device *aw_dev, uint16_t *value) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_get_volume(aw883xx, value); +} + +static void aw_pid_2049_i2s_tx_enable(struct aw_device *aw_dev, bool flag) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + if (flag) { + regmap_update_bits(aw883xx->regmap, AW_PID_2049_I2SCFG1_REG, + ~AW_PID_2049_I2STXEN_MASK, + AW_PID_2049_I2STXEN_ENABLE_VALUE); + } else { + regmap_update_bits(aw883xx->regmap, AW_PID_2049_I2SCFG1_REG, + ~AW_PID_2049_I2STXEN_MASK, + AW_PID_2049_I2STXEN_DISABLE_VALUE); + } +} + +static void aw_pid_2049_set_cfg_f0_fs(struct aw_device *aw_dev, uint32_t *f0_fs) +{ + unsigned int rate_data = 0; + uint32_t fs = 0; + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + regmap_read(aw883xx->regmap, AW_PID_2049_I2SCTRL_REG, &rate_data); + + switch (rate_data & (~AW_PID_2049_I2SSR_MASK)) { + case AW_PID_2049_I2SSR_8_KHZ_VALUE: + fs = 8000; + break; + case AW_PID_2049_I2SSR_16_KHZ_VALUE: + fs = 16000; + break; + case AW_PID_2049_I2SSR_32_KHZ_VALUE: + fs = 32000; + break; + case AW_PID_2049_I2SSR_44_KHZ_VALUE: + fs = 44000; + break; + case AW_PID_2049_I2SSR_48_KHZ_VALUE: + fs = 48000; + break; + case AW_PID_2049_I2SSR_96_KHZ_VALUE: + fs = 96000; + break; + case AW_PID_2049_I2SSR_192KHZ_VALUE: + fs = 192000; + break; + default: + fs = 48000; + dev_err(aw883xx->dev, + "rate can not support, use default 48k"); + break; + } + + dev_dbg(aw883xx->dev, "get i2s fs:%d", fs); + *f0_fs = fs / 8; + + aw883xx_dsp_write(aw883xx, + AW_PID_2049_DSP_REG_CFGF0_FS, *f0_fs, AW_DSP_32_DATA); +} + +static bool aw_pid_2049_check_rd_access(int reg) +{ + if (reg >= AW_PID_2049_REG_MAX) + return false; + + if (aw_pid_2049_reg_access[reg] & REG_RD_ACCESS) + return true; + else + return false; +} + +static bool aw_pid_2049_check_wr_access(int reg) +{ + if (reg >= AW_PID_2049_REG_MAX) + return false; + + if (aw_pid_2049_reg_access[reg] & REG_WR_ACCESS) + return true; + else + return false; +} + +static int aw_pid_2049_get_reg_num(void) +{ + return AW_PID_2049_REG_MAX; +} + +static int aw_pid_2049_dsp_fw_check(struct aw_device *aw_dev) +{ + struct aw_prof_desc *set_prof_desc = NULL; + struct aw_sec_data_desc *dsp_fw_desc = NULL; + uint16_t base_addr = AW_PID_2049_DSP_FW_ADDR; + uint16_t addr = base_addr; + int ret, i; + uint32_t dsp_val; + uint16_t bin_val; + + ret = aw883xx_dev_get_prof_data(aw_dev, aw_dev->cur_prof, &set_prof_desc); + if (ret < 0) + return ret; + + /*update reg*/ + dsp_fw_desc = &set_prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW]; + + for (i = 0; i < AW_FW_CHECK_PART; i++) { + ret = aw883xx_dev_dsp_read(aw_dev, addr, &dsp_val, AW_DSP_16_DATA); + if (ret < 0) { + dev_err(aw_dev->dev, "dsp read failed"); + return ret; + } + + bin_val = AW_GET_16_DATA(dsp_fw_desc->data[2 * (addr - base_addr)], + dsp_fw_desc->data[2 * (addr - base_addr) + 1]); + + if (dsp_val != bin_val) { + dev_err(aw_dev->dev, "check failed, addr[0x%x], read[0x%x] != bindata[0x%x]", + addr, dsp_val, bin_val); + return -EINVAL; + } + + addr += (dsp_fw_desc->len / 2) / AW_FW_CHECK_PART; + if ((addr - base_addr) > dsp_fw_desc->len) { + dev_err(aw_dev->dev, "check failed, addr[0x%x] too large", addr); + return -EINVAL; + } + } + + return 0; +} + +static int aw_pid_2049_set_cali_re_to_dsp(struct aw_device *aw_dev) +{ + struct aw_adpz_re_desc *adpz_re_desc = &aw_dev->adpz_re_desc; + uint32_t cali_re = 0; + int ret = 0; + + cali_re = AW_SHOW_RE_TO_DSP_RE((aw_dev->cali_desc.cali_re + + aw_dev->cali_desc.ra), adpz_re_desc->shift); + + /* set cali re to aw883xx */ + ret = aw_dev->ops.aw_dsp_write(aw_dev, + adpz_re_desc->dsp_reg, cali_re, adpz_re_desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "set cali re error"); + return ret; + } + + ret = aw883xx_dev_modify_dsp_cfg(aw_dev, adpz_re_desc->dsp_reg, + cali_re, adpz_re_desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "modify dsp cfg failed"); + return ret; + } + + return ret; + +} + +static int aw883xx_pid_2049_dev_init(struct aw883xx *aw883xx) +{ + struct aw_device *aw_pa = NULL; + + aw_pa = devm_kzalloc(aw883xx->dev, sizeof(struct aw_device), GFP_KERNEL); + if (!aw_pa) + return -ENOMEM; + + /*call aw device init func*/ + aw_pa->acf = NULL; + aw_pa->prof_info.prof_desc = NULL; + aw_pa->prof_info.count = 0; + aw_pa->prof_info.prof_type = AW_DEV_NONE_TYPE_ID; + aw_pa->channel = 0; + aw_pa->dsp_lock = &aw883xx->dsp_lock; + aw_pa->i2c = aw883xx->i2c; + aw_pa->fw_status = AW_DEV_FW_FAILED; + aw_pa->fade_step = AW_PID_2049_VOLUME_STEP_DB; + + aw_pa->chip_id = aw883xx->chip_id; + aw_pa->private_data = (void *)aw883xx; + aw_pa->dev = aw883xx->dev; + aw_pa->ops.aw_i2c_writes = regmap_raw_write; + aw_pa->ops.aw_i2c_write = regmap_write; + aw_pa->ops.aw_reg_write = regmap_write; + aw_pa->ops.aw_reg_write_bits = regmap_update_bits; + aw_pa->ops.aw_i2c_read = regmap_read; + aw_pa->ops.aw_reg_read = regmap_read; + aw_pa->ops.aw_dsp_read = aw883xx_dev_dsp_read; + aw_pa->ops.aw_dsp_write = aw883xx_dev_dsp_write; + + aw_pa->ops.aw_get_hw_volume = aw_pid_2049_get_volume; + aw_pa->ops.aw_set_hw_volume = aw_pid_2049_set_volume; + aw_pa->ops.aw_reg_val_to_db = aw_pid_2049_reg_val_to_db; + + aw_pa->ops.aw_check_rd_access = aw_pid_2049_check_rd_access; + aw_pa->ops.aw_check_wr_access = aw_pid_2049_check_wr_access; + aw_pa->ops.aw_get_reg_num = aw_pid_2049_get_reg_num; + + aw_pa->ops.aw_i2s_tx_enable = aw_pid_2049_i2s_tx_enable; + + aw_pa->ops.aw_set_cfg_f0_fs = aw_pid_2049_set_cfg_f0_fs; + aw_pa->ops.aw_dsp_fw_check = aw_pid_2049_dsp_fw_check; + + aw_pa->ops.aw_set_cali_re = aw_pid_2049_set_cali_re_to_dsp; + + aw_pa->int_desc.mask_reg = AW_PID_2049_SYSINTM_REG; + aw_pa->int_desc.mask_default = AW_PID_2049_SYSINTM_DEFAULT; + aw_pa->int_desc.int_mask = AW_PID_2049_SYSINTM_DEFAULT; + aw_pa->int_desc.st_reg = AW_PID_2049_SYSINT_REG; + aw_pa->int_desc.intst_mask = AW_PID_2049_BIT_SYSINT_CHECK; + + aw_pa->pwd_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->pwd_desc.mask = AW_PID_2049_PWDN_MASK; + aw_pa->pwd_desc.enable = AW_PID_2049_PWDN_POWER_DOWN_VALUE; + aw_pa->pwd_desc.disable = AW_PID_2049_PWDN_WORKING_VALUE; + + aw_pa->mute_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->mute_desc.mask = AW_PID_2049_HMUTE_MASK; + aw_pa->mute_desc.enable = AW_PID_2049_HMUTE_ENABLE_VALUE; + aw_pa->mute_desc.disable = AW_PID_2049_HMUTE_DISABLE_VALUE; + + aw_pa->vcalb_desc.vcalb_dsp_reg = AW_PID_2049_DSP_REG_VCALB; + aw_pa->vcalb_desc.data_type = AW_DSP_16_DATA; + aw_pa->vcalb_desc.vcal_factor = AW_PID_2049_VCAL_FACTOR; + aw_pa->vcalb_desc.cabl_base_value = AW_PID_2049_CABL_BASE_VALUE; + aw_pa->vcalb_desc.vscal_factor = AW_PID_2049_VSCAL_FACTOR; + aw_pa->vcalb_desc.iscal_factor = AW_PID_2049_ISCAL_FACTOR; + + aw_pa->vcalb_desc.vcalb_adj_shift = AW_PID_2049_VCALB_ADJ_FACTOR; + + aw_pa->vcalb_desc.icalk_value_factor = AW_PID_2049_ICABLK_FACTOR; + aw_pa->vcalb_desc.icalk_reg = AW_PID_2049_EFRM2_REG; + aw_pa->vcalb_desc.icalk_reg_mask = AW_PID_2049_EF_ISN_GESLP_MASK; + aw_pa->vcalb_desc.icalk_sign_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_MASK; + aw_pa->vcalb_desc.icalk_neg_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_NEG; + + aw_pa->vcalb_desc.vcalk_reg = AW_PID_2049_EFRH_REG; + aw_pa->vcalb_desc.vcalk_reg_mask = AW_PID_2049_EF_VSN_GESLP_MASK; + aw_pa->vcalb_desc.vcalk_sign_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_MASK; + aw_pa->vcalb_desc.vcalk_neg_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_NEG; + aw_pa->vcalb_desc.vcalk_value_factor = AW_PID_2049_VCABLK_FACTOR; + aw_pa->vcalb_desc.vcalk_shift = AW_PID_2049_EF_VSENSE_GAIN_SHIFT; + + aw_pa->vcalb_desc.vcalb_vsense_reg = AW_PID_2049_I2SCFG3_REG; + aw_pa->vcalb_desc.vcalk_vdsel_mask = AW_PID_2049_VDSEL_MASK; + aw_pa->vcalb_desc.vcalk_value_factor_vsense_in = AW_PID_2049_VCABLK_FACTOR_DAC; + aw_pa->vcalb_desc.vscal_factor_vsense_in = AW_PID_2049_VSCAL_FACTOR_DAC; + aw_pa->vcalb_desc.vcalk_dac_shift = AW_PID_2049_EF_DAC_GESLP_SHIFT; + aw_pa->vcalb_desc.vcalk_dac_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_MASK; + aw_pa->vcalb_desc.vcalk_dac_neg_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_NEG; + + aw_pa->sysst_desc.reg = AW_PID_2049_SYSST_REG; + aw_pa->sysst_desc.st_check = AW_PID_2049_BIT_SYSST_CHECK; + aw_pa->sysst_desc.st_mask = AW_PID_2049_BIT_SYSST_CHECK_MASK; + aw_pa->sysst_desc.pll_check = AW_PID_2049_BIT_PLL_CHECK; + aw_pa->sysst_desc.dsp_check = AW_PID_2049_DSPS_NORMAL_VALUE; + aw_pa->sysst_desc.dsp_mask = AW_PID_2049_DSPS_MASK; + + aw_pa->profctrl_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->profctrl_desc.mask = AW_PID_2049_RCV_MODE_MASK; + aw_pa->profctrl_desc.rcv_mode_val = AW_PID_2049_RCV_MODE_RECEIVER_VALUE; + + aw_pa->volume_desc.reg = AW_PID_2049_SYSCTRL2_REG; + aw_pa->volume_desc.mask = AW_PID_2049_VOL_MASK; + aw_pa->volume_desc.shift = AW_PID_2049_VOL_START_BIT; + aw_pa->volume_desc.mute_volume = AW_PID_2049_MUTE_VOL; + aw_pa->volume_desc.max_volume = AW_PID_2049_VOL_DEFAULT_VALUE; + aw_pa->volume_desc.ctl_volume = AW_PID_2049_VOL_DEFAULT_VALUE; + + aw_pa->dsp_en_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->dsp_en_desc.mask = AW_PID_2049_DSPBY_MASK; + aw_pa->dsp_en_desc.enable = AW_PID_2049_DSPBY_WORKING_VALUE; + aw_pa->dsp_en_desc.disable = AW_PID_2049_DSPBY_BYPASS_VALUE; + + aw_pa->memclk_desc.reg = AW_PID_2049_DBGCTRL_REG; + aw_pa->memclk_desc.mask = AW_PID_2049_MEM_CLKSEL_MASK; + aw_pa->memclk_desc.mcu_hclk = AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE; + aw_pa->memclk_desc.osc_clk = AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE; + + aw_pa->watch_dog_desc.reg = AW_PID_2049_WDT_REG; + aw_pa->watch_dog_desc.mask = AW_PID_2049_WDT_CNT_MASK; + + aw_pa->dsp_mem_desc.dsp_madd_reg = AW_PID_2049_DSPMADD_REG; + aw_pa->dsp_mem_desc.dsp_mdat_reg = AW_PID_2049_DSPMDAT_REG; + aw_pa->dsp_mem_desc.dsp_cfg_base_addr = AW_PID_2049_DSP_CFG_ADDR; + aw_pa->dsp_mem_desc.dsp_fw_base_addr = AW_PID_2049_DSP_FW_ADDR; + + aw_pa->voltage_desc.reg = AW_PID_2049_VBAT_REG; + aw_pa->voltage_desc.vbat_range = AW_PID_2049_VBAT_RANGE; + aw_pa->voltage_desc.int_bit = AW_PID_2049_INT_10BIT; + + aw_pa->temp_desc.reg = AW_PID_2049_TEMP_REG; + aw_pa->temp_desc.sign_mask = AW_PID_2049_TEMP_SIGN_MASK; + aw_pa->temp_desc.neg_mask = AW_PID_2049_TEMP_NEG_MASK; + + aw_pa->vmax_desc.dsp_reg = AW_PID_2049_DSP_REG_VMAX; + aw_pa->vmax_desc.data_type = AW_DSP_16_DATA; + + aw_pa->ipeak_desc.reg = AW_PID_2049_SYSCTRL2_REG; + aw_pa->ipeak_desc.mask = AW_PID_2049_BST_IPEAK_MASK; + + aw_pa->soft_rst.reg = AW_PID_2049_ID_REG; + aw_pa->soft_rst.reg_value = AW_PID_2049_SOFT_RESET_VALUE; + + aw_pa->dsp_vol_desc.reg = AW_PID_2049_DSPCFG_REG; + aw_pa->dsp_vol_desc.mask = AW_PID_2049_DSP_VOL_MASK; + aw_pa->dsp_vol_desc.mute_st = AW_PID_2049_DSP_VOL_MUTE; + aw_pa->dsp_vol_desc.noise_st = AW_PID_2049_DSP_VOL_NOISE_ST; + + aw_pa->amppd_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->amppd_desc.mask = AW_PID_2049_AMPPD_MASK; + aw_pa->amppd_desc.enable = AW_PID_2049_AMPPD_POWER_DOWN_VALUE; + aw_pa->amppd_desc.disable = AW_PID_2049_AMPPD_WORKING_VALUE; + + aw_pa->spkr_temp_desc.reg = AW_PID_2049_ASR2_REG; + + /*32-bit data types need bypass dsp*/ + aw_pa->ra_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RA; + aw_pa->ra_desc.data_type = AW_DSP_32_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->cali_cfg_desc.actampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH; + aw_pa->cali_cfg_desc.actampth_data_type = AW_DSP_32_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->cali_cfg_desc.noiseampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH; + aw_pa->cali_cfg_desc.noiseampth_data_type = AW_DSP_32_DATA; + + aw_pa->cali_cfg_desc.ustepn_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN; + aw_pa->cali_cfg_desc.ustepn_data_type = AW_DSP_16_DATA; + + aw_pa->cali_cfg_desc.alphan_reg = AW_PID_2049_DSP_REG_CFG_RE_ALPHA; + aw_pa->cali_cfg_desc.alphan_data_type = AW_DSP_16_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->adpz_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RE; + aw_pa->adpz_re_desc.data_type = AW_DSP_32_DATA; + aw_pa->adpz_re_desc.shift = AW_PID_2049_DSP_RE_SHIFT; + + aw_pa->t0_desc.dsp_reg = AW_PID_2049_DSP_CFG_ADPZ_T0; + aw_pa->t0_desc.data_type = AW_DSP_16_DATA; + aw_pa->t0_desc.coilalpha_reg = AW_PID_2049_DSP_CFG_ADPZ_COILALPHA; + aw_pa->t0_desc.coil_type = AW_DSP_16_DATA; + + aw_pa->ste_re_desc.shift = AW_PID_2049_DSP_REG_CALRE_SHIFT; + aw_pa->ste_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CALRE; + aw_pa->ste_re_desc.data_type = AW_DSP_16_DATA; + + aw_pa->noise_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG; + aw_pa->noise_desc.data_type = AW_DSP_16_DATA; + aw_pa->noise_desc.mask = AW_PID_2049_DSP_REG_NOISE_MASK; + + aw_pa->f0_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_F0; + aw_pa->f0_desc.shift = AW_PID_2049_DSP_F0_SHIFT; + aw_pa->f0_desc.data_type = AW_DSP_16_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->cfgf0_fs_desc.dsp_reg = AW_PID_2049_DSP_REG_CFGF0_FS; + aw_pa->cfgf0_fs_desc.data_type = AW_DSP_32_DATA; + + aw_pa->q_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_Q; + aw_pa->q_desc.shift = AW_PID_2049_DSP_Q_SHIFT; + aw_pa->q_desc.data_type = AW_DSP_16_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->dsp_crc_desc.dsp_reg = AW_PID_2049_DSP_REG_CRC_ADDR; + aw_pa->dsp_crc_desc.data_type = AW_DSP_32_DATA; + + aw_pa->dsp_crc_desc.ctl_reg = AW_PID_2049_HAGCCFG7_REG; + aw_pa->dsp_crc_desc.ctl_mask = AW_PID_2049_AGC_DSP_CTL_MASK; + aw_pa->dsp_crc_desc.ctl_enable = AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE; + aw_pa->dsp_crc_desc.ctl_disable = AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE; + + aw_pa->cco_mux_desc.reg = AW_PID_2049_PLLCTRL1_REG; + aw_pa->cco_mux_desc.mask = AW_PID_2049_CCO_MUX_MASK; + aw_pa->cco_mux_desc.divider = AW_PID_2049_CCO_MUX_DIVIDED_VALUE; + aw_pa->cco_mux_desc.bypass = AW_PID_2049_CCO_MUX_BYPASS_VALUE; + + /*hw monitor temp reg*/ + aw_pa->hw_temp_desc.dsp_reg = AW_PID_2049_DSP_REG_TEMP_ADDR; + aw_pa->hw_temp_desc.data_type = AW_DSP_16_DATA; + + aw_pa->chansel_desc.rxchan_reg = AW_PID_2049_I2SCTRL_REG; + aw_pa->chansel_desc.rxchan_mask = AW_PID_2049_CHSEL_MASK; + aw_pa->chansel_desc.txchan_reg = AW_PID_2049_I2SCFG1_REG; + aw_pa->chansel_desc.txchan_mask = AW_PID_2049_I2SCHS_MASK; + + aw_pa->chansel_desc.rx_left = AW_PID_2049_CHSEL_LEFT_VALUE; + aw_pa->chansel_desc.rx_right = AW_PID_2049_CHSEL_RIGHT_VALUE; + aw_pa->chansel_desc.tx_left = AW_PID_2049_I2SCHS_LEFT_VALUE; + aw_pa->chansel_desc.tx_right = AW_PID_2049_I2SCHS_RIGHT_VALUE; + + aw_pa->tx_en_desc.tx_en_mask = AW_PID_2049_I2STXEN_MASK; + aw_pa->tx_en_desc.tx_disable = AW_PID_2049_I2STXEN_DISABLE_VALUE; + + aw_pa->cali_delay_desc.dsp_reg = AW_PID_2049_DSP_CALI_F0_DELAY; + aw_pa->cali_delay_desc.data_type = AW_DSP_16_DATA; + + aw_pa->dsp_st_desc.dsp_reg_s1 = AW_PID_2049_DSP_ST_S1; + aw_pa->dsp_st_desc.dsp_reg_e1 = AW_PID_2049_DSP_ST_E1; + aw_pa->dsp_st_desc.dsp_reg_s2 = AW_PID_2049_DSP_ST_S2; + aw_pa->dsp_st_desc.dsp_reg_e2 = AW_PID_2049_DSP_ST_E2; + + aw883xx_device_probe(aw_pa); + + aw883xx->aw_pa = aw_pa; + + return 0; +} + +int aw883xx_init(struct aw883xx *aw883xx) +{ + int ret = 0; + + switch (aw883xx->chip_id) { + case AW883XX_PID_2049: + ret = aw883xx_pid_2049_dev_init(aw883xx); + break; + default: + ret = -EINVAL; + dev_err(aw883xx->dev, "unsupported device"); + break; + } + return ret; +} + diff --git a/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h new file mode 100644 index 000000000000..e7c4703d1627 --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h @@ -0,0 +1,2300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_PID_2049_REG_H__ +#define __AW883XX_PID_2049_REG_H__ + +#define AW_PID_2049_ID_REG (0x00) +#define AW_PID_2049_SYSST_REG (0x01) +#define AW_PID_2049_SYSINT_REG (0x02) +#define AW_PID_2049_SYSINTM_REG (0x03) +#define AW_PID_2049_SYSCTRL_REG (0x04) +#define AW_PID_2049_SYSCTRL2_REG (0x05) +#define AW_PID_2049_I2SCTRL_REG (0x06) +#define AW_PID_2049_I2SCFG1_REG (0x07) +#define AW_PID_2049_I2SCFG2_REG (0x08) +#define AW_PID_2049_HAGCCFG1_REG (0x09) +#define AW_PID_2049_HAGCCFG2_REG (0x0A) +#define AW_PID_2049_HAGCCFG3_REG (0x0B) +#define AW_PID_2049_HAGCCFG4_REG (0x0C) +#define AW_PID_2049_HAGCCFG5_REG (0x0D) +#define AW_PID_2049_HAGCCFG6_REG (0x0E) +#define AW_PID_2049_HAGCCFG7_REG (0x0F) +#define AW_PID_2049_MPDCFG_REG (0x10) +#define AW_PID_2049_PWMCTRL_REG (0x11) +#define AW_PID_2049_I2SCFG3_REG (0x12) +#define AW_PID_2049_DBGCTRL_REG (0x13) +#define AW_PID_2049_HAGCST_REG (0x20) +#define AW_PID_2049_VBAT_REG (0x21) +#define AW_PID_2049_TEMP_REG (0x22) +#define AW_PID_2049_PVDD_REG (0x23) +#define AW_PID_2049_ISNDAT_REG (0x24) +#define AW_PID_2049_VSNDAT_REG (0x25) +#define AW_PID_2049_I2SINT_REG (0x26) +#define AW_PID_2049_I2SCAPCNT_REG (0x27) +#define AW_PID_2049_ANASTA1_REG (0x28) +#define AW_PID_2049_ANASTA2_REG (0x29) +#define AW_PID_2049_ANASTA3_REG (0x2A) +#define AW_PID_2049_ANASTA4_REG (0x2B) +#define AW_PID_2049_TESTDET_REG (0x2C) +#define AW_PID_2049_TESTIN_REG (0x38) +#define AW_PID_2049_TESTOUT_REG (0x39) +#define AW_PID_2049_DSPMADD_REG (0x40) +#define AW_PID_2049_DSPMDAT_REG (0x41) +#define AW_PID_2049_WDT_REG (0x42) +#define AW_PID_2049_ACR1_REG (0x43) +#define AW_PID_2049_ACR2_REG (0x44) +#define AW_PID_2049_ASR1_REG (0x45) +#define AW_PID_2049_ASR2_REG (0x46) +#define AW_PID_2049_DSPCFG_REG (0x47) +#define AW_PID_2049_ASR3_REG (0x48) +#define AW_PID_2049_ASR4_REG (0x49) +#define AW_PID_2049_VSNCTRL1_REG (0x50) +#define AW_PID_2049_ISNCTRL1_REG (0x51) +#define AW_PID_2049_PLLCTRL1_REG (0x52) +#define AW_PID_2049_PLLCTRL2_REG (0x53) +#define AW_PID_2049_PLLCTRL3_REG (0x54) +#define AW_PID_2049_CDACTRL1_REG (0x55) +#define AW_PID_2049_CDACTRL2_REG (0x56) +#define AW_PID_2049_SADCCTRL1_REG (0x57) +#define AW_PID_2049_SADCCTRL2_REG (0x58) +#define AW_PID_2049_CPCTRL1_REG (0x59) +#define AW_PID_2049_BSTCTRL1_REG (0x60) +#define AW_PID_2049_BSTCTRL2_REG (0x61) +#define AW_PID_2049_BSTCTRL3_REG (0x62) +#define AW_PID_2049_BSTCTRL4_REG (0x63) +#define AW_PID_2049_BSTCTRL5_REG (0x64) +#define AW_PID_2049_BSTCTRL6_REG (0x65) +#define AW_PID_2049_BSTCTRL7_REG (0x66) +#define AW_PID_2049_DSMCFG1_REG (0x67) +#define AW_PID_2049_DSMCFG2_REG (0x68) +#define AW_PID_2049_DSMCFG3_REG (0x69) +#define AW_PID_2049_DSMCFG4_REG (0x6A) +#define AW_PID_2049_DSMCFG5_REG (0x6B) +#define AW_PID_2049_DSMCFG6_REG (0x6C) +#define AW_PID_2049_DSMCFG7_REG (0x6D) +#define AW_PID_2049_DSMCFG8_REG (0x6E) +#define AW_PID_2049_TESTCTRL1_REG (0x70) +#define AW_PID_2049_TESTCTRL2_REG (0x71) +#define AW_PID_2049_EFCTRL1_REG (0x72) +#define AW_PID_2049_EFCTRL2_REG (0x73) +#define AW_PID_2049_EFWH_REG (0x74) +#define AW_PID_2049_EFWM2_REG (0x75) +#define AW_PID_2049_EFWM1_REG (0x76) +#define AW_PID_2049_EFWL_REG (0x77) +#define AW_PID_2049_EFRH_REG (0x78) +#define AW_PID_2049_EFRM2_REG (0x79) +#define AW_PID_2049_EFRM1_REG (0x7A) +#define AW_PID_2049_EFRL_REG (0x7B) +#define AW_PID_2049_TM_REG (0x7C) + +/* + * Register Access + */ +enum aw883xx_id { + AW883XX_PID_2049 = 0x2049, +}; + +#define AW_PID_2049_REG_MAX (0x7D) + +#define REG_NONE_ACCESS (0) +#define REG_RD_ACCESS (1 << 0) +#define REG_WR_ACCESS (1 << 1) + +#define AW_PID_2049_VOLUME_STEP_DB (6 * 8) + +/* detail information of registers begin */ +/* ID (0x00) detail */ +/* IDCODE bit 15:0 (ID 0x00) */ +#define AW_PID_2049_IDCODE_START_BIT (0) +#define AW_PID_2049_IDCODE_BITS_LEN (16) +#define AW_PID_2049_IDCODE_MASK \ + (~(((1<<AW_PID_2049_IDCODE_BITS_LEN)-1) << AW_PID_2049_IDCODE_START_BIT)) + +#define AW_PID_2049_IDCODE_DEFAULT_VALUE (0x2049) +#define AW_PID_2049_IDCODE_DEFAULT \ + (AW_PID_2049_IDCODE_DEFAULT_VALUE << AW_PID_2049_IDCODE_START_BIT) + +#define AW_PID_2049_SOFT_RESET_VALUE (0x55aa) + +/* default value of ID (0x00) */ +/* #define AW_PID_2049_ID_DEFAULT (0x2049) */ + +/* SYSST (0x01) detail */ +/* OVP2S bit 15 (SYSST 0x01) */ +#define AW_PID_2049_OVP2S_START_BIT (15) +#define AW_PID_2049_OVP2S_BITS_LEN (1) +#define AW_PID_2049_OVP2S_MASK \ + (~(((1<<AW_PID_2049_OVP2S_BITS_LEN)-1) << AW_PID_2049_OVP2S_START_BIT)) + +#define AW_PID_2049_OVP2S_NORMAL (0) +#define AW_PID_2049_OVP2S_NORMAL_VALUE \ + (AW_PID_2049_OVP2S_NORMAL << AW_PID_2049_OVP2S_START_BIT) + +#define AW_PID_2049_OVP2S_OVP (1) +#define AW_PID_2049_OVP2S_OVP_VALUE \ + (AW_PID_2049_OVP2S_OVP << AW_PID_2049_OVP2S_START_BIT) + +#define AW_PID_2049_OVP2S_DEFAULT_VALUE (0) +#define AW_PID_2049_OVP2S_DEFAULT \ + (AW_PID_2049_OVP2S_DEFAULT_VALUE << AW_PID_2049_OVP2S_START_BIT) + +/* UVLS bit 14 (SYSST 0x01) */ +#define AW_PID_2049_UVLS_START_BIT (14) +#define AW_PID_2049_UVLS_BITS_LEN (1) +#define AW_PID_2049_UVLS_MASK \ + (~(((1<<AW_PID_2049_UVLS_BITS_LEN)-1) << AW_PID_2049_UVLS_START_BIT)) + +#define AW_PID_2049_UVLS_NORMAL (0) +#define AW_PID_2049_UVLS_NORMAL_VALUE \ + (AW_PID_2049_UVLS_NORMAL << AW_PID_2049_UVLS_START_BIT) + +#define AW_PID_2049_UVLS_UVLO (1) +#define AW_PID_2049_UVLS_UVLO_VALUE \ + (AW_PID_2049_UVLS_UVLO << AW_PID_2049_UVLS_START_BIT) + +#define AW_PID_2049_UVLS_DEFAULT_VALUE (0) +#define AW_PID_2049_UVLS_DEFAULT \ + (AW_PID_2049_UVLS_DEFAULT_VALUE << AW_PID_2049_UVLS_START_BIT) + +/* ADPS bit 13 (SYSST 0x01) */ +#define AW_PID_2049_ADPS_START_BIT (13) +#define AW_PID_2049_ADPS_BITS_LEN (1) +#define AW_PID_2049_ADPS_MASK \ + (~(((1<<AW_PID_2049_ADPS_BITS_LEN)-1) << AW_PID_2049_ADPS_START_BIT)) + +#define AW_PID_2049_ADPS_TRANSPARENT (0) +#define AW_PID_2049_ADPS_TRANSPARENT_VALUE \ + (AW_PID_2049_ADPS_TRANSPARENT << AW_PID_2049_ADPS_START_BIT) + +#define AW_PID_2049_ADPS_BOOST (1) +#define AW_PID_2049_ADPS_BOOST_VALUE \ + (AW_PID_2049_ADPS_BOOST << AW_PID_2049_ADPS_START_BIT) + +#define AW_PID_2049_ADPS_DEFAULT_VALUE (0) +#define AW_PID_2049_ADPS_DEFAULT \ + (AW_PID_2049_ADPS_DEFAULT_VALUE << AW_PID_2049_ADPS_START_BIT) + +/* DSPS bit 12 (SYSST 0x01) */ +#define AW_PID_2049_DSPS_START_BIT (12) +#define AW_PID_2049_DSPS_BITS_LEN (1) +#define AW_PID_2049_DSPS_MASK \ + (~(((1<<AW_PID_2049_DSPS_BITS_LEN)-1) << AW_PID_2049_DSPS_START_BIT)) + +#define AW_PID_2049_DSPS_NORMAL (0) +#define AW_PID_2049_DSPS_NORMAL_VALUE \ + (AW_PID_2049_DSPS_NORMAL << AW_PID_2049_DSPS_START_BIT) + +#define AW_PID_2049_DSPS_DSP_STABLE (1) +#define AW_PID_2049_DSPS_DSP_STABLE_VALUE \ + (AW_PID_2049_DSPS_DSP_STABLE << AW_PID_2049_DSPS_START_BIT) + +#define AW_PID_2049_DSPS_DEFAULT_VALUE (0) +#define AW_PID_2049_DSPS_DEFAULT \ + (AW_PID_2049_DSPS_DEFAULT_VALUE << AW_PID_2049_DSPS_START_BIT) + +/* BSTOCS bit 11 (SYSST 0x01) */ +#define AW_PID_2049_BSTOCS_START_BIT (11) +#define AW_PID_2049_BSTOCS_BITS_LEN (1) +#define AW_PID_2049_BSTOCS_MASK \ + (~(((1<<AW_PID_2049_BSTOCS_BITS_LEN)-1) << AW_PID_2049_BSTOCS_START_BIT)) + +#define AW_PID_2049_BSTOCS_NORMAL (0) +#define AW_PID_2049_BSTOCS_NORMAL_VALUE \ + (AW_PID_2049_BSTOCS_NORMAL << AW_PID_2049_BSTOCS_START_BIT) + +#define AW_PID_2049_BSTOCS_OVER_CURRENT (1) +#define AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE \ + (AW_PID_2049_BSTOCS_OVER_CURRENT << AW_PID_2049_BSTOCS_START_BIT) + +#define AW_PID_2049_BSTOCS_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTOCS_DEFAULT \ + (AW_PID_2049_BSTOCS_DEFAULT_VALUE << AW_PID_2049_BSTOCS_START_BIT) + +/* OVPS bit 10 (SYSST 0x01) */ +#define AW_PID_2049_OVPS_START_BIT (10) +#define AW_PID_2049_OVPS_BITS_LEN (1) +#define AW_PID_2049_OVPS_MASK \ + (~(((1<<AW_PID_2049_OVPS_BITS_LEN)-1) << AW_PID_2049_OVPS_START_BIT)) + +#define AW_PID_2049_OVPS_NORMAL (0) +#define AW_PID_2049_OVPS_NORMAL_VALUE \ + (AW_PID_2049_OVPS_NORMAL << AW_PID_2049_OVPS_START_BIT) + +#define AW_PID_2049_OVPS_OVP (1) +#define AW_PID_2049_OVPS_OVP_VALUE \ + (AW_PID_2049_OVPS_OVP << AW_PID_2049_OVPS_START_BIT) + +#define AW_PID_2049_OVPS_DEFAULT_VALUE (0) +#define AW_PID_2049_OVPS_DEFAULT \ + (AW_PID_2049_OVPS_DEFAULT_VALUE << AW_PID_2049_OVPS_START_BIT) + +/* BSTS bit 9 (SYSST 0x01) */ +#define AW_PID_2049_BSTS_START_BIT (9) +#define AW_PID_2049_BSTS_BITS_LEN (1) +#define AW_PID_2049_BSTS_MASK \ + (~(((1<<AW_PID_2049_BSTS_BITS_LEN)-1) << AW_PID_2049_BSTS_START_BIT)) + +#define AW_PID_2049_BSTS_NOT_FINISHED (0) +#define AW_PID_2049_BSTS_NOT_FINISHED_VALUE \ + (AW_PID_2049_BSTS_NOT_FINISHED << AW_PID_2049_BSTS_START_BIT) + +#define AW_PID_2049_BSTS_FINISHED (1) +#define AW_PID_2049_BSTS_FINISHED_VALUE \ + (AW_PID_2049_BSTS_FINISHED << AW_PID_2049_BSTS_START_BIT) + +#define AW_PID_2049_BSTS_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTS_DEFAULT \ + (AW_PID_2049_BSTS_DEFAULT_VALUE << AW_PID_2049_BSTS_START_BIT) + +/* SWS bit 8 (SYSST 0x01) */ +#define AW_PID_2049_SWS_START_BIT (8) +#define AW_PID_2049_SWS_BITS_LEN (1) +#define AW_PID_2049_SWS_MASK \ + (~(((1<<AW_PID_2049_SWS_BITS_LEN)-1) << AW_PID_2049_SWS_START_BIT)) + +#define AW_PID_2049_SWS_NOT_SWITCHING (0) +#define AW_PID_2049_SWS_NOT_SWITCHING_VALUE \ + (AW_PID_2049_SWS_NOT_SWITCHING << AW_PID_2049_SWS_START_BIT) + +#define AW_PID_2049_SWS_SWITCHING (1) +#define AW_PID_2049_SWS_SWITCHING_VALUE \ + (AW_PID_2049_SWS_SWITCHING << AW_PID_2049_SWS_START_BIT) + +#define AW_PID_2049_SWS_DEFAULT_VALUE (0) +#define AW_PID_2049_SWS_DEFAULT \ + (AW_PID_2049_SWS_DEFAULT_VALUE << AW_PID_2049_SWS_START_BIT) + +/* CLIPS bit 7 (SYSST 0x01) */ +#define AW_PID_2049_CLIPS_START_BIT (7) +#define AW_PID_2049_CLIPS_BITS_LEN (1) +#define AW_PID_2049_CLIPS_MASK \ + (~(((1<<AW_PID_2049_CLIPS_BITS_LEN)-1) << AW_PID_2049_CLIPS_START_BIT)) + +#define AW_PID_2049_CLIPS_NOT_CLIPPING (0) +#define AW_PID_2049_CLIPS_NOT_CLIPPING_VALUE \ + (AW_PID_2049_CLIPS_NOT_CLIPPING << AW_PID_2049_CLIPS_START_BIT) + +#define AW_PID_2049_CLIPS_CLIPPING (1) +#define AW_PID_2049_CLIPS_CLIPPING_VALUE \ + (AW_PID_2049_CLIPS_CLIPPING << AW_PID_2049_CLIPS_START_BIT) + +#define AW_PID_2049_CLIPS_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIPS_DEFAULT \ + (AW_PID_2049_CLIPS_DEFAULT_VALUE << AW_PID_2049_CLIPS_START_BIT) + +/* WDS bit 6 (SYSST 0x01) */ +#define AW_PID_2049_WDS_START_BIT (6) +#define AW_PID_2049_WDS_BITS_LEN (1) +#define AW_PID_2049_WDS_MASK \ + (~(((1<<AW_PID_2049_WDS_BITS_LEN)-1) << AW_PID_2049_WDS_START_BIT)) + +#define AW_PID_2049_WDS_NORMAL (0) +#define AW_PID_2049_WDS_NORMAL_VALUE \ + (AW_PID_2049_WDS_NORMAL << AW_PID_2049_WDS_START_BIT) + +#define AW_PID_2049_WDS_ABNORMAL (1) +#define AW_PID_2049_WDS_ABNORMAL_VALUE \ + (AW_PID_2049_WDS_ABNORMAL << AW_PID_2049_WDS_START_BIT) + +#define AW_PID_2049_WDS_DEFAULT_VALUE (0) +#define AW_PID_2049_WDS_DEFAULT \ + (AW_PID_2049_WDS_DEFAULT_VALUE << AW_PID_2049_WDS_START_BIT) + +/* NOCLKS bit 5 (SYSST 0x01) */ +#define AW_PID_2049_NOCLKS_START_BIT (5) +#define AW_PID_2049_NOCLKS_BITS_LEN (1) +#define AW_PID_2049_NOCLKS_MASK \ + (~(((1<<AW_PID_2049_NOCLKS_BITS_LEN)-1) << AW_PID_2049_NOCLKS_START_BIT)) + +#define AW_PID_2049_NOCLKS_CLOCK_OK (0) +#define AW_PID_2049_NOCLKS_CLOCK_OK_VALUE \ + (AW_PID_2049_NOCLKS_CLOCK_OK << AW_PID_2049_NOCLKS_START_BIT) + +#define AW_PID_2049_NOCLKS_NO_CLOCK (1) +#define AW_PID_2049_NOCLKS_NO_CLOCK_VALUE \ + (AW_PID_2049_NOCLKS_NO_CLOCK << AW_PID_2049_NOCLKS_START_BIT) + +#define AW_PID_2049_NOCLKS_DEFAULT_VALUE (0) +#define AW_PID_2049_NOCLKS_DEFAULT \ + (AW_PID_2049_NOCLKS_DEFAULT_VALUE << AW_PID_2049_NOCLKS_START_BIT) + +/* CLKS bit 4 (SYSST 0x01) */ +#define AW_PID_2049_CLKS_START_BIT (4) +#define AW_PID_2049_CLKS_BITS_LEN (1) +#define AW_PID_2049_CLKS_MASK \ + (~(((1<<AW_PID_2049_CLKS_BITS_LEN)-1) << AW_PID_2049_CLKS_START_BIT)) + +#define AW_PID_2049_CLKS_NOT_STABLE (0) +#define AW_PID_2049_CLKS_NOT_STABLE_VALUE \ + (AW_PID_2049_CLKS_NOT_STABLE << AW_PID_2049_CLKS_START_BIT) + +#define AW_PID_2049_CLKS_STABLE (1) +#define AW_PID_2049_CLKS_STABLE_VALUE \ + (AW_PID_2049_CLKS_STABLE << AW_PID_2049_CLKS_START_BIT) + +#define AW_PID_2049_CLKS_DEFAULT_VALUE (0) +#define AW_PID_2049_CLKS_DEFAULT \ + (AW_PID_2049_CLKS_DEFAULT_VALUE << AW_PID_2049_CLKS_START_BIT) + +/* OCDS bit 3 (SYSST 0x01) */ +#define AW_PID_2049_OCDS_START_BIT (3) +#define AW_PID_2049_OCDS_BITS_LEN (1) +#define AW_PID_2049_OCDS_MASK \ + (~(((1<<AW_PID_2049_OCDS_BITS_LEN)-1) << AW_PID_2049_OCDS_START_BIT)) + +#define AW_PID_2049_OCDS_NORAML (0) +#define AW_PID_2049_OCDS_NORAML_VALUE \ + (AW_PID_2049_OCDS_NORAML << AW_PID_2049_OCDS_START_BIT) + +#define AW_PID_2049_OCDS_OC (1) +#define AW_PID_2049_OCDS_OC_VALUE \ + (AW_PID_2049_OCDS_OC << AW_PID_2049_OCDS_START_BIT) + +#define AW_PID_2049_OCDS_DEFAULT_VALUE (0) +#define AW_PID_2049_OCDS_DEFAULT \ + (AW_PID_2049_OCDS_DEFAULT_VALUE << AW_PID_2049_OCDS_START_BIT) + +/* CLIP_PRES bit 2 (SYSST 0x01) */ +#define AW_PID_2049_CLIP_PRES_START_BIT (2) +#define AW_PID_2049_CLIP_PRES_BITS_LEN (1) +#define AW_PID_2049_CLIP_PRES_MASK \ + (~(((1<<AW_PID_2049_CLIP_PRES_BITS_LEN)-1) << AW_PID_2049_CLIP_PRES_START_BIT)) + +#define AW_PID_2049_CLIP_PRES_NOT_CLIPPING (0) +#define AW_PID_2049_CLIP_PRES_NOT_CLIPPING_VALUE \ + (AW_PID_2049_CLIP_PRES_NOT_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT) + +#define AW_PID_2049_CLIP_PRES_CLIPPING (1) +#define AW_PID_2049_CLIP_PRES_CLIPPING_VALUE \ + (AW_PID_2049_CLIP_PRES_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT) + +#define AW_PID_2049_CLIP_PRES_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIP_PRES_DEFAULT \ + (AW_PID_2049_CLIP_PRES_DEFAULT_VALUE << AW_PID_2049_CLIP_PRES_START_BIT) + +/* OTHS bit 1 (SYSST 0x01) */ +#define AW_PID_2049_OTHS_START_BIT (1) +#define AW_PID_2049_OTHS_BITS_LEN (1) +#define AW_PID_2049_OTHS_MASK \ + (~(((1<<AW_PID_2049_OTHS_BITS_LEN)-1) << AW_PID_2049_OTHS_START_BIT)) + +#define AW_PID_2049_OTHS_NORMAL (0) +#define AW_PID_2049_OTHS_NORMAL_VALUE \ + (AW_PID_2049_OTHS_NORMAL << AW_PID_2049_OTHS_START_BIT) + +#define AW_PID_2049_OTHS_OT (1) +#define AW_PID_2049_OTHS_OT_VALUE \ + (AW_PID_2049_OTHS_OT << AW_PID_2049_OTHS_START_BIT) + +#define AW_PID_2049_OTHS_DEFAULT_VALUE (0) +#define AW_PID_2049_OTHS_DEFAULT \ + (AW_PID_2049_OTHS_DEFAULT_VALUE << AW_PID_2049_OTHS_START_BIT) + +/* PLLS bit 0 (SYSST 0x01) */ +#define AW_PID_2049_PLLS_START_BIT (0) +#define AW_PID_2049_PLLS_BITS_LEN (1) +#define AW_PID_2049_PLLS_MASK \ + (~(((1<<AW_PID_2049_PLLS_BITS_LEN)-1) << AW_PID_2049_PLLS_START_BIT)) + +#define AW_PID_2049_PLLS_UNLOCKED (0) +#define AW_PID_2049_PLLS_UNLOCKED_VALUE \ + (AW_PID_2049_PLLS_UNLOCKED << AW_PID_2049_PLLS_START_BIT) + +#define AW_PID_2049_PLLS_LOCKED (1) +#define AW_PID_2049_PLLS_LOCKED_VALUE \ + (AW_PID_2049_PLLS_LOCKED << AW_PID_2049_PLLS_START_BIT) + +#define AW_PID_2049_PLLS_DEFAULT_VALUE (0) +#define AW_PID_2049_PLLS_DEFAULT \ + (AW_PID_2049_PLLS_DEFAULT_VALUE << AW_PID_2049_PLLS_START_BIT) + + + +#define AW_PID_2049_BIT_PLL_CHECK \ + (AW_PID_2049_CLKS_STABLE_VALUE | \ + AW_PID_2049_PLLS_LOCKED_VALUE) + + +#define AW_PID_2049_BIT_SYSST_CHECK_MASK \ + (~(AW_PID_2049_UVLS_NORMAL_VALUE | \ + AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE | \ + AW_PID_2049_BSTS_FINISHED_VALUE | \ + AW_PID_2049_SWS_SWITCHING_VALUE | \ + AW_PID_2049_NOCLKS_NO_CLOCK_VALUE | \ + AW_PID_2049_CLKS_STABLE_VALUE | \ + AW_PID_2049_OCDS_OC_VALUE | \ + AW_PID_2049_OTHS_OT_VALUE | \ + AW_PID_2049_PLLS_LOCKED_VALUE)) + +#define AW_PID_2049_BIT_SYSST_CHECK \ + (AW_PID_2049_BSTS_FINISHED_VALUE | \ + AW_PID_2049_SWS_SWITCHING_VALUE | \ + AW_PID_2049_CLKS_STABLE_VALUE | \ + AW_PID_2049_PLLS_LOCKED_VALUE) + +/* default value of SYSST (0x01) */ +/* #define AW_PID_2049_SYSST_DEFAULT (0x0000) */ + +/* SYSINT (0x02) detail */ +/* OVP2I bit 15 (SYSINT 0x02) */ +#define AW_PID_2049_OVP2I_START_BIT (15) +#define AW_PID_2049_OVP2I_BITS_LEN (1) +#define AW_PID_2049_OVP2I_MASK \ + (~(((1<<AW_PID_2049_OVP2I_BITS_LEN)-1) << AW_PID_2049_OVP2I_START_BIT)) + +#define AW_PID_2049_OVP2I_DEFAULT_VALUE (0) +#define AW_PID_2049_OVP2I_DEFAULT \ + (AW_PID_2049_OVP2I_DEFAULT_VALUE << AW_PID_2049_OVP2I_START_BIT) + +/* UVLI bit 14 (SYSINT 0x02) */ +#define AW_PID_2049_UVLI_START_BIT (14) +#define AW_PID_2049_UVLI_BITS_LEN (1) +#define AW_PID_2049_UVLI_MASK \ + (~(((1<<AW_PID_2049_UVLI_BITS_LEN)-1) << AW_PID_2049_UVLI_START_BIT)) + +#define AW_PID_2049_UVLI_DEFAULT_VALUE (0) +#define AW_PID_2049_UVLI_DEFAULT \ + (AW_PID_2049_UVLI_DEFAULT_VALUE << AW_PID_2049_UVLI_START_BIT) + +/* ADPI bit 13 (SYSINT 0x02) */ +#define AW_PID_2049_ADPI_START_BIT (13) +#define AW_PID_2049_ADPI_BITS_LEN (1) +#define AW_PID_2049_ADPI_MASK \ + (~(((1<<AW_PID_2049_ADPI_BITS_LEN)-1) << AW_PID_2049_ADPI_START_BIT)) + +#define AW_PID_2049_ADPI_DEFAULT_VALUE (0) +#define AW_PID_2049_ADPI_DEFAULT \ + (AW_PID_2049_ADPI_DEFAULT_VALUE << AW_PID_2049_ADPI_START_BIT) + +/* DSPI bit 12 (SYSINT 0x02) */ +#define AW_PID_2049_DSPI_START_BIT (12) +#define AW_PID_2049_DSPI_BITS_LEN (1) +#define AW_PID_2049_DSPI_MASK \ + (~(((1<<AW_PID_2049_DSPI_BITS_LEN)-1) << AW_PID_2049_DSPI_START_BIT)) + +#define AW_PID_2049_DSPI_DEFAULT_VALUE (0) +#define AW_PID_2049_DSPI_DEFAULT \ + (AW_PID_2049_DSPI_DEFAULT_VALUE << AW_PID_2049_DSPI_START_BIT) + +/* BSTOCI bit 11 (SYSINT 0x02) */ +#define AW_PID_2049_BSTOCI_START_BIT (11) +#define AW_PID_2049_BSTOCI_BITS_LEN (1) +#define AW_PID_2049_BSTOCI_MASK \ + (~(((1<<AW_PID_2049_BSTOCI_BITS_LEN)-1) << AW_PID_2049_BSTOCI_START_BIT)) + +#define AW_PID_2049_BSTOCI_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTOCI_DEFAULT \ + (AW_PID_2049_BSTOCI_DEFAULT_VALUE << AW_PID_2049_BSTOCI_START_BIT) + +/* OVPI bit 10 (SYSINT 0x02) */ +#define AW_PID_2049_OVPI_START_BIT (10) +#define AW_PID_2049_OVPI_BITS_LEN (1) +#define AW_PID_2049_OVPI_MASK \ + (~(((1<<AW_PID_2049_OVPI_BITS_LEN)-1) << AW_PID_2049_OVPI_START_BIT)) + +#define AW_PID_2049_OVPI_DEFAULT_VALUE (0) +#define AW_PID_2049_OVPI_DEFAULT \ + (AW_PID_2049_OVPI_DEFAULT_VALUE << AW_PID_2049_OVPI_START_BIT) + +/* BSTI bit 9 (SYSINT 0x02) */ +#define AW_PID_2049_BSTI_START_BIT (9) +#define AW_PID_2049_BSTI_BITS_LEN (1) +#define AW_PID_2049_BSTI_MASK \ + (~(((1<<AW_PID_2049_BSTI_BITS_LEN)-1) << AW_PID_2049_BSTI_START_BIT)) + +#define AW_PID_2049_BSTI_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTI_DEFAULT \ + (AW_PID_2049_BSTI_DEFAULT_VALUE << AW_PID_2049_BSTI_START_BIT) + +/* SWI bit 8 (SYSINT 0x02) */ +#define AW_PID_2049_SWI_START_BIT (8) +#define AW_PID_2049_SWI_BITS_LEN (1) +#define AW_PID_2049_SWI_MASK \ + (~(((1<<AW_PID_2049_SWI_BITS_LEN)-1) << AW_PID_2049_SWI_START_BIT)) + +#define AW_PID_2049_SWI_DEFAULT_VALUE (0) +#define AW_PID_2049_SWI_DEFAULT \ + (AW_PID_2049_SWI_DEFAULT_VALUE << AW_PID_2049_SWI_START_BIT) + +/* CLIPI bit 7 (SYSINT 0x02) */ +#define AW_PID_2049_CLIPI_START_BIT (7) +#define AW_PID_2049_CLIPI_BITS_LEN (1) +#define AW_PID_2049_CLIPI_MASK \ + (~(((1<<AW_PID_2049_CLIPI_BITS_LEN)-1) << AW_PID_2049_CLIPI_START_BIT)) + +#define AW_PID_2049_CLIPI_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIPI_DEFAULT \ + (AW_PID_2049_CLIPI_DEFAULT_VALUE << AW_PID_2049_CLIPI_START_BIT) + +/* WDI bit 6 (SYSINT 0x02) */ +#define AW_PID_2049_WDI_START_BIT (6) +#define AW_PID_2049_WDI_BITS_LEN (1) +#define AW_PID_2049_WDI_MASK \ + (~(((1<<AW_PID_2049_WDI_BITS_LEN)-1) << AW_PID_2049_WDI_START_BIT)) + +#define AW_PID_2049_WDI_DEFAULT_VALUE (0) +#define AW_PID_2049_WDI_INT_VALUE (1) +#define AW_PID_2049_WDI_DEFAULT \ + (AW_PID_2049_WDI_DEFAULT_VALUE << AW_PID_2049_WDI_START_BIT) +#define AW_PID_2049_WDI_INTERRUPT \ + (AW_PID_2049_WDI_INT_VALUE << AW_PID_2049_WDI_START_BIT) + +/* NOCLKI bit 5 (SYSINT 0x02) */ +#define AW_PID_2049_NOCLKI_START_BIT (5) +#define AW_PID_2049_NOCLKI_BITS_LEN (1) +#define AW_PID_2049_NOCLKI_MASK \ + (~(((1<<AW_PID_2049_NOCLKI_BITS_LEN)-1) << AW_PID_2049_NOCLKI_START_BIT)) + +#define AW_PID_2049_NOCLKI_DEFAULT_VALUE (0) +#define AW_PID_2049_NOCLKI_INT_VALUE (1) +#define AW_PID_2049_NOCLKI_DEFAULT \ + (AW_PID_2049_NOCLKI_DEFAULT_VALUE << AW_PID_2049_NOCLKI_START_BIT) +#define AW_PID_2049_NOCLKI_INTERRUPT \ + (AW_PID_2049_NOCLKI_INT_VALUE << AW_PID_2049_NOCLKI_START_BIT) + +/* CLKI bit 4 (SYSINT 0x02) */ +#define AW_PID_2049_CLKI_START_BIT (4) +#define AW_PID_2049_CLKI_BITS_LEN (1) +#define AW_PID_2049_CLKI_MASK \ + (~(((1<<AW_PID_2049_CLKI_BITS_LEN)-1) << AW_PID_2049_CLKI_START_BIT)) + +#define AW_PID_2049_CLKI_DEFAULT_VALUE (0) +#define AW_PID_2049_CLKI_INT_VALUE (1) +#define AW_PID_2049_CLKI_DEFAULT \ + (AW_PID_2049_CLKI_DEFAULT_VALUE << AW_PID_2049_CLKI_START_BIT) +#define AW_PID_2049_CLKI_INTERRUPT \ + (AW_PID_2049_CLKI_INT_VALUE << AW_PID_2049_CLKI_START_BIT) + +/* OCDI bit 3 (SYSINT 0x02) */ +#define AW_PID_2049_OCDI_START_BIT (3) +#define AW_PID_2049_OCDI_BITS_LEN (1) +#define AW_PID_2049_OCDI_MASK \ + (~(((1<<AW_PID_2049_OCDI_BITS_LEN)-1) << AW_PID_2049_OCDI_START_BIT)) + +#define AW_PID_2049_OCDI_DEFAULT_VALUE (0) +#define AW_PID_2049_OCDI_DEFAULT \ + (AW_PID_2049_OCDI_DEFAULT_VALUE << AW_PID_2049_OCDI_START_BIT) + +/* CLIP_PREI bit 2 (SYSINT 0x02) */ +#define AW_PID_2049_CLIP_PREI_START_BIT (2) +#define AW_PID_2049_CLIP_PREI_BITS_LEN (1) +#define AW_PID_2049_CLIP_PREI_MASK \ + (~(((1<<AW_PID_2049_CLIP_PREI_BITS_LEN)-1) << AW_PID_2049_CLIP_PREI_START_BIT)) + +#define AW_PID_2049_CLIP_PREI_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIP_PREI_DEFAULT \ + (AW_PID_2049_CLIP_PREI_DEFAULT_VALUE << AW_PID_2049_CLIP_PREI_START_BIT) + +/* OTHI bit 1 (SYSINT 0x02) */ +#define AW_PID_2049_OTHI_START_BIT (1) +#define AW_PID_2049_OTHI_BITS_LEN (1) +#define AW_PID_2049_OTHI_MASK \ + (~(((1<<AW_PID_2049_OTHI_BITS_LEN)-1) << AW_PID_2049_OTHI_START_BIT)) + +#define AW_PID_2049_OTHI_DEFAULT_VALUE (0) +#define AW_PID_2049_OTHI_DEFAULT \ + (AW_PID_2049_OTHI_DEFAULT_VALUE << AW_PID_2049_OTHI_START_BIT) + +/* PLLI bit 0 (SYSINT 0x02) */ +#define AW_PID_2049_PLLI_START_BIT (0) +#define AW_PID_2049_PLLI_BITS_LEN (1) +#define AW_PID_2049_PLLI_MASK \ + (~(((1<<AW_PID_2049_PLLI_BITS_LEN)-1) << AW_PID_2049_PLLI_START_BIT)) + +#define AW_PID_2049_PLLI_DEFAULT_VALUE (0) +#define AW_PID_2049_PLLI_INT_VALUE (1) +#define AW_PID_2049_PLLI_DEFAULT \ + (AW_PID_2049_PLLI_DEFAULT_VALUE << AW_PID_2049_PLLI_START_BIT) +#define AW_PID_2049_PLLI_INTERRUPT \ + (AW_PID_2049_PLLI_INT_VALUE << AW_PID_2049_PLLI_START_BIT) + +/* default value of SYSINT (0x02) */ +/* #define AW_PID_2049_SYSINT_DEFAULT (0x0000) */ + +#define AW_PID_2049_BIT_SYSINT_CHECK \ + (AW_PID_2049_WDI_INTERRUPT | \ + AW_PID_2049_CLKI_INTERRUPT | \ + AW_PID_2049_NOCLKI_INTERRUPT | \ + AW_PID_2049_PLLI_INTERRUPT) + +/* SYSINTM (0x03) detail */ +/* OVP2M bit 15 (SYSINTM 0x03) */ +#define AW_PID_2049_OVP2M_START_BIT (15) +#define AW_PID_2049_OVP2M_BITS_LEN (1) +#define AW_PID_2049_OVP2M_MASK \ + (~(((1<<AW_PID_2049_OVP2M_BITS_LEN)-1) << AW_PID_2049_OVP2M_START_BIT)) + +#define AW_PID_2049_OVP2M_DEFAULT_VALUE (1) +#define AW_PID_2049_OVP2M_DEFAULT \ + (AW_PID_2049_OVP2M_DEFAULT_VALUE << AW_PID_2049_OVP2M_START_BIT) + +/* UVLM bit 14 (SYSINTM 0x03) */ +#define AW_PID_2049_UVLM_START_BIT (14) +#define AW_PID_2049_UVLM_BITS_LEN (1) +#define AW_PID_2049_UVLM_MASK \ + (~(((1<<AW_PID_2049_UVLM_BITS_LEN)-1) << AW_PID_2049_UVLM_START_BIT)) + +#define AW_PID_2049_UVLM_DEFAULT_VALUE (1) +#define AW_PID_2049_UVLM_DEFAULT \ + (AW_PID_2049_UVLM_DEFAULT_VALUE << AW_PID_2049_UVLM_START_BIT) + +/* ADPM bit 13 (SYSINTM 0x03) */ +#define AW_PID_2049_ADPM_START_BIT (13) +#define AW_PID_2049_ADPM_BITS_LEN (1) +#define AW_PID_2049_ADPM_MASK \ + (~(((1<<AW_PID_2049_ADPM_BITS_LEN)-1) << AW_PID_2049_ADPM_START_BIT)) + +#define AW_PID_2049_ADPM_DEFAULT_VALUE (1) +#define AW_PID_2049_ADPM_DEFAULT \ + (AW_PID_2049_ADPM_DEFAULT_VALUE << AW_PID_2049_ADPM_START_BIT) + +/* DSPM bit 12 (SYSINTM 0x03) */ +#define AW_PID_2049_DSPM_START_BIT (12) +#define AW_PID_2049_DSPM_BITS_LEN (1) +#define AW_PID_2049_DSPM_MASK \ + (~(((1<<AW_PID_2049_DSPM_BITS_LEN)-1) << AW_PID_2049_DSPM_START_BIT)) + +#define AW_PID_2049_DSPM_DEFAULT_VALUE (1) +#define AW_PID_2049_DSPM_DEFAULT \ + (AW_PID_2049_DSPM_DEFAULT_VALUE << AW_PID_2049_DSPM_START_BIT) + +/* BSTOCM bit 11 (SYSINTM 0x03) */ +#define AW_PID_2049_BSTOCM_START_BIT (11) +#define AW_PID_2049_BSTOCM_BITS_LEN (1) +#define AW_PID_2049_BSTOCM_MASK \ + (~(((1<<AW_PID_2049_BSTOCM_BITS_LEN)-1) << AW_PID_2049_BSTOCM_START_BIT)) + +#define AW_PID_2049_BSTOCM_DEFAULT_VALUE (1) +#define AW_PID_2049_BSTOCM_DEFAULT \ + (AW_PID_2049_BSTOCM_DEFAULT_VALUE << AW_PID_2049_BSTOCM_START_BIT) + +/* OVPM bit 10 (SYSINTM 0x03) */ +#define AW_PID_2049_OVPM_START_BIT (10) +#define AW_PID_2049_OVPM_BITS_LEN (1) +#define AW_PID_2049_OVPM_MASK \ + (~(((1<<AW_PID_2049_OVPM_BITS_LEN)-1) << AW_PID_2049_OVPM_START_BIT)) + +#define AW_PID_2049_OVPM_DEFAULT_VALUE (1) +#define AW_PID_2049_OVPM_DEFAULT \ + (AW_PID_2049_OVPM_DEFAULT_VALUE << AW_PID_2049_OVPM_START_BIT) + +/* BSTM bit 9 (SYSINTM 0x03) */ +#define AW_PID_2049_BSTM_START_BIT (9) +#define AW_PID_2049_BSTM_BITS_LEN (1) +#define AW_PID_2049_BSTM_MASK \ + (~(((1<<AW_PID_2049_BSTM_BITS_LEN)-1) << AW_PID_2049_BSTM_START_BIT)) + +#define AW_PID_2049_BSTM_DEFAULT_VALUE (1) +#define AW_PID_2049_BSTM_DEFAULT \ + (AW_PID_2049_BSTM_DEFAULT_VALUE << AW_PID_2049_BSTM_START_BIT) + +/* SWM bit 8 (SYSINTM 0x03) */ +#define AW_PID_2049_SWM_START_BIT (8) +#define AW_PID_2049_SWM_BITS_LEN (1) +#define AW_PID_2049_SWM_MASK \ + (~(((1<<AW_PID_2049_SWM_BITS_LEN)-1) << AW_PID_2049_SWM_START_BIT)) + +#define AW_PID_2049_SWM_DEFAULT_VALUE (1) +#define AW_PID_2049_SWM_DEFAULT \ + (AW_PID_2049_SWM_DEFAULT_VALUE << AW_PID_2049_SWM_START_BIT) + +/* CLIPM bit 7 (SYSINTM 0x03) */ +#define AW_PID_2049_CLIPM_START_BIT (7) +#define AW_PID_2049_CLIPM_BITS_LEN (1) +#define AW_PID_2049_CLIPM_MASK \ + (~(((1<<AW_PID_2049_CLIPM_BITS_LEN)-1) << AW_PID_2049_CLIPM_START_BIT)) + +#define AW_PID_2049_CLIPM_DEFAULT_VALUE (1) +#define AW_PID_2049_CLIPM_DEFAULT \ + (AW_PID_2049_CLIPM_DEFAULT_VALUE << AW_PID_2049_CLIPM_START_BIT) + +/* WDM bit 6 (SYSINTM 0x03) */ +#define AW_PID_2049_WDM_START_BIT (6) +#define AW_PID_2049_WDM_BITS_LEN (1) +#define AW_PID_2049_WDM_MASK \ + (~(((1<<AW_PID_2049_WDM_BITS_LEN)-1) << AW_PID_2049_WDM_START_BIT)) + +#define AW_PID_2049_WDM_DEFAULT_VALUE (1) +#define AW_PID_2049_WDM_DEFAULT \ + (AW_PID_2049_WDM_DEFAULT_VALUE << AW_PID_2049_WDM_START_BIT) + +/* NOCLKM bit 5 (SYSINTM 0x03) */ +#define AW_PID_2049_NOCLKM_START_BIT (5) +#define AW_PID_2049_NOCLKM_BITS_LEN (1) +#define AW_PID_2049_NOCLKM_MASK \ + (~(((1<<AW_PID_2049_NOCLKM_BITS_LEN)-1) << AW_PID_2049_NOCLKM_START_BIT)) + +#define AW_PID_2049_NOCLKM_DEFAULT_VALUE (1) +#define AW_PID_2049_NOCLKM_DEFAULT \ + (AW_PID_2049_NOCLKM_DEFAULT_VALUE << AW_PID_2049_NOCLKM_START_BIT) + +/* CLKM bit 4 (SYSINTM 0x03) */ +#define AW_PID_2049_CLKM_START_BIT (4) +#define AW_PID_2049_CLKM_BITS_LEN (1) +#define AW_PID_2049_CLKM_MASK \ + (~(((1<<AW_PID_2049_CLKM_BITS_LEN)-1) << AW_PID_2049_CLKM_START_BIT)) + +#define AW_PID_2049_CLKM_DEFAULT_VALUE (1) +#define AW_PID_2049_CLKM_DEFAULT \ + (AW_PID_2049_CLKM_DEFAULT_VALUE << AW_PID_2049_CLKM_START_BIT) + +/* OCDM bit 3 (SYSINTM 0x03) */ +#define AW_PID_2049_OCDM_START_BIT (3) +#define AW_PID_2049_OCDM_BITS_LEN (1) +#define AW_PID_2049_OCDM_MASK \ + (~(((1<<AW_PID_2049_OCDM_BITS_LEN)-1) << AW_PID_2049_OCDM_START_BIT)) + +#define AW_PID_2049_OCDM_DEFAULT_VALUE (1) +#define AW_PID_2049_OCDM_DEFAULT \ + (AW_PID_2049_OCDM_DEFAULT_VALUE << AW_PID_2049_OCDM_START_BIT) + +/* CLIP_PREM bit 2 (SYSINTM 0x03) */ +#define AW_PID_2049_CLIP_PREM_START_BIT (2) +#define AW_PID_2049_CLIP_PREM_BITS_LEN (1) +#define AW_PID_2049_CLIP_PREM_MASK \ + (~(((1<<AW_PID_2049_CLIP_PREM_BITS_LEN)-1) << AW_PID_2049_CLIP_PREM_START_BIT)) + +#define AW_PID_2049_CLIP_PREM_DEFAULT_VALUE (1) +#define AW_PID_2049_CLIP_PREM_DEFAULT \ + (AW_PID_2049_CLIP_PREM_DEFAULT_VALUE << AW_PID_2049_CLIP_PREM_START_BIT) + +/* OTHM bit 1 (SYSINTM 0x03) */ +#define AW_PID_2049_OTHM_START_BIT (1) +#define AW_PID_2049_OTHM_BITS_LEN (1) +#define AW_PID_2049_OTHM_MASK \ + (~(((1<<AW_PID_2049_OTHM_BITS_LEN)-1) << AW_PID_2049_OTHM_START_BIT)) + +#define AW_PID_2049_OTHM_DEFAULT_VALUE (1) +#define AW_PID_2049_OTHM_DEFAULT \ + (AW_PID_2049_OTHM_DEFAULT_VALUE << AW_PID_2049_OTHM_START_BIT) + +/* PLLM bit 0 (SYSINTM 0x03) */ +#define AW_PID_2049_PLLM_START_BIT (0) +#define AW_PID_2049_PLLM_BITS_LEN (1) +#define AW_PID_2049_PLLM_MASK \ + (~(((1<<AW_PID_2049_PLLM_BITS_LEN)-1) << AW_PID_2049_PLLM_START_BIT)) + +#define AW_PID_2049_PLLM_DEFAULT_VALUE (1) +#define AW_PID_2049_PLLM_DEFAULT \ + (AW_PID_2049_PLLM_DEFAULT_VALUE << AW_PID_2049_PLLM_START_BIT) + +/* default value of SYSINTM (0x03) */ +#define AW_PID_2049_SYSINTM_DEFAULT (0xFFFF) + +/* SYSCTRL (0x04) detail */ +/* SPK_GAIN bit 14:12 (SYSCTRL 0x04) */ +#define AW_PID_2049_SPK_GAIN_START_BIT (12) +#define AW_PID_2049_SPK_GAIN_BITS_LEN (3) +#define AW_PID_2049_SPK_GAIN_MASK \ + (~(((1<<AW_PID_2049_SPK_GAIN_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_START_BIT)) + +#define AW_PID_2049_SPK_GAIN_4_AV (0) +#define AW_PID_2049_SPK_GAIN_4_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_4_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_4P67_AV (1) +#define AW_PID_2049_SPK_GAIN_4P67_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_4P67_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_6_AV (2) +#define AW_PID_2049_SPK_GAIN_6_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_6_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_7_AV (3) +#define AW_PID_2049_SPK_GAIN_7_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_7_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_12_AV (4) +#define AW_PID_2049_SPK_GAIN_12_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_12_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_14_AV (5) +#define AW_PID_2049_SPK_GAIN_14_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_14_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_DEFAULT_VALUE (0x5) +#define AW_PID_2049_SPK_GAIN_DEFAULT \ + (AW_PID_2049_SPK_GAIN_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_START_BIT) + +/* RMSE bit 11 (SYSCTRL 0x04) */ +#define AW_PID_2049_RMSE_START_BIT (11) +#define AW_PID_2049_RMSE_BITS_LEN (1) +#define AW_PID_2049_RMSE_MASK \ + (~(((1<<AW_PID_2049_RMSE_BITS_LEN)-1) << AW_PID_2049_RMSE_START_BIT)) + +#define AW_PID_2049_RMSE_PEAK_AGC (0) +#define AW_PID_2049_RMSE_PEAK_AGC_VALUE \ + (AW_PID_2049_RMSE_PEAK_AGC << AW_PID_2049_RMSE_START_BIT) + +#define AW_PID_2049_RMSE_RMS_AGC (1) +#define AW_PID_2049_RMSE_RMS_AGC_VALUE \ + (AW_PID_2049_RMSE_RMS_AGC << AW_PID_2049_RMSE_START_BIT) + +#define AW_PID_2049_RMSE_DEFAULT_VALUE (0) +#define AW_PID_2049_RMSE_DEFAULT \ + (AW_PID_2049_RMSE_DEFAULT_VALUE << AW_PID_2049_RMSE_START_BIT) + +/* HAGCE bit 10 (SYSCTRL 0x04) */ +#define AW_PID_2049_HAGCE_START_BIT (10) +#define AW_PID_2049_HAGCE_BITS_LEN (1) +#define AW_PID_2049_HAGCE_MASK \ + (~(((1<<AW_PID_2049_HAGCE_BITS_LEN)-1) << AW_PID_2049_HAGCE_START_BIT)) + +#define AW_PID_2049_HAGCE_DISABLE (0) +#define AW_PID_2049_HAGCE_DISABLE_VALUE \ + (AW_PID_2049_HAGCE_DISABLE << AW_PID_2049_HAGCE_START_BIT) + +#define AW_PID_2049_HAGCE_ENABLE (1) +#define AW_PID_2049_HAGCE_ENABLE_VALUE \ + (AW_PID_2049_HAGCE_ENABLE << AW_PID_2049_HAGCE_START_BIT) + +#define AW_PID_2049_HAGCE_DEFAULT_VALUE (0) +#define AW_PID_2049_HAGCE_DEFAULT \ + (AW_PID_2049_HAGCE_DEFAULT_VALUE << AW_PID_2049_HAGCE_START_BIT) + +/* HDCCE bit 9 (SYSCTRL 0x04) */ +#define AW_PID_2049_HDCCE_START_BIT (9) +#define AW_PID_2049_HDCCE_BITS_LEN (1) +#define AW_PID_2049_HDCCE_MASK \ + (~(((1<<AW_PID_2049_HDCCE_BITS_LEN)-1) << AW_PID_2049_HDCCE_START_BIT)) + +#define AW_PID_2049_HDCCE_DISABLE (0) +#define AW_PID_2049_HDCCE_DISABLE_VALUE \ + (AW_PID_2049_HDCCE_DISABLE << AW_PID_2049_HDCCE_START_BIT) + +#define AW_PID_2049_HDCCE_ENABLE (1) +#define AW_PID_2049_HDCCE_ENABLE_VALUE \ + (AW_PID_2049_HDCCE_ENABLE << AW_PID_2049_HDCCE_START_BIT) + +#define AW_PID_2049_HDCCE_DEFAULT_VALUE (1) +#define AW_PID_2049_HDCCE_DEFAULT \ + (AW_PID_2049_HDCCE_DEFAULT_VALUE << AW_PID_2049_HDCCE_START_BIT) + +/* HMUTE bit 8 (SYSCTRL 0x04) */ +#define AW_PID_2049_HMUTE_START_BIT (8) +#define AW_PID_2049_HMUTE_BITS_LEN (1) +#define AW_PID_2049_HMUTE_MASK \ + (~(((1<<AW_PID_2049_HMUTE_BITS_LEN)-1) << AW_PID_2049_HMUTE_START_BIT)) + +#define AW_PID_2049_HMUTE_DISABLE (0) +#define AW_PID_2049_HMUTE_DISABLE_VALUE \ + (AW_PID_2049_HMUTE_DISABLE << AW_PID_2049_HMUTE_START_BIT) + +#define AW_PID_2049_HMUTE_ENABLE (1) +#define AW_PID_2049_HMUTE_ENABLE_VALUE \ + (AW_PID_2049_HMUTE_ENABLE << AW_PID_2049_HMUTE_START_BIT) + +#define AW_PID_2049_HMUTE_DEFAULT_VALUE (1) +#define AW_PID_2049_HMUTE_DEFAULT \ + (AW_PID_2049_HMUTE_DEFAULT_VALUE << AW_PID_2049_HMUTE_START_BIT) + +/* RCV_MODE bit 7 (SYSCTRL 0x04) */ +#define AW_PID_2049_RCV_MODE_START_BIT (7) +#define AW_PID_2049_RCV_MODE_BITS_LEN (1) +#define AW_PID_2049_RCV_MODE_MASK \ + (~(((1<<AW_PID_2049_RCV_MODE_BITS_LEN)-1) << AW_PID_2049_RCV_MODE_START_BIT)) + +#define AW_PID_2049_RCV_MODE_SPEAKER (0) +#define AW_PID_2049_RCV_MODE_SPEAKER_VALUE \ + (AW_PID_2049_RCV_MODE_SPEAKER << AW_PID_2049_RCV_MODE_START_BIT) + +#define AW_PID_2049_RCV_MODE_RECEIVER (1) +#define AW_PID_2049_RCV_MODE_RECEIVER_VALUE \ + (AW_PID_2049_RCV_MODE_RECEIVER << AW_PID_2049_RCV_MODE_START_BIT) + +#define AW_PID_2049_RCV_MODE_DEFAULT_VALUE (0) +#define AW_PID_2049_RCV_MODE_DEFAULT \ + (AW_PID_2049_RCV_MODE_DEFAULT_VALUE << AW_PID_2049_RCV_MODE_START_BIT) + +/* I2SEN bit 6 (SYSCTRL 0x04) */ +#define AW_PID_2049_I2SEN_START_BIT (6) +#define AW_PID_2049_I2SEN_BITS_LEN (1) +#define AW_PID_2049_I2SEN_MASK \ + (~(((1<<AW_PID_2049_I2SEN_BITS_LEN)-1) << AW_PID_2049_I2SEN_START_BIT)) + +#define AW_PID_2049_I2SEN_DISABLE (0) +#define AW_PID_2049_I2SEN_DISABLE_VALUE \ + (AW_PID_2049_I2SEN_DISABLE << AW_PID_2049_I2SEN_START_BIT) + +#define AW_PID_2049_I2SEN_ENABLE (1) +#define AW_PID_2049_I2SEN_ENABLE_VALUE \ + (AW_PID_2049_I2SEN_ENABLE << AW_PID_2049_I2SEN_START_BIT) + +#define AW_PID_2049_I2SEN_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SEN_DEFAULT \ + (AW_PID_2049_I2SEN_DEFAULT_VALUE << AW_PID_2049_I2SEN_START_BIT) + +/* WSINV bit 5 (SYSCTRL 0x04) */ +#define AW_PID_2049_WSINV_START_BIT (5) +#define AW_PID_2049_WSINV_BITS_LEN (1) +#define AW_PID_2049_WSINV_MASK \ + (~(((1<<AW_PID_2049_WSINV_BITS_LEN)-1) << AW_PID_2049_WSINV_START_BIT)) + +#define AW_PID_2049_WSINV_NOT_SWITCH (0) +#define AW_PID_2049_WSINV_NOT_SWITCH_VALUE \ + (AW_PID_2049_WSINV_NOT_SWITCH << AW_PID_2049_WSINV_START_BIT) + +#define AW_PID_2049_WSINV_SWITCH (1) +#define AW_PID_2049_WSINV_SWITCH_VALUE \ + (AW_PID_2049_WSINV_SWITCH << AW_PID_2049_WSINV_START_BIT) + +#define AW_PID_2049_WSINV_DEFAULT_VALUE (0) +#define AW_PID_2049_WSINV_DEFAULT \ + (AW_PID_2049_WSINV_DEFAULT_VALUE << AW_PID_2049_WSINV_START_BIT) + +/* BCKINV bit 4 (SYSCTRL 0x04) */ +#define AW_PID_2049_BCKINV_START_BIT (4) +#define AW_PID_2049_BCKINV_BITS_LEN (1) +#define AW_PID_2049_BCKINV_MASK \ + (~(((1<<AW_PID_2049_BCKINV_BITS_LEN)-1) << AW_PID_2049_BCKINV_START_BIT)) + +#define AW_PID_2049_BCKINV_NOT_INVERT (0) +#define AW_PID_2049_BCKINV_NOT_INVERT_VALUE \ + (AW_PID_2049_BCKINV_NOT_INVERT << AW_PID_2049_BCKINV_START_BIT) + +#define AW_PID_2049_BCKINV_INVERTED (1) +#define AW_PID_2049_BCKINV_INVERTED_VALUE \ + (AW_PID_2049_BCKINV_INVERTED << AW_PID_2049_BCKINV_START_BIT) + +#define AW_PID_2049_BCKINV_DEFAULT_VALUE (0) +#define AW_PID_2049_BCKINV_DEFAULT \ + (AW_PID_2049_BCKINV_DEFAULT_VALUE << AW_PID_2049_BCKINV_START_BIT) + +/* IPLL bit 3 (SYSCTRL 0x04) */ +#define AW_PID_2049_IPLL_START_BIT (3) +#define AW_PID_2049_IPLL_BITS_LEN (1) +#define AW_PID_2049_IPLL_MASK \ + (~(((1<<AW_PID_2049_IPLL_BITS_LEN)-1) << AW_PID_2049_IPLL_START_BIT)) + +#define AW_PID_2049_IPLL_BCK (0) +#define AW_PID_2049_IPLL_BCK_VALUE \ + (AW_PID_2049_IPLL_BCK << AW_PID_2049_IPLL_START_BIT) + +#define AW_PID_2049_IPLL_WCK (1) +#define AW_PID_2049_IPLL_WCK_VALUE \ + (AW_PID_2049_IPLL_WCK << AW_PID_2049_IPLL_START_BIT) + +#define AW_PID_2049_IPLL_DEFAULT_VALUE (0) +#define AW_PID_2049_IPLL_DEFAULT \ + (AW_PID_2049_IPLL_DEFAULT_VALUE << AW_PID_2049_IPLL_START_BIT) + +/* DSPBY bit 2 (SYSCTRL 0x04) */ +#define AW_PID_2049_DSPBY_START_BIT (2) +#define AW_PID_2049_DSPBY_BITS_LEN (1) +#define AW_PID_2049_DSPBY_MASK \ + (~(((1<<AW_PID_2049_DSPBY_BITS_LEN)-1) << AW_PID_2049_DSPBY_START_BIT)) + +#define AW_PID_2049_DSPBY_WORKING (0) +#define AW_PID_2049_DSPBY_WORKING_VALUE \ + (AW_PID_2049_DSPBY_WORKING << AW_PID_2049_DSPBY_START_BIT) + +#define AW_PID_2049_DSPBY_BYPASS (1) +#define AW_PID_2049_DSPBY_BYPASS_VALUE \ + (AW_PID_2049_DSPBY_BYPASS << AW_PID_2049_DSPBY_START_BIT) + +#define AW_PID_2049_DSPBY_DEFAULT_VALUE (1) +#define AW_PID_2049_DSPBY_DEFAULT \ + (AW_PID_2049_DSPBY_DEFAULT_VALUE << AW_PID_2049_DSPBY_START_BIT) + +/* AMPPD bit 1 (SYSCTRL 0x04) */ +#define AW_PID_2049_AMPPD_START_BIT (1) +#define AW_PID_2049_AMPPD_BITS_LEN (1) +#define AW_PID_2049_AMPPD_MASK \ + (~(((1<<AW_PID_2049_AMPPD_BITS_LEN)-1) << AW_PID_2049_AMPPD_START_BIT)) + +#define AW_PID_2049_AMPPD_WORKING (0) +#define AW_PID_2049_AMPPD_WORKING_VALUE \ + (AW_PID_2049_AMPPD_WORKING << AW_PID_2049_AMPPD_START_BIT) + +#define AW_PID_2049_AMPPD_POWER_DOWN (1) +#define AW_PID_2049_AMPPD_POWER_DOWN_VALUE \ + (AW_PID_2049_AMPPD_POWER_DOWN << AW_PID_2049_AMPPD_START_BIT) + +#define AW_PID_2049_AMPPD_DEFAULT_VALUE (1) +#define AW_PID_2049_AMPPD_DEFAULT \ + (AW_PID_2049_AMPPD_DEFAULT_VALUE << AW_PID_2049_AMPPD_START_BIT) + +/* PWDN bit 0 (SYSCTRL 0x04) */ +#define AW_PID_2049_PWDN_START_BIT (0) +#define AW_PID_2049_PWDN_BITS_LEN (1) +#define AW_PID_2049_PWDN_MASK \ + (~(((1<<AW_PID_2049_PWDN_BITS_LEN)-1) << AW_PID_2049_PWDN_START_BIT)) + +#define AW_PID_2049_PWDN_WORKING (0) +#define AW_PID_2049_PWDN_WORKING_VALUE \ + (AW_PID_2049_PWDN_WORKING << AW_PID_2049_PWDN_START_BIT) + +#define AW_PID_2049_PWDN_POWER_DOWN (1) +#define AW_PID_2049_PWDN_POWER_DOWN_VALUE \ + (AW_PID_2049_PWDN_POWER_DOWN << AW_PID_2049_PWDN_START_BIT) + +#define AW_PID_2049_PWDN_DEFAULT_VALUE (1) +#define AW_PID_2049_PWDN_DEFAULT \ + (AW_PID_2049_PWDN_DEFAULT_VALUE << AW_PID_2049_PWDN_START_BIT) + +/* default value of SYSCTRL (0x04) */ +/* #define AW_PID_2049_SYSCTRL_DEFAULT (0x5307) */ + +/* SYSCTRL2 (0x05) detail */ +/* VOL bit 15:6 (SYSCTRL2 0x05) */ +#define AW_PID_2049_MUTE_VOL (90 * 8) +#define AW_PID_2049_VOLUME_STEP_DB (6 * 8) + +#define AW_PID_2049_VOL_6DB_START (6) +#define AW_PID_2049_VOL_START_BIT (6) +#define AW_PID_2049_VOL_BITS_LEN (10) +#define AW_PID_2049_VOL_MASK \ + (~(((1<<AW_PID_2049_VOL_BITS_LEN)-1) << AW_PID_2049_VOL_START_BIT)) + +#define AW_PID_2049_VOL_DEFAULT_VALUE (0) +#define AW_PID_2049_VOL_DEFAULT \ + (AW_PID_2049_VOL_DEFAULT_VALUE << AW_PID_2049_VOL_START_BIT) + +/* INTMODE bit 5 (SYSCTRL2 0x05) */ +#define AW_PID_2049_INTMODE_START_BIT (5) +#define AW_PID_2049_INTMODE_BITS_LEN (1) +#define AW_PID_2049_INTMODE_MASK \ + (~(((1<<AW_PID_2049_INTMODE_BITS_LEN)-1) << AW_PID_2049_INTMODE_START_BIT)) + +#define AW_PID_2049_INTMODE_OPENMINUS_DRAIN (0) +#define AW_PID_2049_INTMODE_OPENMINUS_DRAIN_VALUE \ + (AW_PID_2049_INTMODE_OPENMINUS_DRAIN << AW_PID_2049_INTMODE_START_BIT) + +#define AW_PID_2049_INTMODE_PUSHPULL (1) +#define AW_PID_2049_INTMODE_PUSHPULL_VALUE \ + (AW_PID_2049_INTMODE_PUSHPULL << AW_PID_2049_INTMODE_START_BIT) + +#define AW_PID_2049_INTMODE_DEFAULT_VALUE (0) +#define AW_PID_2049_INTMODE_DEFAULT \ + (AW_PID_2049_INTMODE_DEFAULT_VALUE << AW_PID_2049_INTMODE_START_BIT) + +/* INTN bit 4 (SYSCTRL2 0x05) */ +#define AW_PID_2049_INTN_START_BIT (4) +#define AW_PID_2049_INTN_BITS_LEN (1) +#define AW_PID_2049_INTN_MASK \ + (~(((1<<AW_PID_2049_INTN_BITS_LEN)-1) << AW_PID_2049_INTN_START_BIT)) + +#define AW_PID_2049_INTN_SYSINT (0) +#define AW_PID_2049_INTN_SYSINT_VALUE \ + (AW_PID_2049_INTN_SYSINT << AW_PID_2049_INTN_START_BIT) + +#define AW_PID_2049_INTN_SYSST (1) +#define AW_PID_2049_INTN_SYSST_VALUE \ + (AW_PID_2049_INTN_SYSST << AW_PID_2049_INTN_START_BIT) + +#define AW_PID_2049_INTN_DEFAULT_VALUE (0) +#define AW_PID_2049_INTN_DEFAULT \ + (AW_PID_2049_INTN_DEFAULT_VALUE << AW_PID_2049_INTN_START_BIT) + +/* BST_IPEAK bit 3:0 (SYSCTRL2 0x05) */ +#define AW_PID_2049_BST_IPEAK_START_BIT (0) +#define AW_PID_2049_BST_IPEAK_BITS_LEN (4) +#define AW_PID_2049_BST_IPEAK_MASK \ + (~(((1<<AW_PID_2049_BST_IPEAK_BITS_LEN)-1) << AW_PID_2049_BST_IPEAK_START_BIT)) + +#define AW_PID_2049_BST_IPEAK_1P50A (0) +#define AW_PID_2049_BST_IPEAK_1P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_1P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_1P75A (1) +#define AW_PID_2049_BST_IPEAK_1P75A_VALUE \ + (AW_PID_2049_BST_IPEAK_1P75A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P00A (2) +#define AW_PID_2049_BST_IPEAK_2P00A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P00A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P25A (3) +#define AW_PID_2049_BST_IPEAK_2P25A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P25A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P50A (4) +#define AW_PID_2049_BST_IPEAK_2P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P75A (5) +#define AW_PID_2049_BST_IPEAK_2P75A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P75A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P00A (6) +#define AW_PID_2049_BST_IPEAK_3P00A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P00A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P25A (7) +#define AW_PID_2049_BST_IPEAK_3P25A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P25A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P50A (8) +#define AW_PID_2049_BST_IPEAK_3P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P75A (9) +#define AW_PID_2049_BST_IPEAK_3P75A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P75A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_4P00A (10) +#define AW_PID_2049_BST_IPEAK_4P00A_VALUE \ + (AW_PID_2049_BST_IPEAK_4P00A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_4P25A (11) +#define AW_PID_2049_BST_IPEAK_4P25A_VALUE \ + (AW_PID_2049_BST_IPEAK_4P25A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_4P50A (12) +#define AW_PID_2049_BST_IPEAK_4P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_4P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_DEFAULT_VALUE (9) +#define AW_PID_2049_BST_IPEAK_DEFAULT \ + (AW_PID_2049_BST_IPEAK_DEFAULT_VALUE << AW_PID_2049_BST_IPEAK_START_BIT) + +/* default value of SYSCTRL2 (0x05) */ +/* #define AW_PID_2049_SYSCTRL2_DEFAULT (0x0009) */ + +/* I2SCTRL (0x06) detail */ +/* SLOT_NUM bit 14:12 (I2SCTRL 0x06) */ +#define AW_PID_2049_SLOT_NUM_START_BIT (12) +#define AW_PID_2049_SLOT_NUM_BITS_LEN (3) +#define AW_PID_2049_SLOT_NUM_MASK \ + (~(((1<<AW_PID_2049_SLOT_NUM_BITS_LEN)-1) << AW_PID_2049_SLOT_NUM_START_BIT)) + +#define AW_PID_2049_SLOT_NUM_I2S_MODE (0) +#define AW_PID_2049_SLOT_NUM_I2S_MODE_VALUE \ + (AW_PID_2049_SLOT_NUM_I2S_MODE << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM1S (1) +#define AW_PID_2049_SLOT_NUM_TDM1S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM1S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM2S (2) +#define AW_PID_2049_SLOT_NUM_TDM2S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM2S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM4S (3) +#define AW_PID_2049_SLOT_NUM_TDM4S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM4S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM6S (4) +#define AW_PID_2049_SLOT_NUM_TDM6S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM6S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM8S (5) +#define AW_PID_2049_SLOT_NUM_TDM8S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM8S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM16S (6) +#define AW_PID_2049_SLOT_NUM_TDM16S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM16S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_RESERVED (7) +#define AW_PID_2049_SLOT_NUM_RESERVED_VALUE \ + (AW_PID_2049_SLOT_NUM_RESERVED << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_DEFAULT_VALUE (0) +#define AW_PID_2049_SLOT_NUM_DEFAULT \ + (AW_PID_2049_SLOT_NUM_DEFAULT_VALUE << AW_PID_2049_SLOT_NUM_START_BIT) + +/* CHSEL bit 11:10 (I2SCTRL 0x06) */ +#define AW_PID_2049_CHSEL_START_BIT (10) +#define AW_PID_2049_CHSEL_BITS_LEN (2) +#define AW_PID_2049_CHSEL_MASK \ + (~(((1<<AW_PID_2049_CHSEL_BITS_LEN)-1) << AW_PID_2049_CHSEL_START_BIT)) + +#define AW_PID_2049_CHSEL_RESERVED (0) +#define AW_PID_2049_CHSEL_RESERVED_VALUE \ + (AW_PID_2049_CHSEL_RESERVED << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_LEFT (1) +#define AW_PID_2049_CHSEL_LEFT_VALUE \ + (AW_PID_2049_CHSEL_LEFT << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_RIGHT (2) +#define AW_PID_2049_CHSEL_RIGHT_VALUE \ + (AW_PID_2049_CHSEL_RIGHT << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_MONO (3) +#define AW_PID_2049_CHSEL_MONO_VALUE \ + (AW_PID_2049_CHSEL_MONO << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_DEFAULT_VALUE (1) +#define AW_PID_2049_CHSEL_DEFAULT \ + (AW_PID_2049_CHSEL_DEFAULT_VALUE << AW_PID_2049_CHSEL_START_BIT) + +/* I2SMD bit 9:8 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SMD_START_BIT (8) +#define AW_PID_2049_I2SMD_BITS_LEN (2) +#define AW_PID_2049_I2SMD_MASK \ + (~(((1<<AW_PID_2049_I2SMD_BITS_LEN)-1) << AW_PID_2049_I2SMD_START_BIT)) + +#define AW_PID_2049_I2SMD_PHILIP_STANDARD (0) +#define AW_PID_2049_I2SMD_PHILIP_STANDARD_VALUE \ + (AW_PID_2049_I2SMD_PHILIP_STANDARD << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_MSB_JUSTIFIED (1) +#define AW_PID_2049_I2SMD_MSB_JUSTIFIED_VALUE \ + (AW_PID_2049_I2SMD_MSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_LSB_JUSTIFIED (2) +#define AW_PID_2049_I2SMD_LSB_JUSTIFIED_VALUE \ + (AW_PID_2049_I2SMD_LSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_RESERVED (3) +#define AW_PID_2049_I2SMD_RESERVED_VALUE \ + (AW_PID_2049_I2SMD_RESERVED << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SMD_DEFAULT \ + (AW_PID_2049_I2SMD_DEFAULT_VALUE << AW_PID_2049_I2SMD_START_BIT) + +/* I2SFS bit 7:6 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SFS_START_BIT (6) +#define AW_PID_2049_I2SFS_BITS_LEN (2) +#define AW_PID_2049_I2SFS_MASK \ + (~(((1<<AW_PID_2049_I2SFS_BITS_LEN)-1) << AW_PID_2049_I2SFS_START_BIT)) + +#define AW_PID_2049_I2SFS_16_BITS (0) +#define AW_PID_2049_I2SFS_16_BITS_VALUE \ + (AW_PID_2049_I2SFS_16_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_20_BITS (1) +#define AW_PID_2049_I2SFS_20_BITS_VALUE \ + (AW_PID_2049_I2SFS_20_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_24_BITS (2) +#define AW_PID_2049_I2SFS_24_BITS_VALUE \ + (AW_PID_2049_I2SFS_24_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_32_BITS (3) +#define AW_PID_2049_I2SFS_32_BITS_VALUE \ + (AW_PID_2049_I2SFS_32_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_DEFAULT_VALUE (3) +#define AW_PID_2049_I2SFS_DEFAULT \ + (AW_PID_2049_I2SFS_DEFAULT_VALUE << AW_PID_2049_I2SFS_START_BIT) + +/* I2SBCK bit 5:4 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SBCK_START_BIT (4) +#define AW_PID_2049_I2SBCK_BITS_LEN (2) +#define AW_PID_2049_I2SBCK_MASK \ + (~(((1<<AW_PID_2049_I2SBCK_BITS_LEN)-1) << AW_PID_2049_I2SBCK_START_BIT)) + +#define AW_PID_2049_I2SBCK_32FS (0) +#define AW_PID_2049_I2SBCK_32FS_VALUE \ + (AW_PID_2049_I2SBCK_32FS << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_48FS (1) +#define AW_PID_2049_I2SBCK_48FS_VALUE \ + (AW_PID_2049_I2SBCK_48FS << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_64FS (2) +#define AW_PID_2049_I2SBCK_64FS_VALUE \ + (AW_PID_2049_I2SBCK_64FS << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_RESERVED (3) +#define AW_PID_2049_I2SBCK_RESERVED_VALUE \ + (AW_PID_2049_I2SBCK_RESERVED << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_DEFAULT_VALUE (2) +#define AW_PID_2049_I2SBCK_DEFAULT \ + (AW_PID_2049_I2SBCK_DEFAULT_VALUE << AW_PID_2049_I2SBCK_START_BIT) + +/* I2SSR bit 3:0 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SSR_START_BIT (0) +#define AW_PID_2049_I2SSR_BITS_LEN (4) +#define AW_PID_2049_I2SSR_MASK \ + (~(((1<<AW_PID_2049_I2SSR_BITS_LEN)-1) << AW_PID_2049_I2SSR_START_BIT)) + +#define AW_PID_2049_I2SSR_8_KHZ (0) +#define AW_PID_2049_I2SSR_8_KHZ_VALUE \ + (AW_PID_2049_I2SSR_8_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_11_KHZ (1) +#define AW_PID_2049_I2SSR_11_KHZ_VALUE \ + (AW_PID_2049_I2SSR_11_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_12_KHZ (2) +#define AW_PID_2049_I2SSR_12_KHZ_VALUE \ + (AW_PID_2049_I2SSR_12_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_16_KHZ (3) +#define AW_PID_2049_I2SSR_16_KHZ_VALUE \ + (AW_PID_2049_I2SSR_16_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_22_KHZ (4) +#define AW_PID_2049_I2SSR_22_KHZ_VALUE \ + (AW_PID_2049_I2SSR_22_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_24_KHZ (5) +#define AW_PID_2049_I2SSR_24_KHZ_VALUE \ + (AW_PID_2049_I2SSR_24_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_32_KHZ (6) +#define AW_PID_2049_I2SSR_32_KHZ_VALUE \ + (AW_PID_2049_I2SSR_32_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_44_KHZ (7) +#define AW_PID_2049_I2SSR_44_KHZ_VALUE \ + (AW_PID_2049_I2SSR_44_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_48_KHZ (8) +#define AW_PID_2049_I2SSR_48_KHZ_VALUE \ + (AW_PID_2049_I2SSR_48_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_96_KHZ (9) +#define AW_PID_2049_I2SSR_96_KHZ_VALUE \ + (AW_PID_2049_I2SSR_96_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_192KHZ (10) +#define AW_PID_2049_I2SSR_192KHZ_VALUE \ + (AW_PID_2049_I2SSR_192KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_DEFAULT_VALUE (8) +#define AW_PID_2049_I2SSR_DEFAULT \ + (AW_PID_2049_I2SSR_DEFAULT_VALUE << AW_PID_2049_I2SSR_START_BIT) + +/* default value of I2SCTRL (0x06) */ +/* #define AW_PID_2049_I2SCTRL_DEFAULT (0x04E8) */ + +/* I2SCFG1 (0x07) detail */ +/* I2S_RXL_SLOTVLD bit 15:12 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT (12) +#define AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN (4) +#define AW_PID_2049_I2S_RXL_SLOTVLD_MASK \ + (~(((1<<AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0 (0) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1 (1) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2 (2) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3 (3) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15 (15) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE (0) +#define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT \ + (AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +/* I2S_RXR_SLOTVLD bit 11:8 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT (8) +#define AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN (4) +#define AW_PID_2049_I2S_RXR_SLOTVLD_MASK \ + (~(((1<<AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0 (0) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1 (1) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2 (2) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3 (3) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15 (15) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE (1) +#define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT \ + (AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +/* I2S_TX_SLOTVLD bit 7:4 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2S_TX_SLOTVLD_START_BIT (4) +#define AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN (4) +#define AW_PID_2049_I2S_TX_SLOTVLD_MASK \ + (~(((1<<AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0 (0) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1 (1) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2 (2) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3 (3) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15 (15) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE (0) +#define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT \ + (AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +/* FSYNC_TYPE bit 3 (I2SCFG1 0x07) */ +#define AW_PID_2049_FSYNC_TYPE_START_BIT (3) +#define AW_PID_2049_FSYNC_TYPE_BITS_LEN (1) +#define AW_PID_2049_FSYNC_TYPE_MASK \ + (~(((1<<AW_PID_2049_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_2049_FSYNC_TYPE_START_BIT)) + +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT (0) +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT_VALUE \ + (AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT << AW_PID_2049_FSYNC_TYPE_START_BIT) + +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK (1) +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK_VALUE \ + (AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK << AW_PID_2049_FSYNC_TYPE_START_BIT) + +#define AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE (0) +#define AW_PID_2049_FSYNC_TYPE_DEFAULT \ + (AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE << AW_PID_2049_FSYNC_TYPE_START_BIT) + +/* I2SCHS bit 2 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2SCHS_START_BIT (2) +#define AW_PID_2049_I2SCHS_BITS_LEN (1) +#define AW_PID_2049_I2SCHS_MASK \ + (~(((1<<AW_PID_2049_I2SCHS_BITS_LEN)-1) << AW_PID_2049_I2SCHS_START_BIT)) + +#define AW_PID_2049_I2SCHS_LEFT (0) +#define AW_PID_2049_I2SCHS_LEFT_VALUE \ + (AW_PID_2049_I2SCHS_LEFT << AW_PID_2049_I2SCHS_START_BIT) + +#define AW_PID_2049_I2SCHS_RIGHT (1) +#define AW_PID_2049_I2SCHS_RIGHT_VALUE \ + (AW_PID_2049_I2SCHS_RIGHT << AW_PID_2049_I2SCHS_START_BIT) + +#define AW_PID_2049_I2SCHS_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SCHS_DEFAULT \ + (AW_PID_2049_I2SCHS_DEFAULT_VALUE << AW_PID_2049_I2SCHS_START_BIT) + +/* I2SRXEN bit 1 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2SRXEN_START_BIT (1) +#define AW_PID_2049_I2SRXEN_BITS_LEN (1) +#define AW_PID_2049_I2SRXEN_MASK \ + (~(((1<<AW_PID_2049_I2SRXEN_BITS_LEN)-1) << AW_PID_2049_I2SRXEN_START_BIT)) + +#define AW_PID_2049_I2SRXEN_DISABLE (0) +#define AW_PID_2049_I2SRXEN_DISABLE_VALUE \ + (AW_PID_2049_I2SRXEN_DISABLE << AW_PID_2049_I2SRXEN_START_BIT) + +#define AW_PID_2049_I2SRXEN_ENABLE (1) +#define AW_PID_2049_I2SRXEN_ENABLE_VALUE \ + (AW_PID_2049_I2SRXEN_ENABLE << AW_PID_2049_I2SRXEN_START_BIT) + +#define AW_PID_2049_I2SRXEN_DEFAULT_VALUE (1) +#define AW_PID_2049_I2SRXEN_DEFAULT \ + (AW_PID_2049_I2SRXEN_DEFAULT_VALUE << AW_PID_2049_I2SRXEN_START_BIT) + +/* I2STXEN bit 0 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2STXEN_START_BIT (0) +#define AW_PID_2049_I2STXEN_BITS_LEN (1) +#define AW_PID_2049_I2STXEN_MASK \ + (~(((1<<AW_PID_2049_I2STXEN_BITS_LEN)-1) << AW_PID_2049_I2STXEN_START_BIT)) + +#define AW_PID_2049_I2STXEN_DISABLE (0) +#define AW_PID_2049_I2STXEN_DISABLE_VALUE \ + (AW_PID_2049_I2STXEN_DISABLE << AW_PID_2049_I2STXEN_START_BIT) + +#define AW_PID_2049_I2STXEN_ENABLE (1) +#define AW_PID_2049_I2STXEN_ENABLE_VALUE \ + (AW_PID_2049_I2STXEN_ENABLE << AW_PID_2049_I2STXEN_START_BIT) + +#define AW_PID_2049_I2STXEN_DEFAULT_VALUE (0) +#define AW_PID_2049_I2STXEN_DEFAULT \ + (AW_PID_2049_I2STXEN_DEFAULT_VALUE << AW_PID_2049_I2STXEN_START_BIT) + +/* default value of I2SCFG1 (0x07) */ +/* #define AW_PID_2049_I2SCFG1_DEFAULT (0x0102) */ + +/* I2SCFG2 (0x08) detail */ +/* ULS_FIR_MD bit 14 (I2SCFG2 0x08) */ +#define AW_PID_2049_ULS_FIR_MD_START_BIT (14) +#define AW_PID_2049_ULS_FIR_MD_BITS_LEN (1) +#define AW_PID_2049_ULS_FIR_MD_MASK \ + (~(((1<<AW_PID_2049_ULS_FIR_MD_BITS_LEN)-1) << AW_PID_2049_ULS_FIR_MD_START_BIT)) + +#define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED (0) +#define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED_VALUE \ + (AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED << AW_PID_2049_ULS_FIR_MD_START_BIT) + +#define AW_PID_2049_ULS_FIR_MD_USED (1) +#define AW_PID_2049_ULS_FIR_MD_USED_VALUE \ + (AW_PID_2049_ULS_FIR_MD_USED << AW_PID_2049_ULS_FIR_MD_START_BIT) + +#define AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE (0) +#define AW_PID_2049_ULS_FIR_MD_DEFAULT \ + (AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE << AW_PID_2049_ULS_FIR_MD_START_BIT) + +/* ULS_MODE bit 13 (I2SCFG2 0x08) */ +#define AW_PID_2049_ULS_MODE_START_BIT (13) +#define AW_PID_2049_ULS_MODE_BITS_LEN (1) +#define AW_PID_2049_ULS_MODE_MASK \ + (~(((1<<AW_PID_2049_ULS_MODE_BITS_LEN)-1) << AW_PID_2049_ULS_MODE_START_BIT)) + +#define AW_PID_2049_ULS_MODE_LOWPASS (0) +#define AW_PID_2049_ULS_MODE_LOWPASS_VALUE \ + (AW_PID_2049_ULS_MODE_LOWPASS << AW_PID_2049_ULS_MODE_START_BIT) + +#define AW_PID_2049_ULS_MODE_TDM (1) +#define AW_PID_2049_ULS_MODE_TDM_VALUE \ + (AW_PID_2049_ULS_MODE_TDM << AW_PID_2049_ULS_MODE_START_BIT) + +#define AW_PID_2049_ULS_MODE_DEFAULT_VALUE (0) +#define AW_PID_2049_ULS_MODE_DEFAULT \ + (AW_PID_2049_ULS_MODE_DEFAULT_VALUE << AW_PID_2049_ULS_MODE_START_BIT) + +/* ULS_EN bit 12 (I2SCFG2 0x08) */ +#define AW_PID_2049_ULS_EN_START_BIT (12) +#define AW_PID_2049_ULS_EN_BITS_LEN (1) +#define AW_PID_2049_ULS_EN_MASK \ + (~(((1<<AW_PID_2049_ULS_EN_BITS_LEN)-1) << AW_PID_2049_ULS_EN_START_BIT)) + +#define AW_PID_2049_ULS_EN_DISABLE (0) +#define AW_PID_2049_ULS_EN_DISABLE_VALUE \ + (AW_PID_2049_ULS_EN_DISABLE << AW_PID_2049_ULS_EN_START_BIT) + +#define AW_PID_2049_ULS_EN_ENABLE (1) +#define AW_PID_2049_ULS_EN_ENABLE_VALUE \ + (AW_PID_2049_ULS_EN_ENABLE << AW_PID_2049_ULS_EN_START_BIT) + +#define AW_PID_2049_ULS_EN_DEFAULT_VALUE (0) +#define AW_PID_2049_ULS_EN_DEFAULT \ + (AW_PID_2049_ULS_EN_DEFAULT_VALUE << AW_PID_2049_ULS_EN_START_BIT) + +/* IV2CH bit 9 (I2SCFG2 0x08) */ +#define AW_PID_2049_IV2CH_START_BIT (9) +#define AW_PID_2049_IV2CH_BITS_LEN (1) +#define AW_PID_2049_IV2CH_MASK \ + (~(((1<<AW_PID_2049_IV2CH_BITS_LEN)-1) << AW_PID_2049_IV2CH_START_BIT)) + +#define AW_PID_2049_IV2CH_LEGACY (0) +#define AW_PID_2049_IV2CH_LEGACY_VALUE \ + (AW_PID_2049_IV2CH_LEGACY << AW_PID_2049_IV2CH_START_BIT) + +#define AW_PID_2049_IV2CH_SPECIAL (1) +#define AW_PID_2049_IV2CH_SPECIAL_VALUE \ + (AW_PID_2049_IV2CH_SPECIAL << AW_PID_2049_IV2CH_START_BIT) + +#define AW_PID_2049_IV2CH_DEFAULT_VALUE (0) +#define AW_PID_2049_IV2CH_DEFAULT \ + (AW_PID_2049_IV2CH_DEFAULT_VALUE << AW_PID_2049_IV2CH_START_BIT) + +/* I2S_TXEDGE bit 8 (I2SCFG2 0x08) */ +#define AW_PID_2049_I2S_TXEDGE_START_BIT (8) +#define AW_PID_2049_I2S_TXEDGE_BITS_LEN (1) +#define AW_PID_2049_I2S_TXEDGE_MASK \ + (~(((1<<AW_PID_2049_I2S_TXEDGE_BITS_LEN)-1) << AW_PID_2049_I2S_TXEDGE_START_BIT)) + +#define AW_PID_2049_I2S_TXEDGE_NEGEDGE (0) +#define AW_PID_2049_I2S_TXEDGE_NEGEDGE_VALUE \ + (AW_PID_2049_I2S_TXEDGE_NEGEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT) + +#define AW_PID_2049_I2S_TXEDGE_POSEDGE (1) +#define AW_PID_2049_I2S_TXEDGE_POSEDGE_VALUE \ + (AW_PID_2049_I2S_TXEDGE_POSEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT) + +#define AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE (0) +#define AW_PID_2049_I2S_TXEDGE_DEFAULT \ + (AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE << AW_PID_2049_I2S_TXEDGE_START_BIT) + +/* I2SDOSEL bit 7 (I2SCFG2 0x08) */ +#define AW_PID_2049_I2SDOSEL_START_BIT (7) +#define AW_PID_2049_I2SDOSEL_BITS_LEN (1) +#define AW_PID_2049_I2SDOSEL_MASK \ + (~(((1<<AW_PID_2049_I2SDOSEL_BITS_LEN)-1) << AW_PID_2049_I2SDOSEL_START_BIT)) + +#define AW_PID_2049_I2SDOSEL_ZEROS (0) +#define AW_PID_2049_I2SDOSEL_ZEROS_VALUE \ + (AW_PID_2049_I2SDOSEL_ZEROS << AW_PID_2049_I2SDOSEL_START_BIT) + +#define AW_PID_2049_I2SDOSEL_TXDATA (1) +#define AW_PID_2049_I2SDOSEL_TXDATA_VALUE \ + (AW_PID_2049_I2SDOSEL_TXDATA << AW_PID_2049_I2SDOSEL_START_BIT) + +#define AW_PID_2049_I2SDOSEL_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SDOSEL_DEFAULT \ + (AW_PID_2049_I2SDOSEL_DEFAULT_VALUE << AW_PID_2049_I2SDOSEL_START_BIT) + +/* DOHZ bit 6 (I2SCFG2 0x08) */ +#define AW_PID_2049_DOHZ_START_BIT (6) +#define AW_PID_2049_DOHZ_BITS_LEN (1) +#define AW_PID_2049_DOHZ_MASK \ + (~(((1<<AW_PID_2049_DOHZ_BITS_LEN)-1) << AW_PID_2049_DOHZ_START_BIT)) + +#define AW_PID_2049_DOHZ_ALL (0) +#define AW_PID_2049_DOHZ_ALL_VALUE \ + (AW_PID_2049_DOHZ_ALL << AW_PID_2049_DOHZ_START_BIT) + +#define AW_PID_2049_DOHZ_HIZ (1) +#define AW_PID_2049_DOHZ_HIZ_VALUE \ + (AW_PID_2049_DOHZ_HIZ << AW_PID_2049_DOHZ_START_BIT) + +#define AW_PID_2049_DOHZ_DEFAULT_VALUE (1) +#define AW_PID_2049_DOHZ_DEFAULT \ + (AW_PID_2049_DOHZ_DEFAULT_VALUE << AW_PID_2049_DOHZ_START_BIT) + +/* DRVSTREN bit 5 (I2SCFG2 0x08) */ +#define AW_PID_2049_DRVSTREN_START_BIT (5) +#define AW_PID_2049_DRVSTREN_BITS_LEN (1) +#define AW_PID_2049_DRVSTREN_MASK \ + (~(((1<<AW_PID_2049_DRVSTREN_BITS_LEN)-1) << AW_PID_2049_DRVSTREN_START_BIT)) + +#define AW_PID_2049_DRVSTREN_4MA (0) +#define AW_PID_2049_DRVSTREN_4MA_VALUE \ + (AW_PID_2049_DRVSTREN_4MA << AW_PID_2049_DRVSTREN_START_BIT) + +#define AW_PID_2049_DRVSTREN_12MA (1) +#define AW_PID_2049_DRVSTREN_12MA_VALUE \ + (AW_PID_2049_DRVSTREN_12MA << AW_PID_2049_DRVSTREN_START_BIT) + +#define AW_PID_2049_DRVSTREN_DEFAULT_VALUE (1) +#define AW_PID_2049_DRVSTREN_DEFAULT \ + (AW_PID_2049_DRVSTREN_DEFAULT_VALUE << AW_PID_2049_DRVSTREN_START_BIT) + +/* INPLEV bit 4 (I2SCFG2 0x08) */ +#define AW_PID_2049_INPLEV_START_BIT (4) +#define AW_PID_2049_INPLEV_BITS_LEN (1) +#define AW_PID_2049_INPLEV_MASK \ + (~(((1<<AW_PID_2049_INPLEV_BITS_LEN)-1) << AW_PID_2049_INPLEV_START_BIT)) + +#define AW_PID_2049_INPLEV_NOT_ATTENUATED (0) +#define AW_PID_2049_INPLEV_NOT_ATTENUATED_VALUE \ + (AW_PID_2049_INPLEV_NOT_ATTENUATED << AW_PID_2049_INPLEV_START_BIT) + +#define AW_PID_2049_INPLEV_ATTENUATED (1) +#define AW_PID_2049_INPLEV_ATTENUATED_VALUE \ + (AW_PID_2049_INPLEV_ATTENUATED << AW_PID_2049_INPLEV_START_BIT) + +#define AW_PID_2049_INPLEV_DEFAULT_VALUE (0) +#define AW_PID_2049_INPLEV_DEFAULT \ + (AW_PID_2049_INPLEV_DEFAULT_VALUE << AW_PID_2049_INPLEV_START_BIT) + +/* CFSEL bit 2:0 (I2SCFG2 0x08) */ +#define AW_PID_2049_CFSEL_START_BIT (0) +#define AW_PID_2049_CFSEL_BITS_LEN (3) +#define AW_PID_2049_CFSEL_MASK \ + (~(((1<<AW_PID_2049_CFSEL_BITS_LEN)-1) << AW_PID_2049_CFSEL_START_BIT)) + +#define AW_PID_2049_CFSEL_HAGC (0) +#define AW_PID_2049_CFSEL_HAGC_VALUE \ + (AW_PID_2049_CFSEL_HAGC << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_DFIFO (1) +#define AW_PID_2049_CFSEL_DFIFO_VALUE \ + (AW_PID_2049_CFSEL_DFIFO << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_ULS (2) +#define AW_PID_2049_CFSEL_ULS_VALUE \ + (AW_PID_2049_CFSEL_ULS << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_IVT_FS (3) +#define AW_PID_2049_CFSEL_IVT_FS_VALUE \ + (AW_PID_2049_CFSEL_IVT_FS << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_IVT_IPVT (4) +#define AW_PID_2049_CFSEL_IVT_IPVT_VALUE \ + (AW_PID_2049_CFSEL_IVT_IPVT << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_DEFAULT_VALUE (0) +#define AW_PID_2049_CFSEL_DEFAULT \ + (AW_PID_2049_CFSEL_DEFAULT_VALUE << AW_PID_2049_CFSEL_START_BIT) + +/* default value of I2SCFG2 (0x08) */ +/* #define AW_PID_2049_I2SCFG2_DEFAULT (0x0060) */ + +/* HAGCCFG1 (0x09) detail */ +/* RVTH bit 15:8 (HAGCCFG1 0x09) */ +#define AW_PID_2049_RVTH_START_BIT (8) +#define AW_PID_2049_RVTH_BITS_LEN (8) +#define AW_PID_2049_RVTH_MASK \ + (~(((1<<AW_PID_2049_RVTH_BITS_LEN)-1) << AW_PID_2049_RVTH_START_BIT)) + +#define AW_PID_2049_RVTH_DEFAULT_VALUE (0x39) +#define AW_PID_2049_RVTH_DEFAULT \ + (AW_PID_2049_RVTH_DEFAULT_VALUE << AW_PID_2049_RVTH_START_BIT) + +/* AVTH bit 7:0 (HAGCCFG1 0x09) */ +#define AW_PID_2049_AVTH_START_BIT (0) +#define AW_PID_2049_AVTH_BITS_LEN (8) +#define AW_PID_2049_AVTH_MASK \ + (~(((1<<AW_PID_2049_AVTH_BITS_LEN)-1) << AW_PID_2049_AVTH_START_BIT)) + +#define AW_PID_2049_AVTH_DEFAULT_VALUE (0x40) +#define AW_PID_2049_AVTH_DEFAULT \ + (AW_PID_2049_AVTH_DEFAULT_VALUE << AW_PID_2049_AVTH_START_BIT) + +/* default value of HAGCCFG1 (0x09) */ +/* #define AW_PID_2049_HAGCCFG1_DEFAULT (0x3940) */ + +/* HAGCCFG2 (0x0A) detail */ +/* ATTH bit 15:0 (HAGCCFG2 0x0A) */ +#define AW_PID_2049_ATTH_START_BIT (0) +#define AW_PID_2049_ATTH_BITS_LEN (16) +#define AW_PID_2049_ATTH_MASK \ + (~(((1<<AW_PID_2049_ATTH_BITS_LEN)-1) << AW_PID_2049_ATTH_START_BIT)) + +#define AW_PID_2049_ATTH_RESERVED (0) +#define AW_PID_2049_ATTH_RESERVED_VALUE \ + (AW_PID_2049_ATTH_RESERVED << AW_PID_2049_ATTH_START_BIT) + +#define AW_PID_2049_ATTH_DEFAULT_VALUE (0x0030) +#define AW_PID_2049_ATTH_DEFAULT \ + (AW_PID_2049_ATTH_DEFAULT_VALUE << AW_PID_2049_ATTH_START_BIT) + +/* default value of HAGCCFG2 (0x0A) */ +/* #define AW_PID_2049_HAGCCFG2_DEFAULT (0x0030) */ + +/* HAGCCFG3 (0x0B) detail */ +/* RTTH bit 15:0 (HAGCCFG3 0x0B) */ +#define AW_PID_2049_RTTH_START_BIT (0) +#define AW_PID_2049_RTTH_BITS_LEN (16) +#define AW_PID_2049_RTTH_MASK \ + (~(((1<<AW_PID_2049_RTTH_BITS_LEN)-1) << AW_PID_2049_RTTH_START_BIT)) + +#define AW_PID_2049_RTTH_RESERVED (0) +#define AW_PID_2049_RTTH_RESERVED_VALUE \ + (AW_PID_2049_RTTH_RESERVED << AW_PID_2049_RTTH_START_BIT) + +#define AW_PID_2049_RTTH_DEFAULT_VALUE (0x01E0) +#define AW_PID_2049_RTTH_DEFAULT \ + (AW_PID_2049_RTTH_DEFAULT_VALUE << AW_PID_2049_RTTH_START_BIT) + +/* default value of HAGCCFG3 (0x0B) */ +/* #define AW_PID_2049_HAGCCFG3_DEFAULT (0x01E0) */ + +/* HAGCCFG4 (0x0C) detail */ +/* IIC_GEN_ADDR bit 15:9 (HAGCCFG4 0x0C) */ +#define AW_PID_2049_IIC_GEN_ADDR_START_BIT (9) +#define AW_PID_2049_IIC_GEN_ADDR_BITS_LEN (7) +#define AW_PID_2049_IIC_GEN_ADDR_MASK \ + (~(((1<<AW_PID_2049_IIC_GEN_ADDR_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_ADDR_START_BIT)) + +#define AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE (0x0E) +#define AW_PID_2049_IIC_GEN_ADDR_DEFAULT \ + (AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_ADDR_START_BIT) + +/* IIC_GEN_EN bit 8 (HAGCCFG4 0x0C) */ +#define AW_PID_2049_IIC_GEN_EN_START_BIT (8) +#define AW_PID_2049_IIC_GEN_EN_BITS_LEN (1) +#define AW_PID_2049_IIC_GEN_EN_MASK \ + (~(((1<<AW_PID_2049_IIC_GEN_EN_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_EN_START_BIT)) + +#define AW_PID_2049_IIC_GEN_EN_DISABLE (0) +#define AW_PID_2049_IIC_GEN_EN_DISABLE_VALUE \ + (AW_PID_2049_IIC_GEN_EN_DISABLE << AW_PID_2049_IIC_GEN_EN_START_BIT) + +#define AW_PID_2049_IIC_GEN_EN_ENABLE (1) +#define AW_PID_2049_IIC_GEN_EN_ENABLE_VALUE \ + (AW_PID_2049_IIC_GEN_EN_ENABLE << AW_PID_2049_IIC_GEN_EN_START_BIT) + +#define AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE (0) +#define AW_PID_2049_IIC_GEN_EN_DEFAULT \ + (AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_EN_START_BIT) + +/* HOLDTH bit 7:0 (HAGCCFG4 0x0C) */ +#define AW_PID_2049_HOLDTH_START_BIT (0) +#define AW_PID_2049_HOLDTH_BITS_LEN (8) +#define AW_PID_2049_HOLDTH_MASK \ + (~(((1<<AW_PID_2049_HOLDTH_BITS_LEN)-1) << AW_PID_2049_HOLDTH_START_BIT)) + +#define AW_PID_2049_HOLDTH_RESERVED (0) +#define AW_PID_2049_HOLDTH_RESERVED_VALUE \ + (AW_PID_2049_HOLDTH_RESERVED << AW_PID_2049_HOLDTH_START_BIT) + +#define AW_PID_2049_HOLDTH_DEFAULT_VALUE (0x64) +#define AW_PID_2049_HOLDTH_DEFAULT \ + (AW_PID_2049_HOLDTH_DEFAULT_VALUE << AW_PID_2049_HOLDTH_START_BIT) + +/* default value of HAGCCFG4 (0x0C) */ +/* #define AW_PID_2049_HAGCCFG4_DEFAULT (0x1C64) */ + +/* AGC_DSP_CTL bit 15 (HAGCCFG7 0x0F) */ +#define AW_PID_2049_AGC_DSP_CTL_START_BIT (15) +#define AW_PID_2049_AGC_DSP_CTL_BITS_LEN (1) +#define AW_PID_2049_AGC_DSP_CTL_MASK \ + (~(((1<<AW_PID_2049_AGC_DSP_CTL_BITS_LEN)-1) << AW_PID_2049_AGC_DSP_CTL_START_BIT)) + +#define AW_PID_2049_AGC_DSP_CTL_DISABLE (0) +#define AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE \ + (AW_PID_2049_AGC_DSP_CTL_DISABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT) + +#define AW_PID_2049_AGC_DSP_CTL_ENABLE (1) +#define AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE \ + (AW_PID_2049_AGC_DSP_CTL_ENABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT) +/* VDSEL bit 0 (I2SCFG3 0x12) */ +#define AW_PID_2049_VDSEL_START_BIT (0) +#define AW_PID_2049_VDSEL_BITS_LEN (1) +#define AW_PID_2049_VDSEL_MASK \ + (~(((1<<AW_PID_2049_VDSEL_BITS_LEN)-1) << AW_PID_2049_VDSEL_START_BIT)) + +/* MEM_CLKSEL bit 3 (DBGCTRL 0x13) */ +#define AW_PID_2049_MEM_CLKSEL_START_BIT (3) +#define AW_PID_2049_MEM_CLKSEL_BITS_LEN (1) +#define AW_PID_2049_MEM_CLKSEL_MASK \ + (~(((1<<AW_PID_2049_MEM_CLKSEL_BITS_LEN)-1) << AW_PID_2049_MEM_CLKSEL_START_BIT)) + +#define AW_PID_2049_MEM_CLKSEL_OSC_CLK (0) +#define AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE \ + (AW_PID_2049_MEM_CLKSEL_OSC_CLK << AW_PID_2049_MEM_CLKSEL_START_BIT) + +#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK (1) +#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE \ + (AW_PID_2049_MEM_CLKSEL_DAP_HCLK << AW_PID_2049_MEM_CLKSEL_START_BIT) + +/* HAGCST (0x20) detail */ +/* SPK_GAIN_ST bit 10:8 (HAGCST 0x20) */ +#define AW_PID_2049_SPK_GAIN_ST_START_BIT (8) +#define AW_PID_2049_SPK_GAIN_ST_BITS_LEN (3) +#define AW_PID_2049_SPK_GAIN_ST_MASK \ + (~(((1<<AW_PID_2049_SPK_GAIN_ST_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_ST_START_BIT)) + +#define AW_PID_2049_SPK_GAIN_ST_4_AV (0) +#define AW_PID_2049_SPK_GAIN_ST_4_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_4_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_4P67_AV (1) +#define AW_PID_2049_SPK_GAIN_ST_4P67_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_4P67_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_6_AV (2) +#define AW_PID_2049_SPK_GAIN_ST_6_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_6_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_7_AV (3) +#define AW_PID_2049_SPK_GAIN_ST_7_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_7_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_12_AV (4) +#define AW_PID_2049_SPK_GAIN_ST_12_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_12_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_14_AV (5) +#define AW_PID_2049_SPK_GAIN_ST_14_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_14_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE (5) +#define AW_PID_2049_SPK_GAIN_ST_DEFAULT \ + (AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +/* BSTVOUT_ST bit 5:0 (HAGCST 0x20) */ +#define AW_PID_2049_BSTVOUT_ST_START_BIT (0) +#define AW_PID_2049_BSTVOUT_ST_BITS_LEN (6) +#define AW_PID_2049_BSTVOUT_ST_MASK \ + (~(((1<<AW_PID_2049_BSTVOUT_ST_BITS_LEN)-1) << AW_PID_2049_BSTVOUT_ST_START_BIT)) + +#define AW_PID_2049_BSTVOUT_ST_3P125V (0) +#define AW_PID_2049_BSTVOUT_ST_3P125V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P125V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P250V (1) +#define AW_PID_2049_BSTVOUT_ST_3P250V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P250V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P375V (2) +#define AW_PID_2049_BSTVOUT_ST_3P375V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P375V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P500V (3) +#define AW_PID_2049_BSTVOUT_ST_3P500V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P500V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P625V (4) +#define AW_PID_2049_BSTVOUT_ST_3P625V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P625V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P750V (5) +#define AW_PID_2049_BSTVOUT_ST_3P750V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P750V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_11P000V (63) +#define AW_PID_2049_BSTVOUT_ST_11P000V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_11P000V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTVOUT_ST_DEFAULT \ + (AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE << AW_PID_2049_BSTVOUT_ST_START_BIT) + +/* default value of HAGCST (0x20) */ +/* #define AW_PID_2049_HAGCST_DEFAULT (0x0500) */ + +/* VBAT (0x21) detail */ +/* VBAT_DET bit 9:0 (VBAT 0x21) */ +#define AW_PID_2049_VBAT_DET_START_BIT (0) +#define AW_PID_2049_VBAT_DET_BITS_LEN (10) +#define AW_PID_2049_VBAT_DET_MASK \ + (~(((1<<AW_PID_2049_VBAT_DET_BITS_LEN)-1) << AW_PID_2049_VBAT_DET_START_BIT)) + +#define AW_PID_2049_VBAT_DET_DEFAULT_VALUE (0x263) +#define AW_PID_2049_VBAT_DET_DEFAULT \ + (AW_PID_2049_VBAT_DET_DEFAULT_VALUE << AW_PID_2049_VBAT_DET_START_BIT) + +#define AW_PID_2049_VBAT_RANGE (6025) +#define AW_PID_2049_INT_10BIT (1023) +/* default value of VBAT (0x21) */ +/* #define AW_PID_2049_VBAT_DEFAULT (0x0263) */ + +/* TEMP (0x22) detail */ +/* TEMP_DET bit 9:0 (TEMP 0x22) */ +#define AW_PID_2049_TEMP_DET_START_BIT (0) +#define AW_PID_2049_TEMP_DET_BITS_LEN (10) +#define AW_PID_2049_TEMP_DET_MASK \ + (~(((1<<AW_PID_2049_TEMP_DET_BITS_LEN)-1) << AW_PID_2049_TEMP_DET_START_BIT)) + +#define AW_PID_2049_TEMP_DET_MINUS_40 (0x3D8) +#define AW_PID_2049_TEMP_DET_MINUS_40_VALUE \ + (AW_PID_2049_TEMP_DET_MINUS_40 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_0 (0x00) +#define AW_PID_2049_TEMP_DET_0_VALUE \ + (AW_PID_2049_TEMP_DET_0 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_1 (0x01) +#define AW_PID_2049_TEMP_DET_1_VALUE \ + (AW_PID_2049_TEMP_DET_1 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_25 (0x19) +#define AW_PID_2049_TEMP_DET_25_VALUE \ + (AW_PID_2049_TEMP_DET_25 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_55 (0x37) +#define AW_PID_2049_TEMP_DET_55_VALUE \ + (AW_PID_2049_TEMP_DET_55 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_DEFAULT_VALUE (0x019) +#define AW_PID_2049_TEMP_DET_DEFAULT \ + (AW_PID_2049_TEMP_DET_DEFAULT_VALUE << AW_PID_2049_TEMP_DET_START_BIT) +#define AW_PID_2049_TEMP_SIGN_MASK (~(1 << 9)) +#define AW_PID_2049_TEMP_NEG_MASK (0XFC00) + +/* default value of TEMP (0x22) */ +/* #define AW_PID_2049_TEMP_DEFAULT (0x0019) */ + +/* PVDD (0x23) detail */ +/* PVDD_DET bit 9:0 (PVDD 0x23) */ +#define AW_PID_2049_PVDD_DET_START_BIT (0) +#define AW_PID_2049_PVDD_DET_BITS_LEN (10) +#define AW_PID_2049_PVDD_DET_MASK \ + (~(((1<<AW_PID_2049_PVDD_DET_BITS_LEN)-1) << AW_PID_2049_PVDD_DET_START_BIT)) + +#define AW_PID_2049_PVDD_DET_DEFAULT_VALUE (0x263) +#define AW_PID_2049_PVDD_DET_DEFAULT \ + (AW_PID_2049_PVDD_DET_DEFAULT_VALUE << AW_PID_2049_PVDD_DET_START_BIT) + +/* default value of PVDD (0x23) */ +/* #define AW_PID_2049_PVDD_DEFAULT (0x0263) */ + +/* BSTCTRL1 (0x60) detail */ +/* BST_RTH bit 13:8 (BSTCTRL1 0x60) */ +#define AW_PID_2049_BST_RTH_START_BIT (8) +#define AW_PID_2049_BST_RTH_BITS_LEN (6) +#define AW_PID_2049_BST_RTH_MASK \ + (~(((1<<AW_PID_2049_BST_RTH_BITS_LEN)-1) << AW_PID_2049_BST_RTH_START_BIT)) + +#define AW_PID_2049_BST_RTH_DEFAULT_VALUE (4) +#define AW_PID_2049_BST_RTH_DEFAULT \ + (AW_PID_2049_BST_RTH_DEFAULT_VALUE << AW_PID_2049_BST_RTH_START_BIT) + +/* BST_ATH bit 5:0 (BSTCTRL1 0x60) */ +#define AW_PID_2049_BST_ATH_START_BIT (0) +#define AW_PID_2049_BST_ATH_BITS_LEN (6) +#define AW_PID_2049_BST_ATH_MASK \ + (~(((1<<AW_PID_2049_BST_ATH_BITS_LEN)-1) << AW_PID_2049_BST_ATH_START_BIT)) + +#define AW_PID_2049_BST_ATH_DEFAULT_VALUE (2) +#define AW_PID_2049_BST_ATH_DEFAULT \ + (AW_PID_2049_BST_ATH_DEFAULT_VALUE << AW_PID_2049_BST_ATH_START_BIT) + +/* default value of BSTCTRL1 (0x60) */ +/* #define AW_PID_2049_BSTCTRL1_DEFAULT (0x0402) */ + +/* BSTCTRL2 (0x61) detail */ +/* BST_MODE bit 14:12 (BSTCTRL2 0x61) */ +#define AW_PID_2049_BST_MODE_START_BIT (12) +#define AW_PID_2049_BST_MODE_BITS_LEN (3) +#define AW_PID_2049_BST_MODE_MASK \ + (~(((1<<AW_PID_2049_BST_MODE_BITS_LEN)-1) << AW_PID_2049_BST_MODE_START_BIT)) + +#define AW_PID_2049_BST_MODE_TRANSPARENT (0) +#define AW_PID_2049_BST_MODE_TRANSPARENT_VALUE \ + (AW_PID_2049_BST_MODE_TRANSPARENT << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_FORCE_BOOST (1) +#define AW_PID_2049_BST_MODE_FORCE_BOOST_VALUE \ + (AW_PID_2049_BST_MODE_FORCE_BOOST << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_SMART_BOOST1 (5) +#define AW_PID_2049_BST_MODE_SMART_BOOST1_VALUE \ + (AW_PID_2049_BST_MODE_SMART_BOOST1 << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_SMART_BOOST2 (6) +#define AW_PID_2049_BST_MODE_SMART_BOOST2_VALUE \ + (AW_PID_2049_BST_MODE_SMART_BOOST2 << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_DEFAULT_VALUE (0x6) +#define AW_PID_2049_BST_MODE_DEFAULT \ + (AW_PID_2049_BST_MODE_DEFAULT_VALUE << AW_PID_2049_BST_MODE_START_BIT) + +/* WDT_CNT bit 7:0 (WDT 0x42) */ +#define AW_PID_2049_WDT_CNT_START_BIT (0) +#define AW_PID_2049_WDT_CNT_BITS_LEN (8) +#define AW_PID_2049_WDT_CNT_MASK \ + (~(((1<<AW_PID_2049_WDT_CNT_BITS_LEN)-1) << AW_PID_2049_WDT_CNT_START_BIT)) + +/* BST_TDEG bit 11:8 (BSTCTRL2 0x61) */ +#define AW_PID_2049_BST_TDEG_START_BIT (8) +#define AW_PID_2049_BST_TDEG_BITS_LEN (4) +#define AW_PID_2049_BST_TDEG_MASK \ + (~(((1<<AW_PID_2049_BST_TDEG_BITS_LEN)-1) << AW_PID_2049_BST_TDEG_START_BIT)) + +#define AW_PID_2049_BST_TDEG_0P50_MS (0) +#define AW_PID_2049_BST_TDEG_0P50_MS_VALUE \ + (AW_PID_2049_BST_TDEG_0P50_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_1P00_MS (1) +#define AW_PID_2049_BST_TDEG_1P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_1P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_2P00_MS (2) +#define AW_PID_2049_BST_TDEG_2P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_2P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_4P00_MS (3) +#define AW_PID_2049_BST_TDEG_4P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_4P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_8P00_MS (4) +#define AW_PID_2049_BST_TDEG_8P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_8P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_10P7_MS (5) +#define AW_PID_2049_BST_TDEG_10P7_MS_VALUE \ + (AW_PID_2049_BST_TDEG_10P7_MS << AW_PID_2049_BST_TDEG_START_BIT) + +/* ReAbs bit 3 (ASR1 0x45) */ +#define AW_PID_2049_ReAbs_START_BIT (3) +#define AW_PID_2049_ReAbs_BITS_LEN (1) +#define AW_PID_2049_ReAbs_MASK \ + (~(((1<<AW_PID_2049_ReAbs_BITS_LEN)-1) << AW_PID_2049_ReAbs_START_BIT)) + +#define AW_PID_2049_BST_TDEG_13P3_MS (6) +#define AW_PID_2049_BST_TDEG_13P3_MS_VALUE \ + (AW_PID_2049_BST_TDEG_13P3_MS << AW_PID_2049_BST_TDEG_START_BIT) + +/* DSP_VOL bit 15:8 (DSPCFG 0x47) */ +#define AW_PID_2049_DSP_VOL_START_BIT (8) +#define AW_PID_2049_DSP_VOL_BITS_LEN (8) +#define AW_PID_2049_DSP_VOL_MASK \ + (~(((1<<AW_PID_2049_DSP_VOL_BITS_LEN)-1) << AW_PID_2049_DSP_VOL_START_BIT)) + +#define AW_PID_2049_DSP_VOL_MUTE (0XFF00) +#define AW_PID_2049_DSP_VOL_NOISE_ST (0X1800) + +#define AW_PID_2049_BST_TDEG_16P0_MS (7) +#define AW_PID_2049_BST_TDEG_16P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_16P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_18P6_MS (8) +#define AW_PID_2049_BST_TDEG_18P6_MS_VALUE \ + (AW_PID_2049_BST_TDEG_18P6_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_21P3_MS (9) +#define AW_PID_2049_BST_TDEG_21P3_MS_VALUE \ + (AW_PID_2049_BST_TDEG_21P3_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_24P0_MS (10) +#define AW_PID_2049_BST_TDEG_24P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_24P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_32P0_MS (11) +#define AW_PID_2049_BST_TDEG_32P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_32P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_64P0_MS (12) +#define AW_PID_2049_BST_TDEG_64P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_64P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_128_MS (13) +#define AW_PID_2049_BST_TDEG_128_MS_VALUE \ + (AW_PID_2049_BST_TDEG_128_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_256_MS (14) +#define AW_PID_2049_BST_TDEG_256_MS_VALUE \ + (AW_PID_2049_BST_TDEG_256_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_1200_MS (15) +#define AW_PID_2049_BST_TDEG_1200_MS_VALUE \ + (AW_PID_2049_BST_TDEG_1200_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_DEFAULT_VALUE (11) +#define AW_PID_2049_BST_TDEG_DEFAULT \ + (AW_PID_2049_BST_TDEG_DEFAULT_VALUE << AW_PID_2049_BST_TDEG_START_BIT) + +/* VOUT_VREFSET bit 5:0 (BSTCTRL2 0x61) */ +/* CCO_MUX bit 14 (PLLCTRL1 0x52) */ +#define AW_PID_2049_CCO_MUX_START_BIT (14) +#define AW_PID_2049_CCO_MUX_BITS_LEN (1) +#define AW_PID_2049_CCO_MUX_MASK \ + (~(((1<<AW_PID_2049_CCO_MUX_BITS_LEN)-1) << AW_PID_2049_CCO_MUX_START_BIT)) + +#define AW_PID_2049_CCO_MUX_DIVIDED (0) +#define AW_PID_2049_CCO_MUX_DIVIDED_VALUE \ + (AW_PID_2049_CCO_MUX_DIVIDED << AW_PID_2049_CCO_MUX_START_BIT) + +#define AW_PID_2049_CCO_MUX_BYPASS (1) +#define AW_PID_2049_CCO_MUX_BYPASS_VALUE \ + (AW_PID_2049_CCO_MUX_BYPASS << AW_PID_2049_CCO_MUX_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_START_BIT (0) +#define AW_PID_2049_VOUT_VREFSET_BITS_LEN (6) +#define AW_PID_2049_VOUT_VREFSET_MASK \ + (~(((1<<AW_PID_2049_VOUT_VREFSET_BITS_LEN)-1) << AW_PID_2049_VOUT_VREFSET_START_BIT)) + +#define AW_PID_2049_VOUT_VREFSET_3P125V (0) +#define AW_PID_2049_VOUT_VREFSET_3P125V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P125V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P250V (1) +#define AW_PID_2049_VOUT_VREFSET_3P250V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P250V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P375V (2) +#define AW_PID_2049_VOUT_VREFSET_3P375V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P375V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P500V (3) +#define AW_PID_2049_VOUT_VREFSET_3P500V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P500V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P625V (4) +#define AW_PID_2049_VOUT_VREFSET_3P625V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P625V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P750V (5) +#define AW_PID_2049_VOUT_VREFSET_3P750V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P750V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_11P000V (63) +#define AW_PID_2049_VOUT_VREFSET_11P000V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_11P000V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE (0x33) +#define AW_PID_2049_VOUT_VREFSET_DEFAULT \ + (AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE << AW_PID_2049_VOUT_VREFSET_START_BIT) + +/* default value of BSTCTRL2 (0x61) */ +/* #define AW_PID_2049_BSTCTRL2_DEFAULT (0x6B33) */ + +/* detail information of registers end */ + +/* EF_VSN_GESLP bit 9:0 (EFRH 0x78) */ +#define AW_PID_2049_EF_VSN_GESLP_START_BIT (0) +#define AW_PID_2049_EF_VSN_GESLP_BITS_LEN (10) +#define AW_PID_2049_EF_VSN_GESLP_MASK \ + (~(((1<<AW_PID_2049_EF_VSN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_VSN_GESLP_START_BIT)) + +#define AW_PID_2049_EF_VSN_GESLP_SIGN_MASK (~(1 << 9)) +#define AW_PID_2049_EF_VSN_GESLP_SIGN_NEG (0xfe00) +/* EF_ISN_GESLP bit 9:0 (EFRM2 0x79) */ +#define AW_PID_2049_EF_ISN_GESLP_START_BIT (0) +#define AW_PID_2049_EF_ISN_GESLP_BITS_LEN (10) +#define AW_PID_2049_EF_ISN_GESLP_MASK \ + (~(((1<<AW_PID_2049_EF_ISN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_ISN_GESLP_START_BIT)) + +#define AW_PID_2049_EF_ISN_GESLP_SIGN_MASK (~(1 << 9)) +#define AW_PID_2049_EF_ISN_GESLP_SIGN_NEG (0xfe00) +/* + * Vcalb + */ + +#define AW_PID_2049_CABL_BASE_VALUE (1000) +#define AW_PID_2049_ICABLK_FACTOR (1) +#define AW_PID_2049_VCABLK_FACTOR (1) +#define AW_PID_2049_VCAL_FACTOR (1 << 12) +#define AW_PID_2049_VSCAL_FACTOR (16500) +#define AW_PID_2049_ISCAL_FACTOR (3667) +#define AW_PID_2049_EF_VSENSE_GAIN_SHIFT (0) + +#define AW_PID_2049_VCABLK_FACTOR_DAC (2) +#define AW_PID_2049_VSCAL_FACTOR_DAC (11790) +#define AW_PID_2049_EF_DAC_GESLP_SHIFT (10) +#define AW_PID_2049_EF_DAC_GESLP_SIGN_MASK (1 << 5) +#define AW_PID_2049_EF_DAC_GESLP_SIGN_NEG (0xffc0) + +#define AW_PID_2049_VCALB_ADJ_FACTOR (12) + +/* + * AW883XX DSP + */ +#define AW_PID_2049_DSP_CFG_ADDR (0x9C80) +#define AW_PID_2049_DSP_FW_ADDR (0x8C00) + +#define AW_PID_2049_DSP_REG_RESULT_F0 (0x9C58) +#define AW_PID_2049_DSP_F0_SHIFT (1) + +#define AW_PID_2049_DSP_REG_CALRE (0x9C5A) +#define AW_PID_2049_DSP_REG_CALRE_SHIFT (10) +#define AW_PID_2049_DSP_REG_RESULT_Q (0x9C5C) +#define AW_PID_2049_DSP_Q_SHIFT (11) + +#define AW_PID_2049_DSP_REG_VMAX (0x9C94) + + +#define AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG (0x9CE2) +/* bit 0 */ +#define AW_PID_2049_DSP_MONITOR_MASK (~(1 << 0)) +#define AW_PID_2049_DSP_MONITOR_ENABLE (1 << 0) +#define AW_PID_2049_DSP_MONITOR_DISABLE (0 << 0) +/*bit 4*/ +#define AW_PID_2049_DSP_REG_NOISE_MASK (~(1 << 4)) + +#define AW_PID_2049_DSP_TEMP_PEAK_MASK (~(1 << 4)) +#define AW_PID_2049_DSP_TEMP_SEL_FLAG (~(1 << 14)) + +#define AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH (0x9CE4)/*32bit*/ +#define AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH (0x9CE6)/*32bit*/ +#define AW_PID_2049_DSP_REG_VCALB (0x9CF7) + +#define AW_PID_2049_DSP_REG_CFG_ADPZ_RE (0x9D00)/*32bit*/ +#define AW_PID_2049_DSP_RE_SHIFT (12) + +#define AW_PID_2049_DSP_REG_CFG_ADPZ_RA (0x9D02)/*32bit*/ + +#define AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN (0x9D08) + + +#define AW_PID_2049_DSP_REG_CRC_ADDR (0x9F42)/*32bit*/ +#define AW_PID_2049_DSP_REG_CFGF0_FS (0x9F44)/*32bit*/ +#define AW_PID_2049_DSP_REG_CFG_RE_ALPHA (0x9F47) +#define AW_PID_2049_DSP_REG_TEMP_ADDR (0x9C5D) +#define AW_PID_2049_DSP_REG_TEMP_SWITCH (0x9D71)/*16bit*/ +#define AW_PID_2049_DSP_CALI_F0_DELAY (0x9CFD) +#define AW_PID_2049_DSP_CFG_ADPZ_T0 (0x9D11)/*16bit*/ +#define AW_PID_2049_DSP_CFG_ADPZ_COILALPHA (0x9D0F)/*16bit*/ +#define AW_PID_2049_DSP_ST_S1 (0x8180) +#define AW_PID_2049_DSP_ST_E1 (0x83FD) +#define AW_PID_2049_DSP_ST_S2 (0x9C00) +#define AW_PID_2049_DSP_ST_E2 (0x9C5D) + +#endif /* #ifndef __AW_PID_2049_REG_H__ */

From: Weidong Wang wangweidong.a@awinic.com

The Awinic AW883XX is an I2S/TDM input, high efficiency digital Smart K audio amplifier with an integrated 10.25V smart boost convert

Signed-off-by: Nick Li liweilei@awinic.com Signed-off-by: Bruce zhao zhaolei@awinic.com Signed-off-by: Weidong Wang wangweidong.a@awinic.com --- sound/soc/codecs/aw883xx/aw883xx_bin_parse.c | 1294 ++++++++++++++++++ sound/soc/codecs/aw883xx/aw883xx_bin_parse.h | 145 ++ 2 files changed, 1439 insertions(+) create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.c create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.h

diff --git a/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c new file mode 100644 index 000000000000..e4ad58f29b0a --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c @@ -0,0 +1,1294 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * aw_bin_parse.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + */ + +#include <linux/cdev.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/debugfs.h> +#include <linux/firmware.h> +#include <linux/hrtimer.h> +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/miscdevice.h> +#include <linux/of_gpio.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/timer.h> +#include <linux/uaccess.h> +#include <linux/version.h> +#include <linux/workqueue.h> +#include "aw883xx_bin_parse.h" + +#define printing_data_code + +static char *profile_name[AW_PROFILE_MAX] = { + "Music", "Voice", "Voip", "Ringtone", + "Ringtone_hs", "Lowpower", "Bypass", + "Mmi", "Fm", "Notification", "Receiver" +}; + +static int aw_parse_bin_header_1_0_0(struct aw_bin *bin); + +/* + * Interface function + * + * return value: + * value = 0 :success; + * value = -1 :check bin header version + * value = -2 :check bin data type + * value = -3 :check sum or check bin data len error + * value = -4 :check data version + * value = -5 :check register num + * value = -6 :check dsp reg num + * value = -7 :check soc app num + * value = -8 :bin is NULL point + * + */ + +/* + * check sum data + */ +static int aw_check_sum(struct aw_bin *bin, int bin_num) +{ + unsigned int i = 0; + unsigned int sum_data = 0; + unsigned int check_sum = 0; + char *p_check_sum = NULL; + + p_check_sum = &(bin->info.data[(bin->header_info[bin_num].valid_data_addr - + bin->header_info[bin_num].header_len)]); + pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum); + check_sum = GET_32_DATA(*(p_check_sum + 3), *(p_check_sum + 2), + *(p_check_sum + 1), *(p_check_sum)); + + for (i = 4; i < bin->header_info[bin_num].bin_data_len + + bin->header_info[bin_num].header_len; i++) { + sum_data += *(p_check_sum + i); + } + pr_debug("aw_bin_parse bin_num = %d, check_sum = 0x%x, sum_data = 0x%x\n", + bin_num, check_sum, sum_data); + if (sum_data != check_sum) { + p_check_sum = NULL; + pr_err("%s. CheckSum Fail.bin_num=%d, CheckSum:0x%x, SumData:0x%x", + __func__, bin_num, check_sum, sum_data); + return -BIN_DATA_LEN_ERR; + } + p_check_sum = NULL; + + return 0; +} + +static int aw_check_data_version(struct aw_bin *bin, int bin_num) +{ + int i = 0; + + for (i = DATA_VERSION_V1; i < DATA_VERSION_MAX; i++) { + if (bin->header_info[bin_num].bin_data_ver == i) + return 0; + } + pr_err("aw_bin_parse Unrecognized this bin data version\n"); + return -DATA_VER_ERR; +} + +static int aw_check_register_num_v1(struct aw_bin *bin, int bin_num) +{ + unsigned int check_register_num = 0; + unsigned int parse_register_num = 0; + char *p_check_sum = NULL; + struct bin_header_info temp_info; + + temp_info = bin->header_info[bin_num]; + p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]); + pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum); + parse_register_num = GET_32_DATA(*(p_check_sum + 3), *(p_check_sum + 2), + *(p_check_sum + 1), *(p_check_sum)); + check_register_num = (bin->header_info[bin_num].bin_data_len - 4) / + (bin->header_info[bin_num].reg_byte_len + + bin->header_info[bin_num].data_byte_len); + pr_debug("%s bin_num = %d,parse_register_num = 0x%x,check_register_num = 0x%x\n", + __func__, bin_num, parse_register_num, check_register_num); + if (parse_register_num != check_register_num) { + p_check_sum = NULL; + pr_err("%s bin_num = %d,parse_register_num = 0x%x,check_register_num = 0x%x\n", + __func__, bin_num, parse_register_num, check_register_num); + + return -REG_NUM_ERR; + } + bin->header_info[bin_num].reg_num = parse_register_num; + bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - 4; + p_check_sum = NULL; + bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr + 4; + return 0; +} + +static int aw_check_dsp_reg_num_v1(struct aw_bin *bin, int bin_num) +{ + unsigned int check_dsp_reg_num = 0; + unsigned int parse_dsp_reg_num = 0; + char *p_check_sum = NULL; + struct bin_header_info temp_info; + + temp_info = bin->header_info[bin_num]; + p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]); + pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum); + parse_dsp_reg_num = GET_32_DATA(*(p_check_sum + 7), *(p_check_sum + 6), + *(p_check_sum + 5), *(p_check_sum + 4)); + bin->header_info[bin_num].reg_data_byte_len = + GET_32_DATA(*(p_check_sum + 11), *(p_check_sum + 10), + *(p_check_sum + 9), *(p_check_sum + 8)); + check_dsp_reg_num = (bin->header_info[bin_num].bin_data_len - 12) / + bin->header_info[bin_num].reg_data_byte_len; + pr_debug("%s bin_num = %d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x", + __func__, bin_num, check_dsp_reg_num, check_dsp_reg_num); + if (parse_dsp_reg_num != check_dsp_reg_num) { + p_check_sum = NULL; + pr_err("aw_bin_parse check dsp reg num error\n"); + pr_err("%s bin_num = %d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x", + __func__, bin_num, check_dsp_reg_num, check_dsp_reg_num); + return -DSP_REG_NUM_ERR; + } + bin->header_info[bin_num].download_addr = + GET_32_DATA(*(p_check_sum + 3), *(p_check_sum + 2), + *(p_check_sum + 1), *(p_check_sum)); + bin->header_info[bin_num].reg_num = parse_dsp_reg_num; + bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - 12; + p_check_sum = NULL; + bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr + 12; + return 0; +} + +static int aw_check_soc_app_num_v1(struct aw_bin *bin, int bin_num) +{ + unsigned int check_soc_app_num = 0; + unsigned int parse_soc_app_num = 0; + char *p_check_sum = NULL; + struct bin_header_info temp_info; + + temp_info = bin->header_info[bin_num]; + p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]); + pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum); + bin->header_info[bin_num].app_version = GET_32_DATA(*(p_check_sum + 3), + *(p_check_sum + 2), *(p_check_sum + 1), *(p_check_sum)); + parse_soc_app_num = GET_32_DATA(*(p_check_sum + 11), + *(p_check_sum + 10), *(p_check_sum + 9), *(p_check_sum + 8)); + check_soc_app_num = bin->header_info[bin_num].bin_data_len - 12; + pr_debug("%s bin_num = %d, parse_soc_app_num=0x%x, check_soc_app_num = 0x%x\n", + __func__, bin_num, parse_soc_app_num, check_soc_app_num); + if (parse_soc_app_num != check_soc_app_num) { + p_check_sum = NULL; + pr_err("aw_bin_parse check soc app num error\n"); + pr_err("%s bin_num = %d, parse_soc_app_num=0x%x, check_soc_app_num = 0x%x\n", + __func__, bin_num, parse_soc_app_num, check_soc_app_num); + + return -SOC_APP_NUM_ERR; + } + bin->header_info[bin_num].reg_num = parse_soc_app_num; + bin->header_info[bin_num].download_addr = + GET_32_DATA(*(p_check_sum + 7), *(p_check_sum + 6), + *(p_check_sum + 5), *(p_check_sum + 4)); + bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - 12; + p_check_sum = NULL; + bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr + 12; + return 0; +} + +/* + * bin header 1_0_0 + */ +static void aw_get_single_bin_header_1_0_0(struct aw_bin *bin) +{ + int i; + + bin->header_info[bin->all_bin_parse_num].header_len = 60; + bin->header_info[bin->all_bin_parse_num].check_sum = + GET_32_DATA(*(bin->p_addr + 3), *(bin->p_addr + 2), + *(bin->p_addr + 1), *(bin->p_addr)); + bin->header_info[bin->all_bin_parse_num].header_ver = + GET_32_DATA(*(bin->p_addr + 7), *(bin->p_addr + 6), + *(bin->p_addr + 5), *(bin->p_addr + 4)); + bin->header_info[bin->all_bin_parse_num].bin_data_type = + GET_32_DATA(*(bin->p_addr + 11), *(bin->p_addr + 10), + *(bin->p_addr + 9), *(bin->p_addr + 8)); + bin->header_info[bin->all_bin_parse_num].bin_data_ver = + GET_32_DATA(*(bin->p_addr + 15), *(bin->p_addr + 14), + *(bin->p_addr + 13), *(bin->p_addr + 12)); + bin->header_info[bin->all_bin_parse_num].bin_data_len = + GET_32_DATA(*(bin->p_addr + 19), *(bin->p_addr + 18), + *(bin->p_addr + 17), *(bin->p_addr + 16)); + bin->header_info[bin->all_bin_parse_num].ui_ver = + GET_32_DATA(*(bin->p_addr + 23), *(bin->p_addr + 22), + *(bin->p_addr + 21), *(bin->p_addr + 20)); + bin->header_info[bin->all_bin_parse_num].reg_byte_len = + GET_32_DATA(*(bin->p_addr + 35), *(bin->p_addr + 34), + *(bin->p_addr + 33), *(bin->p_addr + 32)); + bin->header_info[bin->all_bin_parse_num].data_byte_len = + GET_32_DATA(*(bin->p_addr + 39), *(bin->p_addr + 38), + *(bin->p_addr + 37), *(bin->p_addr + 36)); + bin->header_info[bin->all_bin_parse_num].device_addr = + GET_32_DATA(*(bin->p_addr + 43), *(bin->p_addr + 42), + *(bin->p_addr + 41), *(bin->p_addr + 40)); + for (i = 0; i < 8; i++) { + bin->header_info[bin->all_bin_parse_num].chip_type[i] = + *(bin->p_addr + 24 + i); + } + bin->header_info[bin->all_bin_parse_num].reg_num = 0x00000000; + bin->header_info[bin->all_bin_parse_num].reg_data_byte_len = 0x00000000; + bin->header_info[bin->all_bin_parse_num].download_addr = 0x00000000; + bin->header_info[bin->all_bin_parse_num].app_version = 0x00000000; + bin->header_info[bin->all_bin_parse_num].valid_data_len = 0x00000000; + bin->all_bin_parse_num += 1; +} + +static int aw_parse_each_of_multi_bins_1_0_0(unsigned int bin_num, int bin_serial_num, + struct aw_bin *bin) +{ + int ret = 0; + unsigned int bin_start_addr = 0; + unsigned int valid_data_len = 0; + struct bin_header_info aw_bin_header_info; + + aw_bin_header_info = bin->header_info[bin->all_bin_parse_num - 1]; + if (!bin_serial_num) { + bin_start_addr = GET_32_DATA(*(bin->p_addr + 67), *(bin->p_addr + + 66), *(bin->p_addr + 65), *(bin->p_addr + 64)); + bin->p_addr += (60 + bin_start_addr); + bin->header_info[bin->all_bin_parse_num].valid_data_addr = + aw_bin_header_info.valid_data_addr + 4 + 8 * bin_num + 60; + } else { + valid_data_len = aw_bin_header_info.bin_data_len; + bin->p_addr += (60 + valid_data_len); + bin->header_info[bin->all_bin_parse_num].valid_data_addr = + aw_bin_header_info.valid_data_addr + + aw_bin_header_info.bin_data_len + + 60; + } + + ret = aw_parse_bin_header_1_0_0(bin); + return ret; +} + +/* Get the number of bins in multi bins, and set a for loop, + * loop processing each bin data + */ +static int aw_get_multi_bin_header_1_0_0(struct aw_bin *bin) +{ + int i = 0; + int ret = 0; + unsigned int bin_num = 0; + + bin_num = GET_32_DATA(*(bin->p_addr + 63), *(bin->p_addr + 62), + *(bin->p_addr + 61), *(bin->p_addr + 60)); + if (bin->multi_bin_parse_num == 1) + bin->header_info[bin->all_bin_parse_num].valid_data_addr = 60; + aw_get_single_bin_header_1_0_0(bin); + + for (i = 0; i < bin_num; i++) { + pr_debug("aw_bin_parse enter multi bin for is %d\n", i); + ret = aw_parse_each_of_multi_bins_1_0_0(bin_num, i, bin); + if (ret < 0) + return ret; + } + return 0; +} + +/* + * If the bin framework header version is 1.0.0, + * determine the data type of bin, and then perform different processing + * according to the data type + * If it is a single bin data type, write the data directly + * into the structure array + * If it is a multi-bin data type, first obtain the number of bins, + * and then recursively call the bin frame header processing function + * according to the bin number to process the frame header information + * of each bin separately + */ +static int aw_parse_bin_header_1_0_0(struct aw_bin *bin) +{ + int ret = 0; + unsigned int bin_data_type; + + bin_data_type = GET_32_DATA(*(bin->p_addr + 11), *(bin->p_addr + 10), + *(bin->p_addr + 9), *(bin->p_addr + 8)); + pr_debug("aw_bin_parse bin_data_type 0x%x\n", bin_data_type); + switch (bin_data_type) { + case DATA_TYPE_REGISTER: + case DATA_TYPE_DSP_REG: + case DATA_TYPE_SOC_APP: + /* Divided into two processing methods, + * one is single bin processing, + * and the other is single bin processing in multi bin + */ + pr_debug("aw_bin_parse enter single bin branch\n"); + bin->single_bin_parse_num += 1; + pr_debug("%s bin->single_bin_parse_num is %d\n", __func__, + bin->single_bin_parse_num); + if (!bin->multi_bin_parse_num) + bin->header_info[bin->all_bin_parse_num].valid_data_addr = 60; + aw_get_single_bin_header_1_0_0(bin); + break; + case DATA_TYPE_MULTI_BINS: + /* Get the number of times to enter multi bins */ + pr_debug("aw_bin_parse enter multi bin branch\n"); + bin->multi_bin_parse_num += 1; + pr_debug("%s bin->multi_bin_parse_num is %d\n", __func__, + bin->multi_bin_parse_num); + ret = aw_get_multi_bin_header_1_0_0(bin); + if (ret < 0) + return ret; + break; + } + return 0; +} + +/* get the bin's header version */ +static int aw_check_bin_header_version(struct aw_bin *bin) +{ + int ret = 0; + unsigned int header_version = 0; + + header_version = GET_32_DATA(*(bin->p_addr + 7), *(bin->p_addr + 6), + *(bin->p_addr + 5), *(bin->p_addr + 4)); + pr_debug("aw_bin_parse header_version 0x%x\n", header_version); + /* Write data to the corresponding structure array + * according to different formats of the bin frame header version + */ + switch (header_version) { + case HEADER_VERSION_1_0_0: + ret = aw_parse_bin_header_1_0_0(bin); + return ret; + default: + pr_err("aw_bin_parse Unrecognized this bin header version\n"); + return -BIN_HEADER_VER_ERR; + } +} + +static int aw_parsing_bin_file(struct aw_bin *bin) +{ + int i = 0; + int ret = 0; + + if (!bin) { + pr_err("aw_bin_parse bin is NULL\n"); + return -BIN_IS_NULL; + } + bin->p_addr = bin->info.data; + bin->all_bin_parse_num = 0; + bin->multi_bin_parse_num = 0; + bin->single_bin_parse_num = 0; + + /* filling bins header info */ + ret = aw_check_bin_header_version(bin); + if (ret < 0) { + pr_err("aw_bin_parse check bin header version error\n"); + return ret; + } + bin->p_addr = NULL; + + /* check bin header info */ + for (i = 0; i < bin->all_bin_parse_num; i++) { + /* check sum */ + ret = aw_check_sum(bin, i); + if (ret < 0) { + pr_err("aw_bin_parse check sum data error\n"); + return ret; + } + /* check bin data version */ + ret = aw_check_data_version(bin, i); + if (ret < 0) { + pr_err("aw_bin_parse check data version error\n"); + return ret; + } + /* check valid data */ + if (bin->header_info[i].bin_data_ver == DATA_VERSION_V1) { + /* check register num */ + if (bin->header_info[i].bin_data_type == + DATA_TYPE_REGISTER) { + ret = aw_check_register_num_v1(bin, i); + if (ret < 0) + return ret; + /* check dsp reg num */ + } else if (bin->header_info[i].bin_data_type == + DATA_TYPE_DSP_REG) { + ret = aw_check_dsp_reg_num_v1(bin, i); + if (ret < 0) + return ret; + /* check soc app num */ + } else if (bin->header_info[i].bin_data_type == + DATA_TYPE_SOC_APP) { + ret = aw_check_soc_app_num_v1(bin, i); + if (ret < 0) + return ret; + } else { + bin->header_info[i].valid_data_len = + bin->header_info[i].bin_data_len; + } + } + } + + return 0; +} + +int aw883xx_dev_dsp_data_order(struct aw_device *aw_dev, + uint8_t *data, uint32_t data_len) +{ + int i = 0; + uint8_t tmp_val = 0; + + if (data_len % 2 != 0) { + dev_dbg(aw_dev->dev, "data_len:%d unsupported", data_len); + return -EINVAL; + } + + for (i = 0; i < data_len; i += 2) { + tmp_val = data[i]; + data[i] = data[i + 1]; + data[i + 1] = tmp_val; + } + + return 0; +} + +static int aw_dev_parse_raw_reg(struct aw_device *aw_dev, + uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc) +{ + prof_desc->sec_desc[AW_DATA_TYPE_REG].data = data; + prof_desc->sec_desc[AW_DATA_TYPE_REG].len = data_len; + + prof_desc->prof_st = AW_PROFILE_OK; + + return 0; +} + +static int aw_dev_parse_raw_dsp_cfg(struct aw_device *aw_dev, + uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc) +{ + int ret; + + ret = aw883xx_dev_dsp_data_order(aw_dev, data, data_len); + if (ret < 0) + return ret; + + prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].data = data; + prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].len = data_len; + + prof_desc->prof_st = AW_PROFILE_OK; + + return 0; +} + +static int aw_dev_parse_raw_dsp_fw(struct aw_device *aw_dev, + uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc) +{ + int ret; + + ret = aw883xx_dev_dsp_data_order(aw_dev, data, data_len); + if (ret < 0) + return ret; + + prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].data = data; + prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].len = data_len; + + prof_desc->prof_st = AW_PROFILE_OK; + + return 0; +} + +static int aw_dev_prof_parse_multi_bin(struct aw_device *aw_dev, + uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc) +{ + struct aw_bin *aw_bin = NULL; + int i; + int ret; + + aw_bin = devm_kzalloc(aw_dev->dev, data_len + sizeof(struct aw_bin), GFP_KERNEL); + if (!aw_bin) + return -ENOMEM; + + aw_bin->info.len = data_len; + memcpy(aw_bin->info.data, data, data_len); + + ret = aw_parsing_bin_file(aw_bin); + if (ret < 0) { + dev_err(aw_dev->dev, "parse bin failed"); + goto parse_bin_failed; + } + + for (i = 0; i < aw_bin->all_bin_parse_num; i++) { + if (aw_bin->header_info[i].bin_data_type == DATA_TYPE_REGISTER) { + prof_desc->sec_desc[AW_DATA_TYPE_REG].len = + aw_bin->header_info[i].valid_data_len; + prof_desc->sec_desc[AW_DATA_TYPE_REG].data = + data + aw_bin->header_info[i].valid_data_addr; + } else if (aw_bin->header_info[i].bin_data_type == DATA_TYPE_DSP_REG) { + ret = aw883xx_dev_dsp_data_order(aw_dev, + data + aw_bin->header_info[i].valid_data_addr, + aw_bin->header_info[i].valid_data_len); + if (ret < 0) + goto parse_bin_failed; + + prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].len = + aw_bin->header_info[i].valid_data_len; + prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].data = + data + aw_bin->header_info[i].valid_data_addr; + } else if (aw_bin->header_info[i].bin_data_type == DATA_TYPE_DSP_FW) { + ret = aw883xx_dev_dsp_data_order(aw_dev, + data + aw_bin->header_info[i].valid_data_addr, + aw_bin->header_info[i].valid_data_len); + if (ret < 0) + goto parse_bin_failed; + + prof_desc->fw_ver = aw_bin->header_info[i].app_version; + prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].len = + aw_bin->header_info[i].valid_data_len; + prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].data = + data + aw_bin->header_info[i].valid_data_addr; + } + } + devm_kfree(aw_dev->dev, aw_bin); + aw_bin = NULL; + prof_desc->prof_st = AW_PROFILE_OK; + return 0; + +parse_bin_failed: + devm_kfree(aw_dev->dev, aw_bin); + aw_bin = NULL; + return ret; +} + +static int aw_dev_parse_data_by_sec_type(struct aw_device *aw_dev, struct aw_cfg_hdr *cfg_hdr, + struct aw_cfg_dde *cfg_dde, struct aw_prof_desc *scene_prof_desc) +{ + + switch (cfg_dde->data_type) { + case ACF_SEC_TYPE_REG: + return aw_dev_parse_raw_reg(aw_dev, + (uint8_t *)cfg_hdr + cfg_dde->data_offset, + cfg_dde->data_size, scene_prof_desc); + case ACF_SEC_TYPE_DSP_CFG: + return aw_dev_parse_raw_dsp_cfg(aw_dev, + (uint8_t *)cfg_hdr + cfg_dde->data_offset, + cfg_dde->data_size, scene_prof_desc); + case ACF_SEC_TYPE_DSP_FW: + return aw_dev_parse_raw_dsp_fw(aw_dev, + (uint8_t *)cfg_hdr + cfg_dde->data_offset, + cfg_dde->data_size, scene_prof_desc); + case ACF_SEC_TYPE_MUTLBIN: + return aw_dev_prof_parse_multi_bin(aw_dev, + (uint8_t *)cfg_hdr + cfg_dde->data_offset, + cfg_dde->data_size, scene_prof_desc); + } + return 0; +} + +static int aw_dev_parse_dev_type(struct aw_device *aw_dev, + struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info) +{ + int i = 0; + int ret; + int sec_num = 0; + struct aw_cfg_dde *cfg_dde = + (struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->a_hdr_offset); + + for (i = 0; i < prof_hdr->a_ddt_num; i++) { + if ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) && + (aw_dev->i2c->addr == cfg_dde[i].dev_addr) && + (cfg_dde[i].type == AW_DEV_TYPE_ID)) { + if (cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR) { + if (cfg_dde[i].dev_profile >= AW_PROFILE_MAX) { + dev_err(aw_dev->dev, "dev_profile [%d] overflow", + cfg_dde[i].dev_profile); + return -EINVAL; + } + ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i], + &all_prof_info->prof_desc[cfg_dde[i].dev_profile]); + if (ret < 0) { + dev_err(aw_dev->dev, "parse failed"); + return ret; + } + sec_num++; + } + } + } + + if (sec_num == 0) { + dev_info(aw_dev->dev, "get dev type num is %d, please use default", + sec_num); + return AW_DEV_TYPE_NONE; + } + + return AW_DEV_TYPE_OK; +} + +static int aw_dev_parse_dev_default_type(struct aw_device *aw_dev, + struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info) +{ + int i = 0; + int ret; + int sec_num = 0; + struct aw_cfg_dde *cfg_dde = + (struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->a_hdr_offset); + + for (i = 0; i < prof_hdr->a_ddt_num; i++) { + if ((aw_dev->channel == cfg_dde[i].dev_index) && + (cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID)) { + if (cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR) { + if (cfg_dde[i].dev_profile >= AW_PROFILE_MAX) { + dev_err(aw_dev->dev, "dev_profile [%d] overflow", + cfg_dde[i].dev_profile); + return -EINVAL; + } + ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i], + &all_prof_info->prof_desc[cfg_dde[i].dev_profile]); + if (ret < 0) { + dev_err(aw_dev->dev, "parse failed"); + return ret; + } + sec_num++; + } + } + } + + if (sec_num == 0) { + dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", sec_num); + return -EINVAL; + } + + return 0; +} + +static int aw_dev_cfg_get_vaild_prof(struct aw_device *aw_dev, + struct aw_all_prof_info all_prof_info) +{ + int i; + int num = 0; + struct aw_sec_data_desc *sec_desc = NULL; + struct aw_prof_desc *prof_desc = all_prof_info.prof_desc; + struct aw_prof_info *prof_info = &aw_dev->prof_info; + + for (i = 0; i < AW_PROFILE_MAX; i++) { + if (prof_desc[i].prof_st == AW_PROFILE_OK) { + sec_desc = prof_desc[i].sec_desc; + if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) && + (sec_desc[AW_DATA_TYPE_REG].len != 0) && + (sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) && + (sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) && + (sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) && + (sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) { + prof_info->count++; + } + } + } + + dev_dbg(aw_dev->dev, "get valid profile:%d", aw_dev->prof_info.count); + + if (!prof_info->count) { + dev_err(aw_dev->dev, "no profile data"); + return -EPERM; + } + + prof_info->prof_desc = devm_kzalloc(aw_dev->dev, + prof_info->count * sizeof(struct aw_prof_desc), + GFP_KERNEL); + if (!prof_info->prof_desc) { + dev_err(aw_dev->dev, "prof_desc kzalloc failed"); + return -ENOMEM; + } + + for (i = 0; i < AW_PROFILE_MAX; i++) { + if (prof_desc[i].prof_st == AW_PROFILE_OK) { + sec_desc = prof_desc[i].sec_desc; + if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) && + (sec_desc[AW_DATA_TYPE_REG].len != 0) && + (sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) && + (sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) && + (sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) && + (sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) { + if (num >= prof_info->count) { + dev_err(aw_dev->dev, "get scene num[%d] overflow count[%d]", + num, prof_info->count); + return -ENOMEM; + } + prof_info->prof_desc[num] = prof_desc[i]; + prof_info->prof_desc[num].id = i; + num++; + } + } + } + + return 0; +} + +static int aw_dev_load_cfg_by_hdr(struct aw_device *aw_dev, + struct aw_cfg_hdr *prof_hdr) +{ + int ret; + struct aw_all_prof_info all_prof_info; + + memset(&all_prof_info, 0, sizeof(struct aw_all_prof_info)); + + ret = aw_dev_parse_dev_type(aw_dev, prof_hdr, &all_prof_info); + if (ret < 0) { + return ret; + } else if (ret == AW_DEV_TYPE_NONE) { + dev_dbg(aw_dev->dev, "get dev type num is 0, parse default dev"); + ret = aw_dev_parse_dev_default_type(aw_dev, prof_hdr, &all_prof_info); + if (ret < 0) + return ret; + } + + ret = aw_dev_cfg_get_vaild_prof(aw_dev, all_prof_info); + if (ret < 0) + return ret; + + aw_dev->prof_info.prof_name_list = profile_name; + + return 0; +} + +static int aw_dev_create_prof_name_list_v_1_0_0_0(struct aw_device *aw_dev) +{ + struct aw_prof_info *prof_info = &aw_dev->prof_info; + struct aw_prof_desc *prof_desc = prof_info->prof_desc; + int i; + + if (!prof_desc) { + dev_err(aw_dev->dev, "prof_desc is NULL"); + return -EINVAL; + } + + prof_info->prof_name_list = devm_kzalloc(aw_dev->dev, + prof_info->count * PROFILE_STR_MAX, + GFP_KERNEL); + if (!prof_info->prof_name_list) { + dev_err(aw_dev->dev, "prof_name_list devm_kzalloc failed"); + return -ENOMEM; + } + + for (i = 0; i < prof_info->count; i++) { + prof_desc[i].id = i; + prof_info->prof_name_list[i] = prof_desc[i].prf_str; + dev_dbg(aw_dev->dev, "prof name is %s", prof_info->prof_name_list[i]); + } + + return 0; +} + +static int aw_get_dde_type_info(struct aw_device *aw_dev, struct aw_container *aw_cfg) +{ + int i; + int dev_num = 0; + int default_num = 0; + struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data; + struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = + (struct aw_cfg_dde_v_1_0_0_0 *)(aw_cfg->data + cfg_hdr->a_hdr_offset); + + for (i = 0; i < cfg_hdr->a_ddt_num; i++) { + if (cfg_dde[i].type == AW_DEV_TYPE_ID) + dev_num++; + + if (cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID) + default_num++; + } + + if (!(dev_num || default_num)) { + dev_err(aw_dev->dev, "can't find scene"); + return -EINVAL; + } + + if (dev_num != 0) + aw_dev->prof_info.prof_type = AW_DEV_TYPE_ID; + else if (default_num != 0) + aw_dev->prof_info.prof_type = AW_DEV_DEFAULT_TYPE_ID; + + return 0; +} + +static int aw_get_dev_scene_count_v_1_0_0_0(struct aw_device *aw_dev, struct aw_container *aw_cfg, + uint32_t *scene_num) +{ + int i; + struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data; + struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = + (struct aw_cfg_dde_v_1_0_0_0 *)(aw_cfg->data + cfg_hdr->a_hdr_offset); + for (i = 0; i < cfg_hdr->a_ddt_num; ++i) { + if ((cfg_dde[i].data_type == ACF_SEC_TYPE_MUTLBIN) && + (aw_dev->chip_id == cfg_dde[i].chip_id) && + ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) && + (aw_dev->i2c->addr == cfg_dde[i].dev_addr))) { + (*scene_num)++; + } + } + + return 0; +} + +static int aw_get_default_scene_count_v_1_0_0_0(struct aw_device *aw_dev, + struct aw_container *aw_cfg, + uint32_t *scene_num) +{ + int i; + struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data; + struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = + (struct aw_cfg_dde_v_1_0_0_0 *)(aw_cfg->data + cfg_hdr->a_hdr_offset); + + for (i = 0; i < cfg_hdr->a_ddt_num; ++i) { + if ((cfg_dde[i].data_type == ACF_SEC_TYPE_MUTLBIN) && + (aw_dev->chip_id == cfg_dde[i].chip_id) && + (aw_dev->channel == cfg_dde[i].dev_index)) + (*scene_num)++; + } + + return 0; +} + +static int aw_dev_parse_scene_count_v_1_0_0_0(struct aw_device *aw_dev, + struct aw_container *aw_cfg, + uint32_t *count) +{ + int ret; + + ret = aw_get_dde_type_info(aw_dev, aw_cfg); + if (ret < 0) + return ret; + + if (aw_dev->prof_info.prof_type == AW_DEV_TYPE_ID) { + aw_get_dev_scene_count_v_1_0_0_0(aw_dev, aw_cfg, count); + } else if (aw_dev->prof_info.prof_type == AW_DEV_DEFAULT_TYPE_ID) { + aw_get_default_scene_count_v_1_0_0_0(aw_dev, aw_cfg, count); + } else { + dev_err(aw_dev->dev, "unsupported prof_type[%x]", + aw_dev->prof_info.prof_type); + return -EINVAL; + } + + dev_info(aw_dev->dev, "scene count is %d", (*count)); + return 0; +} + +static int aw_dev_parse_data_by_sec_type_v_1_0_0_0(struct aw_device *aw_dev, + struct aw_cfg_hdr *prof_hdr, + struct aw_cfg_dde_v_1_0_0_0 *cfg_dde, + int *cur_scene_id) +{ + int ret; + struct aw_prof_info *prof_info = &aw_dev->prof_info; + + switch (cfg_dde->data_type) { + case ACF_SEC_TYPE_MUTLBIN: + ret = aw_dev_prof_parse_multi_bin(aw_dev, + (uint8_t *)prof_hdr + cfg_dde->data_offset, + cfg_dde->data_size, &prof_info->prof_desc[*cur_scene_id]); + if (ret < 0) { + dev_err(aw_dev->dev, "parse multi bin failed"); + return ret; + } + prof_info->prof_desc[*cur_scene_id].prf_str = cfg_dde->dev_profile_str; + prof_info->prof_desc[*cur_scene_id].id = cfg_dde->dev_profile; + (*cur_scene_id)++; + break; + default: + pr_err("unsupported SEC_TYPE [%d]", cfg_dde->data_type); + return -EINVAL; + } + + return 0; +} + +static int aw_dev_parse_dev_type_v_1_0_0_0(struct aw_device *aw_dev, + struct aw_cfg_hdr *prof_hdr) +{ + int i = 0; + int ret; + int cur_scene_id = 0; + struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = + (struct aw_cfg_dde_v_1_0_0_0 *)((char *)prof_hdr + prof_hdr->a_hdr_offset); + + for (i = 0; i < prof_hdr->a_ddt_num; i++) { + if ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) && + (aw_dev->i2c->addr == cfg_dde[i].dev_addr) && + (aw_dev->chip_id == cfg_dde[i].chip_id)) { + ret = aw_dev_parse_data_by_sec_type_v_1_0_0_0(aw_dev, prof_hdr, + &cfg_dde[i], &cur_scene_id); + if (ret < 0) { + dev_err(aw_dev->dev, "parse failed"); + return ret; + } + } + } + + if (cur_scene_id == 0) { + dev_err(aw_dev->dev, "get dev type failed, get num [%d]", cur_scene_id); + return -EINVAL; + } + + return 0; +} + +static int aw_dev_parse_default_type_v_1_0_0_0(struct aw_device *aw_dev, + struct aw_cfg_hdr *prof_hdr) +{ + int i = 0; + int ret; + int cur_scene_id = 0; + struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = + (struct aw_cfg_dde_v_1_0_0_0 *)((char *)prof_hdr + prof_hdr->a_hdr_offset); + + for (i = 0; i < prof_hdr->a_ddt_num; i++) { + if ((aw_dev->channel == cfg_dde[i].dev_index) && + (aw_dev->chip_id == cfg_dde[i].chip_id)) { + ret = aw_dev_parse_data_by_sec_type_v_1_0_0_0(aw_dev, prof_hdr, + &cfg_dde[i], &cur_scene_id); + if (ret < 0) { + dev_err(aw_dev->dev, "parse failed"); + return ret; + } + } + } + + if (cur_scene_id == 0) { + dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", cur_scene_id); + return -EINVAL; + } + + return 0; +} + +static int aw_dev_parse_by_hdr_v_1_0_0_0(struct aw_device *aw_dev, + struct aw_cfg_hdr *cfg_hdr) +{ + int ret; + + if (aw_dev->prof_info.prof_type == AW_DEV_TYPE_ID) { + ret = aw_dev_parse_dev_type_v_1_0_0_0(aw_dev, cfg_hdr); + if (ret < 0) + return ret; + } else if (aw_dev->prof_info.prof_type == AW_DEV_DEFAULT_TYPE_ID) { + ret = aw_dev_parse_default_type_v_1_0_0_0(aw_dev, cfg_hdr); + if (ret < 0) + return ret; + } else { + dev_err(aw_dev->dev, "prof type matched failed, get num[%d]", + aw_dev->prof_info.prof_type); + return -EINVAL; + } + + return 0; +} + +static int aw_dev_load_cfg_by_hdr_v_1_0_0_0(struct aw_device *aw_dev, struct aw_container *aw_cfg) +{ + struct aw_prof_info *prof_info = &aw_dev->prof_info; + struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data; + int ret; + + ret = aw_dev_parse_scene_count_v_1_0_0_0(aw_dev, aw_cfg, &prof_info->count); + if (ret < 0) { + dev_err(aw_dev->dev, "get scene count failed"); + return ret; + } + + prof_info->prof_desc = devm_kzalloc(aw_dev->dev, + prof_info->count * sizeof(struct aw_prof_desc), + GFP_KERNEL); + if (!prof_info->prof_desc) + return -ENOMEM; + + ret = aw_dev_parse_by_hdr_v_1_0_0_0(aw_dev, cfg_hdr); + if (ret < 0) { + dev_err(aw_dev->dev, " failed"); + return ret; + } + + ret = aw_dev_create_prof_name_list_v_1_0_0_0(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "create prof name list failed"); + return ret; + } + + return 0; +} + +int aw883xx_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg) +{ + struct aw_cfg_hdr *cfg_hdr = NULL; + int ret; + + cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data; + switch (cfg_hdr->a_hdr_version) { + case AW_CFG_HDR_VER_0_0_0_1: + ret = aw_dev_load_cfg_by_hdr(aw_dev, cfg_hdr); + if (ret < 0) { + dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed", + cfg_hdr->a_hdr_version); + return ret; + } + break; + case AW_CFG_HDR_VER_1_0_0_0: + ret = aw_dev_load_cfg_by_hdr_v_1_0_0_0(aw_dev, aw_cfg); + if (ret < 0) { + dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed", + cfg_hdr->a_hdr_version); + return ret; + } + break; + default: + pr_err("unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version); + return -EINVAL; + } + + aw_dev->fw_status = AW_DEV_FW_OK; + return 0; +} + +static uint8_t aw_dev_crc8_check(unsigned char *data, uint32_t data_size) +{ + uint8_t crc_value = 0x00; + uint8_t pdatabuf = 0; + int i; + + while (data_size--) { + pdatabuf = *data++; + for (i = 0; i < 8; i++) { + /*if the lowest bit is 1*/ + if ((crc_value ^ (pdatabuf)) & 0x01) { + /*Xor multinomial*/ + crc_value ^= 0x18; + crc_value >>= 1; + crc_value |= 0x80; + } else { + crc_value >>= 1; + } + pdatabuf >>= 1; + } + } + return crc_value; +} + +static int aw_dev_check_cfg_by_hdr(struct aw_container *aw_cfg) +{ + struct aw_cfg_hdr *cfg_hdr = NULL; + struct aw_cfg_dde *cfg_dde = NULL; + unsigned int end_data_offset = 0; + unsigned int act_data = 0; + unsigned int hdr_ddt_len = 0; + uint8_t act_crc8 = 0; + int i; + + cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data; + + /*check file type id is awinic acf file*/ + if (cfg_hdr->a_id != ACF_FILE_ID) { + pr_err("not acf type file"); + return -EINVAL; + } + + hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size; + if (hdr_ddt_len > aw_cfg->len) { + pr_err("hdrlen with ddt_len [%d] overflow file size[%d]", + cfg_hdr->a_hdr_offset, aw_cfg->len); + return -EINVAL; + } + + /*check data size*/ + cfg_dde = (struct aw_cfg_dde *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset); + act_data += hdr_ddt_len; + for (i = 0; i < cfg_hdr->a_ddt_num; i++) + act_data += cfg_dde[i].data_size; + + if (act_data != aw_cfg->len) { + pr_err("act_data[%d] not equal to file size[%d]!", + act_data, aw_cfg->len); + return -EINVAL; + } + + for (i = 0; i < cfg_hdr->a_ddt_num; i++) { + /* data check */ + end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size; + if (end_data_offset > aw_cfg->len) { + pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]", + i, end_data_offset, aw_cfg->len); + return -EINVAL; + } + + /* crc check */ + act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset, + cfg_dde[i].data_size); + if (act_crc8 != cfg_dde[i].data_crc) { + pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x", + i, (uint32_t)act_crc8, cfg_dde[i].data_crc); + return -EINVAL; + } + } + + return 0; +} + +static int aw_dev_check_acf_by_hdr_v_1_0_0_0(struct aw_container *aw_cfg) +{ + struct aw_cfg_hdr *cfg_hdr = NULL; + struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = NULL; + unsigned int end_data_offset = 0; + unsigned int act_data = 0; + unsigned int hdr_ddt_len = 0; + uint8_t act_crc8 = 0; + int i; + + cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data; + + /*check file type id is awinic acf file*/ + if (cfg_hdr->a_id != ACF_FILE_ID) { + pr_err("not acf type file"); + return -EINVAL; + } + + hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size; + if (hdr_ddt_len > aw_cfg->len) { + pr_err("hdrlen with ddt_len [%d] overflow file size[%d]", + cfg_hdr->a_hdr_offset, aw_cfg->len); + return -EINVAL; + } + + /*check data size*/ + cfg_dde = (struct aw_cfg_dde_v_1_0_0_0 *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset); + act_data += hdr_ddt_len; + for (i = 0; i < cfg_hdr->a_ddt_num; i++) + act_data += cfg_dde[i].data_size; + + if (act_data != aw_cfg->len) { + pr_err("act_data[%d] not equal to file size[%d]!", + act_data, aw_cfg->len); + return -EINVAL; + } + + for (i = 0; i < cfg_hdr->a_ddt_num; i++) { + /* data check */ + end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size; + if (end_data_offset > aw_cfg->len) { + pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]", + i, end_data_offset, aw_cfg->len); + return -EINVAL; + } + + /* crc check */ + act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset, + cfg_dde[i].data_size); + if (act_crc8 != cfg_dde[i].data_crc) { + pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x", + i, (uint32_t)act_crc8, cfg_dde[i].data_crc); + return -EINVAL; + } + } + + return 0; + +} + +int aw883xx_dev_load_acf_check(struct aw_container *aw_cfg) +{ + struct aw_cfg_hdr *cfg_hdr = NULL; + + if (!aw_cfg) { + pr_err("aw_prof is NULL"); + return -ENOMEM; + } + + if (aw_cfg->len < sizeof(struct aw_cfg_hdr)) { + pr_err("cfg hdr size[%d] overflow file size[%d]", + aw_cfg->len, (int)sizeof(struct aw_cfg_hdr)); + return -EINVAL; + } + + cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data; + switch (cfg_hdr->a_hdr_version) { + case AW_CFG_HDR_VER_0_0_0_1: + return aw_dev_check_cfg_by_hdr(aw_cfg); + case AW_CFG_HDR_VER_1_0_0_0: + return aw_dev_check_acf_by_hdr_v_1_0_0_0(aw_cfg); + default: + pr_err("unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version); + return -EINVAL; + } + + return 0; +} + +int aw883xx_dev_get_profile_count(struct aw_device *aw_dev) +{ + if (!aw_dev) { + pr_err("aw_dev is NULL"); + return -ENOMEM; + } + + return aw_dev->prof_info.count; +} + +int aw883xx_dev_check_profile_index(struct aw_device *aw_dev, int index) +{ + if ((index >= aw_dev->prof_info.count) || (index < 0)) + return -EINVAL; + else + return 0; +} + +int aw883xx_dev_get_profile_index(struct aw_device *aw_dev) +{ + return aw_dev->set_prof; +} + +int aw883xx_dev_set_profile_index(struct aw_device *aw_dev, int index) +{ + struct aw_prof_desc *prof_desc = NULL; + + if ((index < aw_dev->prof_info.count) && (index >= 0)) { + aw_dev->set_prof = index; + prof_desc = &aw_dev->prof_info.prof_desc[index]; + + dev_dbg(aw_dev->dev, "set prof[%s]", + aw_dev->prof_info.prof_name_list[prof_desc->id]); + } else { + return -EINVAL; + } + + return 0; +} + +char *aw_dev_get_prof_name(struct aw_device *aw_dev, int index) +{ + struct aw_prof_desc *prof_desc = NULL; + struct aw_prof_info *prof_info = &aw_dev->prof_info; + + if ((index >= aw_dev->prof_info.count) || (index < 0)) { + dev_err(aw_dev->dev, "index[%d] overflow count[%d]", + index, aw_dev->prof_info.count); + return NULL; + } + + prof_desc = &aw_dev->prof_info.prof_desc[index]; + + return prof_info->prof_name_list[prof_desc->id]; +} + +int aw883xx_dev_get_prof_data(struct aw_device *aw_dev, int index, + struct aw_prof_desc **prof_desc) +{ + if ((index >= aw_dev->prof_info.count) || (index < 0)) { + dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n", + __func__, index, aw_dev->prof_info.count); + return -EINVAL; + } + + *prof_desc = &aw_dev->prof_info.prof_desc[index]; + + return 0; +} + diff --git a/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h new file mode 100644 index 000000000000..126c41a1e42c --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_BIN_PARSE_H__ +#define __AW883XX_BIN_PARSE_H__ + +#include "aw883xx_device.h" + +#define NULL ((void *)0) +#define GET_32_DATA(w, x, y, z) \ + ((unsigned int)((((uint8_t)w) << 24) | \ + (((uint8_t)x) << 16) | (((uint8_t)y) << 8) | \ + ((uint8_t)z))) +#define BIN_NUM_MAX 100 +#define HEADER_LEN 60 +/* + * header information + */ +enum return_enum { + BIN_HEADER_VER_ERR = 1, + BIN_DATA_TYPE_ERR = 2, + BIN_DATA_LEN_ERR = 3, + DATA_VER_ERR = 4, + REG_NUM_ERR = 5, + DSP_REG_NUM_ERR = 6, + SOC_APP_NUM_ERR = 7, + BIN_IS_NULL = 8, +}; + +enum bin_header_version_enum { + HEADER_VERSION_1_0_0 = 0x01000000, +}; + +enum data_type_enum { + DATA_TYPE_REGISTER = 0x00000000, + DATA_TYPE_DSP_REG = 0x00000010, + DATA_TYPE_DSP_CFG = 0x00000011, + DATA_TYPE_SOC_REG = 0x00000020, + DATA_TYPE_SOC_APP = 0x00000021, + DATA_TYPE_DSP_FW = DATA_TYPE_SOC_APP, + DATA_TYPE_MULTI_BINS = 0x00002000, +}; + +/** + * @DATA_VERSION_V1：default little edian + */ +enum data_version_enum { + DATA_VERSION_V1 = 0X00000001, + DATA_VERSION_MAX, +}; + +/** + * @header_len: Frame header length + * @check_sum: Frame header information-Checksum + * @header_ver: Frame header information-Frame header version + * @bin_data_type: Frame header information-Data type + * @bin_data_ver: Frame header information-Data version + * @bin_data_len: Frame header information-Data length + * @ui_ver: Frame header information-ui version + * @chip_type[8]: Frame header information-chip type + * @reg_byte_len: Frame header information-reg byte len + * @data_byte_len: Frame header information-data byte len + * @device_addr: Frame header information-device addr + * @valid_data_len: Length of valid data obtained after parsing + * @valid_data_addr: The offset address of the valid data obtained + * after parsing relative to info + * @reg_num: The number of registers obtained after parsing + * @reg_data_byte_len: The byte length of the register obtained after parsing + * @download_addr: The starting address or download address obtained + * after parsing + * @app_version: The software version number obtained after parsing + */ +struct bin_header_info { + unsigned int header_len; + unsigned int check_sum; + unsigned int header_ver; + unsigned int bin_data_type; + unsigned int bin_data_ver; + unsigned int bin_data_len; + unsigned int ui_ver; + unsigned char chip_type[8]; + unsigned int reg_byte_len; + unsigned int data_byte_len; + unsigned int device_addr; + unsigned int valid_data_len; + unsigned int valid_data_addr; + + unsigned int reg_num; + unsigned int reg_data_byte_len; + unsigned int download_addr; + unsigned int app_version; +}; + +/* + * function define + * + */ +/* + * @len: The size of the bin file obtained from the firmware + * @data[]: Store the bin file obtained from the firmware + */ +struct bin_container { + unsigned int len; + unsigned char data[]; +}; + +/** + * @p_addr: Offset pointer (backward offset pointer to obtain frame header + * information and important information) + * @all_bin_parse_num: The number of all bin files + * @multi_bin_parse_num: The number of single bin files + * @single_bin_parse_num: The number of multiple bin files + * @header_info[BIN_NUM_MAX]: Frame header information and other important data + * obtained after parsing + * @info: Obtained bin file data that needs to be parsed + */ +struct aw_bin { + unsigned char *p_addr; + unsigned int all_bin_parse_num; + unsigned int multi_bin_parse_num; + unsigned int single_bin_parse_num; + struct bin_header_info header_info[BIN_NUM_MAX]; + struct bin_container info; +}; + +/*******************awinic audio parse acf***********************/ +int aw883xx_dev_dsp_data_order(struct aw_device *aw_dev, + uint8_t *data, uint32_t data_len); +int aw883xx_dev_get_prof_data(struct aw_device *aw_dev, int index, + struct aw_prof_desc **prof_desc); +char *aw_dev_get_prof_name(struct aw_device *aw_dev, int index); +int aw883xx_dev_set_profile_index(struct aw_device *aw_dev, int index); +int aw883xx_dev_get_profile_index(struct aw_device *aw_dev); +int aw883xx_dev_check_profile_index(struct aw_device *aw_dev, int index); +int aw883xx_dev_get_profile_count(struct aw_device *aw_dev); +int aw883xx_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg); +int aw883xx_dev_load_acf_check(struct aw_container *aw_cfg); + +#endif

From: Weidong Wang wangweidong.a@awinic.com

The Awinic AW883XX is an I2S/TDM input, high efficiency digital Smart K audio amplifier with an integrated 10.25V smart boost convert

Signed-off-by: Nick Li liweilei@awinic.com Signed-off-by: Bruce zhao zhaolei@awinic.com Signed-off-by: Weidong Wang wangweidong.a@awinic.com --- sound/soc/codecs/aw883xx/aw883xx_data_type.h | 148 ++ sound/soc/codecs/aw883xx/aw883xx_init.c | 635 +++++ .../soc/codecs/aw883xx/aw883xx_pid_2049_reg.h | 2300 +++++++++++++++++ 3 files changed, 3083 insertions(+) create mode 100644 sound/soc/codecs/aw883xx/aw883xx_data_type.h create mode 100644 sound/soc/codecs/aw883xx/aw883xx_init.c create mode 100644 sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h

diff --git a/sound/soc/codecs/aw883xx/aw883xx_data_type.h b/sound/soc/codecs/aw883xx/aw883xx_data_type.h new file mode 100644 index 000000000000..a72d2d59025f --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_data_type.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_DATA_TYPE_H__ +#define __AW883XX_DATA_TYPE_H__ + +#define AW_NAME_BUF_MAX (50) + +/* + * aw profile + */ +#define PROJECT_NAME_MAX (24) +#define CUSTOMER_NAME_MAX (16) +#define CFG_VERSION_MAX (4) +#define DEV_NAME_MAX (16) +#define PROFILE_STR_MAX (32) + +#define ACF_FILE_ID (0xa15f908) + +enum aw_cfg_hdr_version { + AW_CFG_HDR_VER_0_0_0_1 = 0x00000001, + AW_CFG_HDR_VER_1_0_0_0 = 0x01000000, +}; + +enum aw_cfg_dde_type { + AW_DEV_NONE_TYPE_ID = 0xFFFFFFFF, + AW_DEV_TYPE_ID = 0x00000000, + AW_SKT_TYPE_ID = 0x00000001, + AW_DEV_DEFAULT_TYPE_ID = 0x00000002, +}; + +enum aw_sec_type { + ACF_SEC_TYPE_REG = 0, + ACF_SEC_TYPE_DSP, + ACF_SEC_TYPE_DSP_CFG, + ACF_SEC_TYPE_DSP_FW, + ACF_SEC_TYPE_HDR_REG, + ACF_SEC_TYPE_HDR_DSP_CFG, + ACF_SEC_TYPE_HDR_DSP_FW, + ACF_SEC_TYPE_MUTLBIN, + ACF_SEC_TYPE_SKT_PROJECT, + ACF_SEC_TYPE_DSP_PROJECT, + ACF_SEC_TYPE_MONITOR, + ACF_SEC_TYPE_MAX, +}; + +enum profile_data_type { + AW_DATA_TYPE_REG = 0, + AW_DATA_TYPE_DSP_CFG, + AW_DATA_TYPE_DSP_FW, + AW_DATA_TYPE_MAX, +}; + +enum aw_prof_type { + AW_PROFILE_MUSIC = 0, + AW_PROFILE_VOICE, + AW_PROFILE_VOIP, + AW_PROFILE_RINGTONE, + AW_PROFILE_RINGTONE_HS, + AW_PROFILE_LOWPOWER, + AW_PROFILE_BYPASS, + AW_PROFILE_MMI, + AW_PROFILE_FM, + AW_PROFILE_NOTIFICATION, + AW_PROFILE_RECEIVER, + AW_PROFILE_MAX, +}; + +enum aw_profile_status { + AW_PROFILE_WAIT = 0, + AW_PROFILE_OK, +}; + +struct aw_cfg_hdr { + uint32_t a_id; /*acf file ID 0xa15f908*/ + char a_project[PROJECT_NAME_MAX]; /*project name*/ + char a_custom[CUSTOMER_NAME_MAX]; /*custom name :huawei xiaomi vivo oppo*/ + char a_version[CFG_VERSION_MAX]; /*author update version*/ + uint32_t a_author_id; /*author id*/ + uint32_t a_ddt_size; /*sub section table entry size*/ + uint32_t a_ddt_num; /*sub section table entry num*/ + uint32_t a_hdr_offset; /*sub section table offset in file*/ + uint32_t a_hdr_version; /*sub section table version*/ + uint32_t reserve[3]; +}; + +struct aw_cfg_dde { + uint32_t type; /*DDE type id*/ + char dev_name[DEV_NAME_MAX]; + uint16_t dev_index; /*dev id*/ + uint16_t dev_bus; /*dev bus id*/ + uint16_t dev_addr; /*dev addr id*/ + uint16_t dev_profile; /*dev profile id*/ + uint32_t data_type; /*data type id*/ + uint32_t data_size; + uint32_t data_offset; + uint32_t data_crc; + uint32_t reserve[5]; +}; + +struct aw_cfg_dde_v_1_0_0_0 { + uint32_t type; /*DDE type id*/ + char dev_name[DEV_NAME_MAX]; + uint16_t dev_index; /*dev id*/ + uint16_t dev_bus; /*dev bus id*/ + uint16_t dev_addr; /*dev addr id*/ + uint16_t dev_profile; /*dev profile id*/ + uint32_t data_type; /*data type id*/ + uint32_t data_size; + uint32_t data_offset; + uint32_t data_crc; + char dev_profile_str[PROFILE_STR_MAX]; + uint32_t chip_id; + uint32_t reserve[4]; +}; + +struct aw_sec_data_desc { + uint32_t len; + unsigned char *data; +}; + +struct aw_prof_desc { + uint32_t id; + uint32_t prof_st; + char *prf_str; + uint32_t fw_ver; + struct aw_sec_data_desc sec_desc[AW_DATA_TYPE_MAX]; +}; + +struct aw_all_prof_info { + struct aw_prof_desc prof_desc[AW_PROFILE_MAX]; +}; + +struct aw_prof_info { + int count; + int prof_type; + char **prof_name_list; + struct aw_prof_desc *prof_desc; +}; + +#endif + diff --git a/sound/soc/codecs/aw883xx/aw883xx_init.c b/sound/soc/codecs/aw883xx/aw883xx_init.c new file mode 100644 index 000000000000..d2de2e199d49 --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_init.c @@ -0,0 +1,635 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/firmware.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/regmap.h> +#include <linux/syscalls.h> +#include <linux/uaccess.h> +#include <linux/version.h> +#include <linux/workqueue.h> +#include <sound/control.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include "aw883xx.h" +#include "aw883xx_bin_parse.h" +#include "aw883xx_pid_2049_reg.h" + +#define AW_FW_CHECK_PART (10) +#define AW_GET_32_DATA(w, x, y, z) \ + ((uint32_t)((((uint8_t)w) << 24) | (((uint8_t)x) << 16) | \ + (((uint8_t)y) << 8) | ((uint8_t)z))) +#define AW_GET_16_DATA(x, y) \ + ((uint16_t)((((uint8_t)x) << 8) | (uint8_t)y)) + +static const unsigned char aw_pid_2049_reg_access[AW_PID_2049_REG_MAX] = { + [AW_PID_2049_ID_REG] = (REG_RD_ACCESS), + [AW_PID_2049_SYSST_REG] = (REG_RD_ACCESS), + [AW_PID_2049_SYSINT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_SYSINTM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SYSCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_MPDCFG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PWMCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DBGCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCST_REG] = (REG_RD_ACCESS), + [AW_PID_2049_VBAT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TEMP_REG] = (REG_RD_ACCESS), + [AW_PID_2049_PVDD_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ISNDAT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_VSNDAT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_I2SINT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_I2SCAPCNT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA1_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA2_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA3_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA4_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TESTDET_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TESTIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_TESTOUT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_DSPMADD_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSPMDAT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_WDT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ACR1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ACR2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ASR1_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ASR2_REG] = (REG_RD_ACCESS), + [AW_PID_2049_DSPCFG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ASR3_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ASR4_REG] = (REG_RD_ACCESS), + [AW_PID_2049_VSNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ISNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PLLCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PLLCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PLLCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_CDACTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_CDACTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SADCCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SADCCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_CPCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG8_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_TESTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_TESTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWM2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWM1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFRH_REG] = (REG_RD_ACCESS), + [AW_PID_2049_EFRM2_REG] = (REG_RD_ACCESS), + [AW_PID_2049_EFRM1_REG] = (REG_RD_ACCESS), + [AW_PID_2049_EFRL_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TM_REG] = (REG_NONE_ACCESS), +}; + +static int aw883xx_dev_dsp_write(struct aw_device *aw_dev, + uint16_t dsp_addr, uint32_t dsp_data, uint8_t data_type) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_dsp_write(aw883xx, dsp_addr, dsp_data, data_type); +} + +static int aw883xx_dev_dsp_read(struct aw_device *aw_dev, + uint16_t dsp_addr, uint32_t *dsp_data, uint8_t data_type) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_dsp_read(aw883xx, dsp_addr, dsp_data, data_type); +} + +/* + * aw883xx i2c write/read + */ +/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB real_value = value * 8 : 0.125db --> 1*/ +static unsigned int aw_pid_2049_reg_val_to_db(unsigned int value) +{ + return (((value >> AW_PID_2049_VOL_6DB_START) * AW_PID_2049_VOLUME_STEP_DB) + + ((value & 0x3f) % AW_PID_2049_VOLUME_STEP_DB)); +} + +/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB reg_value = value / step << 6 + value % step ; step = 6 * 8*/ +static uint16_t aw_pid_2049_db_val_to_reg(uint16_t value) +{ + return (((value / AW_PID_2049_VOLUME_STEP_DB) << AW_PID_2049_VOL_6DB_START) + + (value % AW_PID_2049_VOLUME_STEP_DB)); +} + +static int aw883xx_set_volume(struct aw883xx *aw883xx, uint16_t value) +{ + unsigned int reg_value = 0; + uint16_t real_value = 0; + uint16_t volume = 0; + struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc; + + volume = AW_GET_MIN_VALUE(value, vol_desc->mute_volume); + real_value = aw_pid_2049_db_val_to_reg(volume); + + /* cal real value */ + regmap_read(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, &reg_value); + + dev_dbg(aw883xx->dev, "value 0x%x , reg:0x%x", value, real_value); + + /*[15 : 6] volume*/ + real_value = (real_value << AW_PID_2049_VOL_START_BIT) | (reg_value & AW_PID_2049_VOL_MASK); + + /* write value */ + regmap_write(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, real_value); + + return 0; +} + +static int aw883xx_get_volume(struct aw883xx *aw883xx, uint16_t *value) +{ + unsigned int reg_value = 0; + uint16_t real_value = 0; + + /* read value */ + regmap_read(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, &reg_value); + + /*[15 : 6] volume*/ + real_value = reg_value >> AW_PID_2049_VOL_START_BIT; + + real_value = aw_pid_2049_reg_val_to_db(real_value); + + *value = real_value; + + return 0; +} + +static int aw_pid_2049_set_volume(struct aw_device *aw_dev, uint16_t value) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_set_volume(aw883xx, value); +} + +static int aw_pid_2049_get_volume(struct aw_device *aw_dev, uint16_t *value) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_get_volume(aw883xx, value); +} + +static void aw_pid_2049_i2s_tx_enable(struct aw_device *aw_dev, bool flag) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + if (flag) { + regmap_update_bits(aw883xx->regmap, AW_PID_2049_I2SCFG1_REG, + ~AW_PID_2049_I2STXEN_MASK, + AW_PID_2049_I2STXEN_ENABLE_VALUE); + } else { + regmap_update_bits(aw883xx->regmap, AW_PID_2049_I2SCFG1_REG, + ~AW_PID_2049_I2STXEN_MASK, + AW_PID_2049_I2STXEN_DISABLE_VALUE); + } +} + +static void aw_pid_2049_set_cfg_f0_fs(struct aw_device *aw_dev, uint32_t *f0_fs) +{ + unsigned int rate_data = 0; + uint32_t fs = 0; + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + regmap_read(aw883xx->regmap, AW_PID_2049_I2SCTRL_REG, &rate_data); + + switch (rate_data & (~AW_PID_2049_I2SSR_MASK)) { + case AW_PID_2049_I2SSR_8_KHZ_VALUE: + fs = 8000; + break; + case AW_PID_2049_I2SSR_16_KHZ_VALUE: + fs = 16000; + break; + case AW_PID_2049_I2SSR_32_KHZ_VALUE: + fs = 32000; + break; + case AW_PID_2049_I2SSR_44_KHZ_VALUE: + fs = 44000; + break; + case AW_PID_2049_I2SSR_48_KHZ_VALUE: + fs = 48000; + break; + case AW_PID_2049_I2SSR_96_KHZ_VALUE: + fs = 96000; + break; + case AW_PID_2049_I2SSR_192KHZ_VALUE: + fs = 192000; + break; + default: + fs = 48000; + dev_err(aw883xx->dev, + "rate can not support, use default 48k"); + break; + } + + dev_dbg(aw883xx->dev, "get i2s fs:%d", fs); + *f0_fs = fs / 8; + + aw883xx_dsp_write(aw883xx, + AW_PID_2049_DSP_REG_CFGF0_FS, *f0_fs, AW_DSP_32_DATA); +} + +static bool aw_pid_2049_check_rd_access(int reg) +{ + if (reg >= AW_PID_2049_REG_MAX) + return false; + + if (aw_pid_2049_reg_access[reg] & REG_RD_ACCESS) + return true; + else + return false; +} + +static bool aw_pid_2049_check_wr_access(int reg) +{ + if (reg >= AW_PID_2049_REG_MAX) + return false; + + if (aw_pid_2049_reg_access[reg] & REG_WR_ACCESS) + return true; + else + return false; +} + +static int aw_pid_2049_get_reg_num(void) +{ + return AW_PID_2049_REG_MAX; +} + +static int aw_pid_2049_dsp_fw_check(struct aw_device *aw_dev) +{ + struct aw_prof_desc *set_prof_desc = NULL; + struct aw_sec_data_desc *dsp_fw_desc = NULL; + uint16_t base_addr = AW_PID_2049_DSP_FW_ADDR; + uint16_t addr = base_addr; + int ret, i; + uint32_t dsp_val; + uint16_t bin_val; + + ret = aw883xx_dev_get_prof_data(aw_dev, aw_dev->cur_prof, &set_prof_desc); + if (ret < 0) + return ret; + + /*update reg*/ + dsp_fw_desc = &set_prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW]; + + for (i = 0; i < AW_FW_CHECK_PART; i++) { + ret = aw883xx_dev_dsp_read(aw_dev, addr, &dsp_val, AW_DSP_16_DATA); + if (ret < 0) { + dev_err(aw_dev->dev, "dsp read failed"); + return ret; + } + + bin_val = AW_GET_16_DATA(dsp_fw_desc->data[2 * (addr - base_addr)], + dsp_fw_desc->data[2 * (addr - base_addr) + 1]); + + if (dsp_val != bin_val) { + dev_err(aw_dev->dev, "check failed, addr[0x%x], read[0x%x] != bindata[0x%x]", + addr, dsp_val, bin_val); + return -EINVAL; + } + + addr += (dsp_fw_desc->len / 2) / AW_FW_CHECK_PART; + if ((addr - base_addr) > dsp_fw_desc->len) { + dev_err(aw_dev->dev, "check failed, addr[0x%x] too large", addr); + return -EINVAL; + } + } + + return 0; +} + +static int aw_pid_2049_set_cali_re_to_dsp(struct aw_device *aw_dev) +{ + struct aw_adpz_re_desc *adpz_re_desc = &aw_dev->adpz_re_desc; + uint32_t cali_re = 0; + int ret = 0; + + cali_re = AW_SHOW_RE_TO_DSP_RE((aw_dev->cali_desc.cali_re + + aw_dev->cali_desc.ra), adpz_re_desc->shift); + + /* set cali re to aw883xx */ + ret = aw_dev->ops.aw_dsp_write(aw_dev, + adpz_re_desc->dsp_reg, cali_re, adpz_re_desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "set cali re error"); + return ret; + } + + ret = aw883xx_dev_modify_dsp_cfg(aw_dev, adpz_re_desc->dsp_reg, + cali_re, adpz_re_desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "modify dsp cfg failed"); + return ret; + } + + return ret; + +} + +static int aw883xx_pid_2049_dev_init(struct aw883xx *aw883xx) +{ + struct aw_device *aw_pa = NULL; + + aw_pa = devm_kzalloc(aw883xx->dev, sizeof(struct aw_device), GFP_KERNEL); + if (!aw_pa) + return -ENOMEM; + + /*call aw device init func*/ + aw_pa->acf = NULL; + aw_pa->prof_info.prof_desc = NULL; + aw_pa->prof_info.count = 0; + aw_pa->prof_info.prof_type = AW_DEV_NONE_TYPE_ID; + aw_pa->channel = 0; + aw_pa->dsp_lock = &aw883xx->dsp_lock; + aw_pa->i2c = aw883xx->i2c; + aw_pa->fw_status = AW_DEV_FW_FAILED; + aw_pa->fade_step = AW_PID_2049_VOLUME_STEP_DB; + + aw_pa->chip_id = aw883xx->chip_id; + aw_pa->private_data = (void *)aw883xx; + aw_pa->dev = aw883xx->dev; + aw_pa->ops.aw_i2c_writes = regmap_raw_write; + aw_pa->ops.aw_i2c_write = regmap_write; + aw_pa->ops.aw_reg_write = regmap_write; + aw_pa->ops.aw_reg_write_bits = regmap_update_bits; + aw_pa->ops.aw_i2c_read = regmap_read; + aw_pa->ops.aw_reg_read = regmap_read; + aw_pa->ops.aw_dsp_read = aw883xx_dev_dsp_read; + aw_pa->ops.aw_dsp_write = aw883xx_dev_dsp_write; + + aw_pa->ops.aw_get_hw_volume = aw_pid_2049_get_volume; + aw_pa->ops.aw_set_hw_volume = aw_pid_2049_set_volume; + aw_pa->ops.aw_reg_val_to_db = aw_pid_2049_reg_val_to_db; + + aw_pa->ops.aw_check_rd_access = aw_pid_2049_check_rd_access; + aw_pa->ops.aw_check_wr_access = aw_pid_2049_check_wr_access; + aw_pa->ops.aw_get_reg_num = aw_pid_2049_get_reg_num; + + aw_pa->ops.aw_i2s_tx_enable = aw_pid_2049_i2s_tx_enable; + + aw_pa->ops.aw_set_cfg_f0_fs = aw_pid_2049_set_cfg_f0_fs; + aw_pa->ops.aw_dsp_fw_check = aw_pid_2049_dsp_fw_check; + + aw_pa->ops.aw_set_cali_re = aw_pid_2049_set_cali_re_to_dsp; + + aw_pa->int_desc.mask_reg = AW_PID_2049_SYSINTM_REG; + aw_pa->int_desc.mask_default = AW_PID_2049_SYSINTM_DEFAULT; + aw_pa->int_desc.int_mask = AW_PID_2049_SYSINTM_DEFAULT; + aw_pa->int_desc.st_reg = AW_PID_2049_SYSINT_REG; + aw_pa->int_desc.intst_mask = AW_PID_2049_BIT_SYSINT_CHECK; + + aw_pa->pwd_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->pwd_desc.mask = AW_PID_2049_PWDN_MASK; + aw_pa->pwd_desc.enable = AW_PID_2049_PWDN_POWER_DOWN_VALUE; + aw_pa->pwd_desc.disable = AW_PID_2049_PWDN_WORKING_VALUE; + + aw_pa->mute_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->mute_desc.mask = AW_PID_2049_HMUTE_MASK; + aw_pa->mute_desc.enable = AW_PID_2049_HMUTE_ENABLE_VALUE; + aw_pa->mute_desc.disable = AW_PID_2049_HMUTE_DISABLE_VALUE; + + aw_pa->vcalb_desc.vcalb_dsp_reg = AW_PID_2049_DSP_REG_VCALB; + aw_pa->vcalb_desc.data_type = AW_DSP_16_DATA; + aw_pa->vcalb_desc.vcal_factor = AW_PID_2049_VCAL_FACTOR; + aw_pa->vcalb_desc.cabl_base_value = AW_PID_2049_CABL_BASE_VALUE; + aw_pa->vcalb_desc.vscal_factor = AW_PID_2049_VSCAL_FACTOR; + aw_pa->vcalb_desc.iscal_factor = AW_PID_2049_ISCAL_FACTOR; + + aw_pa->vcalb_desc.vcalb_adj_shift = AW_PID_2049_VCALB_ADJ_FACTOR; + + aw_pa->vcalb_desc.icalk_value_factor = AW_PID_2049_ICABLK_FACTOR; + aw_pa->vcalb_desc.icalk_reg = AW_PID_2049_EFRM2_REG; + aw_pa->vcalb_desc.icalk_reg_mask = AW_PID_2049_EF_ISN_GESLP_MASK; + aw_pa->vcalb_desc.icalk_sign_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_MASK; + aw_pa->vcalb_desc.icalk_neg_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_NEG; + + aw_pa->vcalb_desc.vcalk_reg = AW_PID_2049_EFRH_REG; + aw_pa->vcalb_desc.vcalk_reg_mask = AW_PID_2049_EF_VSN_GESLP_MASK; + aw_pa->vcalb_desc.vcalk_sign_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_MASK; + aw_pa->vcalb_desc.vcalk_neg_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_NEG; + aw_pa->vcalb_desc.vcalk_value_factor = AW_PID_2049_VCABLK_FACTOR; + aw_pa->vcalb_desc.vcalk_shift = AW_PID_2049_EF_VSENSE_GAIN_SHIFT; + + aw_pa->vcalb_desc.vcalb_vsense_reg = AW_PID_2049_I2SCFG3_REG; + aw_pa->vcalb_desc.vcalk_vdsel_mask = AW_PID_2049_VDSEL_MASK; + aw_pa->vcalb_desc.vcalk_value_factor_vsense_in = AW_PID_2049_VCABLK_FACTOR_DAC; + aw_pa->vcalb_desc.vscal_factor_vsense_in = AW_PID_2049_VSCAL_FACTOR_DAC; + aw_pa->vcalb_desc.vcalk_dac_shift = AW_PID_2049_EF_DAC_GESLP_SHIFT; + aw_pa->vcalb_desc.vcalk_dac_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_MASK; + aw_pa->vcalb_desc.vcalk_dac_neg_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_NEG; + + aw_pa->sysst_desc.reg = AW_PID_2049_SYSST_REG; + aw_pa->sysst_desc.st_check = AW_PID_2049_BIT_SYSST_CHECK; + aw_pa->sysst_desc.st_mask = AW_PID_2049_BIT_SYSST_CHECK_MASK; + aw_pa->sysst_desc.pll_check = AW_PID_2049_BIT_PLL_CHECK; + aw_pa->sysst_desc.dsp_check = AW_PID_2049_DSPS_NORMAL_VALUE; + aw_pa->sysst_desc.dsp_mask = AW_PID_2049_DSPS_MASK; + + aw_pa->profctrl_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->profctrl_desc.mask = AW_PID_2049_RCV_MODE_MASK; + aw_pa->profctrl_desc.rcv_mode_val = AW_PID_2049_RCV_MODE_RECEIVER_VALUE; + + aw_pa->volume_desc.reg = AW_PID_2049_SYSCTRL2_REG; + aw_pa->volume_desc.mask = AW_PID_2049_VOL_MASK; + aw_pa->volume_desc.shift = AW_PID_2049_VOL_START_BIT; + aw_pa->volume_desc.mute_volume = AW_PID_2049_MUTE_VOL; + aw_pa->volume_desc.max_volume = AW_PID_2049_VOL_DEFAULT_VALUE; + aw_pa->volume_desc.ctl_volume = AW_PID_2049_VOL_DEFAULT_VALUE; + + aw_pa->dsp_en_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->dsp_en_desc.mask = AW_PID_2049_DSPBY_MASK; + aw_pa->dsp_en_desc.enable = AW_PID_2049_DSPBY_WORKING_VALUE; + aw_pa->dsp_en_desc.disable = AW_PID_2049_DSPBY_BYPASS_VALUE; + + aw_pa->memclk_desc.reg = AW_PID_2049_DBGCTRL_REG; + aw_pa->memclk_desc.mask = AW_PID_2049_MEM_CLKSEL_MASK; + aw_pa->memclk_desc.mcu_hclk = AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE; + aw_pa->memclk_desc.osc_clk = AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE; + + aw_pa->watch_dog_desc.reg = AW_PID_2049_WDT_REG; + aw_pa->watch_dog_desc.mask = AW_PID_2049_WDT_CNT_MASK; + + aw_pa->dsp_mem_desc.dsp_madd_reg = AW_PID_2049_DSPMADD_REG; + aw_pa->dsp_mem_desc.dsp_mdat_reg = AW_PID_2049_DSPMDAT_REG; + aw_pa->dsp_mem_desc.dsp_cfg_base_addr = AW_PID_2049_DSP_CFG_ADDR; + aw_pa->dsp_mem_desc.dsp_fw_base_addr = AW_PID_2049_DSP_FW_ADDR; + + aw_pa->voltage_desc.reg = AW_PID_2049_VBAT_REG; + aw_pa->voltage_desc.vbat_range = AW_PID_2049_VBAT_RANGE; + aw_pa->voltage_desc.int_bit = AW_PID_2049_INT_10BIT; + + aw_pa->temp_desc.reg = AW_PID_2049_TEMP_REG; + aw_pa->temp_desc.sign_mask = AW_PID_2049_TEMP_SIGN_MASK; + aw_pa->temp_desc.neg_mask = AW_PID_2049_TEMP_NEG_MASK; + + aw_pa->vmax_desc.dsp_reg = AW_PID_2049_DSP_REG_VMAX; + aw_pa->vmax_desc.data_type = AW_DSP_16_DATA; + + aw_pa->ipeak_desc.reg = AW_PID_2049_SYSCTRL2_REG; + aw_pa->ipeak_desc.mask = AW_PID_2049_BST_IPEAK_MASK; + + aw_pa->soft_rst.reg = AW_PID_2049_ID_REG; + aw_pa->soft_rst.reg_value = AW_PID_2049_SOFT_RESET_VALUE; + + aw_pa->dsp_vol_desc.reg = AW_PID_2049_DSPCFG_REG; + aw_pa->dsp_vol_desc.mask = AW_PID_2049_DSP_VOL_MASK; + aw_pa->dsp_vol_desc.mute_st = AW_PID_2049_DSP_VOL_MUTE; + aw_pa->dsp_vol_desc.noise_st = AW_PID_2049_DSP_VOL_NOISE_ST; + + aw_pa->amppd_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->amppd_desc.mask = AW_PID_2049_AMPPD_MASK; + aw_pa->amppd_desc.enable = AW_PID_2049_AMPPD_POWER_DOWN_VALUE; + aw_pa->amppd_desc.disable = AW_PID_2049_AMPPD_WORKING_VALUE; + + aw_pa->spkr_temp_desc.reg = AW_PID_2049_ASR2_REG; + + /*32-bit data types need bypass dsp*/ + aw_pa->ra_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RA; + aw_pa->ra_desc.data_type = AW_DSP_32_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->cali_cfg_desc.actampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH; + aw_pa->cali_cfg_desc.actampth_data_type = AW_DSP_32_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->cali_cfg_desc.noiseampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH; + aw_pa->cali_cfg_desc.noiseampth_data_type = AW_DSP_32_DATA; + + aw_pa->cali_cfg_desc.ustepn_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN; + aw_pa->cali_cfg_desc.ustepn_data_type = AW_DSP_16_DATA; + + aw_pa->cali_cfg_desc.alphan_reg = AW_PID_2049_DSP_REG_CFG_RE_ALPHA; + aw_pa->cali_cfg_desc.alphan_data_type = AW_DSP_16_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->adpz_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RE; + aw_pa->adpz_re_desc.data_type = AW_DSP_32_DATA; + aw_pa->adpz_re_desc.shift = AW_PID_2049_DSP_RE_SHIFT; + + aw_pa->t0_desc.dsp_reg = AW_PID_2049_DSP_CFG_ADPZ_T0; + aw_pa->t0_desc.data_type = AW_DSP_16_DATA; + aw_pa->t0_desc.coilalpha_reg = AW_PID_2049_DSP_CFG_ADPZ_COILALPHA; + aw_pa->t0_desc.coil_type = AW_DSP_16_DATA; + + aw_pa->ste_re_desc.shift = AW_PID_2049_DSP_REG_CALRE_SHIFT; + aw_pa->ste_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CALRE; + aw_pa->ste_re_desc.data_type = AW_DSP_16_DATA; + + aw_pa->noise_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG; + aw_pa->noise_desc.data_type = AW_DSP_16_DATA; + aw_pa->noise_desc.mask = AW_PID_2049_DSP_REG_NOISE_MASK; + + aw_pa->f0_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_F0; + aw_pa->f0_desc.shift = AW_PID_2049_DSP_F0_SHIFT; + aw_pa->f0_desc.data_type = AW_DSP_16_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->cfgf0_fs_desc.dsp_reg = AW_PID_2049_DSP_REG_CFGF0_FS; + aw_pa->cfgf0_fs_desc.data_type = AW_DSP_32_DATA; + + aw_pa->q_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_Q; + aw_pa->q_desc.shift = AW_PID_2049_DSP_Q_SHIFT; + aw_pa->q_desc.data_type = AW_DSP_16_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->dsp_crc_desc.dsp_reg = AW_PID_2049_DSP_REG_CRC_ADDR; + aw_pa->dsp_crc_desc.data_type = AW_DSP_32_DATA; + + aw_pa->dsp_crc_desc.ctl_reg = AW_PID_2049_HAGCCFG7_REG; + aw_pa->dsp_crc_desc.ctl_mask = AW_PID_2049_AGC_DSP_CTL_MASK; + aw_pa->dsp_crc_desc.ctl_enable = AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE; + aw_pa->dsp_crc_desc.ctl_disable = AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE; + + aw_pa->cco_mux_desc.reg = AW_PID_2049_PLLCTRL1_REG; + aw_pa->cco_mux_desc.mask = AW_PID_2049_CCO_MUX_MASK; + aw_pa->cco_mux_desc.divider = AW_PID_2049_CCO_MUX_DIVIDED_VALUE; + aw_pa->cco_mux_desc.bypass = AW_PID_2049_CCO_MUX_BYPASS_VALUE; + + /*hw monitor temp reg*/ + aw_pa->hw_temp_desc.dsp_reg = AW_PID_2049_DSP_REG_TEMP_ADDR; + aw_pa->hw_temp_desc.data_type = AW_DSP_16_DATA; + + aw_pa->chansel_desc.rxchan_reg = AW_PID_2049_I2SCTRL_REG; + aw_pa->chansel_desc.rxchan_mask = AW_PID_2049_CHSEL_MASK; + aw_pa->chansel_desc.txchan_reg = AW_PID_2049_I2SCFG1_REG; + aw_pa->chansel_desc.txchan_mask = AW_PID_2049_I2SCHS_MASK; + + aw_pa->chansel_desc.rx_left = AW_PID_2049_CHSEL_LEFT_VALUE; + aw_pa->chansel_desc.rx_right = AW_PID_2049_CHSEL_RIGHT_VALUE; + aw_pa->chansel_desc.tx_left = AW_PID_2049_I2SCHS_LEFT_VALUE; + aw_pa->chansel_desc.tx_right = AW_PID_2049_I2SCHS_RIGHT_VALUE; + + aw_pa->tx_en_desc.tx_en_mask = AW_PID_2049_I2STXEN_MASK; + aw_pa->tx_en_desc.tx_disable = AW_PID_2049_I2STXEN_DISABLE_VALUE; + + aw_pa->cali_delay_desc.dsp_reg = AW_PID_2049_DSP_CALI_F0_DELAY; + aw_pa->cali_delay_desc.data_type = AW_DSP_16_DATA; + + aw_pa->dsp_st_desc.dsp_reg_s1 = AW_PID_2049_DSP_ST_S1; + aw_pa->dsp_st_desc.dsp_reg_e1 = AW_PID_2049_DSP_ST_E1; + aw_pa->dsp_st_desc.dsp_reg_s2 = AW_PID_2049_DSP_ST_S2; + aw_pa->dsp_st_desc.dsp_reg_e2 = AW_PID_2049_DSP_ST_E2; + + aw883xx_device_probe(aw_pa); + + aw883xx->aw_pa = aw_pa; + + return 0; +} + +int aw883xx_init(struct aw883xx *aw883xx) +{ + int ret = 0; + + switch (aw883xx->chip_id) { + case AW883XX_PID_2049: + ret = aw883xx_pid_2049_dev_init(aw883xx); + break; + default: + ret = -EINVAL; + dev_err(aw883xx->dev, "unsupported device"); + break; + } + return ret; +} + diff --git a/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h new file mode 100644 index 000000000000..e7c4703d1627 --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h @@ -0,0 +1,2300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_PID_2049_REG_H__ +#define __AW883XX_PID_2049_REG_H__ + +#define AW_PID_2049_ID_REG (0x00) +#define AW_PID_2049_SYSST_REG (0x01) +#define AW_PID_2049_SYSINT_REG (0x02) +#define AW_PID_2049_SYSINTM_REG (0x03) +#define AW_PID_2049_SYSCTRL_REG (0x04) +#define AW_PID_2049_SYSCTRL2_REG (0x05) +#define AW_PID_2049_I2SCTRL_REG (0x06) +#define AW_PID_2049_I2SCFG1_REG (0x07) +#define AW_PID_2049_I2SCFG2_REG (0x08) +#define AW_PID_2049_HAGCCFG1_REG (0x09) +#define AW_PID_2049_HAGCCFG2_REG (0x0A) +#define AW_PID_2049_HAGCCFG3_REG (0x0B) +#define AW_PID_2049_HAGCCFG4_REG (0x0C) +#define AW_PID_2049_HAGCCFG5_REG (0x0D) +#define AW_PID_2049_HAGCCFG6_REG (0x0E) +#define AW_PID_2049_HAGCCFG7_REG (0x0F) +#define AW_PID_2049_MPDCFG_REG (0x10) +#define AW_PID_2049_PWMCTRL_REG (0x11) +#define AW_PID_2049_I2SCFG3_REG (0x12) +#define AW_PID_2049_DBGCTRL_REG (0x13) +#define AW_PID_2049_HAGCST_REG (0x20) +#define AW_PID_2049_VBAT_REG (0x21) +#define AW_PID_2049_TEMP_REG (0x22) +#define AW_PID_2049_PVDD_REG (0x23) +#define AW_PID_2049_ISNDAT_REG (0x24) +#define AW_PID_2049_VSNDAT_REG (0x25) +#define AW_PID_2049_I2SINT_REG (0x26) +#define AW_PID_2049_I2SCAPCNT_REG (0x27) +#define AW_PID_2049_ANASTA1_REG (0x28) +#define AW_PID_2049_ANASTA2_REG (0x29) +#define AW_PID_2049_ANASTA3_REG (0x2A) +#define AW_PID_2049_ANASTA4_REG (0x2B) +#define AW_PID_2049_TESTDET_REG (0x2C) +#define AW_PID_2049_TESTIN_REG (0x38) +#define AW_PID_2049_TESTOUT_REG (0x39) +#define AW_PID_2049_DSPMADD_REG (0x40) +#define AW_PID_2049_DSPMDAT_REG (0x41) +#define AW_PID_2049_WDT_REG (0x42) +#define AW_PID_2049_ACR1_REG (0x43) +#define AW_PID_2049_ACR2_REG (0x44) +#define AW_PID_2049_ASR1_REG (0x45) +#define AW_PID_2049_ASR2_REG (0x46) +#define AW_PID_2049_DSPCFG_REG (0x47) +#define AW_PID_2049_ASR3_REG (0x48) +#define AW_PID_2049_ASR4_REG (0x49) +#define AW_PID_2049_VSNCTRL1_REG (0x50) +#define AW_PID_2049_ISNCTRL1_REG (0x51) +#define AW_PID_2049_PLLCTRL1_REG (0x52) +#define AW_PID_2049_PLLCTRL2_REG (0x53) +#define AW_PID_2049_PLLCTRL3_REG (0x54) +#define AW_PID_2049_CDACTRL1_REG (0x55) +#define AW_PID_2049_CDACTRL2_REG (0x56) +#define AW_PID_2049_SADCCTRL1_REG (0x57) +#define AW_PID_2049_SADCCTRL2_REG (0x58) +#define AW_PID_2049_CPCTRL1_REG (0x59) +#define AW_PID_2049_BSTCTRL1_REG (0x60) +#define AW_PID_2049_BSTCTRL2_REG (0x61) +#define AW_PID_2049_BSTCTRL3_REG (0x62) +#define AW_PID_2049_BSTCTRL4_REG (0x63) +#define AW_PID_2049_BSTCTRL5_REG (0x64) +#define AW_PID_2049_BSTCTRL6_REG (0x65) +#define AW_PID_2049_BSTCTRL7_REG (0x66) +#define AW_PID_2049_DSMCFG1_REG (0x67) +#define AW_PID_2049_DSMCFG2_REG (0x68) +#define AW_PID_2049_DSMCFG3_REG (0x69) +#define AW_PID_2049_DSMCFG4_REG (0x6A) +#define AW_PID_2049_DSMCFG5_REG (0x6B) +#define AW_PID_2049_DSMCFG6_REG (0x6C) +#define AW_PID_2049_DSMCFG7_REG (0x6D) +#define AW_PID_2049_DSMCFG8_REG (0x6E) +#define AW_PID_2049_TESTCTRL1_REG (0x70) +#define AW_PID_2049_TESTCTRL2_REG (0x71) +#define AW_PID_2049_EFCTRL1_REG (0x72) +#define AW_PID_2049_EFCTRL2_REG (0x73) +#define AW_PID_2049_EFWH_REG (0x74) +#define AW_PID_2049_EFWM2_REG (0x75) +#define AW_PID_2049_EFWM1_REG (0x76) +#define AW_PID_2049_EFWL_REG (0x77) +#define AW_PID_2049_EFRH_REG (0x78) +#define AW_PID_2049_EFRM2_REG (0x79) +#define AW_PID_2049_EFRM1_REG (0x7A) +#define AW_PID_2049_EFRL_REG (0x7B) +#define AW_PID_2049_TM_REG (0x7C) + +/* + * Register Access + */ +enum aw883xx_id { + AW883XX_PID_2049 = 0x2049, +}; + +#define AW_PID_2049_REG_MAX (0x7D) + +#define REG_NONE_ACCESS (0) +#define REG_RD_ACCESS (1 << 0) +#define REG_WR_ACCESS (1 << 1) + +#define AW_PID_2049_VOLUME_STEP_DB (6 * 8) + +/* detail information of registers begin */ +/* ID (0x00) detail */ +/* IDCODE bit 15:0 (ID 0x00) */ +#define AW_PID_2049_IDCODE_START_BIT (0) +#define AW_PID_2049_IDCODE_BITS_LEN (16) +#define AW_PID_2049_IDCODE_MASK \ + (~(((1<<AW_PID_2049_IDCODE_BITS_LEN)-1) << AW_PID_2049_IDCODE_START_BIT)) + +#define AW_PID_2049_IDCODE_DEFAULT_VALUE (0x2049) +#define AW_PID_2049_IDCODE_DEFAULT \ + (AW_PID_2049_IDCODE_DEFAULT_VALUE << AW_PID_2049_IDCODE_START_BIT) + +#define AW_PID_2049_SOFT_RESET_VALUE (0x55aa) + +/* default value of ID (0x00) */ +/* #define AW_PID_2049_ID_DEFAULT (0x2049) */ + +/* SYSST (0x01) detail */ +/* OVP2S bit 15 (SYSST 0x01) */ +#define AW_PID_2049_OVP2S_START_BIT (15) +#define AW_PID_2049_OVP2S_BITS_LEN (1) +#define AW_PID_2049_OVP2S_MASK \ + (~(((1<<AW_PID_2049_OVP2S_BITS_LEN)-1) << AW_PID_2049_OVP2S_START_BIT)) + +#define AW_PID_2049_OVP2S_NORMAL (0) +#define AW_PID_2049_OVP2S_NORMAL_VALUE \ + (AW_PID_2049_OVP2S_NORMAL << AW_PID_2049_OVP2S_START_BIT) + +#define AW_PID_2049_OVP2S_OVP (1) +#define AW_PID_2049_OVP2S_OVP_VALUE \ + (AW_PID_2049_OVP2S_OVP << AW_PID_2049_OVP2S_START_BIT) + +#define AW_PID_2049_OVP2S_DEFAULT_VALUE (0) +#define AW_PID_2049_OVP2S_DEFAULT \ + (AW_PID_2049_OVP2S_DEFAULT_VALUE << AW_PID_2049_OVP2S_START_BIT) + +/* UVLS bit 14 (SYSST 0x01) */ +#define AW_PID_2049_UVLS_START_BIT (14) +#define AW_PID_2049_UVLS_BITS_LEN (1) +#define AW_PID_2049_UVLS_MASK \ + (~(((1<<AW_PID_2049_UVLS_BITS_LEN)-1) << AW_PID_2049_UVLS_START_BIT)) + +#define AW_PID_2049_UVLS_NORMAL (0) +#define AW_PID_2049_UVLS_NORMAL_VALUE \ + (AW_PID_2049_UVLS_NORMAL << AW_PID_2049_UVLS_START_BIT) + +#define AW_PID_2049_UVLS_UVLO (1) +#define AW_PID_2049_UVLS_UVLO_VALUE \ + (AW_PID_2049_UVLS_UVLO << AW_PID_2049_UVLS_START_BIT) + +#define AW_PID_2049_UVLS_DEFAULT_VALUE (0) +#define AW_PID_2049_UVLS_DEFAULT \ + (AW_PID_2049_UVLS_DEFAULT_VALUE << AW_PID_2049_UVLS_START_BIT) + +/* ADPS bit 13 (SYSST 0x01) */ +#define AW_PID_2049_ADPS_START_BIT (13) +#define AW_PID_2049_ADPS_BITS_LEN (1) +#define AW_PID_2049_ADPS_MASK \ + (~(((1<<AW_PID_2049_ADPS_BITS_LEN)-1) << AW_PID_2049_ADPS_START_BIT)) + +#define AW_PID_2049_ADPS_TRANSPARENT (0) +#define AW_PID_2049_ADPS_TRANSPARENT_VALUE \ + (AW_PID_2049_ADPS_TRANSPARENT << AW_PID_2049_ADPS_START_BIT) + +#define AW_PID_2049_ADPS_BOOST (1) +#define AW_PID_2049_ADPS_BOOST_VALUE \ + (AW_PID_2049_ADPS_BOOST << AW_PID_2049_ADPS_START_BIT) + +#define AW_PID_2049_ADPS_DEFAULT_VALUE (0) +#define AW_PID_2049_ADPS_DEFAULT \ + (AW_PID_2049_ADPS_DEFAULT_VALUE << AW_PID_2049_ADPS_START_BIT) + +/* DSPS bit 12 (SYSST 0x01) */ +#define AW_PID_2049_DSPS_START_BIT (12) +#define AW_PID_2049_DSPS_BITS_LEN (1) +#define AW_PID_2049_DSPS_MASK \ + (~(((1<<AW_PID_2049_DSPS_BITS_LEN)-1) << AW_PID_2049_DSPS_START_BIT)) + +#define AW_PID_2049_DSPS_NORMAL (0) +#define AW_PID_2049_DSPS_NORMAL_VALUE \ + (AW_PID_2049_DSPS_NORMAL << AW_PID_2049_DSPS_START_BIT) + +#define AW_PID_2049_DSPS_DSP_STABLE (1) +#define AW_PID_2049_DSPS_DSP_STABLE_VALUE \ + (AW_PID_2049_DSPS_DSP_STABLE << AW_PID_2049_DSPS_START_BIT) + +#define AW_PID_2049_DSPS_DEFAULT_VALUE (0) +#define AW_PID_2049_DSPS_DEFAULT \ + (AW_PID_2049_DSPS_DEFAULT_VALUE << AW_PID_2049_DSPS_START_BIT) + +/* BSTOCS bit 11 (SYSST 0x01) */ +#define AW_PID_2049_BSTOCS_START_BIT (11) +#define AW_PID_2049_BSTOCS_BITS_LEN (1) +#define AW_PID_2049_BSTOCS_MASK \ + (~(((1<<AW_PID_2049_BSTOCS_BITS_LEN)-1) << AW_PID_2049_BSTOCS_START_BIT)) + +#define AW_PID_2049_BSTOCS_NORMAL (0) +#define AW_PID_2049_BSTOCS_NORMAL_VALUE \ + (AW_PID_2049_BSTOCS_NORMAL << AW_PID_2049_BSTOCS_START_BIT) + +#define AW_PID_2049_BSTOCS_OVER_CURRENT (1) +#define AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE \ + (AW_PID_2049_BSTOCS_OVER_CURRENT << AW_PID_2049_BSTOCS_START_BIT) + +#define AW_PID_2049_BSTOCS_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTOCS_DEFAULT \ + (AW_PID_2049_BSTOCS_DEFAULT_VALUE << AW_PID_2049_BSTOCS_START_BIT) + +/* OVPS bit 10 (SYSST 0x01) */ +#define AW_PID_2049_OVPS_START_BIT (10) +#define AW_PID_2049_OVPS_BITS_LEN (1) +#define AW_PID_2049_OVPS_MASK \ + (~(((1<<AW_PID_2049_OVPS_BITS_LEN)-1) << AW_PID_2049_OVPS_START_BIT)) + +#define AW_PID_2049_OVPS_NORMAL (0) +#define AW_PID_2049_OVPS_NORMAL_VALUE \ + (AW_PID_2049_OVPS_NORMAL << AW_PID_2049_OVPS_START_BIT) + +#define AW_PID_2049_OVPS_OVP (1) +#define AW_PID_2049_OVPS_OVP_VALUE \ + (AW_PID_2049_OVPS_OVP << AW_PID_2049_OVPS_START_BIT) + +#define AW_PID_2049_OVPS_DEFAULT_VALUE (0) +#define AW_PID_2049_OVPS_DEFAULT \ + (AW_PID_2049_OVPS_DEFAULT_VALUE << AW_PID_2049_OVPS_START_BIT) + +/* BSTS bit 9 (SYSST 0x01) */ +#define AW_PID_2049_BSTS_START_BIT (9) +#define AW_PID_2049_BSTS_BITS_LEN (1) +#define AW_PID_2049_BSTS_MASK \ + (~(((1<<AW_PID_2049_BSTS_BITS_LEN)-1) << AW_PID_2049_BSTS_START_BIT)) + +#define AW_PID_2049_BSTS_NOT_FINISHED (0) +#define AW_PID_2049_BSTS_NOT_FINISHED_VALUE \ + (AW_PID_2049_BSTS_NOT_FINISHED << AW_PID_2049_BSTS_START_BIT) + +#define AW_PID_2049_BSTS_FINISHED (1) +#define AW_PID_2049_BSTS_FINISHED_VALUE \ + (AW_PID_2049_BSTS_FINISHED << AW_PID_2049_BSTS_START_BIT) + +#define AW_PID_2049_BSTS_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTS_DEFAULT \ + (AW_PID_2049_BSTS_DEFAULT_VALUE << AW_PID_2049_BSTS_START_BIT) + +/* SWS bit 8 (SYSST 0x01) */ +#define AW_PID_2049_SWS_START_BIT (8) +#define AW_PID_2049_SWS_BITS_LEN (1) +#define AW_PID_2049_SWS_MASK \ + (~(((1<<AW_PID_2049_SWS_BITS_LEN)-1) << AW_PID_2049_SWS_START_BIT)) + +#define AW_PID_2049_SWS_NOT_SWITCHING (0) +#define AW_PID_2049_SWS_NOT_SWITCHING_VALUE \ + (AW_PID_2049_SWS_NOT_SWITCHING << AW_PID_2049_SWS_START_BIT) + +#define AW_PID_2049_SWS_SWITCHING (1) +#define AW_PID_2049_SWS_SWITCHING_VALUE \ + (AW_PID_2049_SWS_SWITCHING << AW_PID_2049_SWS_START_BIT) + +#define AW_PID_2049_SWS_DEFAULT_VALUE (0) +#define AW_PID_2049_SWS_DEFAULT \ + (AW_PID_2049_SWS_DEFAULT_VALUE << AW_PID_2049_SWS_START_BIT) + +/* CLIPS bit 7 (SYSST 0x01) */ +#define AW_PID_2049_CLIPS_START_BIT (7) +#define AW_PID_2049_CLIPS_BITS_LEN (1) +#define AW_PID_2049_CLIPS_MASK \ + (~(((1<<AW_PID_2049_CLIPS_BITS_LEN)-1) << AW_PID_2049_CLIPS_START_BIT)) + +#define AW_PID_2049_CLIPS_NOT_CLIPPING (0) +#define AW_PID_2049_CLIPS_NOT_CLIPPING_VALUE \ + (AW_PID_2049_CLIPS_NOT_CLIPPING << AW_PID_2049_CLIPS_START_BIT) + +#define AW_PID_2049_CLIPS_CLIPPING (1) +#define AW_PID_2049_CLIPS_CLIPPING_VALUE \ + (AW_PID_2049_CLIPS_CLIPPING << AW_PID_2049_CLIPS_START_BIT) + +#define AW_PID_2049_CLIPS_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIPS_DEFAULT \ + (AW_PID_2049_CLIPS_DEFAULT_VALUE << AW_PID_2049_CLIPS_START_BIT) + +/* WDS bit 6 (SYSST 0x01) */ +#define AW_PID_2049_WDS_START_BIT (6) +#define AW_PID_2049_WDS_BITS_LEN (1) +#define AW_PID_2049_WDS_MASK \ + (~(((1<<AW_PID_2049_WDS_BITS_LEN)-1) << AW_PID_2049_WDS_START_BIT)) + +#define AW_PID_2049_WDS_NORMAL (0) +#define AW_PID_2049_WDS_NORMAL_VALUE \ + (AW_PID_2049_WDS_NORMAL << AW_PID_2049_WDS_START_BIT) + +#define AW_PID_2049_WDS_ABNORMAL (1) +#define AW_PID_2049_WDS_ABNORMAL_VALUE \ + (AW_PID_2049_WDS_ABNORMAL << AW_PID_2049_WDS_START_BIT) + +#define AW_PID_2049_WDS_DEFAULT_VALUE (0) +#define AW_PID_2049_WDS_DEFAULT \ + (AW_PID_2049_WDS_DEFAULT_VALUE << AW_PID_2049_WDS_START_BIT) + +/* NOCLKS bit 5 (SYSST 0x01) */ +#define AW_PID_2049_NOCLKS_START_BIT (5) +#define AW_PID_2049_NOCLKS_BITS_LEN (1) +#define AW_PID_2049_NOCLKS_MASK \ + (~(((1<<AW_PID_2049_NOCLKS_BITS_LEN)-1) << AW_PID_2049_NOCLKS_START_BIT)) + +#define AW_PID_2049_NOCLKS_CLOCK_OK (0) +#define AW_PID_2049_NOCLKS_CLOCK_OK_VALUE \ + (AW_PID_2049_NOCLKS_CLOCK_OK << AW_PID_2049_NOCLKS_START_BIT) + +#define AW_PID_2049_NOCLKS_NO_CLOCK (1) +#define AW_PID_2049_NOCLKS_NO_CLOCK_VALUE \ + (AW_PID_2049_NOCLKS_NO_CLOCK << AW_PID_2049_NOCLKS_START_BIT) + +#define AW_PID_2049_NOCLKS_DEFAULT_VALUE (0) +#define AW_PID_2049_NOCLKS_DEFAULT \ + (AW_PID_2049_NOCLKS_DEFAULT_VALUE << AW_PID_2049_NOCLKS_START_BIT) + +/* CLKS bit 4 (SYSST 0x01) */ +#define AW_PID_2049_CLKS_START_BIT (4) +#define AW_PID_2049_CLKS_BITS_LEN (1) +#define AW_PID_2049_CLKS_MASK \ + (~(((1<<AW_PID_2049_CLKS_BITS_LEN)-1) << AW_PID_2049_CLKS_START_BIT)) + +#define AW_PID_2049_CLKS_NOT_STABLE (0) +#define AW_PID_2049_CLKS_NOT_STABLE_VALUE \ + (AW_PID_2049_CLKS_NOT_STABLE << AW_PID_2049_CLKS_START_BIT) + +#define AW_PID_2049_CLKS_STABLE (1) +#define AW_PID_2049_CLKS_STABLE_VALUE \ + (AW_PID_2049_CLKS_STABLE << AW_PID_2049_CLKS_START_BIT) + +#define AW_PID_2049_CLKS_DEFAULT_VALUE (0) +#define AW_PID_2049_CLKS_DEFAULT \ + (AW_PID_2049_CLKS_DEFAULT_VALUE << AW_PID_2049_CLKS_START_BIT) + +/* OCDS bit 3 (SYSST 0x01) */ +#define AW_PID_2049_OCDS_START_BIT (3) +#define AW_PID_2049_OCDS_BITS_LEN (1) +#define AW_PID_2049_OCDS_MASK \ + (~(((1<<AW_PID_2049_OCDS_BITS_LEN)-1) << AW_PID_2049_OCDS_START_BIT)) + +#define AW_PID_2049_OCDS_NORAML (0) +#define AW_PID_2049_OCDS_NORAML_VALUE \ + (AW_PID_2049_OCDS_NORAML << AW_PID_2049_OCDS_START_BIT) + +#define AW_PID_2049_OCDS_OC (1) +#define AW_PID_2049_OCDS_OC_VALUE \ + (AW_PID_2049_OCDS_OC << AW_PID_2049_OCDS_START_BIT) + +#define AW_PID_2049_OCDS_DEFAULT_VALUE (0) +#define AW_PID_2049_OCDS_DEFAULT \ + (AW_PID_2049_OCDS_DEFAULT_VALUE << AW_PID_2049_OCDS_START_BIT) + +/* CLIP_PRES bit 2 (SYSST 0x01) */ +#define AW_PID_2049_CLIP_PRES_START_BIT (2) +#define AW_PID_2049_CLIP_PRES_BITS_LEN (1) +#define AW_PID_2049_CLIP_PRES_MASK \ + (~(((1<<AW_PID_2049_CLIP_PRES_BITS_LEN)-1) << AW_PID_2049_CLIP_PRES_START_BIT)) + +#define AW_PID_2049_CLIP_PRES_NOT_CLIPPING (0) +#define AW_PID_2049_CLIP_PRES_NOT_CLIPPING_VALUE \ + (AW_PID_2049_CLIP_PRES_NOT_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT) + +#define AW_PID_2049_CLIP_PRES_CLIPPING (1) +#define AW_PID_2049_CLIP_PRES_CLIPPING_VALUE \ + (AW_PID_2049_CLIP_PRES_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT) + +#define AW_PID_2049_CLIP_PRES_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIP_PRES_DEFAULT \ + (AW_PID_2049_CLIP_PRES_DEFAULT_VALUE << AW_PID_2049_CLIP_PRES_START_BIT) + +/* OTHS bit 1 (SYSST 0x01) */ +#define AW_PID_2049_OTHS_START_BIT (1) +#define AW_PID_2049_OTHS_BITS_LEN (1) +#define AW_PID_2049_OTHS_MASK \ + (~(((1<<AW_PID_2049_OTHS_BITS_LEN)-1) << AW_PID_2049_OTHS_START_BIT)) + +#define AW_PID_2049_OTHS_NORMAL (0) +#define AW_PID_2049_OTHS_NORMAL_VALUE \ + (AW_PID_2049_OTHS_NORMAL << AW_PID_2049_OTHS_START_BIT) + +#define AW_PID_2049_OTHS_OT (1) +#define AW_PID_2049_OTHS_OT_VALUE \ + (AW_PID_2049_OTHS_OT << AW_PID_2049_OTHS_START_BIT) + +#define AW_PID_2049_OTHS_DEFAULT_VALUE (0) +#define AW_PID_2049_OTHS_DEFAULT \ + (AW_PID_2049_OTHS_DEFAULT_VALUE << AW_PID_2049_OTHS_START_BIT) + +/* PLLS bit 0 (SYSST 0x01) */ +#define AW_PID_2049_PLLS_START_BIT (0) +#define AW_PID_2049_PLLS_BITS_LEN (1) +#define AW_PID_2049_PLLS_MASK \ + (~(((1<<AW_PID_2049_PLLS_BITS_LEN)-1) << AW_PID_2049_PLLS_START_BIT)) + +#define AW_PID_2049_PLLS_UNLOCKED (0) +#define AW_PID_2049_PLLS_UNLOCKED_VALUE \ + (AW_PID_2049_PLLS_UNLOCKED << AW_PID_2049_PLLS_START_BIT) + +#define AW_PID_2049_PLLS_LOCKED (1) +#define AW_PID_2049_PLLS_LOCKED_VALUE \ + (AW_PID_2049_PLLS_LOCKED << AW_PID_2049_PLLS_START_BIT) + +#define AW_PID_2049_PLLS_DEFAULT_VALUE (0) +#define AW_PID_2049_PLLS_DEFAULT \ + (AW_PID_2049_PLLS_DEFAULT_VALUE << AW_PID_2049_PLLS_START_BIT) + + + +#define AW_PID_2049_BIT_PLL_CHECK \ + (AW_PID_2049_CLKS_STABLE_VALUE | \ + AW_PID_2049_PLLS_LOCKED_VALUE) + + +#define AW_PID_2049_BIT_SYSST_CHECK_MASK \ + (~(AW_PID_2049_UVLS_NORMAL_VALUE | \ + AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE | \ + AW_PID_2049_BSTS_FINISHED_VALUE | \ + AW_PID_2049_SWS_SWITCHING_VALUE | \ + AW_PID_2049_NOCLKS_NO_CLOCK_VALUE | \ + AW_PID_2049_CLKS_STABLE_VALUE | \ + AW_PID_2049_OCDS_OC_VALUE | \ + AW_PID_2049_OTHS_OT_VALUE | \ + AW_PID_2049_PLLS_LOCKED_VALUE)) + +#define AW_PID_2049_BIT_SYSST_CHECK \ + (AW_PID_2049_BSTS_FINISHED_VALUE | \ + AW_PID_2049_SWS_SWITCHING_VALUE | \ + AW_PID_2049_CLKS_STABLE_VALUE | \ + AW_PID_2049_PLLS_LOCKED_VALUE) + +/* default value of SYSST (0x01) */ +/* #define AW_PID_2049_SYSST_DEFAULT (0x0000) */ + +/* SYSINT (0x02) detail */ +/* OVP2I bit 15 (SYSINT 0x02) */ +#define AW_PID_2049_OVP2I_START_BIT (15) +#define AW_PID_2049_OVP2I_BITS_LEN (1) +#define AW_PID_2049_OVP2I_MASK \ + (~(((1<<AW_PID_2049_OVP2I_BITS_LEN)-1) << AW_PID_2049_OVP2I_START_BIT)) + +#define AW_PID_2049_OVP2I_DEFAULT_VALUE (0) +#define AW_PID_2049_OVP2I_DEFAULT \ + (AW_PID_2049_OVP2I_DEFAULT_VALUE << AW_PID_2049_OVP2I_START_BIT) + +/* UVLI bit 14 (SYSINT 0x02) */ +#define AW_PID_2049_UVLI_START_BIT (14) +#define AW_PID_2049_UVLI_BITS_LEN (1) +#define AW_PID_2049_UVLI_MASK \ + (~(((1<<AW_PID_2049_UVLI_BITS_LEN)-1) << AW_PID_2049_UVLI_START_BIT)) + +#define AW_PID_2049_UVLI_DEFAULT_VALUE (0) +#define AW_PID_2049_UVLI_DEFAULT \ + (AW_PID_2049_UVLI_DEFAULT_VALUE << AW_PID_2049_UVLI_START_BIT) + +/* ADPI bit 13 (SYSINT 0x02) */ +#define AW_PID_2049_ADPI_START_BIT (13) +#define AW_PID_2049_ADPI_BITS_LEN (1) +#define AW_PID_2049_ADPI_MASK \ + (~(((1<<AW_PID_2049_ADPI_BITS_LEN)-1) << AW_PID_2049_ADPI_START_BIT)) + +#define AW_PID_2049_ADPI_DEFAULT_VALUE (0) +#define AW_PID_2049_ADPI_DEFAULT \ + (AW_PID_2049_ADPI_DEFAULT_VALUE << AW_PID_2049_ADPI_START_BIT) + +/* DSPI bit 12 (SYSINT 0x02) */ +#define AW_PID_2049_DSPI_START_BIT (12) +#define AW_PID_2049_DSPI_BITS_LEN (1) +#define AW_PID_2049_DSPI_MASK \ + (~(((1<<AW_PID_2049_DSPI_BITS_LEN)-1) << AW_PID_2049_DSPI_START_BIT)) + +#define AW_PID_2049_DSPI_DEFAULT_VALUE (0) +#define AW_PID_2049_DSPI_DEFAULT \ + (AW_PID_2049_DSPI_DEFAULT_VALUE << AW_PID_2049_DSPI_START_BIT) + +/* BSTOCI bit 11 (SYSINT 0x02) */ +#define AW_PID_2049_BSTOCI_START_BIT (11) +#define AW_PID_2049_BSTOCI_BITS_LEN (1) +#define AW_PID_2049_BSTOCI_MASK \ + (~(((1<<AW_PID_2049_BSTOCI_BITS_LEN)-1) << AW_PID_2049_BSTOCI_START_BIT)) + +#define AW_PID_2049_BSTOCI_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTOCI_DEFAULT \ + (AW_PID_2049_BSTOCI_DEFAULT_VALUE << AW_PID_2049_BSTOCI_START_BIT) + +/* OVPI bit 10 (SYSINT 0x02) */ +#define AW_PID_2049_OVPI_START_BIT (10) +#define AW_PID_2049_OVPI_BITS_LEN (1) +#define AW_PID_2049_OVPI_MASK \ + (~(((1<<AW_PID_2049_OVPI_BITS_LEN)-1) << AW_PID_2049_OVPI_START_BIT)) + +#define AW_PID_2049_OVPI_DEFAULT_VALUE (0) +#define AW_PID_2049_OVPI_DEFAULT \ + (AW_PID_2049_OVPI_DEFAULT_VALUE << AW_PID_2049_OVPI_START_BIT) + +/* BSTI bit 9 (SYSINT 0x02) */ +#define AW_PID_2049_BSTI_START_BIT (9) +#define AW_PID_2049_BSTI_BITS_LEN (1) +#define AW_PID_2049_BSTI_MASK \ + (~(((1<<AW_PID_2049_BSTI_BITS_LEN)-1) << AW_PID_2049_BSTI_START_BIT)) + +#define AW_PID_2049_BSTI_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTI_DEFAULT \ + (AW_PID_2049_BSTI_DEFAULT_VALUE << AW_PID_2049_BSTI_START_BIT) + +/* SWI bit 8 (SYSINT 0x02) */ +#define AW_PID_2049_SWI_START_BIT (8) +#define AW_PID_2049_SWI_BITS_LEN (1) +#define AW_PID_2049_SWI_MASK \ + (~(((1<<AW_PID_2049_SWI_BITS_LEN)-1) << AW_PID_2049_SWI_START_BIT)) + +#define AW_PID_2049_SWI_DEFAULT_VALUE (0) +#define AW_PID_2049_SWI_DEFAULT \ + (AW_PID_2049_SWI_DEFAULT_VALUE << AW_PID_2049_SWI_START_BIT) + +/* CLIPI bit 7 (SYSINT 0x02) */ +#define AW_PID_2049_CLIPI_START_BIT (7) +#define AW_PID_2049_CLIPI_BITS_LEN (1) +#define AW_PID_2049_CLIPI_MASK \ + (~(((1<<AW_PID_2049_CLIPI_BITS_LEN)-1) << AW_PID_2049_CLIPI_START_BIT)) + +#define AW_PID_2049_CLIPI_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIPI_DEFAULT \ + (AW_PID_2049_CLIPI_DEFAULT_VALUE << AW_PID_2049_CLIPI_START_BIT) + +/* WDI bit 6 (SYSINT 0x02) */ +#define AW_PID_2049_WDI_START_BIT (6) +#define AW_PID_2049_WDI_BITS_LEN (1) +#define AW_PID_2049_WDI_MASK \ + (~(((1<<AW_PID_2049_WDI_BITS_LEN)-1) << AW_PID_2049_WDI_START_BIT)) + +#define AW_PID_2049_WDI_DEFAULT_VALUE (0) +#define AW_PID_2049_WDI_INT_VALUE (1) +#define AW_PID_2049_WDI_DEFAULT \ + (AW_PID_2049_WDI_DEFAULT_VALUE << AW_PID_2049_WDI_START_BIT) +#define AW_PID_2049_WDI_INTERRUPT \ + (AW_PID_2049_WDI_INT_VALUE << AW_PID_2049_WDI_START_BIT) + +/* NOCLKI bit 5 (SYSINT 0x02) */ +#define AW_PID_2049_NOCLKI_START_BIT (5) +#define AW_PID_2049_NOCLKI_BITS_LEN (1) +#define AW_PID_2049_NOCLKI_MASK \ + (~(((1<<AW_PID_2049_NOCLKI_BITS_LEN)-1) << AW_PID_2049_NOCLKI_START_BIT)) + +#define AW_PID_2049_NOCLKI_DEFAULT_VALUE (0) +#define AW_PID_2049_NOCLKI_INT_VALUE (1) +#define AW_PID_2049_NOCLKI_DEFAULT \ + (AW_PID_2049_NOCLKI_DEFAULT_VALUE << AW_PID_2049_NOCLKI_START_BIT) +#define AW_PID_2049_NOCLKI_INTERRUPT \ + (AW_PID_2049_NOCLKI_INT_VALUE << AW_PID_2049_NOCLKI_START_BIT) + +/* CLKI bit 4 (SYSINT 0x02) */ +#define AW_PID_2049_CLKI_START_BIT (4) +#define AW_PID_2049_CLKI_BITS_LEN (1) +#define AW_PID_2049_CLKI_MASK \ + (~(((1<<AW_PID_2049_CLKI_BITS_LEN)-1) << AW_PID_2049_CLKI_START_BIT)) + +#define AW_PID_2049_CLKI_DEFAULT_VALUE (0) +#define AW_PID_2049_CLKI_INT_VALUE (1) +#define AW_PID_2049_CLKI_DEFAULT \ + (AW_PID_2049_CLKI_DEFAULT_VALUE << AW_PID_2049_CLKI_START_BIT) +#define AW_PID_2049_CLKI_INTERRUPT \ + (AW_PID_2049_CLKI_INT_VALUE << AW_PID_2049_CLKI_START_BIT) + +/* OCDI bit 3 (SYSINT 0x02) */ +#define AW_PID_2049_OCDI_START_BIT (3) +#define AW_PID_2049_OCDI_BITS_LEN (1) +#define AW_PID_2049_OCDI_MASK \ + (~(((1<<AW_PID_2049_OCDI_BITS_LEN)-1) << AW_PID_2049_OCDI_START_BIT)) + +#define AW_PID_2049_OCDI_DEFAULT_VALUE (0) +#define AW_PID_2049_OCDI_DEFAULT \ + (AW_PID_2049_OCDI_DEFAULT_VALUE << AW_PID_2049_OCDI_START_BIT) + +/* CLIP_PREI bit 2 (SYSINT 0x02) */ +#define AW_PID_2049_CLIP_PREI_START_BIT (2) +#define AW_PID_2049_CLIP_PREI_BITS_LEN (1) +#define AW_PID_2049_CLIP_PREI_MASK \ + (~(((1<<AW_PID_2049_CLIP_PREI_BITS_LEN)-1) << AW_PID_2049_CLIP_PREI_START_BIT)) + +#define AW_PID_2049_CLIP_PREI_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIP_PREI_DEFAULT \ + (AW_PID_2049_CLIP_PREI_DEFAULT_VALUE << AW_PID_2049_CLIP_PREI_START_BIT) + +/* OTHI bit 1 (SYSINT 0x02) */ +#define AW_PID_2049_OTHI_START_BIT (1) +#define AW_PID_2049_OTHI_BITS_LEN (1) +#define AW_PID_2049_OTHI_MASK \ + (~(((1<<AW_PID_2049_OTHI_BITS_LEN)-1) << AW_PID_2049_OTHI_START_BIT)) + +#define AW_PID_2049_OTHI_DEFAULT_VALUE (0) +#define AW_PID_2049_OTHI_DEFAULT \ + (AW_PID_2049_OTHI_DEFAULT_VALUE << AW_PID_2049_OTHI_START_BIT) + +/* PLLI bit 0 (SYSINT 0x02) */ +#define AW_PID_2049_PLLI_START_BIT (0) +#define AW_PID_2049_PLLI_BITS_LEN (1) +#define AW_PID_2049_PLLI_MASK \ + (~(((1<<AW_PID_2049_PLLI_BITS_LEN)-1) << AW_PID_2049_PLLI_START_BIT)) + +#define AW_PID_2049_PLLI_DEFAULT_VALUE (0) +#define AW_PID_2049_PLLI_INT_VALUE (1) +#define AW_PID_2049_PLLI_DEFAULT \ + (AW_PID_2049_PLLI_DEFAULT_VALUE << AW_PID_2049_PLLI_START_BIT) +#define AW_PID_2049_PLLI_INTERRUPT \ + (AW_PID_2049_PLLI_INT_VALUE << AW_PID_2049_PLLI_START_BIT) + +/* default value of SYSINT (0x02) */ +/* #define AW_PID_2049_SYSINT_DEFAULT (0x0000) */ + +#define AW_PID_2049_BIT_SYSINT_CHECK \ + (AW_PID_2049_WDI_INTERRUPT | \ + AW_PID_2049_CLKI_INTERRUPT | \ + AW_PID_2049_NOCLKI_INTERRUPT | \ + AW_PID_2049_PLLI_INTERRUPT) + +/* SYSINTM (0x03) detail */ +/* OVP2M bit 15 (SYSINTM 0x03) */ +#define AW_PID_2049_OVP2M_START_BIT (15) +#define AW_PID_2049_OVP2M_BITS_LEN (1) +#define AW_PID_2049_OVP2M_MASK \ + (~(((1<<AW_PID_2049_OVP2M_BITS_LEN)-1) << AW_PID_2049_OVP2M_START_BIT)) + +#define AW_PID_2049_OVP2M_DEFAULT_VALUE (1) +#define AW_PID_2049_OVP2M_DEFAULT \ + (AW_PID_2049_OVP2M_DEFAULT_VALUE << AW_PID_2049_OVP2M_START_BIT) + +/* UVLM bit 14 (SYSINTM 0x03) */ +#define AW_PID_2049_UVLM_START_BIT (14) +#define AW_PID_2049_UVLM_BITS_LEN (1) +#define AW_PID_2049_UVLM_MASK \ + (~(((1<<AW_PID_2049_UVLM_BITS_LEN)-1) << AW_PID_2049_UVLM_START_BIT)) + +#define AW_PID_2049_UVLM_DEFAULT_VALUE (1) +#define AW_PID_2049_UVLM_DEFAULT \ + (AW_PID_2049_UVLM_DEFAULT_VALUE << AW_PID_2049_UVLM_START_BIT) + +/* ADPM bit 13 (SYSINTM 0x03) */ +#define AW_PID_2049_ADPM_START_BIT (13) +#define AW_PID_2049_ADPM_BITS_LEN (1) +#define AW_PID_2049_ADPM_MASK \ + (~(((1<<AW_PID_2049_ADPM_BITS_LEN)-1) << AW_PID_2049_ADPM_START_BIT)) + +#define AW_PID_2049_ADPM_DEFAULT_VALUE (1) +#define AW_PID_2049_ADPM_DEFAULT \ + (AW_PID_2049_ADPM_DEFAULT_VALUE << AW_PID_2049_ADPM_START_BIT) + +/* DSPM bit 12 (SYSINTM 0x03) */ +#define AW_PID_2049_DSPM_START_BIT (12) +#define AW_PID_2049_DSPM_BITS_LEN (1) +#define AW_PID_2049_DSPM_MASK \ + (~(((1<<AW_PID_2049_DSPM_BITS_LEN)-1) << AW_PID_2049_DSPM_START_BIT)) + +#define AW_PID_2049_DSPM_DEFAULT_VALUE (1) +#define AW_PID_2049_DSPM_DEFAULT \ + (AW_PID_2049_DSPM_DEFAULT_VALUE << AW_PID_2049_DSPM_START_BIT) + +/* BSTOCM bit 11 (SYSINTM 0x03) */ +#define AW_PID_2049_BSTOCM_START_BIT (11) +#define AW_PID_2049_BSTOCM_BITS_LEN (1) +#define AW_PID_2049_BSTOCM_MASK \ + (~(((1<<AW_PID_2049_BSTOCM_BITS_LEN)-1) << AW_PID_2049_BSTOCM_START_BIT)) + +#define AW_PID_2049_BSTOCM_DEFAULT_VALUE (1) +#define AW_PID_2049_BSTOCM_DEFAULT \ + (AW_PID_2049_BSTOCM_DEFAULT_VALUE << AW_PID_2049_BSTOCM_START_BIT) + +/* OVPM bit 10 (SYSINTM 0x03) */ +#define AW_PID_2049_OVPM_START_BIT (10) +#define AW_PID_2049_OVPM_BITS_LEN (1) +#define AW_PID_2049_OVPM_MASK \ + (~(((1<<AW_PID_2049_OVPM_BITS_LEN)-1) << AW_PID_2049_OVPM_START_BIT)) + +#define AW_PID_2049_OVPM_DEFAULT_VALUE (1) +#define AW_PID_2049_OVPM_DEFAULT \ + (AW_PID_2049_OVPM_DEFAULT_VALUE << AW_PID_2049_OVPM_START_BIT) + +/* BSTM bit 9 (SYSINTM 0x03) */ +#define AW_PID_2049_BSTM_START_BIT (9) +#define AW_PID_2049_BSTM_BITS_LEN (1) +#define AW_PID_2049_BSTM_MASK \ + (~(((1<<AW_PID_2049_BSTM_BITS_LEN)-1) << AW_PID_2049_BSTM_START_BIT)) + +#define AW_PID_2049_BSTM_DEFAULT_VALUE (1) +#define AW_PID_2049_BSTM_DEFAULT \ + (AW_PID_2049_BSTM_DEFAULT_VALUE << AW_PID_2049_BSTM_START_BIT) + +/* SWM bit 8 (SYSINTM 0x03) */ +#define AW_PID_2049_SWM_START_BIT (8) +#define AW_PID_2049_SWM_BITS_LEN (1) +#define AW_PID_2049_SWM_MASK \ + (~(((1<<AW_PID_2049_SWM_BITS_LEN)-1) << AW_PID_2049_SWM_START_BIT)) + +#define AW_PID_2049_SWM_DEFAULT_VALUE (1) +#define AW_PID_2049_SWM_DEFAULT \ + (AW_PID_2049_SWM_DEFAULT_VALUE << AW_PID_2049_SWM_START_BIT) + +/* CLIPM bit 7 (SYSINTM 0x03) */ +#define AW_PID_2049_CLIPM_START_BIT (7) +#define AW_PID_2049_CLIPM_BITS_LEN (1) +#define AW_PID_2049_CLIPM_MASK \ + (~(((1<<AW_PID_2049_CLIPM_BITS_LEN)-1) << AW_PID_2049_CLIPM_START_BIT)) + +#define AW_PID_2049_CLIPM_DEFAULT_VALUE (1) +#define AW_PID_2049_CLIPM_DEFAULT \ + (AW_PID_2049_CLIPM_DEFAULT_VALUE << AW_PID_2049_CLIPM_START_BIT) + +/* WDM bit 6 (SYSINTM 0x03) */ +#define AW_PID_2049_WDM_START_BIT (6) +#define AW_PID_2049_WDM_BITS_LEN (1) +#define AW_PID_2049_WDM_MASK \ + (~(((1<<AW_PID_2049_WDM_BITS_LEN)-1) << AW_PID_2049_WDM_START_BIT)) + +#define AW_PID_2049_WDM_DEFAULT_VALUE (1) +#define AW_PID_2049_WDM_DEFAULT \ + (AW_PID_2049_WDM_DEFAULT_VALUE << AW_PID_2049_WDM_START_BIT) + +/* NOCLKM bit 5 (SYSINTM 0x03) */ +#define AW_PID_2049_NOCLKM_START_BIT (5) +#define AW_PID_2049_NOCLKM_BITS_LEN (1) +#define AW_PID_2049_NOCLKM_MASK \ + (~(((1<<AW_PID_2049_NOCLKM_BITS_LEN)-1) << AW_PID_2049_NOCLKM_START_BIT)) + +#define AW_PID_2049_NOCLKM_DEFAULT_VALUE (1) +#define AW_PID_2049_NOCLKM_DEFAULT \ + (AW_PID_2049_NOCLKM_DEFAULT_VALUE << AW_PID_2049_NOCLKM_START_BIT) + +/* CLKM bit 4 (SYSINTM 0x03) */ +#define AW_PID_2049_CLKM_START_BIT (4) +#define AW_PID_2049_CLKM_BITS_LEN (1) +#define AW_PID_2049_CLKM_MASK \ + (~(((1<<AW_PID_2049_CLKM_BITS_LEN)-1) << AW_PID_2049_CLKM_START_BIT)) + +#define AW_PID_2049_CLKM_DEFAULT_VALUE (1) +#define AW_PID_2049_CLKM_DEFAULT \ + (AW_PID_2049_CLKM_DEFAULT_VALUE << AW_PID_2049_CLKM_START_BIT) + +/* OCDM bit 3 (SYSINTM 0x03) */ +#define AW_PID_2049_OCDM_START_BIT (3) +#define AW_PID_2049_OCDM_BITS_LEN (1) +#define AW_PID_2049_OCDM_MASK \ + (~(((1<<AW_PID_2049_OCDM_BITS_LEN)-1) << AW_PID_2049_OCDM_START_BIT)) + +#define AW_PID_2049_OCDM_DEFAULT_VALUE (1) +#define AW_PID_2049_OCDM_DEFAULT \ + (AW_PID_2049_OCDM_DEFAULT_VALUE << AW_PID_2049_OCDM_START_BIT) + +/* CLIP_PREM bit 2 (SYSINTM 0x03) */ +#define AW_PID_2049_CLIP_PREM_START_BIT (2) +#define AW_PID_2049_CLIP_PREM_BITS_LEN (1) +#define AW_PID_2049_CLIP_PREM_MASK \ + (~(((1<<AW_PID_2049_CLIP_PREM_BITS_LEN)-1) << AW_PID_2049_CLIP_PREM_START_BIT)) + +#define AW_PID_2049_CLIP_PREM_DEFAULT_VALUE (1) +#define AW_PID_2049_CLIP_PREM_DEFAULT \ + (AW_PID_2049_CLIP_PREM_DEFAULT_VALUE << AW_PID_2049_CLIP_PREM_START_BIT) + +/* OTHM bit 1 (SYSINTM 0x03) */ +#define AW_PID_2049_OTHM_START_BIT (1) +#define AW_PID_2049_OTHM_BITS_LEN (1) +#define AW_PID_2049_OTHM_MASK \ + (~(((1<<AW_PID_2049_OTHM_BITS_LEN)-1) << AW_PID_2049_OTHM_START_BIT)) + +#define AW_PID_2049_OTHM_DEFAULT_VALUE (1) +#define AW_PID_2049_OTHM_DEFAULT \ + (AW_PID_2049_OTHM_DEFAULT_VALUE << AW_PID_2049_OTHM_START_BIT) + +/* PLLM bit 0 (SYSINTM 0x03) */ +#define AW_PID_2049_PLLM_START_BIT (0) +#define AW_PID_2049_PLLM_BITS_LEN (1) +#define AW_PID_2049_PLLM_MASK \ + (~(((1<<AW_PID_2049_PLLM_BITS_LEN)-1) << AW_PID_2049_PLLM_START_BIT)) + +#define AW_PID_2049_PLLM_DEFAULT_VALUE (1) +#define AW_PID_2049_PLLM_DEFAULT \ + (AW_PID_2049_PLLM_DEFAULT_VALUE << AW_PID_2049_PLLM_START_BIT) + +/* default value of SYSINTM (0x03) */ +#define AW_PID_2049_SYSINTM_DEFAULT (0xFFFF) + +/* SYSCTRL (0x04) detail */ +/* SPK_GAIN bit 14:12 (SYSCTRL 0x04) */ +#define AW_PID_2049_SPK_GAIN_START_BIT (12) +#define AW_PID_2049_SPK_GAIN_BITS_LEN (3) +#define AW_PID_2049_SPK_GAIN_MASK \ + (~(((1<<AW_PID_2049_SPK_GAIN_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_START_BIT)) + +#define AW_PID_2049_SPK_GAIN_4_AV (0) +#define AW_PID_2049_SPK_GAIN_4_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_4_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_4P67_AV (1) +#define AW_PID_2049_SPK_GAIN_4P67_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_4P67_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_6_AV (2) +#define AW_PID_2049_SPK_GAIN_6_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_6_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_7_AV (3) +#define AW_PID_2049_SPK_GAIN_7_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_7_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_12_AV (4) +#define AW_PID_2049_SPK_GAIN_12_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_12_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_14_AV (5) +#define AW_PID_2049_SPK_GAIN_14_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_14_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_DEFAULT_VALUE (0x5) +#define AW_PID_2049_SPK_GAIN_DEFAULT \ + (AW_PID_2049_SPK_GAIN_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_START_BIT) + +/* RMSE bit 11 (SYSCTRL 0x04) */ +#define AW_PID_2049_RMSE_START_BIT (11) +#define AW_PID_2049_RMSE_BITS_LEN (1) +#define AW_PID_2049_RMSE_MASK \ + (~(((1<<AW_PID_2049_RMSE_BITS_LEN)-1) << AW_PID_2049_RMSE_START_BIT)) + +#define AW_PID_2049_RMSE_PEAK_AGC (0) +#define AW_PID_2049_RMSE_PEAK_AGC_VALUE \ + (AW_PID_2049_RMSE_PEAK_AGC << AW_PID_2049_RMSE_START_BIT) + +#define AW_PID_2049_RMSE_RMS_AGC (1) +#define AW_PID_2049_RMSE_RMS_AGC_VALUE \ + (AW_PID_2049_RMSE_RMS_AGC << AW_PID_2049_RMSE_START_BIT) + +#define AW_PID_2049_RMSE_DEFAULT_VALUE (0) +#define AW_PID_2049_RMSE_DEFAULT \ + (AW_PID_2049_RMSE_DEFAULT_VALUE << AW_PID_2049_RMSE_START_BIT) + +/* HAGCE bit 10 (SYSCTRL 0x04) */ +#define AW_PID_2049_HAGCE_START_BIT (10) +#define AW_PID_2049_HAGCE_BITS_LEN (1) +#define AW_PID_2049_HAGCE_MASK \ + (~(((1<<AW_PID_2049_HAGCE_BITS_LEN)-1) << AW_PID_2049_HAGCE_START_BIT)) + +#define AW_PID_2049_HAGCE_DISABLE (0) +#define AW_PID_2049_HAGCE_DISABLE_VALUE \ + (AW_PID_2049_HAGCE_DISABLE << AW_PID_2049_HAGCE_START_BIT) + +#define AW_PID_2049_HAGCE_ENABLE (1) +#define AW_PID_2049_HAGCE_ENABLE_VALUE \ + (AW_PID_2049_HAGCE_ENABLE << AW_PID_2049_HAGCE_START_BIT) + +#define AW_PID_2049_HAGCE_DEFAULT_VALUE (0) +#define AW_PID_2049_HAGCE_DEFAULT \ + (AW_PID_2049_HAGCE_DEFAULT_VALUE << AW_PID_2049_HAGCE_START_BIT) + +/* HDCCE bit 9 (SYSCTRL 0x04) */ +#define AW_PID_2049_HDCCE_START_BIT (9) +#define AW_PID_2049_HDCCE_BITS_LEN (1) +#define AW_PID_2049_HDCCE_MASK \ + (~(((1<<AW_PID_2049_HDCCE_BITS_LEN)-1) << AW_PID_2049_HDCCE_START_BIT)) + +#define AW_PID_2049_HDCCE_DISABLE (0) +#define AW_PID_2049_HDCCE_DISABLE_VALUE \ + (AW_PID_2049_HDCCE_DISABLE << AW_PID_2049_HDCCE_START_BIT) + +#define AW_PID_2049_HDCCE_ENABLE (1) +#define AW_PID_2049_HDCCE_ENABLE_VALUE \ + (AW_PID_2049_HDCCE_ENABLE << AW_PID_2049_HDCCE_START_BIT) + +#define AW_PID_2049_HDCCE_DEFAULT_VALUE (1) +#define AW_PID_2049_HDCCE_DEFAULT \ + (AW_PID_2049_HDCCE_DEFAULT_VALUE << AW_PID_2049_HDCCE_START_BIT) + +/* HMUTE bit 8 (SYSCTRL 0x04) */ +#define AW_PID_2049_HMUTE_START_BIT (8) +#define AW_PID_2049_HMUTE_BITS_LEN (1) +#define AW_PID_2049_HMUTE_MASK \ + (~(((1<<AW_PID_2049_HMUTE_BITS_LEN)-1) << AW_PID_2049_HMUTE_START_BIT)) + +#define AW_PID_2049_HMUTE_DISABLE (0) +#define AW_PID_2049_HMUTE_DISABLE_VALUE \ + (AW_PID_2049_HMUTE_DISABLE << AW_PID_2049_HMUTE_START_BIT) + +#define AW_PID_2049_HMUTE_ENABLE (1) +#define AW_PID_2049_HMUTE_ENABLE_VALUE \ + (AW_PID_2049_HMUTE_ENABLE << AW_PID_2049_HMUTE_START_BIT) + +#define AW_PID_2049_HMUTE_DEFAULT_VALUE (1) +#define AW_PID_2049_HMUTE_DEFAULT \ + (AW_PID_2049_HMUTE_DEFAULT_VALUE << AW_PID_2049_HMUTE_START_BIT) + +/* RCV_MODE bit 7 (SYSCTRL 0x04) */ +#define AW_PID_2049_RCV_MODE_START_BIT (7) +#define AW_PID_2049_RCV_MODE_BITS_LEN (1) +#define AW_PID_2049_RCV_MODE_MASK \ + (~(((1<<AW_PID_2049_RCV_MODE_BITS_LEN)-1) << AW_PID_2049_RCV_MODE_START_BIT)) + +#define AW_PID_2049_RCV_MODE_SPEAKER (0) +#define AW_PID_2049_RCV_MODE_SPEAKER_VALUE \ + (AW_PID_2049_RCV_MODE_SPEAKER << AW_PID_2049_RCV_MODE_START_BIT) + +#define AW_PID_2049_RCV_MODE_RECEIVER (1) +#define AW_PID_2049_RCV_MODE_RECEIVER_VALUE \ + (AW_PID_2049_RCV_MODE_RECEIVER << AW_PID_2049_RCV_MODE_START_BIT) + +#define AW_PID_2049_RCV_MODE_DEFAULT_VALUE (0) +#define AW_PID_2049_RCV_MODE_DEFAULT \ + (AW_PID_2049_RCV_MODE_DEFAULT_VALUE << AW_PID_2049_RCV_MODE_START_BIT) + +/* I2SEN bit 6 (SYSCTRL 0x04) */ +#define AW_PID_2049_I2SEN_START_BIT (6) +#define AW_PID_2049_I2SEN_BITS_LEN (1) +#define AW_PID_2049_I2SEN_MASK \ + (~(((1<<AW_PID_2049_I2SEN_BITS_LEN)-1) << AW_PID_2049_I2SEN_START_BIT)) + +#define AW_PID_2049_I2SEN_DISABLE (0) +#define AW_PID_2049_I2SEN_DISABLE_VALUE \ + (AW_PID_2049_I2SEN_DISABLE << AW_PID_2049_I2SEN_START_BIT) + +#define AW_PID_2049_I2SEN_ENABLE (1) +#define AW_PID_2049_I2SEN_ENABLE_VALUE \ + (AW_PID_2049_I2SEN_ENABLE << AW_PID_2049_I2SEN_START_BIT) + +#define AW_PID_2049_I2SEN_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SEN_DEFAULT \ + (AW_PID_2049_I2SEN_DEFAULT_VALUE << AW_PID_2049_I2SEN_START_BIT) + +/* WSINV bit 5 (SYSCTRL 0x04) */ +#define AW_PID_2049_WSINV_START_BIT (5) +#define AW_PID_2049_WSINV_BITS_LEN (1) +#define AW_PID_2049_WSINV_MASK \ + (~(((1<<AW_PID_2049_WSINV_BITS_LEN)-1) << AW_PID_2049_WSINV_START_BIT)) + +#define AW_PID_2049_WSINV_NOT_SWITCH (0) +#define AW_PID_2049_WSINV_NOT_SWITCH_VALUE \ + (AW_PID_2049_WSINV_NOT_SWITCH << AW_PID_2049_WSINV_START_BIT) + +#define AW_PID_2049_WSINV_SWITCH (1) +#define AW_PID_2049_WSINV_SWITCH_VALUE \ + (AW_PID_2049_WSINV_SWITCH << AW_PID_2049_WSINV_START_BIT) + +#define AW_PID_2049_WSINV_DEFAULT_VALUE (0) +#define AW_PID_2049_WSINV_DEFAULT \ + (AW_PID_2049_WSINV_DEFAULT_VALUE << AW_PID_2049_WSINV_START_BIT) + +/* BCKINV bit 4 (SYSCTRL 0x04) */ +#define AW_PID_2049_BCKINV_START_BIT (4) +#define AW_PID_2049_BCKINV_BITS_LEN (1) +#define AW_PID_2049_BCKINV_MASK \ + (~(((1<<AW_PID_2049_BCKINV_BITS_LEN)-1) << AW_PID_2049_BCKINV_START_BIT)) + +#define AW_PID_2049_BCKINV_NOT_INVERT (0) +#define AW_PID_2049_BCKINV_NOT_INVERT_VALUE \ + (AW_PID_2049_BCKINV_NOT_INVERT << AW_PID_2049_BCKINV_START_BIT) + +#define AW_PID_2049_BCKINV_INVERTED (1) +#define AW_PID_2049_BCKINV_INVERTED_VALUE \ + (AW_PID_2049_BCKINV_INVERTED << AW_PID_2049_BCKINV_START_BIT) + +#define AW_PID_2049_BCKINV_DEFAULT_VALUE (0) +#define AW_PID_2049_BCKINV_DEFAULT \ + (AW_PID_2049_BCKINV_DEFAULT_VALUE << AW_PID_2049_BCKINV_START_BIT) + +/* IPLL bit 3 (SYSCTRL 0x04) */ +#define AW_PID_2049_IPLL_START_BIT (3) +#define AW_PID_2049_IPLL_BITS_LEN (1) +#define AW_PID_2049_IPLL_MASK \ + (~(((1<<AW_PID_2049_IPLL_BITS_LEN)-1) << AW_PID_2049_IPLL_START_BIT)) + +#define AW_PID_2049_IPLL_BCK (0) +#define AW_PID_2049_IPLL_BCK_VALUE \ + (AW_PID_2049_IPLL_BCK << AW_PID_2049_IPLL_START_BIT) + +#define AW_PID_2049_IPLL_WCK (1) +#define AW_PID_2049_IPLL_WCK_VALUE \ + (AW_PID_2049_IPLL_WCK << AW_PID_2049_IPLL_START_BIT) + +#define AW_PID_2049_IPLL_DEFAULT_VALUE (0) +#define AW_PID_2049_IPLL_DEFAULT \ + (AW_PID_2049_IPLL_DEFAULT_VALUE << AW_PID_2049_IPLL_START_BIT) + +/* DSPBY bit 2 (SYSCTRL 0x04) */ +#define AW_PID_2049_DSPBY_START_BIT (2) +#define AW_PID_2049_DSPBY_BITS_LEN (1) +#define AW_PID_2049_DSPBY_MASK \ + (~(((1<<AW_PID_2049_DSPBY_BITS_LEN)-1) << AW_PID_2049_DSPBY_START_BIT)) + +#define AW_PID_2049_DSPBY_WORKING (0) +#define AW_PID_2049_DSPBY_WORKING_VALUE \ + (AW_PID_2049_DSPBY_WORKING << AW_PID_2049_DSPBY_START_BIT) + +#define AW_PID_2049_DSPBY_BYPASS (1) +#define AW_PID_2049_DSPBY_BYPASS_VALUE \ + (AW_PID_2049_DSPBY_BYPASS << AW_PID_2049_DSPBY_START_BIT) + +#define AW_PID_2049_DSPBY_DEFAULT_VALUE (1) +#define AW_PID_2049_DSPBY_DEFAULT \ + (AW_PID_2049_DSPBY_DEFAULT_VALUE << AW_PID_2049_DSPBY_START_BIT) + +/* AMPPD bit 1 (SYSCTRL 0x04) */ +#define AW_PID_2049_AMPPD_START_BIT (1) +#define AW_PID_2049_AMPPD_BITS_LEN (1) +#define AW_PID_2049_AMPPD_MASK \ + (~(((1<<AW_PID_2049_AMPPD_BITS_LEN)-1) << AW_PID_2049_AMPPD_START_BIT)) + +#define AW_PID_2049_AMPPD_WORKING (0) +#define AW_PID_2049_AMPPD_WORKING_VALUE \ + (AW_PID_2049_AMPPD_WORKING << AW_PID_2049_AMPPD_START_BIT) + +#define AW_PID_2049_AMPPD_POWER_DOWN (1) +#define AW_PID_2049_AMPPD_POWER_DOWN_VALUE \ + (AW_PID_2049_AMPPD_POWER_DOWN << AW_PID_2049_AMPPD_START_BIT) + +#define AW_PID_2049_AMPPD_DEFAULT_VALUE (1) +#define AW_PID_2049_AMPPD_DEFAULT \ + (AW_PID_2049_AMPPD_DEFAULT_VALUE << AW_PID_2049_AMPPD_START_BIT) + +/* PWDN bit 0 (SYSCTRL 0x04) */ +#define AW_PID_2049_PWDN_START_BIT (0) +#define AW_PID_2049_PWDN_BITS_LEN (1) +#define AW_PID_2049_PWDN_MASK \ + (~(((1<<AW_PID_2049_PWDN_BITS_LEN)-1) << AW_PID_2049_PWDN_START_BIT)) + +#define AW_PID_2049_PWDN_WORKING (0) +#define AW_PID_2049_PWDN_WORKING_VALUE \ + (AW_PID_2049_PWDN_WORKING << AW_PID_2049_PWDN_START_BIT) + +#define AW_PID_2049_PWDN_POWER_DOWN (1) +#define AW_PID_2049_PWDN_POWER_DOWN_VALUE \ + (AW_PID_2049_PWDN_POWER_DOWN << AW_PID_2049_PWDN_START_BIT) + +#define AW_PID_2049_PWDN_DEFAULT_VALUE (1) +#define AW_PID_2049_PWDN_DEFAULT \ + (AW_PID_2049_PWDN_DEFAULT_VALUE << AW_PID_2049_PWDN_START_BIT) + +/* default value of SYSCTRL (0x04) */ +/* #define AW_PID_2049_SYSCTRL_DEFAULT (0x5307) */ + +/* SYSCTRL2 (0x05) detail */ +/* VOL bit 15:6 (SYSCTRL2 0x05) */ +#define AW_PID_2049_MUTE_VOL (90 * 8) +#define AW_PID_2049_VOLUME_STEP_DB (6 * 8) + +#define AW_PID_2049_VOL_6DB_START (6) +#define AW_PID_2049_VOL_START_BIT (6) +#define AW_PID_2049_VOL_BITS_LEN (10) +#define AW_PID_2049_VOL_MASK \ + (~(((1<<AW_PID_2049_VOL_BITS_LEN)-1) << AW_PID_2049_VOL_START_BIT)) + +#define AW_PID_2049_VOL_DEFAULT_VALUE (0) +#define AW_PID_2049_VOL_DEFAULT \ + (AW_PID_2049_VOL_DEFAULT_VALUE << AW_PID_2049_VOL_START_BIT) + +/* INTMODE bit 5 (SYSCTRL2 0x05) */ +#define AW_PID_2049_INTMODE_START_BIT (5) +#define AW_PID_2049_INTMODE_BITS_LEN (1) +#define AW_PID_2049_INTMODE_MASK \ + (~(((1<<AW_PID_2049_INTMODE_BITS_LEN)-1) << AW_PID_2049_INTMODE_START_BIT)) + +#define AW_PID_2049_INTMODE_OPENMINUS_DRAIN (0) +#define AW_PID_2049_INTMODE_OPENMINUS_DRAIN_VALUE \ + (AW_PID_2049_INTMODE_OPENMINUS_DRAIN << AW_PID_2049_INTMODE_START_BIT) + +#define AW_PID_2049_INTMODE_PUSHPULL (1) +#define AW_PID_2049_INTMODE_PUSHPULL_VALUE \ + (AW_PID_2049_INTMODE_PUSHPULL << AW_PID_2049_INTMODE_START_BIT) + +#define AW_PID_2049_INTMODE_DEFAULT_VALUE (0) +#define AW_PID_2049_INTMODE_DEFAULT \ + (AW_PID_2049_INTMODE_DEFAULT_VALUE << AW_PID_2049_INTMODE_START_BIT) + +/* INTN bit 4 (SYSCTRL2 0x05) */ +#define AW_PID_2049_INTN_START_BIT (4) +#define AW_PID_2049_INTN_BITS_LEN (1) +#define AW_PID_2049_INTN_MASK \ + (~(((1<<AW_PID_2049_INTN_BITS_LEN)-1) << AW_PID_2049_INTN_START_BIT)) + +#define AW_PID_2049_INTN_SYSINT (0) +#define AW_PID_2049_INTN_SYSINT_VALUE \ + (AW_PID_2049_INTN_SYSINT << AW_PID_2049_INTN_START_BIT) + +#define AW_PID_2049_INTN_SYSST (1) +#define AW_PID_2049_INTN_SYSST_VALUE \ + (AW_PID_2049_INTN_SYSST << AW_PID_2049_INTN_START_BIT) + +#define AW_PID_2049_INTN_DEFAULT_VALUE (0) +#define AW_PID_2049_INTN_DEFAULT \ + (AW_PID_2049_INTN_DEFAULT_VALUE << AW_PID_2049_INTN_START_BIT) + +/* BST_IPEAK bit 3:0 (SYSCTRL2 0x05) */ +#define AW_PID_2049_BST_IPEAK_START_BIT (0) +#define AW_PID_2049_BST_IPEAK_BITS_LEN (4) +#define AW_PID_2049_BST_IPEAK_MASK \ + (~(((1<<AW_PID_2049_BST_IPEAK_BITS_LEN)-1) << AW_PID_2049_BST_IPEAK_START_BIT)) + +#define AW_PID_2049_BST_IPEAK_1P50A (0) +#define AW_PID_2049_BST_IPEAK_1P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_1P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_1P75A (1) +#define AW_PID_2049_BST_IPEAK_1P75A_VALUE \ + (AW_PID_2049_BST_IPEAK_1P75A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P00A (2) +#define AW_PID_2049_BST_IPEAK_2P00A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P00A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P25A (3) +#define AW_PID_2049_BST_IPEAK_2P25A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P25A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P50A (4) +#define AW_PID_2049_BST_IPEAK_2P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P75A (5) +#define AW_PID_2049_BST_IPEAK_2P75A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P75A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P00A (6) +#define AW_PID_2049_BST_IPEAK_3P00A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P00A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P25A (7) +#define AW_PID_2049_BST_IPEAK_3P25A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P25A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P50A (8) +#define AW_PID_2049_BST_IPEAK_3P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P75A (9) +#define AW_PID_2049_BST_IPEAK_3P75A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P75A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_4P00A (10) +#define AW_PID_2049_BST_IPEAK_4P00A_VALUE \ + (AW_PID_2049_BST_IPEAK_4P00A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_4P25A (11) +#define AW_PID_2049_BST_IPEAK_4P25A_VALUE \ + (AW_PID_2049_BST_IPEAK_4P25A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_4P50A (12) +#define AW_PID_2049_BST_IPEAK_4P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_4P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_DEFAULT_VALUE (9) +#define AW_PID_2049_BST_IPEAK_DEFAULT \ + (AW_PID_2049_BST_IPEAK_DEFAULT_VALUE << AW_PID_2049_BST_IPEAK_START_BIT) + +/* default value of SYSCTRL2 (0x05) */ +/* #define AW_PID_2049_SYSCTRL2_DEFAULT (0x0009) */ + +/* I2SCTRL (0x06) detail */ +/* SLOT_NUM bit 14:12 (I2SCTRL 0x06) */ +#define AW_PID_2049_SLOT_NUM_START_BIT (12) +#define AW_PID_2049_SLOT_NUM_BITS_LEN (3) +#define AW_PID_2049_SLOT_NUM_MASK \ + (~(((1<<AW_PID_2049_SLOT_NUM_BITS_LEN)-1) << AW_PID_2049_SLOT_NUM_START_BIT)) + +#define AW_PID_2049_SLOT_NUM_I2S_MODE (0) +#define AW_PID_2049_SLOT_NUM_I2S_MODE_VALUE \ + (AW_PID_2049_SLOT_NUM_I2S_MODE << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM1S (1) +#define AW_PID_2049_SLOT_NUM_TDM1S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM1S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM2S (2) +#define AW_PID_2049_SLOT_NUM_TDM2S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM2S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM4S (3) +#define AW_PID_2049_SLOT_NUM_TDM4S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM4S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM6S (4) +#define AW_PID_2049_SLOT_NUM_TDM6S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM6S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM8S (5) +#define AW_PID_2049_SLOT_NUM_TDM8S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM8S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM16S (6) +#define AW_PID_2049_SLOT_NUM_TDM16S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM16S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_RESERVED (7) +#define AW_PID_2049_SLOT_NUM_RESERVED_VALUE \ + (AW_PID_2049_SLOT_NUM_RESERVED << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_DEFAULT_VALUE (0) +#define AW_PID_2049_SLOT_NUM_DEFAULT \ + (AW_PID_2049_SLOT_NUM_DEFAULT_VALUE << AW_PID_2049_SLOT_NUM_START_BIT) + +/* CHSEL bit 11:10 (I2SCTRL 0x06) */ +#define AW_PID_2049_CHSEL_START_BIT (10) +#define AW_PID_2049_CHSEL_BITS_LEN (2) +#define AW_PID_2049_CHSEL_MASK \ + (~(((1<<AW_PID_2049_CHSEL_BITS_LEN)-1) << AW_PID_2049_CHSEL_START_BIT)) + +#define AW_PID_2049_CHSEL_RESERVED (0) +#define AW_PID_2049_CHSEL_RESERVED_VALUE \ + (AW_PID_2049_CHSEL_RESERVED << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_LEFT (1) +#define AW_PID_2049_CHSEL_LEFT_VALUE \ + (AW_PID_2049_CHSEL_LEFT << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_RIGHT (2) +#define AW_PID_2049_CHSEL_RIGHT_VALUE \ + (AW_PID_2049_CHSEL_RIGHT << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_MONO (3) +#define AW_PID_2049_CHSEL_MONO_VALUE \ + (AW_PID_2049_CHSEL_MONO << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_DEFAULT_VALUE (1) +#define AW_PID_2049_CHSEL_DEFAULT \ + (AW_PID_2049_CHSEL_DEFAULT_VALUE << AW_PID_2049_CHSEL_START_BIT) + +/* I2SMD bit 9:8 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SMD_START_BIT (8) +#define AW_PID_2049_I2SMD_BITS_LEN (2) +#define AW_PID_2049_I2SMD_MASK \ + (~(((1<<AW_PID_2049_I2SMD_BITS_LEN)-1) << AW_PID_2049_I2SMD_START_BIT)) + +#define AW_PID_2049_I2SMD_PHILIP_STANDARD (0) +#define AW_PID_2049_I2SMD_PHILIP_STANDARD_VALUE \ + (AW_PID_2049_I2SMD_PHILIP_STANDARD << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_MSB_JUSTIFIED (1) +#define AW_PID_2049_I2SMD_MSB_JUSTIFIED_VALUE \ + (AW_PID_2049_I2SMD_MSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_LSB_JUSTIFIED (2) +#define AW_PID_2049_I2SMD_LSB_JUSTIFIED_VALUE \ + (AW_PID_2049_I2SMD_LSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_RESERVED (3) +#define AW_PID_2049_I2SMD_RESERVED_VALUE \ + (AW_PID_2049_I2SMD_RESERVED << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SMD_DEFAULT \ + (AW_PID_2049_I2SMD_DEFAULT_VALUE << AW_PID_2049_I2SMD_START_BIT) + +/* I2SFS bit 7:6 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SFS_START_BIT (6) +#define AW_PID_2049_I2SFS_BITS_LEN (2) +#define AW_PID_2049_I2SFS_MASK \ + (~(((1<<AW_PID_2049_I2SFS_BITS_LEN)-1) << AW_PID_2049_I2SFS_START_BIT)) + +#define AW_PID_2049_I2SFS_16_BITS (0) +#define AW_PID_2049_I2SFS_16_BITS_VALUE \ + (AW_PID_2049_I2SFS_16_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_20_BITS (1) +#define AW_PID_2049_I2SFS_20_BITS_VALUE \ + (AW_PID_2049_I2SFS_20_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_24_BITS (2) +#define AW_PID_2049_I2SFS_24_BITS_VALUE \ + (AW_PID_2049_I2SFS_24_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_32_BITS (3) +#define AW_PID_2049_I2SFS_32_BITS_VALUE \ + (AW_PID_2049_I2SFS_32_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_DEFAULT_VALUE (3) +#define AW_PID_2049_I2SFS_DEFAULT \ + (AW_PID_2049_I2SFS_DEFAULT_VALUE << AW_PID_2049_I2SFS_START_BIT) + +/* I2SBCK bit 5:4 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SBCK_START_BIT (4) +#define AW_PID_2049_I2SBCK_BITS_LEN (2) +#define AW_PID_2049_I2SBCK_MASK \ + (~(((1<<AW_PID_2049_I2SBCK_BITS_LEN)-1) << AW_PID_2049_I2SBCK_START_BIT)) + +#define AW_PID_2049_I2SBCK_32FS (0) +#define AW_PID_2049_I2SBCK_32FS_VALUE \ + (AW_PID_2049_I2SBCK_32FS << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_48FS (1) +#define AW_PID_2049_I2SBCK_48FS_VALUE \ + (AW_PID_2049_I2SBCK_48FS << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_64FS (2) +#define AW_PID_2049_I2SBCK_64FS_VALUE \ + (AW_PID_2049_I2SBCK_64FS << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_RESERVED (3) +#define AW_PID_2049_I2SBCK_RESERVED_VALUE \ + (AW_PID_2049_I2SBCK_RESERVED << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_DEFAULT_VALUE (2) +#define AW_PID_2049_I2SBCK_DEFAULT \ + (AW_PID_2049_I2SBCK_DEFAULT_VALUE << AW_PID_2049_I2SBCK_START_BIT) + +/* I2SSR bit 3:0 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SSR_START_BIT (0) +#define AW_PID_2049_I2SSR_BITS_LEN (4) +#define AW_PID_2049_I2SSR_MASK \ + (~(((1<<AW_PID_2049_I2SSR_BITS_LEN)-1) << AW_PID_2049_I2SSR_START_BIT)) + +#define AW_PID_2049_I2SSR_8_KHZ (0) +#define AW_PID_2049_I2SSR_8_KHZ_VALUE \ + (AW_PID_2049_I2SSR_8_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_11_KHZ (1) +#define AW_PID_2049_I2SSR_11_KHZ_VALUE \ + (AW_PID_2049_I2SSR_11_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_12_KHZ (2) +#define AW_PID_2049_I2SSR_12_KHZ_VALUE \ + (AW_PID_2049_I2SSR_12_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_16_KHZ (3) +#define AW_PID_2049_I2SSR_16_KHZ_VALUE \ + (AW_PID_2049_I2SSR_16_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_22_KHZ (4) +#define AW_PID_2049_I2SSR_22_KHZ_VALUE \ + (AW_PID_2049_I2SSR_22_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_24_KHZ (5) +#define AW_PID_2049_I2SSR_24_KHZ_VALUE \ + (AW_PID_2049_I2SSR_24_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_32_KHZ (6) +#define AW_PID_2049_I2SSR_32_KHZ_VALUE \ + (AW_PID_2049_I2SSR_32_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_44_KHZ (7) +#define AW_PID_2049_I2SSR_44_KHZ_VALUE \ + (AW_PID_2049_I2SSR_44_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_48_KHZ (8) +#define AW_PID_2049_I2SSR_48_KHZ_VALUE \ + (AW_PID_2049_I2SSR_48_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_96_KHZ (9) +#define AW_PID_2049_I2SSR_96_KHZ_VALUE \ + (AW_PID_2049_I2SSR_96_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_192KHZ (10) +#define AW_PID_2049_I2SSR_192KHZ_VALUE \ + (AW_PID_2049_I2SSR_192KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_DEFAULT_VALUE (8) +#define AW_PID_2049_I2SSR_DEFAULT \ + (AW_PID_2049_I2SSR_DEFAULT_VALUE << AW_PID_2049_I2SSR_START_BIT) + +/* default value of I2SCTRL (0x06) */ +/* #define AW_PID_2049_I2SCTRL_DEFAULT (0x04E8) */ + +/* I2SCFG1 (0x07) detail */ +/* I2S_RXL_SLOTVLD bit 15:12 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT (12) +#define AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN (4) +#define AW_PID_2049_I2S_RXL_SLOTVLD_MASK \ + (~(((1<<AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0 (0) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1 (1) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2 (2) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3 (3) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15 (15) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE (0) +#define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT \ + (AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +/* I2S_RXR_SLOTVLD bit 11:8 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT (8) +#define AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN (4) +#define AW_PID_2049_I2S_RXR_SLOTVLD_MASK \ + (~(((1<<AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0 (0) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1 (1) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2 (2) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3 (3) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15 (15) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE (1) +#define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT \ + (AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +/* I2S_TX_SLOTVLD bit 7:4 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2S_TX_SLOTVLD_START_BIT (4) +#define AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN (4) +#define AW_PID_2049_I2S_TX_SLOTVLD_MASK \ + (~(((1<<AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0 (0) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1 (1) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2 (2) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3 (3) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15 (15) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE (0) +#define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT \ + (AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +/* FSYNC_TYPE bit 3 (I2SCFG1 0x07) */ +#define AW_PID_2049_FSYNC_TYPE_START_BIT (3) +#define AW_PID_2049_FSYNC_TYPE_BITS_LEN (1) +#define AW_PID_2049_FSYNC_TYPE_MASK \ + (~(((1<<AW_PID_2049_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_2049_FSYNC_TYPE_START_BIT)) + +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT (0) +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT_VALUE \ + (AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT << AW_PID_2049_FSYNC_TYPE_START_BIT) + +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK (1) +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK_VALUE \ + (AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK << AW_PID_2049_FSYNC_TYPE_START_BIT) + +#define AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE (0) +#define AW_PID_2049_FSYNC_TYPE_DEFAULT \ + (AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE << AW_PID_2049_FSYNC_TYPE_START_BIT) + +/* I2SCHS bit 2 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2SCHS_START_BIT (2) +#define AW_PID_2049_I2SCHS_BITS_LEN (1) +#define AW_PID_2049_I2SCHS_MASK \ + (~(((1<<AW_PID_2049_I2SCHS_BITS_LEN)-1) << AW_PID_2049_I2SCHS_START_BIT)) + +#define AW_PID_2049_I2SCHS_LEFT (0) +#define AW_PID_2049_I2SCHS_LEFT_VALUE \ + (AW_PID_2049_I2SCHS_LEFT << AW_PID_2049_I2SCHS_START_BIT) + +#define AW_PID_2049_I2SCHS_RIGHT (1) +#define AW_PID_2049_I2SCHS_RIGHT_VALUE \ + (AW_PID_2049_I2SCHS_RIGHT << AW_PID_2049_I2SCHS_START_BIT) + +#define AW_PID_2049_I2SCHS_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SCHS_DEFAULT \ + (AW_PID_2049_I2SCHS_DEFAULT_VALUE << AW_PID_2049_I2SCHS_START_BIT) + +/* I2SRXEN bit 1 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2SRXEN_START_BIT (1) +#define AW_PID_2049_I2SRXEN_BITS_LEN (1) +#define AW_PID_2049_I2SRXEN_MASK \ + (~(((1<<AW_PID_2049_I2SRXEN_BITS_LEN)-1) << AW_PID_2049_I2SRXEN_START_BIT)) + +#define AW_PID_2049_I2SRXEN_DISABLE (0) +#define AW_PID_2049_I2SRXEN_DISABLE_VALUE \ + (AW_PID_2049_I2SRXEN_DISABLE << AW_PID_2049_I2SRXEN_START_BIT) + +#define AW_PID_2049_I2SRXEN_ENABLE (1) +#define AW_PID_2049_I2SRXEN_ENABLE_VALUE \ + (AW_PID_2049_I2SRXEN_ENABLE << AW_PID_2049_I2SRXEN_START_BIT) + +#define AW_PID_2049_I2SRXEN_DEFAULT_VALUE (1) +#define AW_PID_2049_I2SRXEN_DEFAULT \ + (AW_PID_2049_I2SRXEN_DEFAULT_VALUE << AW_PID_2049_I2SRXEN_START_BIT) + +/* I2STXEN bit 0 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2STXEN_START_BIT (0) +#define AW_PID_2049_I2STXEN_BITS_LEN (1) +#define AW_PID_2049_I2STXEN_MASK \ + (~(((1<<AW_PID_2049_I2STXEN_BITS_LEN)-1) << AW_PID_2049_I2STXEN_START_BIT)) + +#define AW_PID_2049_I2STXEN_DISABLE (0) +#define AW_PID_2049_I2STXEN_DISABLE_VALUE \ + (AW_PID_2049_I2STXEN_DISABLE << AW_PID_2049_I2STXEN_START_BIT) + +#define AW_PID_2049_I2STXEN_ENABLE (1) +#define AW_PID_2049_I2STXEN_ENABLE_VALUE \ + (AW_PID_2049_I2STXEN_ENABLE << AW_PID_2049_I2STXEN_START_BIT) + +#define AW_PID_2049_I2STXEN_DEFAULT_VALUE (0) +#define AW_PID_2049_I2STXEN_DEFAULT \ + (AW_PID_2049_I2STXEN_DEFAULT_VALUE << AW_PID_2049_I2STXEN_START_BIT) + +/* default value of I2SCFG1 (0x07) */ +/* #define AW_PID_2049_I2SCFG1_DEFAULT (0x0102) */ + +/* I2SCFG2 (0x08) detail */ +/* ULS_FIR_MD bit 14 (I2SCFG2 0x08) */ +#define AW_PID_2049_ULS_FIR_MD_START_BIT (14) +#define AW_PID_2049_ULS_FIR_MD_BITS_LEN (1) +#define AW_PID_2049_ULS_FIR_MD_MASK \ + (~(((1<<AW_PID_2049_ULS_FIR_MD_BITS_LEN)-1) << AW_PID_2049_ULS_FIR_MD_START_BIT)) + +#define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED (0) +#define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED_VALUE \ + (AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED << AW_PID_2049_ULS_FIR_MD_START_BIT) + +#define AW_PID_2049_ULS_FIR_MD_USED (1) +#define AW_PID_2049_ULS_FIR_MD_USED_VALUE \ + (AW_PID_2049_ULS_FIR_MD_USED << AW_PID_2049_ULS_FIR_MD_START_BIT) + +#define AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE (0) +#define AW_PID_2049_ULS_FIR_MD_DEFAULT \ + (AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE << AW_PID_2049_ULS_FIR_MD_START_BIT) + +/* ULS_MODE bit 13 (I2SCFG2 0x08) */ +#define AW_PID_2049_ULS_MODE_START_BIT (13) +#define AW_PID_2049_ULS_MODE_BITS_LEN (1) +#define AW_PID_2049_ULS_MODE_MASK \ + (~(((1<<AW_PID_2049_ULS_MODE_BITS_LEN)-1) << AW_PID_2049_ULS_MODE_START_BIT)) + +#define AW_PID_2049_ULS_MODE_LOWPASS (0) +#define AW_PID_2049_ULS_MODE_LOWPASS_VALUE \ + (AW_PID_2049_ULS_MODE_LOWPASS << AW_PID_2049_ULS_MODE_START_BIT) + +#define AW_PID_2049_ULS_MODE_TDM (1) +#define AW_PID_2049_ULS_MODE_TDM_VALUE \ + (AW_PID_2049_ULS_MODE_TDM << AW_PID_2049_ULS_MODE_START_BIT) + +#define AW_PID_2049_ULS_MODE_DEFAULT_VALUE (0) +#define AW_PID_2049_ULS_MODE_DEFAULT \ + (AW_PID_2049_ULS_MODE_DEFAULT_VALUE << AW_PID_2049_ULS_MODE_START_BIT) + +/* ULS_EN bit 12 (I2SCFG2 0x08) */ +#define AW_PID_2049_ULS_EN_START_BIT (12) +#define AW_PID_2049_ULS_EN_BITS_LEN (1) +#define AW_PID_2049_ULS_EN_MASK \ + (~(((1<<AW_PID_2049_ULS_EN_BITS_LEN)-1) << AW_PID_2049_ULS_EN_START_BIT)) + +#define AW_PID_2049_ULS_EN_DISABLE (0) +#define AW_PID_2049_ULS_EN_DISABLE_VALUE \ + (AW_PID_2049_ULS_EN_DISABLE << AW_PID_2049_ULS_EN_START_BIT) + +#define AW_PID_2049_ULS_EN_ENABLE (1) +#define AW_PID_2049_ULS_EN_ENABLE_VALUE \ + (AW_PID_2049_ULS_EN_ENABLE << AW_PID_2049_ULS_EN_START_BIT) + +#define AW_PID_2049_ULS_EN_DEFAULT_VALUE (0) +#define AW_PID_2049_ULS_EN_DEFAULT \ + (AW_PID_2049_ULS_EN_DEFAULT_VALUE << AW_PID_2049_ULS_EN_START_BIT) + +/* IV2CH bit 9 (I2SCFG2 0x08) */ +#define AW_PID_2049_IV2CH_START_BIT (9) +#define AW_PID_2049_IV2CH_BITS_LEN (1) +#define AW_PID_2049_IV2CH_MASK \ + (~(((1<<AW_PID_2049_IV2CH_BITS_LEN)-1) << AW_PID_2049_IV2CH_START_BIT)) + +#define AW_PID_2049_IV2CH_LEGACY (0) +#define AW_PID_2049_IV2CH_LEGACY_VALUE \ + (AW_PID_2049_IV2CH_LEGACY << AW_PID_2049_IV2CH_START_BIT) + +#define AW_PID_2049_IV2CH_SPECIAL (1) +#define AW_PID_2049_IV2CH_SPECIAL_VALUE \ + (AW_PID_2049_IV2CH_SPECIAL << AW_PID_2049_IV2CH_START_BIT) + +#define AW_PID_2049_IV2CH_DEFAULT_VALUE (0) +#define AW_PID_2049_IV2CH_DEFAULT \ + (AW_PID_2049_IV2CH_DEFAULT_VALUE << AW_PID_2049_IV2CH_START_BIT) + +/* I2S_TXEDGE bit 8 (I2SCFG2 0x08) */ +#define AW_PID_2049_I2S_TXEDGE_START_BIT (8) +#define AW_PID_2049_I2S_TXEDGE_BITS_LEN (1) +#define AW_PID_2049_I2S_TXEDGE_MASK \ + (~(((1<<AW_PID_2049_I2S_TXEDGE_BITS_LEN)-1) << AW_PID_2049_I2S_TXEDGE_START_BIT)) + +#define AW_PID_2049_I2S_TXEDGE_NEGEDGE (0) +#define AW_PID_2049_I2S_TXEDGE_NEGEDGE_VALUE \ + (AW_PID_2049_I2S_TXEDGE_NEGEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT) + +#define AW_PID_2049_I2S_TXEDGE_POSEDGE (1) +#define AW_PID_2049_I2S_TXEDGE_POSEDGE_VALUE \ + (AW_PID_2049_I2S_TXEDGE_POSEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT) + +#define AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE (0) +#define AW_PID_2049_I2S_TXEDGE_DEFAULT \ + (AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE << AW_PID_2049_I2S_TXEDGE_START_BIT) + +/* I2SDOSEL bit 7 (I2SCFG2 0x08) */ +#define AW_PID_2049_I2SDOSEL_START_BIT (7) +#define AW_PID_2049_I2SDOSEL_BITS_LEN (1) +#define AW_PID_2049_I2SDOSEL_MASK \ + (~(((1<<AW_PID_2049_I2SDOSEL_BITS_LEN)-1) << AW_PID_2049_I2SDOSEL_START_BIT)) + +#define AW_PID_2049_I2SDOSEL_ZEROS (0) +#define AW_PID_2049_I2SDOSEL_ZEROS_VALUE \ + (AW_PID_2049_I2SDOSEL_ZEROS << AW_PID_2049_I2SDOSEL_START_BIT) + +#define AW_PID_2049_I2SDOSEL_TXDATA (1) +#define AW_PID_2049_I2SDOSEL_TXDATA_VALUE \ + (AW_PID_2049_I2SDOSEL_TXDATA << AW_PID_2049_I2SDOSEL_START_BIT) + +#define AW_PID_2049_I2SDOSEL_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SDOSEL_DEFAULT \ + (AW_PID_2049_I2SDOSEL_DEFAULT_VALUE << AW_PID_2049_I2SDOSEL_START_BIT) + +/* DOHZ bit 6 (I2SCFG2 0x08) */ +#define AW_PID_2049_DOHZ_START_BIT (6) +#define AW_PID_2049_DOHZ_BITS_LEN (1) +#define AW_PID_2049_DOHZ_MASK \ + (~(((1<<AW_PID_2049_DOHZ_BITS_LEN)-1) << AW_PID_2049_DOHZ_START_BIT)) + +#define AW_PID_2049_DOHZ_ALL (0) +#define AW_PID_2049_DOHZ_ALL_VALUE \ + (AW_PID_2049_DOHZ_ALL << AW_PID_2049_DOHZ_START_BIT) + +#define AW_PID_2049_DOHZ_HIZ (1) +#define AW_PID_2049_DOHZ_HIZ_VALUE \ + (AW_PID_2049_DOHZ_HIZ << AW_PID_2049_DOHZ_START_BIT) + +#define AW_PID_2049_DOHZ_DEFAULT_VALUE (1) +#define AW_PID_2049_DOHZ_DEFAULT \ + (AW_PID_2049_DOHZ_DEFAULT_VALUE << AW_PID_2049_DOHZ_START_BIT) + +/* DRVSTREN bit 5 (I2SCFG2 0x08) */ +#define AW_PID_2049_DRVSTREN_START_BIT (5) +#define AW_PID_2049_DRVSTREN_BITS_LEN (1) +#define AW_PID_2049_DRVSTREN_MASK \ + (~(((1<<AW_PID_2049_DRVSTREN_BITS_LEN)-1) << AW_PID_2049_DRVSTREN_START_BIT)) + +#define AW_PID_2049_DRVSTREN_4MA (0) +#define AW_PID_2049_DRVSTREN_4MA_VALUE \ + (AW_PID_2049_DRVSTREN_4MA << AW_PID_2049_DRVSTREN_START_BIT) + +#define AW_PID_2049_DRVSTREN_12MA (1) +#define AW_PID_2049_DRVSTREN_12MA_VALUE \ + (AW_PID_2049_DRVSTREN_12MA << AW_PID_2049_DRVSTREN_START_BIT) + +#define AW_PID_2049_DRVSTREN_DEFAULT_VALUE (1) +#define AW_PID_2049_DRVSTREN_DEFAULT \ + (AW_PID_2049_DRVSTREN_DEFAULT_VALUE << AW_PID_2049_DRVSTREN_START_BIT) + +/* INPLEV bit 4 (I2SCFG2 0x08) */ +#define AW_PID_2049_INPLEV_START_BIT (4) +#define AW_PID_2049_INPLEV_BITS_LEN (1) +#define AW_PID_2049_INPLEV_MASK \ + (~(((1<<AW_PID_2049_INPLEV_BITS_LEN)-1) << AW_PID_2049_INPLEV_START_BIT)) + +#define AW_PID_2049_INPLEV_NOT_ATTENUATED (0) +#define AW_PID_2049_INPLEV_NOT_ATTENUATED_VALUE \ + (AW_PID_2049_INPLEV_NOT_ATTENUATED << AW_PID_2049_INPLEV_START_BIT) + +#define AW_PID_2049_INPLEV_ATTENUATED (1) +#define AW_PID_2049_INPLEV_ATTENUATED_VALUE \ + (AW_PID_2049_INPLEV_ATTENUATED << AW_PID_2049_INPLEV_START_BIT) + +#define AW_PID_2049_INPLEV_DEFAULT_VALUE (0) +#define AW_PID_2049_INPLEV_DEFAULT \ + (AW_PID_2049_INPLEV_DEFAULT_VALUE << AW_PID_2049_INPLEV_START_BIT) + +/* CFSEL bit 2:0 (I2SCFG2 0x08) */ +#define AW_PID_2049_CFSEL_START_BIT (0) +#define AW_PID_2049_CFSEL_BITS_LEN (3) +#define AW_PID_2049_CFSEL_MASK \ + (~(((1<<AW_PID_2049_CFSEL_BITS_LEN)-1) << AW_PID_2049_CFSEL_START_BIT)) + +#define AW_PID_2049_CFSEL_HAGC (0) +#define AW_PID_2049_CFSEL_HAGC_VALUE \ + (AW_PID_2049_CFSEL_HAGC << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_DFIFO (1) +#define AW_PID_2049_CFSEL_DFIFO_VALUE \ + (AW_PID_2049_CFSEL_DFIFO << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_ULS (2) +#define AW_PID_2049_CFSEL_ULS_VALUE \ + (AW_PID_2049_CFSEL_ULS << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_IVT_FS (3) +#define AW_PID_2049_CFSEL_IVT_FS_VALUE \ + (AW_PID_2049_CFSEL_IVT_FS << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_IVT_IPVT (4) +#define AW_PID_2049_CFSEL_IVT_IPVT_VALUE \ + (AW_PID_2049_CFSEL_IVT_IPVT << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_DEFAULT_VALUE (0) +#define AW_PID_2049_CFSEL_DEFAULT \ + (AW_PID_2049_CFSEL_DEFAULT_VALUE << AW_PID_2049_CFSEL_START_BIT) + +/* default value of I2SCFG2 (0x08) */ +/* #define AW_PID_2049_I2SCFG2_DEFAULT (0x0060) */ + +/* HAGCCFG1 (0x09) detail */ +/* RVTH bit 15:8 (HAGCCFG1 0x09) */ +#define AW_PID_2049_RVTH_START_BIT (8) +#define AW_PID_2049_RVTH_BITS_LEN (8) +#define AW_PID_2049_RVTH_MASK \ + (~(((1<<AW_PID_2049_RVTH_BITS_LEN)-1) << AW_PID_2049_RVTH_START_BIT)) + +#define AW_PID_2049_RVTH_DEFAULT_VALUE (0x39) +#define AW_PID_2049_RVTH_DEFAULT \ + (AW_PID_2049_RVTH_DEFAULT_VALUE << AW_PID_2049_RVTH_START_BIT) + +/* AVTH bit 7:0 (HAGCCFG1 0x09) */ +#define AW_PID_2049_AVTH_START_BIT (0) +#define AW_PID_2049_AVTH_BITS_LEN (8) +#define AW_PID_2049_AVTH_MASK \ + (~(((1<<AW_PID_2049_AVTH_BITS_LEN)-1) << AW_PID_2049_AVTH_START_BIT)) + +#define AW_PID_2049_AVTH_DEFAULT_VALUE (0x40) +#define AW_PID_2049_AVTH_DEFAULT \ + (AW_PID_2049_AVTH_DEFAULT_VALUE << AW_PID_2049_AVTH_START_BIT) + +/* default value of HAGCCFG1 (0x09) */ +/* #define AW_PID_2049_HAGCCFG1_DEFAULT (0x3940) */ + +/* HAGCCFG2 (0x0A) detail */ +/* ATTH bit 15:0 (HAGCCFG2 0x0A) */ +#define AW_PID_2049_ATTH_START_BIT (0) +#define AW_PID_2049_ATTH_BITS_LEN (16) +#define AW_PID_2049_ATTH_MASK \ + (~(((1<<AW_PID_2049_ATTH_BITS_LEN)-1) << AW_PID_2049_ATTH_START_BIT)) + +#define AW_PID_2049_ATTH_RESERVED (0) +#define AW_PID_2049_ATTH_RESERVED_VALUE \ + (AW_PID_2049_ATTH_RESERVED << AW_PID_2049_ATTH_START_BIT) + +#define AW_PID_2049_ATTH_DEFAULT_VALUE (0x0030) +#define AW_PID_2049_ATTH_DEFAULT \ + (AW_PID_2049_ATTH_DEFAULT_VALUE << AW_PID_2049_ATTH_START_BIT) + +/* default value of HAGCCFG2 (0x0A) */ +/* #define AW_PID_2049_HAGCCFG2_DEFAULT (0x0030) */ + +/* HAGCCFG3 (0x0B) detail */ +/* RTTH bit 15:0 (HAGCCFG3 0x0B) */ +#define AW_PID_2049_RTTH_START_BIT (0) +#define AW_PID_2049_RTTH_BITS_LEN (16) +#define AW_PID_2049_RTTH_MASK \ + (~(((1<<AW_PID_2049_RTTH_BITS_LEN)-1) << AW_PID_2049_RTTH_START_BIT)) + +#define AW_PID_2049_RTTH_RESERVED (0) +#define AW_PID_2049_RTTH_RESERVED_VALUE \ + (AW_PID_2049_RTTH_RESERVED << AW_PID_2049_RTTH_START_BIT) + +#define AW_PID_2049_RTTH_DEFAULT_VALUE (0x01E0) +#define AW_PID_2049_RTTH_DEFAULT \ + (AW_PID_2049_RTTH_DEFAULT_VALUE << AW_PID_2049_RTTH_START_BIT) + +/* default value of HAGCCFG3 (0x0B) */ +/* #define AW_PID_2049_HAGCCFG3_DEFAULT (0x01E0) */ + +/* HAGCCFG4 (0x0C) detail */ +/* IIC_GEN_ADDR bit 15:9 (HAGCCFG4 0x0C) */ +#define AW_PID_2049_IIC_GEN_ADDR_START_BIT (9) +#define AW_PID_2049_IIC_GEN_ADDR_BITS_LEN (7) +#define AW_PID_2049_IIC_GEN_ADDR_MASK \ + (~(((1<<AW_PID_2049_IIC_GEN_ADDR_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_ADDR_START_BIT)) + +#define AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE (0x0E) +#define AW_PID_2049_IIC_GEN_ADDR_DEFAULT \ + (AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_ADDR_START_BIT) + +/* IIC_GEN_EN bit 8 (HAGCCFG4 0x0C) */ +#define AW_PID_2049_IIC_GEN_EN_START_BIT (8) +#define AW_PID_2049_IIC_GEN_EN_BITS_LEN (1) +#define AW_PID_2049_IIC_GEN_EN_MASK \ + (~(((1<<AW_PID_2049_IIC_GEN_EN_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_EN_START_BIT)) + +#define AW_PID_2049_IIC_GEN_EN_DISABLE (0) +#define AW_PID_2049_IIC_GEN_EN_DISABLE_VALUE \ + (AW_PID_2049_IIC_GEN_EN_DISABLE << AW_PID_2049_IIC_GEN_EN_START_BIT) + +#define AW_PID_2049_IIC_GEN_EN_ENABLE (1) +#define AW_PID_2049_IIC_GEN_EN_ENABLE_VALUE \ + (AW_PID_2049_IIC_GEN_EN_ENABLE << AW_PID_2049_IIC_GEN_EN_START_BIT) + +#define AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE (0) +#define AW_PID_2049_IIC_GEN_EN_DEFAULT \ + (AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_EN_START_BIT) + +/* HOLDTH bit 7:0 (HAGCCFG4 0x0C) */ +#define AW_PID_2049_HOLDTH_START_BIT (0) +#define AW_PID_2049_HOLDTH_BITS_LEN (8) +#define AW_PID_2049_HOLDTH_MASK \ + (~(((1<<AW_PID_2049_HOLDTH_BITS_LEN)-1) << AW_PID_2049_HOLDTH_START_BIT)) + +#define AW_PID_2049_HOLDTH_RESERVED (0) +#define AW_PID_2049_HOLDTH_RESERVED_VALUE \ + (AW_PID_2049_HOLDTH_RESERVED << AW_PID_2049_HOLDTH_START_BIT) + +#define AW_PID_2049_HOLDTH_DEFAULT_VALUE (0x64) +#define AW_PID_2049_HOLDTH_DEFAULT \ + (AW_PID_2049_HOLDTH_DEFAULT_VALUE << AW_PID_2049_HOLDTH_START_BIT) + +/* default value of HAGCCFG4 (0x0C) */ +/* #define AW_PID_2049_HAGCCFG4_DEFAULT (0x1C64) */ + +/* AGC_DSP_CTL bit 15 (HAGCCFG7 0x0F) */ +#define AW_PID_2049_AGC_DSP_CTL_START_BIT (15) +#define AW_PID_2049_AGC_DSP_CTL_BITS_LEN (1) +#define AW_PID_2049_AGC_DSP_CTL_MASK \ + (~(((1<<AW_PID_2049_AGC_DSP_CTL_BITS_LEN)-1) << AW_PID_2049_AGC_DSP_CTL_START_BIT)) + +#define AW_PID_2049_AGC_DSP_CTL_DISABLE (0) +#define AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE \ + (AW_PID_2049_AGC_DSP_CTL_DISABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT) + +#define AW_PID_2049_AGC_DSP_CTL_ENABLE (1) +#define AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE \ + (AW_PID_2049_AGC_DSP_CTL_ENABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT) +/* VDSEL bit 0 (I2SCFG3 0x12) */ +#define AW_PID_2049_VDSEL_START_BIT (0) +#define AW_PID_2049_VDSEL_BITS_LEN (1) +#define AW_PID_2049_VDSEL_MASK \ + (~(((1<<AW_PID_2049_VDSEL_BITS_LEN)-1) << AW_PID_2049_VDSEL_START_BIT)) + +/* MEM_CLKSEL bit 3 (DBGCTRL 0x13) */ +#define AW_PID_2049_MEM_CLKSEL_START_BIT (3) +#define AW_PID_2049_MEM_CLKSEL_BITS_LEN (1) +#define AW_PID_2049_MEM_CLKSEL_MASK \ + (~(((1<<AW_PID_2049_MEM_CLKSEL_BITS_LEN)-1) << AW_PID_2049_MEM_CLKSEL_START_BIT)) + +#define AW_PID_2049_MEM_CLKSEL_OSC_CLK (0) +#define AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE \ + (AW_PID_2049_MEM_CLKSEL_OSC_CLK << AW_PID_2049_MEM_CLKSEL_START_BIT) + +#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK (1) +#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE \ + (AW_PID_2049_MEM_CLKSEL_DAP_HCLK << AW_PID_2049_MEM_CLKSEL_START_BIT) + +/* HAGCST (0x20) detail */ +/* SPK_GAIN_ST bit 10:8 (HAGCST 0x20) */ +#define AW_PID_2049_SPK_GAIN_ST_START_BIT (8) +#define AW_PID_2049_SPK_GAIN_ST_BITS_LEN (3) +#define AW_PID_2049_SPK_GAIN_ST_MASK \ + (~(((1<<AW_PID_2049_SPK_GAIN_ST_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_ST_START_BIT)) + +#define AW_PID_2049_SPK_GAIN_ST_4_AV (0) +#define AW_PID_2049_SPK_GAIN_ST_4_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_4_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_4P67_AV (1) +#define AW_PID_2049_SPK_GAIN_ST_4P67_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_4P67_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_6_AV (2) +#define AW_PID_2049_SPK_GAIN_ST_6_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_6_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_7_AV (3) +#define AW_PID_2049_SPK_GAIN_ST_7_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_7_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_12_AV (4) +#define AW_PID_2049_SPK_GAIN_ST_12_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_12_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_14_AV (5) +#define AW_PID_2049_SPK_GAIN_ST_14_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_14_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE (5) +#define AW_PID_2049_SPK_GAIN_ST_DEFAULT \ + (AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +/* BSTVOUT_ST bit 5:0 (HAGCST 0x20) */ +#define AW_PID_2049_BSTVOUT_ST_START_BIT (0) +#define AW_PID_2049_BSTVOUT_ST_BITS_LEN (6) +#define AW_PID_2049_BSTVOUT_ST_MASK \ + (~(((1<<AW_PID_2049_BSTVOUT_ST_BITS_LEN)-1) << AW_PID_2049_BSTVOUT_ST_START_BIT)) + +#define AW_PID_2049_BSTVOUT_ST_3P125V (0) +#define AW_PID_2049_BSTVOUT_ST_3P125V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P125V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P250V (1) +#define AW_PID_2049_BSTVOUT_ST_3P250V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P250V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P375V (2) +#define AW_PID_2049_BSTVOUT_ST_3P375V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P375V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P500V (3) +#define AW_PID_2049_BSTVOUT_ST_3P500V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P500V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P625V (4) +#define AW_PID_2049_BSTVOUT_ST_3P625V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P625V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P750V (5) +#define AW_PID_2049_BSTVOUT_ST_3P750V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P750V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_11P000V (63) +#define AW_PID_2049_BSTVOUT_ST_11P000V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_11P000V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTVOUT_ST_DEFAULT \ + (AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE << AW_PID_2049_BSTVOUT_ST_START_BIT) + +/* default value of HAGCST (0x20) */ +/* #define AW_PID_2049_HAGCST_DEFAULT (0x0500) */ + +/* VBAT (0x21) detail */ +/* VBAT_DET bit 9:0 (VBAT 0x21) */ +#define AW_PID_2049_VBAT_DET_START_BIT (0) +#define AW_PID_2049_VBAT_DET_BITS_LEN (10) +#define AW_PID_2049_VBAT_DET_MASK \ + (~(((1<<AW_PID_2049_VBAT_DET_BITS_LEN)-1) << AW_PID_2049_VBAT_DET_START_BIT)) + +#define AW_PID_2049_VBAT_DET_DEFAULT_VALUE (0x263) +#define AW_PID_2049_VBAT_DET_DEFAULT \ + (AW_PID_2049_VBAT_DET_DEFAULT_VALUE << AW_PID_2049_VBAT_DET_START_BIT) + +#define AW_PID_2049_VBAT_RANGE (6025) +#define AW_PID_2049_INT_10BIT (1023) +/* default value of VBAT (0x21) */ +/* #define AW_PID_2049_VBAT_DEFAULT (0x0263) */ + +/* TEMP (0x22) detail */ +/* TEMP_DET bit 9:0 (TEMP 0x22) */ +#define AW_PID_2049_TEMP_DET_START_BIT (0) +#define AW_PID_2049_TEMP_DET_BITS_LEN (10) +#define AW_PID_2049_TEMP_DET_MASK \ + (~(((1<<AW_PID_2049_TEMP_DET_BITS_LEN)-1) << AW_PID_2049_TEMP_DET_START_BIT)) + +#define AW_PID_2049_TEMP_DET_MINUS_40 (0x3D8) +#define AW_PID_2049_TEMP_DET_MINUS_40_VALUE \ + (AW_PID_2049_TEMP_DET_MINUS_40 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_0 (0x00) +#define AW_PID_2049_TEMP_DET_0_VALUE \ + (AW_PID_2049_TEMP_DET_0 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_1 (0x01) +#define AW_PID_2049_TEMP_DET_1_VALUE \ + (AW_PID_2049_TEMP_DET_1 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_25 (0x19) +#define AW_PID_2049_TEMP_DET_25_VALUE \ + (AW_PID_2049_TEMP_DET_25 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_55 (0x37) +#define AW_PID_2049_TEMP_DET_55_VALUE \ + (AW_PID_2049_TEMP_DET_55 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_DEFAULT_VALUE (0x019) +#define AW_PID_2049_TEMP_DET_DEFAULT \ + (AW_PID_2049_TEMP_DET_DEFAULT_VALUE << AW_PID_2049_TEMP_DET_START_BIT) +#define AW_PID_2049_TEMP_SIGN_MASK (~(1 << 9)) +#define AW_PID_2049_TEMP_NEG_MASK (0XFC00) + +/* default value of TEMP (0x22) */ +/* #define AW_PID_2049_TEMP_DEFAULT (0x0019) */ + +/* PVDD (0x23) detail */ +/* PVDD_DET bit 9:0 (PVDD 0x23) */ +#define AW_PID_2049_PVDD_DET_START_BIT (0) +#define AW_PID_2049_PVDD_DET_BITS_LEN (10) +#define AW_PID_2049_PVDD_DET_MASK \ + (~(((1<<AW_PID_2049_PVDD_DET_BITS_LEN)-1) << AW_PID_2049_PVDD_DET_START_BIT)) + +#define AW_PID_2049_PVDD_DET_DEFAULT_VALUE (0x263) +#define AW_PID_2049_PVDD_DET_DEFAULT \ + (AW_PID_2049_PVDD_DET_DEFAULT_VALUE << AW_PID_2049_PVDD_DET_START_BIT) + +/* default value of PVDD (0x23) */ +/* #define AW_PID_2049_PVDD_DEFAULT (0x0263) */ + +/* BSTCTRL1 (0x60) detail */ +/* BST_RTH bit 13:8 (BSTCTRL1 0x60) */ +#define AW_PID_2049_BST_RTH_START_BIT (8) +#define AW_PID_2049_BST_RTH_BITS_LEN (6) +#define AW_PID_2049_BST_RTH_MASK \ + (~(((1<<AW_PID_2049_BST_RTH_BITS_LEN)-1) << AW_PID_2049_BST_RTH_START_BIT)) + +#define AW_PID_2049_BST_RTH_DEFAULT_VALUE (4) +#define AW_PID_2049_BST_RTH_DEFAULT \ + (AW_PID_2049_BST_RTH_DEFAULT_VALUE << AW_PID_2049_BST_RTH_START_BIT) + +/* BST_ATH bit 5:0 (BSTCTRL1 0x60) */ +#define AW_PID_2049_BST_ATH_START_BIT (0) +#define AW_PID_2049_BST_ATH_BITS_LEN (6) +#define AW_PID_2049_BST_ATH_MASK \ + (~(((1<<AW_PID_2049_BST_ATH_BITS_LEN)-1) << AW_PID_2049_BST_ATH_START_BIT)) + +#define AW_PID_2049_BST_ATH_DEFAULT_VALUE (2) +#define AW_PID_2049_BST_ATH_DEFAULT \ + (AW_PID_2049_BST_ATH_DEFAULT_VALUE << AW_PID_2049_BST_ATH_START_BIT) + +/* default value of BSTCTRL1 (0x60) */ +/* #define AW_PID_2049_BSTCTRL1_DEFAULT (0x0402) */ + +/* BSTCTRL2 (0x61) detail */ +/* BST_MODE bit 14:12 (BSTCTRL2 0x61) */ +#define AW_PID_2049_BST_MODE_START_BIT (12) +#define AW_PID_2049_BST_MODE_BITS_LEN (3) +#define AW_PID_2049_BST_MODE_MASK \ + (~(((1<<AW_PID_2049_BST_MODE_BITS_LEN)-1) << AW_PID_2049_BST_MODE_START_BIT)) + +#define AW_PID_2049_BST_MODE_TRANSPARENT (0) +#define AW_PID_2049_BST_MODE_TRANSPARENT_VALUE \ + (AW_PID_2049_BST_MODE_TRANSPARENT << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_FORCE_BOOST (1) +#define AW_PID_2049_BST_MODE_FORCE_BOOST_VALUE \ + (AW_PID_2049_BST_MODE_FORCE_BOOST << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_SMART_BOOST1 (5) +#define AW_PID_2049_BST_MODE_SMART_BOOST1_VALUE \ + (AW_PID_2049_BST_MODE_SMART_BOOST1 << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_SMART_BOOST2 (6) +#define AW_PID_2049_BST_MODE_SMART_BOOST2_VALUE \ + (AW_PID_2049_BST_MODE_SMART_BOOST2 << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_DEFAULT_VALUE (0x6) +#define AW_PID_2049_BST_MODE_DEFAULT \ + (AW_PID_2049_BST_MODE_DEFAULT_VALUE << AW_PID_2049_BST_MODE_START_BIT) + +/* WDT_CNT bit 7:0 (WDT 0x42) */ +#define AW_PID_2049_WDT_CNT_START_BIT (0) +#define AW_PID_2049_WDT_CNT_BITS_LEN (8) +#define AW_PID_2049_WDT_CNT_MASK \ + (~(((1<<AW_PID_2049_WDT_CNT_BITS_LEN)-1) << AW_PID_2049_WDT_CNT_START_BIT)) + +/* BST_TDEG bit 11:8 (BSTCTRL2 0x61) */ +#define AW_PID_2049_BST_TDEG_START_BIT (8) +#define AW_PID_2049_BST_TDEG_BITS_LEN (4) +#define AW_PID_2049_BST_TDEG_MASK \ + (~(((1<<AW_PID_2049_BST_TDEG_BITS_LEN)-1) << AW_PID_2049_BST_TDEG_START_BIT)) + +#define AW_PID_2049_BST_TDEG_0P50_MS (0) +#define AW_PID_2049_BST_TDEG_0P50_MS_VALUE \ + (AW_PID_2049_BST_TDEG_0P50_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_1P00_MS (1) +#define AW_PID_2049_BST_TDEG_1P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_1P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_2P00_MS (2) +#define AW_PID_2049_BST_TDEG_2P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_2P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_4P00_MS (3) +#define AW_PID_2049_BST_TDEG_4P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_4P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_8P00_MS (4) +#define AW_PID_2049_BST_TDEG_8P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_8P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_10P7_MS (5) +#define AW_PID_2049_BST_TDEG_10P7_MS_VALUE \ + (AW_PID_2049_BST_TDEG_10P7_MS << AW_PID_2049_BST_TDEG_START_BIT) + +/* ReAbs bit 3 (ASR1 0x45) */ +#define AW_PID_2049_ReAbs_START_BIT (3) +#define AW_PID_2049_ReAbs_BITS_LEN (1) +#define AW_PID_2049_ReAbs_MASK \ + (~(((1<<AW_PID_2049_ReAbs_BITS_LEN)-1) << AW_PID_2049_ReAbs_START_BIT)) + +#define AW_PID_2049_BST_TDEG_13P3_MS (6) +#define AW_PID_2049_BST_TDEG_13P3_MS_VALUE \ + (AW_PID_2049_BST_TDEG_13P3_MS << AW_PID_2049_BST_TDEG_START_BIT) + +/* DSP_VOL bit 15:8 (DSPCFG 0x47) */ +#define AW_PID_2049_DSP_VOL_START_BIT (8) +#define AW_PID_2049_DSP_VOL_BITS_LEN (8) +#define AW_PID_2049_DSP_VOL_MASK \ + (~(((1<<AW_PID_2049_DSP_VOL_BITS_LEN)-1) << AW_PID_2049_DSP_VOL_START_BIT)) + +#define AW_PID_2049_DSP_VOL_MUTE (0XFF00) +#define AW_PID_2049_DSP_VOL_NOISE_ST (0X1800) + +#define AW_PID_2049_BST_TDEG_16P0_MS (7) +#define AW_PID_2049_BST_TDEG_16P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_16P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_18P6_MS (8) +#define AW_PID_2049_BST_TDEG_18P6_MS_VALUE \ + (AW_PID_2049_BST_TDEG_18P6_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_21P3_MS (9) +#define AW_PID_2049_BST_TDEG_21P3_MS_VALUE \ + (AW_PID_2049_BST_TDEG_21P3_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_24P0_MS (10) +#define AW_PID_2049_BST_TDEG_24P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_24P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_32P0_MS (11) +#define AW_PID_2049_BST_TDEG_32P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_32P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_64P0_MS (12) +#define AW_PID_2049_BST_TDEG_64P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_64P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_128_MS (13) +#define AW_PID_2049_BST_TDEG_128_MS_VALUE \ + (AW_PID_2049_BST_TDEG_128_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_256_MS (14) +#define AW_PID_2049_BST_TDEG_256_MS_VALUE \ + (AW_PID_2049_BST_TDEG_256_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_1200_MS (15) +#define AW_PID_2049_BST_TDEG_1200_MS_VALUE \ + (AW_PID_2049_BST_TDEG_1200_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_DEFAULT_VALUE (11) +#define AW_PID_2049_BST_TDEG_DEFAULT \ + (AW_PID_2049_BST_TDEG_DEFAULT_VALUE << AW_PID_2049_BST_TDEG_START_BIT) + +/* VOUT_VREFSET bit 5:0 (BSTCTRL2 0x61) */ +/* CCO_MUX bit 14 (PLLCTRL1 0x52) */ +#define AW_PID_2049_CCO_MUX_START_BIT (14) +#define AW_PID_2049_CCO_MUX_BITS_LEN (1) +#define AW_PID_2049_CCO_MUX_MASK \ + (~(((1<<AW_PID_2049_CCO_MUX_BITS_LEN)-1) << AW_PID_2049_CCO_MUX_START_BIT)) + +#define AW_PID_2049_CCO_MUX_DIVIDED (0) +#define AW_PID_2049_CCO_MUX_DIVIDED_VALUE \ + (AW_PID_2049_CCO_MUX_DIVIDED << AW_PID_2049_CCO_MUX_START_BIT) + +#define AW_PID_2049_CCO_MUX_BYPASS (1) +#define AW_PID_2049_CCO_MUX_BYPASS_VALUE \ + (AW_PID_2049_CCO_MUX_BYPASS << AW_PID_2049_CCO_MUX_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_START_BIT (0) +#define AW_PID_2049_VOUT_VREFSET_BITS_LEN (6) +#define AW_PID_2049_VOUT_VREFSET_MASK \ + (~(((1<<AW_PID_2049_VOUT_VREFSET_BITS_LEN)-1) << AW_PID_2049_VOUT_VREFSET_START_BIT)) + +#define AW_PID_2049_VOUT_VREFSET_3P125V (0) +#define AW_PID_2049_VOUT_VREFSET_3P125V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P125V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P250V (1) +#define AW_PID_2049_VOUT_VREFSET_3P250V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P250V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P375V (2) +#define AW_PID_2049_VOUT_VREFSET_3P375V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P375V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P500V (3) +#define AW_PID_2049_VOUT_VREFSET_3P500V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P500V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P625V (4) +#define AW_PID_2049_VOUT_VREFSET_3P625V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P625V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P750V (5) +#define AW_PID_2049_VOUT_VREFSET_3P750V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P750V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_11P000V (63) +#define AW_PID_2049_VOUT_VREFSET_11P000V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_11P000V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE (0x33) +#define AW_PID_2049_VOUT_VREFSET_DEFAULT \ + (AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE << AW_PID_2049_VOUT_VREFSET_START_BIT) + +/* default value of BSTCTRL2 (0x61) */ +/* #define AW_PID_2049_BSTCTRL2_DEFAULT (0x6B33) */ + +/* detail information of registers end */ + +/* EF_VSN_GESLP bit 9:0 (EFRH 0x78) */ +#define AW_PID_2049_EF_VSN_GESLP_START_BIT (0) +#define AW_PID_2049_EF_VSN_GESLP_BITS_LEN (10) +#define AW_PID_2049_EF_VSN_GESLP_MASK \ + (~(((1<<AW_PID_2049_EF_VSN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_VSN_GESLP_START_BIT)) + +#define AW_PID_2049_EF_VSN_GESLP_SIGN_MASK (~(1 << 9)) +#define AW_PID_2049_EF_VSN_GESLP_SIGN_NEG (0xfe00) +/* EF_ISN_GESLP bit 9:0 (EFRM2 0x79) */ +#define AW_PID_2049_EF_ISN_GESLP_START_BIT (0) +#define AW_PID_2049_EF_ISN_GESLP_BITS_LEN (10) +#define AW_PID_2049_EF_ISN_GESLP_MASK \ + (~(((1<<AW_PID_2049_EF_ISN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_ISN_GESLP_START_BIT)) + +#define AW_PID_2049_EF_ISN_GESLP_SIGN_MASK (~(1 << 9)) +#define AW_PID_2049_EF_ISN_GESLP_SIGN_NEG (0xfe00) +/* + * Vcalb + */ + +#define AW_PID_2049_CABL_BASE_VALUE (1000) +#define AW_PID_2049_ICABLK_FACTOR (1) +#define AW_PID_2049_VCABLK_FACTOR (1) +#define AW_PID_2049_VCAL_FACTOR (1 << 12) +#define AW_PID_2049_VSCAL_FACTOR (16500) +#define AW_PID_2049_ISCAL_FACTOR (3667) +#define AW_PID_2049_EF_VSENSE_GAIN_SHIFT (0) + +#define AW_PID_2049_VCABLK_FACTOR_DAC (2) +#define AW_PID_2049_VSCAL_FACTOR_DAC (11790) +#define AW_PID_2049_EF_DAC_GESLP_SHIFT (10) +#define AW_PID_2049_EF_DAC_GESLP_SIGN_MASK (1 << 5) +#define AW_PID_2049_EF_DAC_GESLP_SIGN_NEG (0xffc0) + +#define AW_PID_2049_VCALB_ADJ_FACTOR (12) + +/* + * AW883XX DSP + */ +#define AW_PID_2049_DSP_CFG_ADDR (0x9C80) +#define AW_PID_2049_DSP_FW_ADDR (0x8C00) + +#define AW_PID_2049_DSP_REG_RESULT_F0 (0x9C58) +#define AW_PID_2049_DSP_F0_SHIFT (1) + +#define AW_PID_2049_DSP_REG_CALRE (0x9C5A) +#define AW_PID_2049_DSP_REG_CALRE_SHIFT (10) +#define AW_PID_2049_DSP_REG_RESULT_Q (0x9C5C) +#define AW_PID_2049_DSP_Q_SHIFT (11) + +#define AW_PID_2049_DSP_REG_VMAX (0x9C94) + + +#define AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG (0x9CE2) +/* bit 0 */ +#define AW_PID_2049_DSP_MONITOR_MASK (~(1 << 0)) +#define AW_PID_2049_DSP_MONITOR_ENABLE (1 << 0) +#define AW_PID_2049_DSP_MONITOR_DISABLE (0 << 0) +/*bit 4*/ +#define AW_PID_2049_DSP_REG_NOISE_MASK (~(1 << 4)) + +#define AW_PID_2049_DSP_TEMP_PEAK_MASK (~(1 << 4)) +#define AW_PID_2049_DSP_TEMP_SEL_FLAG (~(1 << 14)) + +#define AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH (0x9CE4)/*32bit*/ +#define AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH (0x9CE6)/*32bit*/ +#define AW_PID_2049_DSP_REG_VCALB (0x9CF7) + +#define AW_PID_2049_DSP_REG_CFG_ADPZ_RE (0x9D00)/*32bit*/ +#define AW_PID_2049_DSP_RE_SHIFT (12) + +#define AW_PID_2049_DSP_REG_CFG_ADPZ_RA (0x9D02)/*32bit*/ + +#define AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN (0x9D08) + + +#define AW_PID_2049_DSP_REG_CRC_ADDR (0x9F42)/*32bit*/ +#define AW_PID_2049_DSP_REG_CFGF0_FS (0x9F44)/*32bit*/ +#define AW_PID_2049_DSP_REG_CFG_RE_ALPHA (0x9F47) +#define AW_PID_2049_DSP_REG_TEMP_ADDR (0x9C5D) +#define AW_PID_2049_DSP_REG_TEMP_SWITCH (0x9D71)/*16bit*/ +#define AW_PID_2049_DSP_CALI_F0_DELAY (0x9CFD) +#define AW_PID_2049_DSP_CFG_ADPZ_T0 (0x9D11)/*16bit*/ +#define AW_PID_2049_DSP_CFG_ADPZ_COILALPHA (0x9D0F)/*16bit*/ +#define AW_PID_2049_DSP_ST_S1 (0x8180) +#define AW_PID_2049_DSP_ST_E1 (0x83FD) +#define AW_PID_2049_DSP_ST_S2 (0x9C00) +#define AW_PID_2049_DSP_ST_E2 (0x9C5D) + +#endif /* #ifndef __AW_PID_2049_REG_H__ */

On 15/11/2022 03:24, wangweidong.a@awinic.com wrote:

From: Weidong Wang wangweidong.a@awinic.com

Add a DT schema for describing Awinic AW883xx audio amplifiers. They are controlled using I2C.

Signed-off-by: Weidong Wang wangweidong.a@awinic.com

.../bindings/sound/awinic,aw883xx.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml

diff --git a/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml new file mode 100644 index 000000000000..04cdcf25a6d4 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/awinic,aw883xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: Awinic AW883xx Smart Audio Amplifier

+maintainers:

• • Stephan Gerhold stephan@gerhold.net

+description:

• The Awinic AW883XX is an I2S/TDM input, high efficiency
• digital Smart K audio amplifier with an integrated 10.25V
• smart boost convert.

+allOf:

• • $ref: name-prefix.yaml#

+properties:

• compatible:
• const: awinic,aw883xx_smartpa
• reg:
• description:

•  The I2C address of the device for I2C
  

What happened here? This was not present before. Drop description.

• maxItems: 1
• reset-gpios:
• description:

•  Reset pin of aw883xx chip
  

The same case. Drop description.

I commented only for irq-gpios that they need description.

• maxItems: 1
• sound-channel:
• description:

•  Number of sound channels of the aw883xx chip
  

Your description does not explain me much. Number of supported sound channels is usually fixed in the hardware, thus coming from compatible. Therefore this might mean something else... but anyway your driver does not use it really, so just drop it.

Best regards, Krzysztof

From: Weidong Wang wangweidong.a@awinic.com

Modified the Makefile and Kconfig to compile aw883xx

Signed-off-by: Weidong Wang wangweidong.a@awinic.com --- sound/soc/codecs/Kconfig | 10 ++++++++++ sound/soc/codecs/Makefile | 7 +++++++ 2 files changed, 17 insertions(+)

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 7022e6286e6c..f14e0a78acd4 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -54,6 +54,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_ALC5623 imply SND_SOC_ALC5632 imply SND_SOC_AW8738 + imply SND_SOC_AW883XX imply SND_SOC_BT_SCO imply SND_SOC_BD28623 imply SND_SOC_CQ0093VC @@ -2161,4 +2162,13 @@ config SND_SOC_LPASS_TX_MACRO select SND_SOC_LPASS_MACRO_COMMON tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)"

+config SND_SOC_AW883XX + tristate "Soc Audio for awinic aw883xx series" + depends on I2C + help + this option enables support for aw883xx series Smart PA. + The Awinic AW883XX is an I2S/TDM input, high efficiency + digital Smart K audio amplifier with an integrated 10V + smart boost convert. + endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9170ee1447dd..858ca24ad398 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -357,6 +357,11 @@ snd-soc-tas2780-objs := tas2780.o # Mux snd-soc-simple-mux-objs := simple-mux.o

+snd_soc_aw883xx-objs := aw883xx/aw883xx.o \ + aw883xx/aw883xx_init.o \ + aw883xx/aw883xx_device.o \ + aw883xx/aw883xx_bin_parse.o \ + obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o @@ -719,3 +724,5 @@ obj-$(CONFIG_SND_SOC_LPASS_TX_MACRO) += snd-soc-lpass-tx-macro.o

# Mux obj-$(CONFIG_SND_SOC_SIMPLE_MUX) += snd-soc-simple-mux.o + +obj-$(CONFIG_SND_SOC_AW883XX) +=snd_soc_aw883xx.o