[PATCH v1 0/2] Revise mt8186 ADSP clock driver
Initialize the dependent clock sources for mt8186 ADSP and fix the enable/disable order of ADSP clocks.
--- Tinghan Shen (2): dt-bindings: dsp: mediatek: Add default clock sources for mt8186 dsp ASoC: SOF: mediatek: Revise mt8186 ADSP clock driver
.../bindings/dsp/mediatek,mt8186-dsp.yaml | 12 +++++-- sound/soc/sof/mediatek/mt8186/mt8186-clk.c | 35 +++++++++++++++---- sound/soc/sof/mediatek/mt8186/mt8186-clk.h | 2 ++ 3 files changed, 39 insertions(+), 10 deletions(-)
Add the default clock sources used by mt8186 dsp.
Signed-off-by: Tinghan Shen tinghan.shen@mediatek.com --- .../devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml index 3e63f79890b4..4cc0634c876b 100644 --- a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml @@ -35,11 +35,15 @@ properties: items: - description: mux for audio dsp clock - description: mux for audio dsp local bus + - description: default clock source for dsp local bus + - description: default clock source for dsp core
clock-names: items: - const: audiodsp - const: adsp_bus + - const: mainpll_d2_d2 + - const: clk26m
power-domains: maxItems: 1 @@ -82,9 +86,11 @@ examples: <0x1068f000 0x1000>; reg-names = "cfg", "sram", "sec", "bus"; clocks = <&topckgen CLK_TOP_AUDIODSP>, - <&topckgen CLK_TOP_ADSP_BUS>; - clock-names = "audiodsp", - "adsp_bus"; + <&topckgen CLK_TOP_ADSP_BUS>, + <&topckgen CLK_TOP_MAINPLL_D2_D2>, + <&clk26m>; + clock-names = "audiodsp", "adsp_bus", + "mainpll_d2_d2", "clk26m"; power-domains = <&spm 6>; mbox-names = "rx", "tx"; mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
Il 01/11/22 07:11, Tinghan Shen ha scritto:
Add the default clock sources used by mt8186 dsp.
Signed-off-by: Tinghan Shen tinghan.shen@mediatek.com
.../devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml index 3e63f79890b4..4cc0634c876b 100644 --- a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml @@ -35,11 +35,15 @@ properties: items: - description: mux for audio dsp clock - description: mux for audio dsp local bus
- description: default clock source for dsp local bus- description: default clock source for dsp coreclock-names: items: - const: audiodsp - const: adsp_bus
- const: mainpll_d2_d2- const: clk26mpower-domains: maxItems: 1
@@ -82,9 +86,11 @@ examples: <0x1068f000 0x1000>; reg-names = "cfg", "sram", "sec", "bus"; clocks = <&topckgen CLK_TOP_AUDIODSP>,
<&topckgen CLK_TOP_ADSP_BUS>;clock-names = "audiodsp","adsp_bus";
<&topckgen CLK_TOP_ADSP_BUS>,<&topckgen CLK_TOP_MAINPLL_D2_D2>,<&clk26m>;clock-names = "audiodsp", "adsp_bus","mainpll_d2_d2", "clk26m";
You are assigning those clocks just to be able to call clk_set_parent() in the DSP mt8186-clk driver... and that's not necessary, nor it is the best way of doing what you're trying to.
In reality, you don't need to add new clocks and you don't need to manage that into the driver, as you can simply assign clock parents in devicetree ... like:
assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
without any clk_set_parent() call in the driver.
When the driver will call clk_prepare_enable() for top_audiodsp and/or for top_adsp_bus, the assigned parents' refcount will also be increased (and if the parent clock is not enabled, the clk framework will enable it).
Regards, Angelo
On Wed, 2022-11-02 at 10:13 +0100, AngeloGioacchino Del Regno wrote:
Il 01/11/22 07:11, Tinghan Shen ha scritto:
Add the default clock sources used by mt8186 dsp.
Signed-off-by: Tinghan Shen tinghan.shen@mediatek.com
.../devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml
b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml
index 3e63f79890b4..4cc0634c876b 100644 --- a/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8186-dsp.yaml @@ -35,11 +35,15 @@ properties: items: - description: mux for audio dsp clock - description: mux for audio dsp local bus
- description: default clock source for dsp local bus- description: default clock source for dsp coreclock-names: items: - const: audiodsp - const: adsp_bus
- const: mainpll_d2_d2- const: clk26mpower-domains: maxItems: 1
@@ -82,9 +86,11 @@ examples: <0x1068f000 0x1000>; reg-names = "cfg", "sram", "sec", "bus"; clocks = <&topckgen CLK_TOP_AUDIODSP>,
<&topckgen CLK_TOP_ADSP_BUS>;clock-names = "audiodsp","adsp_bus";
<&topckgen CLK_TOP_ADSP_BUS>,<&topckgen CLK_TOP_MAINPLL_D2_D2>,<&clk26m>;clock-names = "audiodsp", "adsp_bus","mainpll_d2_d2", "clk26m";You are assigning those clocks just to be able to call clk_set_parent() in the DSP mt8186-clk driver... and that's not necessary, nor it is the best way of doing what you're trying to.
In reality, you don't need to add new clocks and you don't need to manage that into the driver, as you can simply assign clock parents in devicetree ... like:
assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
without any clk_set_parent() call in the driver.
When the driver will call clk_prepare_enable() for top_audiodsp and/or for top_adsp_bus, the assigned parents' refcount will also be increased (and if the parent clock is not enabled, the clk framework will enable it).
Regards, Angelo
Hi Angelo,
Thank you very much!
I will abandon this series. Thank you!
-- Best regards, TingHan
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Initialize the required clocks for mt8186 ADSP. The ADSP core is expected booting with 26M clock, and using the mainpll_d2_d2 clock for ADSP bus.
The enable/disable order of clocks is also revised. The clock should be enabled as mainpll_d2_d2 -> adsp bus -> adsp, and disabled in the reversed order.
Fixes: 210b3ab932f7 ("ASoC: SOF: mediatek: Add mt8186 dsp clock support") Signed-off-by: Tinghan Shen tinghan.shen@mediatek.com --- sound/soc/sof/mediatek/mt8186/mt8186-clk.c | 35 +++++++++++++++++----- sound/soc/sof/mediatek/mt8186/mt8186-clk.h | 2 ++ 2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/sound/soc/sof/mediatek/mt8186/mt8186-clk.c b/sound/soc/sof/mediatek/mt8186/mt8186-clk.c index 2df3b7ae1c6f..c86391aa7948 100644 --- a/sound/soc/sof/mediatek/mt8186/mt8186-clk.c +++ b/sound/soc/sof/mediatek/mt8186/mt8186-clk.c @@ -20,6 +20,8 @@ static const char *adsp_clks[ADSP_CLK_MAX] = { [CLK_TOP_AUDIODSP] = "audiodsp", [CLK_TOP_ADSP_BUS] = "adsp_bus", + [CLK_TOP_MAINPLL_D2_D2] = "mainpll_d2_d2", + [CLK_TOP_CLK26M] = "clk26m", };
int mt8186_adsp_init_clock(struct snd_sof_dev *sdev) @@ -48,18 +50,36 @@ static int adsp_enable_all_clock(struct snd_sof_dev *sdev) struct device *dev = sdev->dev; int ret;
- ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIODSP]); + ret = clk_set_parent(priv->clk[CLK_TOP_AUDIODSP], priv->clk[CLK_TOP_CLK26M]); + if (ret) { + dev_err(dev, "set audiodsp clock fail %d\n", ret); + return ret; + } + + ret = clk_set_parent(priv->clk[CLK_TOP_ADSP_BUS], priv->clk[CLK_TOP_MAINPLL_D2_D2]); + if (ret) { + dev_err(dev, "set adsp bus clock fail %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(priv->clk[CLK_TOP_MAINPLL_D2_D2]); if (ret) { - dev_err(dev, "%s clk_prepare_enable(audiodsp) fail %d\n", - __func__, ret); + dev_err(dev, "clk_prepare_enable(mainpll_d2_d2) fail %d\n", ret); return ret; }
ret = clk_prepare_enable(priv->clk[CLK_TOP_ADSP_BUS]); if (ret) { - dev_err(dev, "%s clk_prepare_enable(adsp_bus) fail %d\n", - __func__, ret); - clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]); + dev_err(dev, "clk_prepare_enable(adsp_bus) fail %d\n", ret); + clk_disable_unprepare(priv->clk[CLK_TOP_MAINPLL_D2_D2]); + return ret; + } + + ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIODSP]); + if (ret) { + dev_err(dev, "clk_prepare_enable(audiodsp) fail %d\n", ret); + clk_disable_unprepare(priv->clk[CLK_TOP_MAINPLL_D2_D2]); + clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]); return ret; }
@@ -70,8 +90,9 @@ static void adsp_disable_all_clock(struct snd_sof_dev *sdev) { struct adsp_priv *priv = sdev->pdata->hw_pdata;
- clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]); clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]); + clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]); + clk_disable_unprepare(priv->clk[CLK_TOP_MAINPLL_D2_D2]); }
int mt8186_adsp_clock_on(struct snd_sof_dev *sdev) diff --git a/sound/soc/sof/mediatek/mt8186/mt8186-clk.h b/sound/soc/sof/mediatek/mt8186/mt8186-clk.h index 89c23caf0fee..37f5cfa2b230 100644 --- a/sound/soc/sof/mediatek/mt8186/mt8186-clk.h +++ b/sound/soc/sof/mediatek/mt8186/mt8186-clk.h @@ -15,6 +15,8 @@ struct snd_sof_dev; enum adsp_clk_id { CLK_TOP_AUDIODSP, CLK_TOP_ADSP_BUS, + CLK_TOP_MAINPLL_D2_D2, + CLK_TOP_CLK26M, ADSP_CLK_MAX };
participants (3)
-
AngeloGioacchino Del Regno -
Tinghan Shen -
TingHan Shen (沈廷翰)