[alsa-devel] [PATCH RESEND 0/3] conf: Add vendor tuples in conf
Topology changes in alsa-lib allow driver data for modules to be be passed in topology conf file using tuples. These changes allow private data to represented by tuples of type UUID, byte, short, word and strings.
This patch series adds changes to : - include tuple and token list in the conf file to define module private data. - Private data blobs for modules are no longer required. So, remove the binary blobs and the tool used to generate the blobs. - Then add bxt conf file which is based on tuples
Shreyas NC (3): conf: sklrt286: define module private data through tuples in skylake conf: sklrt286: Remove tool to generate private data blobs conf: bxtrt298: Add topology conf file for bxt
configure.ac | 2 +- src/conf/topology/Makefile.am | 2 +- src/conf/topology/bxtrt298/Makefile.am | 4 + src/conf/topology/bxtrt298/bxt_i2s.conf | 3323 ++++++++++++++++++++ src/conf/topology/sklrt286/Makefile.am | 3 +- src/conf/topology/sklrt286/codec0_in-cpr-1.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec0_in-mi.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec0_out-cpr-4.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec0_out-mo.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec1_out-cpr-5.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec1_out-mo.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/data/Makefile.am | 6 - src/conf/topology/sklrt286/data/pvt.c | 1815 ----------- src/conf/topology/sklrt286/data/pvt_data.c | 90 - src/conf/topology/sklrt286/data/pvt_local.h | 9 - .../topology/sklrt286/data/skl-tplg-interface.h | 232 -- .../topology/sklrt286/dmic01_hifi_in-cpr-3.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/dmic01_hifi_in-mi.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi1_pt_out-cpr-7.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi1_pt_out-cpr-8.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi2_pt_out-cpr-10.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi2_pt_out-cpr-9.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi3_pt_out-cpr-11.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi3_pt_out-cpr-12.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/media0_in-cpr-0.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/media0_in-mi.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/media0_out-cpr-6.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/media0_out-mo.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/skl_i2s.conf | 2694 +++++++++++++++- 29 files changed, 5988 insertions(+), 2192 deletions(-) create mode 100644 src/conf/topology/bxtrt298/Makefile.am create mode 100644 src/conf/topology/bxtrt298/bxt_i2s.conf delete mode 100644 src/conf/topology/sklrt286/codec0_in-cpr-1.bin delete mode 100644 src/conf/topology/sklrt286/codec0_in-mi.bin delete mode 100644 src/conf/topology/sklrt286/codec0_out-cpr-4.bin delete mode 100644 src/conf/topology/sklrt286/codec0_out-mo.bin delete mode 100644 src/conf/topology/sklrt286/codec1_out-cpr-5.bin delete mode 100644 src/conf/topology/sklrt286/codec1_out-mo.bin delete mode 100644 src/conf/topology/sklrt286/data/Makefile.am delete mode 100644 src/conf/topology/sklrt286/data/pvt.c delete mode 100644 src/conf/topology/sklrt286/data/pvt_data.c delete mode 100644 src/conf/topology/sklrt286/data/pvt_local.h delete mode 100644 src/conf/topology/sklrt286/data/skl-tplg-interface.h delete mode 100644 src/conf/topology/sklrt286/dmic01_hifi_in-cpr-3.bin delete mode 100644 src/conf/topology/sklrt286/dmic01_hifi_in-mi.bin delete mode 100644 src/conf/topology/sklrt286/hdmi1_pt_out-cpr-7.bin delete mode 100644 src/conf/topology/sklrt286/hdmi1_pt_out-cpr-8.bin delete mode 100644 src/conf/topology/sklrt286/hdmi2_pt_out-cpr-10.bin delete mode 100644 src/conf/topology/sklrt286/hdmi2_pt_out-cpr-9.bin delete mode 100644 src/conf/topology/sklrt286/hdmi3_pt_out-cpr-11.bin delete mode 100644 src/conf/topology/sklrt286/hdmi3_pt_out-cpr-12.bin delete mode 100644 src/conf/topology/sklrt286/media0_in-cpr-0.bin delete mode 100644 src/conf/topology/sklrt286/media0_in-mi.bin delete mode 100644 src/conf/topology/sklrt286/media0_out-cpr-6.bin delete mode 100644 src/conf/topology/sklrt286/media0_out-mo.bin
From: Shreyas NC shreyas.nc@intel.com
In the conf file, module private data can be described through tuples instead of blobs defined by vendor defined structures.
This patch defines the tuple section and the token list. The tokens are then used to build the tuple array.
The module data may have both driver data and firmware data. The driver data is passed using the tuple array and the firmware data using byte data. A descriptor tuple array is defined to describe the succeeding data block.
Signed-off-by: Shreyas NC shreyas.nc@intel.com Signed-off-by: Vinod Koul vinod.koul@intel.com --- src/conf/topology/sklrt286/Makefile.am | 2 +- src/conf/topology/sklrt286/skl_i2s.conf | 2694 ++++++++++++++++++++++++++++++- 2 files changed, 2659 insertions(+), 37 deletions(-)
diff --git a/src/conf/topology/sklrt286/Makefile.am b/src/conf/topology/sklrt286/Makefile.am index ed58b775e6eb..4e7a9d017b62 100644 --- a/src/conf/topology/sklrt286/Makefile.am +++ b/src/conf/topology/sklrt286/Makefile.am @@ -1,5 +1,5 @@ alsaconfigdir = @ALSA_CONFIG_DIR@ SUBDIRS = data sklrt286dir = $(alsaconfigdir)/topology/sklrt286 -sklrt286_DATA = skl_i2s.conf media0_in-cpr-0.bin media0_in-mi.bin media0_out-mo.bin media0_out-cpr-6.bin codec0_out-mo.bin codec0_out-cpr-4.bin codec1_out-mo.bin codec1_out-cpr-5.bin codec0_in-cpr-1.bin codec0_in-mi.bin dmic01_hifi_in-cpr-3.bin dmic01_hifi_in-mi.bin hdmi1_pt_out-cpr-7.bin hdmi1_pt_out-cpr-8.bin hdmi2_pt_out-cpr-9.bin hdmi2_pt_out-cpr-10.bin hdmi3_pt_out-cpr-11.bin hdmi3_pt_out-cpr-12.bin +sklrt286_DATA = skl_i2s.conf EXTRA_DIST = $(sklrt286_DATA) diff --git a/src/conf/topology/sklrt286/skl_i2s.conf b/src/conf/topology/sklrt286/skl_i2s.conf index 6da224fb4d2b..bb1fe4f8435f 100644 --- a/src/conf/topology/sklrt286/skl_i2s.conf +++ b/src/conf/topology/sklrt286/skl_i2s.conf @@ -1,58 +1,2608 @@ +SectionVendorTokens."skl_tokens" { + SKL_TKN_UUID "1" + SKL_TKN_U8_NUM_BLOCKS "2" + SKL_TKN_U8_BLOCK_TYPE "3" + SKL_TKN_U8_IN_PIN_TYPE "4" + SKL_TKN_U8_OUT_PIN_TYPE "5" + SKL_TKN_U8_DYN_IN_PIN "6" + SKL_TKN_U8_DYN_OUT_PIN "7" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "9" + SKL_TKN_U8_TIME_SLOT "10" + SKL_TKN_U8_CORE_ID "11" + SKL_TKN_U8_MODULE_TYPE "12" + SKL_TKN_U8_CONN_TYPE "13" + SKL_TKN_U8_DEV_TYPE "14" + SKL_TKN_U8_HW_CONN_TYPE "15" + SKL_TKN_U16_MOD_INST_ID "16" + SKL_TKN_U16_BLOCK_SIZE "17" + SKL_TKN_U32_MAX_MCPS "18" + SKL_TKN_U32_MEM_PAGES "19" + SKL_TKN_U32_OBS "20" + SKL_TKN_U32_IBS "21" + SKL_TKN_U32_VBUS_ID "22" + SKL_TKN_U32_PARAMS_FIXUP "23" + SKL_TKN_U32_CONVERTER "24" + SKL_TKN_U32_PIPE_ID "25" + SKL_TKN_U32_PIPE_CONN_TYPE "26" + SKL_TKN_U32_PIPE_PRIORITY "27" + SKL_TKN_U32_PIPE_MEM_PGS "28" + SKL_TKN_U32_DIR_PIN_COUNT "29" + SKL_TKN_U32_FMT_CH "30" + SKL_TKN_U32_FMT_FREQ "31" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "33" + SKL_TKN_U32_FMT_CH_CONFIG "34" + SKL_TKN_U32_FMT_INTERLEAVE "35" + SKL_TKN_U32_FMT_SAMPLE_TYPE "36" + SKL_TKN_U32_FMT_CH_MAP "37" + SKL_TKN_U32_PIN_MOD_ID "38" + SKL_TKN_U32_PIN_INST_ID "39" + SKL_TKN_U32_MOD_SET_PARAMS "40" + SKL_TKN_U32_MOD_PARAM_ID "41" + SKL_TKN_U32_CAPS_SET_PARAMS "42" + SKL_TKN_U32_CAPS_PARAMS_ID "43" + SKL_TKN_U32_CAPS_SIZE "44" +} + +SectionVendorTuples."media0_in cpr 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."media0_in cpr 0_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."media0_in cpr 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."media0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."media0_in mi_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "412" + } +} + +SectionVendorTuples."media0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, + 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."media0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."media0_out mo_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "1084" + } +} + +SectionVendorTuples."media0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, + 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."media0_out cpr 6 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."media0_out cpr 6_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."media0_out cpr 6" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec0_out mo_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "1084" + } +} + +SectionVendorTuples."codec0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, + 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "4" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec0_out cpr 4 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec0_out cpr 4_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."codec0_out cpr 4" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "2" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0x0" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "4" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec1_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec1_out mo_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "1084" + } +} + +SectionVendorTuples."codec1_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, + 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec1_out cpr 5 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec1_out cpr 5_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."codec1_out cpr 5" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "2" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "2" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0x0" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec0_in cpr 1 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec0_in cpr 1_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."codec0_in cpr 1" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "2" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0x0" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec0_in mi_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "412" + } +} + +SectionVendorTuples."codec0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, + 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."dmic01_hifi_in cpr 3 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."dmic01_hifi_in cpr 3_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."dmic01_hifi_in cpr 3" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "1" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0x0" + SKL_TKN_U32_PARAMS_FIXUP "4" + SKL_TKN_U32_CONVERTER "4" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."dmic01_hifi_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."dmic01_hifi_in mi_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "412" + } +} + +SectionVendorTuples."dmic01_hifi_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, + 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 7 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 7_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 7" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "7" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 8 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 8_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 8" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "8" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 9 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 9_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 9" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "9" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 10 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 10_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 10" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "10" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 11 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 11_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 11" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "11" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "32" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 12 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 12_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "508" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 12" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "12" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + + +SectionData."media0_in cpr 0 num_desc" { + tuples "media0_in cpr 0 num_desc" +} + +SectionData."media0_in cpr 0_size_desc" { + tuples "media0_in cpr 0_size_desc" +} + SectionData."media0_in cpr 0" { - file "sklrt286/media0_in-cpr-0.bin" + tuples "media0_in cpr 0" } + +SectionData."media0_in mi num_desc" { + tuples "media0_in mi num_desc" +} + +SectionData."media0_in mi_size_desc" { + tuples "media0_in mi_size_desc" +} + SectionData."media0_in mi" { - file "sklrt286/media0_in-mi.bin" + tuples "media0_in mi" +} + +SectionData."media0_out mo num_desc" { + tuples "media0_out mo num_desc" +} + +SectionData."media0_out mo_size_desc" { + tuples "media0_out mo_size_desc" } + SectionData."media0_out mo" { - file "sklrt286/media0_out-mo.bin" + tuples "media0_out mo" +} + +SectionData."media0_out cpr 6 num_desc" { + tuples "media0_out cpr 6 num_desc" } + +SectionData."media0_out cpr 6_size_desc" { + tuples "media0_out cpr 6_size_desc" +} + SectionData."media0_out cpr 6" { - file "sklrt286/media0_out-cpr-6.bin" + tuples "media0_out cpr 6" +} + +SectionData."codec0_out mo num_desc" { + tuples "codec0_out mo num_desc" +} + +SectionData."codec0_out mo_size_desc" { + tuples "codec0_out mo_size_desc" } + SectionData."codec0_out mo" { - file "sklrt286/codec0_out-mo.bin" + tuples "codec0_out mo" +} + +SectionData."codec0_out cpr 4 num_desc" { + tuples "codec0_out cpr 4 num_desc" +} + +SectionData."codec0_out cpr 4_size_desc" { + tuples "codec0_out cpr 4_size_desc" } + SectionData."codec0_out cpr 4" { - file "sklrt286/codec0_out-cpr-4.bin" + tuples "codec0_out cpr 4" +} + +SectionData."codec1_out mo num_desc" { + tuples "codec1_out mo num_desc" +} + +SectionData."codec1_out mo_size_desc" { + tuples "codec1_out mo_size_desc" } + SectionData."codec1_out mo" { - file "sklrt286/codec1_out-mo.bin" + tuples "codec1_out mo" +} + +SectionData."codec1_out cpr 5 num_desc" { + tuples "codec1_out cpr 5 num_desc" } + +SectionData."codec1_out cpr 5_size_desc" { + tuples "codec1_out cpr 5_size_desc" +} + SectionData."codec1_out cpr 5" { - file "sklrt286/codec1_out-cpr-5.bin" + tuples "codec1_out cpr 5" +} + +SectionData."codec0_in cpr 1 num_desc" { + tuples "codec0_in cpr 1 num_desc" +} + +SectionData."codec0_in cpr 1_size_desc" { + tuples "codec0_in cpr 1_size_desc" } + SectionData."codec0_in cpr 1" { - file "sklrt286/codec0_in-cpr-1.bin" + tuples "codec0_in cpr 1" } + +SectionData."codec0_in mi num_desc" { + tuples "codec0_in mi num_desc" +} + +SectionData."codec0_in mi_size_desc" { + tuples "codec0_in mi_size_desc" +} + SectionData."codec0_in mi" { - file "sklrt286/codec0_in-mi.bin" + tuples "codec0_in mi" +} + +SectionData."dmic01_hifi_in cpr 3 num_desc" { + tuples "dmic01_hifi_in cpr 3 num_desc" +} + +SectionData."dmic01_hifi_in cpr 3_size_desc" { + tuples "dmic01_hifi_in cpr 3_size_desc" } + SectionData."dmic01_hifi_in cpr 3" { - file "sklrt286/dmic01_hifi_in-cpr-3.bin" + tuples "dmic01_hifi_in cpr 3" +} + +SectionData."dmic01_hifi_in mi num_desc" { + tuples "dmic01_hifi_in mi num_desc" } + +SectionData."dmic01_hifi_in mi_size_desc" { + tuples "dmic01_hifi_in mi_size_desc" +} + SectionData."dmic01_hifi_in mi" { - file "sklrt286/dmic01_hifi_in-mi.bin" + tuples "dmic01_hifi_in mi" +} + +SectionData."hdmi1_pt_out cpr 7 num_desc" { + tuples "hdmi1_pt_out cpr 7 num_desc" +} + +SectionData."hdmi1_pt_out cpr 7_size_desc" { + tuples "hdmi1_pt_out cpr 7_size_desc" } + SectionData."hdmi1_pt_out cpr 7" { - file "sklrt286/hdmi1_pt_out-cpr-7.bin" + tuples "hdmi1_pt_out cpr 7" +} + +SectionData."hdmi1_pt_out cpr 8 num_desc" { + tuples "hdmi1_pt_out cpr 8 num_desc" +} + +SectionData."hdmi1_pt_out cpr 8_size_desc" { + tuples "hdmi1_pt_out cpr 8_size_desc" } + SectionData."hdmi1_pt_out cpr 8" { - file "sklrt286/hdmi1_pt_out-cpr-8.bin" + tuples "hdmi1_pt_out cpr 8" +} + +SectionData."hdmi2_pt_out cpr 9 num_desc" { + tuples "hdmi2_pt_out cpr 9 num_desc" +} + +SectionData."hdmi2_pt_out cpr 9_size_desc" { + tuples "hdmi2_pt_out cpr 9_size_desc" } + SectionData."hdmi2_pt_out cpr 9" { - file "sklrt286/hdmi2_pt_out-cpr-9.bin" + tuples "hdmi2_pt_out cpr 9" +} + +SectionData."hdmi2_pt_out cpr 10 num_desc" { + tuples "hdmi2_pt_out cpr 10 num_desc" } + +SectionData."hdmi2_pt_out cpr 10_size_desc" { + tuples "hdmi2_pt_out cpr 10_size_desc" +} + SectionData."hdmi2_pt_out cpr 10" { - file "sklrt286/hdmi2_pt_out-cpr-10.bin" + tuples "hdmi2_pt_out cpr 10" +} + +SectionData."hdmi3_pt_out cpr 11 num_desc" { + tuples "hdmi3_pt_out cpr 11 num_desc" +} + +SectionData."hdmi3_pt_out cpr 11_size_desc" { + tuples "hdmi3_pt_out cpr 11_size_desc" } + SectionData."hdmi3_pt_out cpr 11" { - file "sklrt286/hdmi3_pt_out-cpr-11.bin" + tuples "hdmi3_pt_out cpr 11" } + +SectionData."hdmi3_pt_out cpr 12 num_desc" { + tuples "hdmi3_pt_out cpr 12 num_desc" +} + +SectionData."hdmi3_pt_out cpr 12_size_desc" { + tuples "hdmi3_pt_out cpr 12_size_desc" +} + SectionData."hdmi3_pt_out cpr 12" { - file "sklrt286/hdmi3_pt_out-cpr-12.bin" + tuples "hdmi3_pt_out cpr 12" }
+ SectionControlMixer."media0_in mi Switch" { index"1" invert "false" @@ -121,7 +2671,11 @@ SectionWidget."media0_in cpr 0" { no_pm "true" event_type "3" event_flags "9" - data "media0_in cpr 0" + data [ + "media0_in cpr 0 num_desc" + "media0_in cpr 0_size_desc" + "media0_in cpr 0" + ] } SectionWidget."media0_in mi" { index"1" @@ -130,7 +2684,11 @@ SectionWidget."media0_in mi" { event_type "4" event_flags "9" subseq "10" - data "media0_in mi" + data [ + "media0_in mi num_desc" + "media0_in mi_size_desc" + "media0_in mi" + ] } SectionWidget."media0_out mo" { index"1" @@ -139,7 +2697,11 @@ SectionWidget."media0_out mo" { event_type "1" event_flags "15" subseq "10" - data "media0_out mo" + data [ + "media0_out mo num_desc" + "media0_out mo_size_desc" + "media0_out mo" + ] mixer [ "media0_in mi Switch" "codec0_in mi Switch" @@ -151,7 +2713,11 @@ SectionWidget."media0_out cpr 6" { type"pga" no_pm "true" event_type "4" - data "media0_out cpr 6" + data [ + "media0_out cpr 6 num_desc" + "media0_out cpr 6_size_desc" + "media0_out cpr 6" + ] } SectionWidget."codec0_out mo" { index"1" @@ -160,7 +2726,11 @@ SectionWidget."codec0_out mo" { event_type "1" event_flags "15" subseq "10" - data "codec0_out mo" + data [ + "codec0_out mo num_desc" + "codec0_out mo_size_desc" + "codec0_out mo" + ] mixer [ "media0_in mi Switch" "codec0_in mi Switch" @@ -172,7 +2742,11 @@ SectionWidget."codec0_out cpr 4" { type"pga" no_pm "true" event_type "4" - data "codec0_out cpr 4" + data [ + "codec0_out cpr 4 num_desc" + "codec0_out cpr 4_size_desc" + "codec0_out cpr 4" + ] } SectionWidget."codec0_out" { index"1" @@ -186,7 +2760,11 @@ SectionWidget."codec1_out mo" { event_type "1" event_flags "15" subseq "10" - data "codec1_out mo" + data [ + "codec1_out mo num_desc" + "codec1_out mo_size_desc" + "codec1_out mo" + ] mixer [ "media0_in mi Switch" "codec0_in mi Switch" @@ -198,7 +2776,11 @@ SectionWidget."codec1_out cpr 5" { type"pga" no_pm "true" event_type "4" - data "codec1_out cpr 5" + data [ + "codec1_out cpr 5 num_desc" + "codec1_out cpr 5_size_desc" + "codec1_out cpr 5" + ] } SectionWidget."codec1_out" { index"1" @@ -211,7 +2793,11 @@ SectionWidget."codec0_in cpr 1" { no_pm "true" event_type "3" event_flags "9" - data "codec0_in cpr 1" + data [ + "codec0_in cpr 1 num_desc" + "codec0_in cpr 1_size_desc" + "codec0_in cpr 1" + ] } SectionWidget."codec0_in mi" { index"1" @@ -220,7 +2806,11 @@ SectionWidget."codec0_in mi" { event_type "4" event_flags "9" subseq "10" - data "codec0_in mi" + data [ + "codec0_in mi num_desc" + "codec0_in mi_size_desc" + "codec0_in mi" + ] } SectionWidget."codec0_in" { index"1" @@ -233,7 +2823,11 @@ SectionWidget."dmic01_hifi_in cpr 3" { no_pm "true" event_type "3" event_flags "9" - data "dmic01_hifi_in cpr 3" + data [ + "dmic01_hifi_in cpr 3 num_desc" + "dmic01_hifi_in cpr 3_size_desc" + "dmic01_hifi_in cpr 3" + ] } SectionWidget."dmic01_hifi_in mi" { index"1" @@ -242,7 +2836,11 @@ SectionWidget."dmic01_hifi_in mi" { event_type "4" event_flags "9" subseq "10" - data "dmic01_hifi_in mi" + data [ + "dmic01_hifi_in mi num_desc" + "dmic01_hifi_in mi_size_desc" + "dmic01_hifi_in mi" + ] } SectionWidget."dmic01_hifi" { index"1" @@ -255,14 +2853,22 @@ SectionWidget."hdmi1_pt_out cpr 7" { no_pm "true" event_type "3" event_flags "9" - data "hdmi1_pt_out cpr 7" + data [ + "hdmi1_pt_out cpr 7 num_desc" + "hdmi1_pt_out cpr 7_size_desc" + "hdmi1_pt_out cpr 7" + ] } SectionWidget."hdmi1_pt_out cpr 8" { index"1" type"pga" no_pm "true" event_type "4" - data "hdmi1_pt_out cpr 8" + data [ + "hdmi1_pt_out cpr 8 num_desc" + "hdmi1_pt_out cpr 8_size_desc" + "hdmi1_pt_out cpr 8" + ] } SectionWidget."iDisp1_out" { index"1" @@ -275,14 +2881,22 @@ SectionWidget."hdmi2_pt_out cpr 9" { no_pm "true" event_type "3" event_flags "9" - data "hdmi2_pt_out cpr 9" + data [ + "hdmi2_pt_out cpr 9 num_desc" + "hdmi2_pt_out cpr 9_size_desc" + "hdmi2_pt_out cpr 9" + ] } SectionWidget."hdmi2_pt_out cpr 10" { index"1" type"pga" no_pm "true" event_type "4" - data "hdmi2_pt_out cpr 10" + data [ + "hdmi2_pt_out cpr 10 num_desc" + "hdmi2_pt_out cpr 10_size_desc" + "hdmi2_pt_out cpr 10" + ] } SectionWidget."iDisp2_out" { index"1" @@ -295,14 +2909,22 @@ SectionWidget."hdmi3_pt_out cpr 11" { no_pm "true" event_type "3" event_flags "9" - data "hdmi3_pt_out cpr 11" + data [ + "hdmi3_pt_out cpr 11 num_desc" + "hdmi3_pt_out cpr 11_size_desc" + "hdmi3_pt_out cpr 11" + ] } SectionWidget."hdmi3_pt_out cpr 12" { index"1" type"pga" no_pm "true" event_type "4" - data "hdmi3_pt_out cpr 12" + data [ + "hdmi3_pt_out cpr 12 num_desc" + "hdmi3_pt_out cpr 12_size_desc" + "hdmi3_pt_out cpr 12" + ] } SectionGraph."Pipeline 1 Graph" { index"1"
From: Shreyas NC shreyas.nc@intel.com
Since tuples are used to define driver private data, the private data blobs are no longer required.
So, remove the source files required to generate the private data blobs and the private data blobs.
Signed-off-by: Shreyas NC shreyas.nc@intel.com Signed-off-by: Vinod Koul vinod.koul@intel.com --- configure.ac | 1 - src/conf/topology/sklrt286/Makefile.am | 1 - src/conf/topology/sklrt286/codec0_in-cpr-1.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec0_in-mi.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec0_out-cpr-4.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec0_out-mo.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec1_out-cpr-5.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/codec1_out-mo.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/data/Makefile.am | 6 - src/conf/topology/sklrt286/data/pvt.c | 1815 -------------------- src/conf/topology/sklrt286/data/pvt_data.c | 90 - src/conf/topology/sklrt286/data/pvt_local.h | 9 - .../topology/sklrt286/data/skl-tplg-interface.h | 232 --- .../topology/sklrt286/dmic01_hifi_in-cpr-3.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/dmic01_hifi_in-mi.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi1_pt_out-cpr-7.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi1_pt_out-cpr-8.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi2_pt_out-cpr-10.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi2_pt_out-cpr-9.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi3_pt_out-cpr-11.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/hdmi3_pt_out-cpr-12.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/media0_in-cpr-0.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/media0_in-mi.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/media0_out-cpr-6.bin | Bin 4244 -> 0 bytes src/conf/topology/sklrt286/media0_out-mo.bin | Bin 4244 -> 0 bytes 25 files changed, 2154 deletions(-) delete mode 100644 src/conf/topology/sklrt286/codec0_in-cpr-1.bin delete mode 100644 src/conf/topology/sklrt286/codec0_in-mi.bin delete mode 100644 src/conf/topology/sklrt286/codec0_out-cpr-4.bin delete mode 100644 src/conf/topology/sklrt286/codec0_out-mo.bin delete mode 100644 src/conf/topology/sklrt286/codec1_out-cpr-5.bin delete mode 100644 src/conf/topology/sklrt286/codec1_out-mo.bin delete mode 100644 src/conf/topology/sklrt286/data/Makefile.am delete mode 100644 src/conf/topology/sklrt286/data/pvt.c delete mode 100644 src/conf/topology/sklrt286/data/pvt_data.c delete mode 100644 src/conf/topology/sklrt286/data/pvt_local.h delete mode 100644 src/conf/topology/sklrt286/data/skl-tplg-interface.h delete mode 100644 src/conf/topology/sklrt286/dmic01_hifi_in-cpr-3.bin delete mode 100644 src/conf/topology/sklrt286/dmic01_hifi_in-mi.bin delete mode 100644 src/conf/topology/sklrt286/hdmi1_pt_out-cpr-7.bin delete mode 100644 src/conf/topology/sklrt286/hdmi1_pt_out-cpr-8.bin delete mode 100644 src/conf/topology/sklrt286/hdmi2_pt_out-cpr-10.bin delete mode 100644 src/conf/topology/sklrt286/hdmi2_pt_out-cpr-9.bin delete mode 100644 src/conf/topology/sklrt286/hdmi3_pt_out-cpr-11.bin delete mode 100644 src/conf/topology/sklrt286/hdmi3_pt_out-cpr-12.bin delete mode 100644 src/conf/topology/sklrt286/media0_in-cpr-0.bin delete mode 100644 src/conf/topology/sklrt286/media0_in-mi.bin delete mode 100644 src/conf/topology/sklrt286/media0_out-cpr-6.bin delete mode 100644 src/conf/topology/sklrt286/media0_out-mo.bin
diff --git a/configure.ac b/configure.ac index 014af5f3d27b..6de8efea3b7c 100644 --- a/configure.ac +++ b/configure.ac @@ -679,7 +679,6 @@ AC_OUTPUT(Makefile doc/Makefile doc/pictures/Makefile doc/doxygen.cfg \ src/conf/topology/Makefile \ src/conf/topology/broadwell/Makefile \ modules/Makefile modules/mixer/Makefile modules/mixer/simple/Makefile \ - src/conf/topology/sklrt286/data/Makefile \ src/conf/topology/sklrt286/Makefile \ alsalisp/Makefile aserver/Makefile \ test/Makefile test/lsb/Makefile \ diff --git a/src/conf/topology/sklrt286/Makefile.am b/src/conf/topology/sklrt286/Makefile.am index 4e7a9d017b62..2cbfd0595a2a 100644 --- a/src/conf/topology/sklrt286/Makefile.am +++ b/src/conf/topology/sklrt286/Makefile.am @@ -1,5 +1,4 @@ alsaconfigdir = @ALSA_CONFIG_DIR@ -SUBDIRS = data sklrt286dir = $(alsaconfigdir)/topology/sklrt286 sklrt286_DATA = skl_i2s.conf EXTRA_DIST = $(sklrt286_DATA) diff --git a/src/conf/topology/sklrt286/codec0_in-cpr-1.bin b/src/conf/topology/sklrt286/codec0_in-cpr-1.bin deleted file mode 100644 index a3079d4226460671d06667498baf333f08d33def..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001
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diff --git a/src/conf/topology/sklrt286/codec0_in-mi.bin b/src/conf/topology/sklrt286/codec0_in-mi.bin deleted file mode 100644 index 8e431d472a5c6ac679e6cb1251b7bf8e27ef5808..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001
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diff --git a/src/conf/topology/sklrt286/codec1_out-mo.bin b/src/conf/topology/sklrt286/codec1_out-mo.bin deleted file mode 100644 index c878060faf1429d379101185e2218afae0ff03f1..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001
literal 4244 zcmazF2(!7a((kzU&cUyX*JwRpVqj!g(8dTP85kOX1PK2J0uGQs0*K&YU}0clVgkwU zW?)bN(jW|yfdK)a`jIXV3yV>DGz3ONU^E0qLtr!nMnhmU1V%$(Gz3ONU^E0qLtr!n KMneF52mk;^7&tlr
diff --git a/src/conf/topology/sklrt286/data/Makefile.am b/src/conf/topology/sklrt286/data/Makefile.am deleted file mode 100644 index 5178672fccc3..000000000000 --- a/src/conf/topology/sklrt286/data/Makefile.am +++ /dev/null @@ -1,6 +0,0 @@ -noinst_PROGRAMS = pvt_data -pvt_data_SOURCES = pvt_data.c -noinst_HEADERS = pvt_local.h skl-tplg-interface.h -EXTRA_DIST = pvt.c -AM_CPPFLAGS = \ - -Wall -I$(top_srcdir)/include diff --git a/src/conf/topology/sklrt286/data/pvt.c b/src/conf/topology/sklrt286/data/pvt.c deleted file mode 100644 index 3447e3e0226b..000000000000 --- a/src/conf/topology/sklrt286/data/pvt.c +++ /dev/null @@ -1,1815 +0,0 @@ -/* -* Copyright(c) 2014-2016 Intel Corporation -* All rights reserved. -* -* This library is free software; you can redistribute it and/or -* modify it under the terms of the GNU Lesser General Public -* License as published by the Free Software Foundation; either -* version 2 of the License, or (at your option) any later version. - -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -* General Public License for more details. -* -* Authors: Shreyas Nc shreyas.nc@intel.com -* -*/ -#include "pvt_local.h" - -struct skl_dfw_module_mod dfw_wrap[] = { -{ -.name = "media0_in cpr 0", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 0, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 1, - .dev_type = 5, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 1, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "media0_in mi", -.skl_dfw_mod = { - .uuid = {178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9}, - .module_id = 1, - .instance_id = 0, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 1, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 0, - .conn_type = 0, - .dev_type = 6, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 1, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "media0_out mo", -.skl_dfw_mod = { - .uuid = {90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224}, - .module_id = 2, - .instance_id = 2, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 8, - .max_out_queue = 1, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 0, - .conn_type = 0, - .dev_type = 6, - .hw_conn_type = 2, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 2, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "media0_out cpr 6", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 6, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 0, - .dev_type = 5, - .hw_conn_type = 2, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 2, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "codec0_out mo", -.skl_dfw_mod = { - .uuid = {90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224}, - .module_id = 2, - .instance_id = 0, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 8, - .max_out_queue = 1, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 0, - .conn_type = 0, - .dev_type = 6, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 3, - .pipe_priority = 0, - .conn_type = 2, - .rsvd = 0, - .memory_pages = 0x4, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "codec0_out cpr 4", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 4, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = 0, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 2, - .dev_type = 2, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 3, - .pipe_priority = 0, - .conn_type = 2, - .rsvd = 0, - .memory_pages = 0x4, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "codec1_out mo", -.skl_dfw_mod = { - .uuid = {90, 80, 86, 60, 215, 36, 143, 65, 189, 220, 193, 245, 163, 172, 42, 224}, - .module_id = 2, - .instance_id = 1, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 8, - .max_out_queue = 1, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 0, - .conn_type = 0, - .dev_type = 6, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 4, - .pipe_priority = 0, - .conn_type = 2, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "codec1_out cpr 5", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 5, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = 0, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 2, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 2, - .dev_type = 2, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 4, - .pipe_priority = 0, - .conn_type = 2, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "codec0_in cpr 1", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 1, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = 0, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 2, - .dev_type = 2, - .hw_conn_type = 2, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 5, - .pipe_priority = 0, - .conn_type = 2, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "codec0_in mi", -.skl_dfw_mod = { - .uuid = {178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9}, - .module_id = 1, - .instance_id = 1, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 1, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 0, - .conn_type = 0, - .dev_type = 6, - .hw_conn_type = 2, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 5, - .pipe_priority = 0, - .conn_type = 2, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "dmic01_hifi_in cpr 3", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 3, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = 0, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 2, - .dev_type = 1, - .hw_conn_type = 2, - .rsvd2 = 0, - .params_fixup = 4, - .converter = 4, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 6, - .pipe_priority = 0, - .conn_type = 2, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "dmic01_hifi_in mi", -.skl_dfw_mod = { - .uuid = {178, 110, 101, 57, 113, 59, 73, 64, 141, 63, 249, 44, 213, 196, 60, 9}, - .module_id = 1, - .instance_id = 3, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 1, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 0, - .conn_type = 0, - .dev_type = 6, - .hw_conn_type = 2, - .rsvd2 = 0, - .params_fixup = 0, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 6, - .pipe_priority = 0, - .conn_type = 2, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "hdmi1_pt_out cpr 7", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 7, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 1, - .dev_type = 5, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 7, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 7, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "hdmi1_pt_out cpr 8", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 8, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 1, - .dev_type = 4, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 7, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 7, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "hdmi2_pt_out cpr 9", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 9, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 1, - .dev_type = 5, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 7, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 8, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "hdmi2_pt_out cpr 10", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 10, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 1, - .dev_type = 4, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 7, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 8, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "hdmi3_pt_out cpr 11", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 11, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 1, - .dev_type = 5, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 7, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 9, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 32, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, -{ -.name = "hdmi3_pt_out cpr 12", -.skl_dfw_mod = { - .uuid = {131, 12, 160, 155, 18, 202, 131, 74, 148, 60, 31, 162, 232, 47, 157, 218}, - .module_id = 3, - .instance_id = 12, - .max_mcps = 0x186a0, - .mem_pages = 0x1, - .obs = 384, - .ibs = 384, - .vbus_id = -1, - .max_in_queue = 1, - .max_out_queue = 2, - .time_slot = 0, - .core_id = 0, - .rsvd1 = 0, - .module_type = 1, - .conn_type = 1, - .dev_type = 4, - .hw_conn_type = 1, - .rsvd2 = 0, - .params_fixup = 7, - .converter = 0, - .input_pin_type = 0, - .output_pin_type = 0, - .is_dynamic_in_pin = 1, - .is_dynamic_out_pin = 1, - .is_loadable = 0, - .rsvd3 = 0, - .pipe = { - .pipe_id = 9, - .pipe_priority = 0, - .conn_type = 1, - .rsvd = 0, - .memory_pages = 0x2, - }, - .in_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .out_fmt = { - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - { - .channels = 2, - .freq = 48000, - .bit_depth = 32, - .valid_bit_depth = 24, - .ch_cfg = 1, - .interleaving_style = 0, - .sample_type = 0, - .ch_map = 0xffffff10, - }, - }, - .in_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - }, - .out_pin = { - { - .module_id = 0, - .instance_id = 0, - }, - { - .module_id = 0, - .instance_id = 0, - }, - }, - }, -}, - }; diff --git a/src/conf/topology/sklrt286/data/pvt_data.c b/src/conf/topology/sklrt286/data/pvt_data.c deleted file mode 100644 index dd55c3a38b3b..000000000000 --- a/src/conf/topology/sklrt286/data/pvt_data.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright(c) 2014-2016 Intel Corporation - * All rights reserved. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * Authors: Shreyas Nc shreyas.nc@intel.com - * - */ -#include "pvt.c" -#include "stdio.h" -#include "fcntl.h" -#include <local.h> -#include <limits.h> -#include <stdint.h> -#include <linux/types.h> -#include "global.h" -#include "list.h" - -#include <sound/asound.h> -#include <sound/asoc.h> - -int replace_space(char *path, char *newpath) -{ - char buffer[52]; - char *p; - - strcpy(buffer, path); - - while ((p = strchr(buffer, ' '))) - p[0] = '-'; - - strcpy(newpath, buffer); - return 0; -} - -/* - * The private data structures are written into a - * binary blob. These contain module private data - * information - */ -int main(void) -{ - unsigned int i; - FILE *fd; - char path[128]; - char new_path[128]; - struct snd_soc_tplg_private *priv = NULL; - - memset(path, 0, sizeof(path)); - memset(new_path, 0, sizeof(new_path)); - - priv = calloc(1, sizeof(dfw_wrap) + sizeof(uint32_t)); - - for (i = 0; i < ARRAY_SIZE(dfw_wrap); i++) { - strcat(path, "../"); - strcat(path, dfw_wrap[i].name); - strcat(path, ".bin"); - - replace_space(path, new_path); - - priv->size = (uint32_t)sizeof(dfw_wrap[i].skl_dfw_mod); - - memcpy(priv->data, &dfw_wrap[i].skl_dfw_mod, - priv->size); - - fd = fopen(new_path, "wb"); - - if (fd == NULL) - return -ENOENT; - - if (fwrite(priv->data, priv->size, 1, fd) != 1) { - fclose(fd); - return -1; - } - - memset(path, 0, sizeof(path)); - } - - free(priv); - return 0; -} diff --git a/src/conf/topology/sklrt286/data/pvt_local.h b/src/conf/topology/sklrt286/data/pvt_local.h deleted file mode 100644 index 5edf7bd71ce9..000000000000 --- a/src/conf/topology/sklrt286/data/pvt_local.h +++ /dev/null @@ -1,9 +0,0 @@ -#include <stdio.h> -#include "skl-tplg-interface.h" - -struct skl_dfw_module_mod { - char name[100]; - struct skl_dfw_module skl_dfw_mod; -}; - - diff --git a/src/conf/topology/sklrt286/data/skl-tplg-interface.h b/src/conf/topology/sklrt286/data/skl-tplg-interface.h deleted file mode 100644 index e7389bce1244..000000000000 --- a/src/conf/topology/sklrt286/data/skl-tplg-interface.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * skl-tplg-interface.h - Intel DSP FW private data interface - * - * Copyright (C) 2015 Intel Corp - * Author: Jeeja KP jeeja.kp@intel.com - * Nilofer, Samreen samreen.nilofer@intel.com - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ - -#ifndef __HDA_TPLG_INTERFACE_H__ -#define __HDA_TPLG_INTERFACE_H__ - -#include <sound/type_compat.h> -/* - * Default types range from 0~12. type can range from 0 to 0xff - * SST types start at higher to avoid any overlapping in future - */ -#define SKL_CONTROL_TYPE_BYTE_TLV 0x100 - -#define HDA_SST_CFG_MAX 900 /* size of copier cfg*/ -#define MAX_IN_QUEUE 8 -#define MAX_OUT_QUEUE 8 - -#define SKL_UUID_STR_SZ 40 -/* Event types goes here */ -/* Reserve event type 0 for no event handlers */ -enum skl_event_types { - SKL_EVENT_NONE = 0, - SKL_MIXER_EVENT, - SKL_MUX_EVENT, - SKL_VMIXER_EVENT, - SKL_PGA_EVENT -}; - -/** - * enum skl_ch_cfg - channel configuration - * - * @SKL_CH_CFG_MONO: One channel only - * @SKL_CH_CFG_STEREO: L & R - * @SKL_CH_CFG_2_1: L, R & LFE - * @SKL_CH_CFG_3_0: L, C & R - * @SKL_CH_CFG_3_1: L, C, R & LFE - * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs - * @SKL_CH_CFG_4_0: L, C, R & Cs - * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs - * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE - * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two - * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ] - * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ] - * @SKL_CH_CFG_INVALID: Invalid - */ -enum skl_ch_cfg { - SKL_CH_CFG_MONO = 0, - SKL_CH_CFG_STEREO = 1, - SKL_CH_CFG_2_1 = 2, - SKL_CH_CFG_3_0 = 3, - SKL_CH_CFG_3_1 = 4, - SKL_CH_CFG_QUATRO = 5, - SKL_CH_CFG_4_0 = 6, - SKL_CH_CFG_5_0 = 7, - SKL_CH_CFG_5_1 = 8, - SKL_CH_CFG_DUAL_MONO = 9, - SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10, - SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11, - SKL_CH_CFG_4_CHANNEL = 12, - SKL_CH_CFG_INVALID -}; - -enum skl_module_type { - SKL_MODULE_TYPE_MIXER = 0, - SKL_MODULE_TYPE_COPIER, - SKL_MODULE_TYPE_UPDWMIX, - SKL_MODULE_TYPE_SRCINT, - SKL_MODULE_TYPE_ALGO, - SKL_MODULE_TYPE_BASE_OUTFMT -}; - -enum skl_core_affinity { - SKL_AFFINITY_CORE_0 = 0, - SKL_AFFINITY_CORE_1, - SKL_AFFINITY_CORE_MAX -}; - -enum skl_pipe_conn_type { - SKL_PIPE_CONN_TYPE_NONE = 0, - SKL_PIPE_CONN_TYPE_FE, - SKL_PIPE_CONN_TYPE_BE -}; - -enum skl_hw_conn_type { - SKL_CONN_NONE = 0, - SKL_CONN_SOURCE = 1, - SKL_CONN_SINK = 2 -}; - -enum skl_dev_type { - SKL_DEVICE_BT = 0x0, - SKL_DEVICE_DMIC = 0x1, - SKL_DEVICE_I2S = 0x2, - SKL_DEVICE_SLIMBUS = 0x3, - SKL_DEVICE_HDALINK = 0x4, - SKL_DEVICE_HDAHOST = 0x5, - SKL_DEVICE_NONE -}; - -/** - * enum skl_interleaving - interleaving style - * - * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN] - * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN] - */ -enum skl_interleaving { - SKL_INTERLEAVING_PER_CHANNEL = 0, - SKL_INTERLEAVING_PER_SAMPLE = 1, -}; - -enum skl_sample_type { - SKL_SAMPLE_TYPE_INT_MSB = 0, - SKL_SAMPLE_TYPE_INT_LSB = 1, - SKL_SAMPLE_TYPE_INT_SIGNED = 2, - SKL_SAMPLE_TYPE_INT_UNSIGNED = 3, - SKL_SAMPLE_TYPE_FLOAT = 4 -}; - -enum module_pin_type { - /* All pins of the module takes same PCM inputs or outputs - * e.g. mixout - */ - SKL_PIN_TYPE_HOMOGENEOUS, - /* All pins of the module takes different PCM inputs or outputs - * e.g mux - */ - SKL_PIN_TYPE_HETEROGENEOUS, -}; - -enum skl_module_param_type { - SKL_PARAM_DEFAULT = 0, - SKL_PARAM_INIT, - SKL_PARAM_SET, - SKL_PARAM_BIND -}; - -struct skl_dfw_module_pin { - __le16 module_id; - __le16 instance_id; -} __attribute__((packed)); - -struct skl_dfw_module_fmt { - __le32 channels; - __le32 freq; - __le32 bit_depth; - __le32 valid_bit_depth; - __le32 ch_cfg; - __le32 interleaving_style; - __le32 sample_type; - __le32 ch_map; -} __attribute__((packed)); - -struct skl_dfw_module_caps { - __le32 set_params:2; - __le32 rsvd:30; - __le32 param_id; - __le32 caps_size; - __le32 caps[HDA_SST_CFG_MAX]; -}; - -struct skl_dfw_pipe { - __le8 pipe_id; - __le8 pipe_priority; - __le16 conn_type:4; - __le16 rsvd:4; - __le16 memory_pages:8; -} __attribute__((packed)); - -struct skl_dfw_module { - __le8 uuid[16]; - - __le16 module_id; - __le16 instance_id; - __le32 max_mcps; - __le32 mem_pages; - __le32 obs; - __le32 ibs; - __le32 vbus_id; - - __le32 max_in_queue:8; - __le32 max_out_queue:8; - __le32 time_slot:8; - __le32 core_id:4; - __le32 rsvd1:4; - - __le32 module_type:8; - __le32 conn_type:4; - __le32 dev_type:4; - __le32 hw_conn_type:4; - __le32 rsvd2:12; - - __le32 params_fixup:8; - __le32 converter:8; - __le32 input_pin_type:1; - __le32 output_pin_type:1; - __le32 is_dynamic_in_pin:1; - __le32 is_dynamic_out_pin:1; - __le32 is_loadable:1; - __le32 rsvd3:11; - - struct skl_dfw_pipe pipe; - struct skl_dfw_module_fmt in_fmt[MAX_IN_QUEUE]; - struct skl_dfw_module_fmt out_fmt[MAX_OUT_QUEUE]; - struct skl_dfw_module_pin in_pin[MAX_IN_QUEUE]; - struct skl_dfw_module_pin out_pin[MAX_OUT_QUEUE]; - struct skl_dfw_module_caps caps; -} __attribute__((packed)); - -struct skl_dfw_algo_data { - __le32 set_params:2; - __le32 rsvd:30; - __le32 param_id; - __le32 max; - char params[0]; -} __attribute__((packed)); - -#endif diff --git a/src/conf/topology/sklrt286/dmic01_hifi_in-cpr-3.bin b/src/conf/topology/sklrt286/dmic01_hifi_in-cpr-3.bin deleted file mode 100644 index 4cba682fe4fd39f383748d945e80c0dfd4337094..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001
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diff --git a/src/conf/topology/sklrt286/media0_out-mo.bin b/src/conf/topology/sklrt286/media0_out-mo.bin deleted file mode 100644 index 4e2273579a9c75a722cdf2607f13ded3a1d54bb4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001
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From: Shreyas NC shreyas.nc@intel.com
Add the conf file for bxt platform as well to define module private data.
Signed-off-by: Shreyas NC shreyas.nc@intel.com Signed-off-by: Vinod Koul vinod.koul@intel.com --- configure.ac | 1 + src/conf/topology/Makefile.am | 2 +- src/conf/topology/bxtrt298/Makefile.am | 4 + src/conf/topology/bxtrt298/bxt_i2s.conf | 3323 +++++++++++++++++++++++++++++++ 4 files changed, 3329 insertions(+), 1 deletion(-) create mode 100644 src/conf/topology/bxtrt298/Makefile.am create mode 100644 src/conf/topology/bxtrt298/bxt_i2s.conf
diff --git a/configure.ac b/configure.ac index 6de8efea3b7c..a1de230e588c 100644 --- a/configure.ac +++ b/configure.ac @@ -680,6 +680,7 @@ AC_OUTPUT(Makefile doc/Makefile doc/pictures/Makefile doc/doxygen.cfg \ src/conf/topology/broadwell/Makefile \ modules/Makefile modules/mixer/Makefile modules/mixer/simple/Makefile \ src/conf/topology/sklrt286/Makefile \ + src/conf/topology/bxtrt298/Makefile \ alsalisp/Makefile aserver/Makefile \ test/Makefile test/lsb/Makefile \ utils/Makefile utils/alsa-lib.spec utils/alsa.pc) diff --git a/src/conf/topology/Makefile.am b/src/conf/topology/Makefile.am index cbdb7cf07c97..8adaed903053 100644 --- a/src/conf/topology/Makefile.am +++ b/src/conf/topology/Makefile.am @@ -1 +1 @@ -SUBDIRS=broadwell sklrt286 +SUBDIRS=broadwell sklrt286 bxtrt298 diff --git a/src/conf/topology/bxtrt298/Makefile.am b/src/conf/topology/bxtrt298/Makefile.am new file mode 100644 index 000000000000..152d5cff4fc4 --- /dev/null +++ b/src/conf/topology/bxtrt298/Makefile.am @@ -0,0 +1,4 @@ +alsaconfigdir = @ALSA_CONFIG_DIR@ +bxtrt298dir = $(alsaconfigdir)/topology/bxtrt298 +bxtrt298_DATA = bxt_i2s.conf +EXTRA_DIST = $(bxtrt298_DATA) diff --git a/src/conf/topology/bxtrt298/bxt_i2s.conf b/src/conf/topology/bxtrt298/bxt_i2s.conf new file mode 100644 index 000000000000..3b7a54e3a323 --- /dev/null +++ b/src/conf/topology/bxtrt298/bxt_i2s.conf @@ -0,0 +1,3323 @@ +SectionVendorTokens."skl_tokens" { + SKL_TKN_UUID "1" + SKL_TKN_U8_NUM_BLOCKS "2" + SKL_TKN_U8_BLOCK_TYPE "3" + SKL_TKN_U8_IN_PIN_TYPE "4" + SKL_TKN_U8_OUT_PIN_TYPE "5" + SKL_TKN_U8_DYN_IN_PIN "6" + SKL_TKN_U8_DYN_OUT_PIN "7" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "9" + SKL_TKN_U8_TIME_SLOT "10" + SKL_TKN_U8_CORE_ID "11" + SKL_TKN_U8_MODULE_TYPE "12" + SKL_TKN_U8_CONN_TYPE "13" + SKL_TKN_U8_DEV_TYPE "14" + SKL_TKN_U8_HW_CONN_TYPE "15" + SKL_TKN_U16_MOD_INST_ID "16" + SKL_TKN_U16_BLOCK_SIZE "17" + SKL_TKN_U32_MAX_MCPS "18" + SKL_TKN_U32_MEM_PAGES "19" + SKL_TKN_U32_OBS "20" + SKL_TKN_U32_IBS "21" + SKL_TKN_U32_VBUS_ID "22" + SKL_TKN_U32_PARAMS_FIXUP "23" + SKL_TKN_U32_CONVERTER "24" + SKL_TKN_U32_PIPE_ID "25" + SKL_TKN_U32_PIPE_CONN_TYPE "26" + SKL_TKN_U32_PIPE_PRIORITY "27" + SKL_TKN_U32_PIPE_MEM_PGS "28" + SKL_TKN_U32_DIR_PIN_COUNT "29" + SKL_TKN_U32_FMT_CH "30" + SKL_TKN_U32_FMT_FREQ "31" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "33" + SKL_TKN_U32_FMT_CH_CONFIG "34" + SKL_TKN_U32_FMT_INTERLEAVE "35" + SKL_TKN_U32_FMT_SAMPLE_TYPE "36" + SKL_TKN_U32_FMT_CH_MAP "37" + SKL_TKN_U32_PIN_MOD_ID "38" + SKL_TKN_U32_PIN_INST_ID "39" + SKL_TKN_U32_MOD_SET_PARAMS "40" + SKL_TKN_U32_MOD_PARAM_ID "41" + SKL_TKN_U32_CAPS_SET_PARAMS "42" + SKL_TKN_U32_CAPS_PARAMS_ID "43" + SKL_TKN_U32_CAPS_SIZE "44" + SKL_TKN_U32_PROC_DOMAIN "45" + SKL_TKN_U32_LIB_COUNT "46" + SKL_TKN_STR_LIB_NAME "47" +} + +SectionVendorTuples."media0_in cpr 0 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."media0_in cpr 0_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."media0_in cpr 0" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."media0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."media0_in mi_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "420" + } +} + +SectionVendorTuples."media0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, + 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "1" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec0_in cpr 1 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec0_in cpr 1_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."codec0_in cpr 1" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "2" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0x5" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec0_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec0_in mi_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "420" + } +} + +SectionVendorTuples."codec0_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, + 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "2" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec0_out mo_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "1092" + } +} + +SectionVendorTuples."codec0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, + 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "0" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec0_out cpr 2 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec0_out cpr 2_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."codec0_out cpr 2" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "2" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0x5" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "3" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."media0_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."media0_out mo_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "1092" + } +} + +SectionVendorTuples."media0_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, + 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "1" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."media0_out cpr 3 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."media0_out cpr 3_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."media0_out cpr 3" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "3" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "4" + SKL_TKN_U32_CONVERTER "4" + SKL_TKN_U32_PIPE_ID "4" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."dmic01_hifi_in cpr 4 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."dmic01_hifi_in cpr 4_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."dmic01_hifi_in cpr 4" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "1" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "4" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0x0" + SKL_TKN_U32_PARAMS_FIXUP "4" + SKL_TKN_U32_CONVERTER "4" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."dmic01_hifi_in mi num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."dmic01_hifi_in mi_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "420" + } +} + +SectionVendorTuples."dmic01_hifi_in mi" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "178, 110, 101, 57, 113, 59, + 73, 64, 141, 63, 249, 44, 213, 196, 60, 9" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "5" + SKL_TKN_U32_PIPE_CONN_TYPE "0" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec1_out mo num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec1_out mo_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "1092" + } +} + +SectionVendorTuples."codec1_out mo" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "90, 80, 86, 60, 215, 36, + 143, 65, 189, 220, 193, 245, 163, 172, 42, 224" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "8" + SKL_TKN_U8_OUT_QUEUE_COUNT "1" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "0" + SKL_TKN_U8_CONN_TYPE "0" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "6" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "2" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_fmt_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "16" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_2" { + SKL_TKN_U32_DIR_PIN_COUNT "32" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_3" { + SKL_TKN_U32_DIR_PIN_COUNT "48" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_4" { + SKL_TKN_U32_DIR_PIN_COUNT "64" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_5" { + SKL_TKN_U32_DIR_PIN_COUNT "80" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_6" { + SKL_TKN_U32_DIR_PIN_COUNT "96" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.in_pin_7" { + SKL_TKN_U32_DIR_PIN_COUNT "112" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."codec1_out cpr 5 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."codec1_out cpr 5_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."codec1_out cpr 5" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "2" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "5" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0x5" + SKL_TKN_U32_PARAMS_FIXUP "0" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "6" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 6 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 6_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 6" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "6" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 7 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 7_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."hdmi1_pt_out cpr 7" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "7" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "7" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 8 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 8_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 8" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "8" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 9 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 9_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."hdmi2_pt_out cpr 9" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "9" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "8" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 10 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 10_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 10" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "10" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 11 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 11_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."hdmi3_pt_out cpr 11" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "1" + SKL_TKN_U8_HW_CONN_TYPE "1" + SKL_TKN_U8_DEV_TYPE "4" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "11" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "384" + SKL_TKN_U32_IBS "384" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "7" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "9" + SKL_TKN_U32_PIPE_CONN_TYPE "1" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "2" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffffff10" + SKL_TKN_U32_FMT_CH_CONFIG "0x1" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."mch_cap_in cpr 12 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."mch_cap_in cpr 12_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."mch_cap_in cpr 12" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "1" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "12" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "200000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "768" + SKL_TKN_U32_IBS "768" + SKL_TKN_U32_VBUS_ID "0x0" + SKL_TKN_U32_PARAMS_FIXUP "4" + SKL_TKN_U32_CONVERTER "0" + SKL_TKN_U32_PIPE_ID "10" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffff4320" + SKL_TKN_U32_FMT_CH_CONFIG "0x5" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffff4320" + SKL_TKN_U32_FMT_CH_CONFIG "0x5" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffff4320" + SKL_TKN_U32_FMT_CH_CONFIG "0x5" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."mch_cap_in cpr 13 num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."mch_cap_in cpr 13_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "516" + } +} + +SectionVendorTuples."mch_cap_in cpr 13" { + tokens "skl_tokens" + + tuples."uuid" { + SKL_TKN_UUID "131, 12, 160, 155, 18, 202, + 131, 74, 148, 60, 31, 162, 232, 47, 157, 218" + } + + tuples."byte.u8_data" { + SKL_TKN_U8_IN_PIN_TYPE "0" + SKL_TKN_U8_OUT_PIN_TYPE "0" + SKL_TKN_U8_IN_QUEUE_COUNT "1" + SKL_TKN_U8_OUT_QUEUE_COUNT "2" + SKL_TKN_U8_DYN_IN_PIN "1" + SKL_TKN_U8_DYN_OUT_PIN "1" + SKL_TKN_U8_TIME_SLOT "0" + SKL_TKN_U8_CORE_ID "0" + SKL_TKN_U8_MODULE_TYPE "1" + SKL_TKN_U8_CONN_TYPE "2" + SKL_TKN_U8_HW_CONN_TYPE "2" + SKL_TKN_U8_DEV_TYPE "5" + } + + tuples."short.u16_data" { + SKL_TKN_U16_MOD_INST_ID "13" + } + + tuples."word.u32_data" { + SKL_TKN_U32_MAX_MCPS "100000" + SKL_TKN_U32_MEM_PAGES "1" + SKL_TKN_U32_OBS "768" + SKL_TKN_U32_IBS "768" + SKL_TKN_U32_VBUS_ID "0xffffffff" + SKL_TKN_U32_PARAMS_FIXUP "4" + SKL_TKN_U32_CONVERTER "4" + SKL_TKN_U32_PIPE_ID "10" + SKL_TKN_U32_PIPE_CONN_TYPE "2" + SKL_TKN_U32_PIPE_PRIORITY "0" + SKL_TKN_U32_PIPE_MEM_PGS "2" + SKL_TKN_U32_CAPS_SIZE "0" + SKL_TKN_U32_PROC_DOMAIN "0" + } + + tuples."word.in_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffff4320" + SKL_TKN_U32_FMT_CH_CONFIG "0x5" + } + + tuples."word.out_fmt_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffff4320" + SKL_TKN_U32_FMT_CH_CONFIG "0x5" + } + + tuples."word.out_fmt_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_FMT_CH "4" + SKL_TKN_U32_FMT_FREQ "48000" + SKL_TKN_U32_FMT_BIT_DEPTH "32" + SKL_TKN_U32_FMT_SAMPLE_SIZE "24" + SKL_TKN_U32_FMT_INTERLEAVE "0" + SKL_TKN_U32_FMT_SAMPLE_TYPE "0" + SKL_TKN_U32_FMT_CH_MAP "0xffff4320" + SKL_TKN_U32_FMT_CH_CONFIG "0x5" + } + + tuples."word.in_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "0" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_0" { + SKL_TKN_U32_DIR_PIN_COUNT "1" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } + + tuples."word.out_pin_1" { + SKL_TKN_U32_DIR_PIN_COUNT "17" + SKL_TKN_U32_PIN_MOD_ID "0" + SKL_TKN_U32_PIN_INST_ID "0" + } +} + +SectionVendorTuples."lib_data num_desc" { + tokens "skl_tokens" + + tuples."byte.u8_num_blocks" { + SKL_TKN_U8_NUM_BLOCKS "1" + } +} + +SectionVendorTuples."lib_data_size_desc" { + tokens "skl_tokens" + tuples."byte.u8_block_type"{ + SKL_TKN_U8_BLOCK_TYPE "0" + } + tuples."short.u16_size_desc"{ + SKL_TKN_U16_BLOCK_SIZE "56" + } +} + +SectionVendorTuples."lib_data" { + tokens "skl_tokens" + + tuples."word.lib_name" { + SKL_TKN_U32_LIB_COUNT "1" + } + + tuples."string.lib_name_0" { + SKL_TKN_STR_LIB_NAME "base_fw" + } + +} + + +SectionData."media0_in cpr 0 num_desc" { + tuples "media0_in cpr 0 num_desc" +} + +SectionData."media0_in cpr 0_size_desc" { + tuples "media0_in cpr 0_size_desc" +} + +SectionData."media0_in cpr 0" { + tuples "media0_in cpr 0" +} + +SectionData."media0_in mi num_desc" { + tuples "media0_in mi num_desc" +} + +SectionData."media0_in mi_size_desc" { + tuples "media0_in mi_size_desc" +} + +SectionData."media0_in mi" { + tuples "media0_in mi" +} + +SectionData."codec0_in cpr 1 num_desc" { + tuples "codec0_in cpr 1 num_desc" +} + +SectionData."codec0_in cpr 1_size_desc" { + tuples "codec0_in cpr 1_size_desc" +} + +SectionData."codec0_in cpr 1" { + tuples "codec0_in cpr 1" +} + +SectionData."codec0_in mi num_desc" { + tuples "codec0_in mi num_desc" +} + +SectionData."codec0_in mi_size_desc" { + tuples "codec0_in mi_size_desc" +} + +SectionData."codec0_in mi" { + tuples "codec0_in mi" +} + +SectionData."codec0_out mo num_desc" { + tuples "codec0_out mo num_desc" +} + +SectionData."codec0_out mo_size_desc" { + tuples "codec0_out mo_size_desc" +} + +SectionData."codec0_out mo" { + tuples "codec0_out mo" +} + +SectionData."codec0_out cpr 2 num_desc" { + tuples "codec0_out cpr 2 num_desc" +} + +SectionData."codec0_out cpr 2_size_desc" { + tuples "codec0_out cpr 2_size_desc" +} + +SectionData."codec0_out cpr 2" { + tuples "codec0_out cpr 2" +} + +SectionData."media0_out mo num_desc" { + tuples "media0_out mo num_desc" +} + +SectionData."media0_out mo_size_desc" { + tuples "media0_out mo_size_desc" +} + +SectionData."media0_out mo" { + tuples "media0_out mo" +} + +SectionData."media0_out cpr 3 num_desc" { + tuples "media0_out cpr 3 num_desc" +} + +SectionData."media0_out cpr 3_size_desc" { + tuples "media0_out cpr 3_size_desc" +} + +SectionData."media0_out cpr 3" { + tuples "media0_out cpr 3" +} + +SectionData."dmic01_hifi_in cpr 4 num_desc" { + tuples "dmic01_hifi_in cpr 4 num_desc" +} + +SectionData."dmic01_hifi_in cpr 4_size_desc" { + tuples "dmic01_hifi_in cpr 4_size_desc" +} + +SectionData."dmic01_hifi_in cpr 4" { + tuples "dmic01_hifi_in cpr 4" +} + +SectionData."dmic01_hifi_in mi num_desc" { + tuples "dmic01_hifi_in mi num_desc" +} + +SectionData."dmic01_hifi_in mi_size_desc" { + tuples "dmic01_hifi_in mi_size_desc" +} + +SectionData."dmic01_hifi_in mi" { + tuples "dmic01_hifi_in mi" +} + +SectionData."codec1_out mo num_desc" { + tuples "codec1_out mo num_desc" +} + +SectionData."codec1_out mo_size_desc" { + tuples "codec1_out mo_size_desc" +} + +SectionData."codec1_out mo" { + tuples "codec1_out mo" +} + +SectionData."codec1_out cpr 5 num_desc" { + tuples "codec1_out cpr 5 num_desc" +} + +SectionData."codec1_out cpr 5_size_desc" { + tuples "codec1_out cpr 5_size_desc" +} + +SectionData."codec1_out cpr 5" { + tuples "codec1_out cpr 5" +} + +SectionData."hdmi1_pt_out cpr 6 num_desc" { + tuples "hdmi1_pt_out cpr 6 num_desc" +} + +SectionData."hdmi1_pt_out cpr 6_size_desc" { + tuples "hdmi1_pt_out cpr 6_size_desc" +} + +SectionData."hdmi1_pt_out cpr 6" { + tuples "hdmi1_pt_out cpr 6" +} + +SectionData."hdmi1_pt_out cpr 7 num_desc" { + tuples "hdmi1_pt_out cpr 7 num_desc" +} + +SectionData."hdmi1_pt_out cpr 7_size_desc" { + tuples "hdmi1_pt_out cpr 7_size_desc" +} + +SectionData."hdmi1_pt_out cpr 7" { + tuples "hdmi1_pt_out cpr 7" +} + +SectionData."hdmi2_pt_out cpr 8 num_desc" { + tuples "hdmi2_pt_out cpr 8 num_desc" +} + +SectionData."hdmi2_pt_out cpr 8_size_desc" { + tuples "hdmi2_pt_out cpr 8_size_desc" +} + +SectionData."hdmi2_pt_out cpr 8" { + tuples "hdmi2_pt_out cpr 8" +} + +SectionData."hdmi2_pt_out cpr 9 num_desc" { + tuples "hdmi2_pt_out cpr 9 num_desc" +} + +SectionData."hdmi2_pt_out cpr 9_size_desc" { + tuples "hdmi2_pt_out cpr 9_size_desc" +} + +SectionData."hdmi2_pt_out cpr 9" { + tuples "hdmi2_pt_out cpr 9" +} + +SectionData."hdmi3_pt_out cpr 10 num_desc" { + tuples "hdmi3_pt_out cpr 10 num_desc" +} + +SectionData."hdmi3_pt_out cpr 10_size_desc" { + tuples "hdmi3_pt_out cpr 10_size_desc" +} + +SectionData."hdmi3_pt_out cpr 10" { + tuples "hdmi3_pt_out cpr 10" +} + +SectionData."hdmi3_pt_out cpr 11 num_desc" { + tuples "hdmi3_pt_out cpr 11 num_desc" +} + +SectionData."hdmi3_pt_out cpr 11_size_desc" { + tuples "hdmi3_pt_out cpr 11_size_desc" +} + +SectionData."hdmi3_pt_out cpr 11" { + tuples "hdmi3_pt_out cpr 11" +} + +SectionData."mch_cap_in cpr 12 num_desc" { + tuples "mch_cap_in cpr 12 num_desc" +} + +SectionData."mch_cap_in cpr 12_size_desc" { + tuples "mch_cap_in cpr 12_size_desc" +} + +SectionData."mch_cap_in cpr 12" { + tuples "mch_cap_in cpr 12" +} + +SectionData."mch_cap_in cpr 13 num_desc" { + tuples "mch_cap_in cpr 13 num_desc" +} + +SectionData."mch_cap_in cpr 13_size_desc" { + tuples "mch_cap_in cpr 13_size_desc" +} + +SectionData."mch_cap_in cpr 13" { + tuples "mch_cap_in cpr 13" +} + +SectionData."lib_data num_desc" { + tuples "lib_data num_desc" +} + +SectionData."lib_data_size_desc" { + tuples "lib_data_size_desc" +} + +SectionData."lib_data" { + tuples "lib_data" +} + + +SectionControlMixer."media0_in mi Switch" { + index"1" + invert "false" + max "1" + min"0" + no_pm "true" + channel."fl" { + reg "-1" + shift "0" + } + channel."fr" { + reg "-1" + shift "0" + } + ops."ctl" { + get "64" + put "64" + info "64" + } +} +SectionControlMixer."dmic01_hifi_in mi Switch" { + index"1" + invert "false" + max "1" + min"0" + no_pm "true" + channel."fl" { + reg "-1" + shift "0" + } + channel."fr" { + reg "-1" + shift "0" + } + ops."ctl" { + get "64" + put "64" + info "64" + } +} +SectionControlMixer."codec0_in mi Switch" { + index"1" + invert "false" + max "1" + min"0" + no_pm "true" + channel."fl" { + reg "-1" + shift "0" + } + channel."fr" { + reg "-1" + shift "0" + } + ops."ctl" { + get "64" + put "64" + info "64" + } +} + + +SectionWidget."media0_in cpr 0" { + index"1" + type"mixer" + no_pm "true" + event_type "3" + event_flags "9" + data [ + "media0_in cpr 0 num_desc" + "media0_in cpr 0_size_desc" + "media0_in cpr 0" + ] +} +SectionWidget."media0_in mi" { + index"1" + type"pga" + no_pm "true" + event_type "4" + event_flags "9" + subseq "10" + data [ + "media0_in mi num_desc" + "media0_in mi_size_desc" + "media0_in mi" + ] +} +SectionWidget."codec0_in cpr 1" { + index"1" + type"mixer" + no_pm "true" + event_type "3" + event_flags "9" + data [ + "codec0_in cpr 1 num_desc" + "codec0_in cpr 1_size_desc" + "codec0_in cpr 1" + ] +} +SectionWidget."codec0_in mi" { + index"1" + type"pga" + no_pm "true" + event_type "4" + event_flags "9" + subseq "10" + data [ + "codec0_in mi num_desc" + "codec0_in mi_size_desc" + "codec0_in mi" + ] +} +SectionWidget."codec0_in" { + index"1" + type"aif_in" + no_pm "true" +} +SectionWidget."codec0_out mo" { + index"1" + type"mixer" + no_pm "true" + event_type "1" + event_flags "15" + subseq "10" + data [ + "codec0_out mo num_desc" + "codec0_out mo_size_desc" + "codec0_out mo" + ] + mixer [ + "media0_in mi Switch" + "dmic01_hifi_in mi Switch" + "codec0_in mi Switch" + ] +} +SectionWidget."codec0_out cpr 2" { + index"1" + type"pga" + no_pm "true" + event_type "4" + data [ + "codec0_out cpr 2 num_desc" + "codec0_out cpr 2_size_desc" + "codec0_out cpr 2" + ] +} +SectionWidget."codec0_out" { + index"1" + type"aif_out" + no_pm "true" +} +SectionWidget."media0_out mo" { + index"1" + type"mixer" + no_pm "true" + event_type "1" + event_flags "15" + subseq "10" + data [ + "media0_out mo num_desc" + "media0_out mo_size_desc" + "media0_out mo" + ] + mixer [ + "media0_in mi Switch" + "dmic01_hifi_in mi Switch" + "codec0_in mi Switch" + ] +} +SectionWidget."media0_out cpr 3" { + index"1" + type"pga" + no_pm "true" + event_type "4" + data [ + "media0_out cpr 3 num_desc" + "media0_out cpr 3_size_desc" + "media0_out cpr 3" + ] +} +SectionWidget."dmic01_hifi_in cpr 4" { + index"1" + type"mixer" + no_pm "true" + event_type "3" + event_flags "9" + data [ + "dmic01_hifi_in cpr 4 num_desc" + "dmic01_hifi_in cpr 4_size_desc" + "dmic01_hifi_in cpr 4" + ] +} +SectionWidget."dmic01_hifi_in mi" { + index"1" + type"pga" + no_pm "true" + event_type "4" + event_flags "9" + subseq "10" + data [ + "dmic01_hifi_in mi num_desc" + "dmic01_hifi_in mi_size_desc" + "dmic01_hifi_in mi" + ] +} +SectionWidget."dmic01_hifi" { + index"1" + type"aif_in" + no_pm "true" +} +SectionWidget."codec1_out mo" { + index"1" + type"mixer" + no_pm "true" + event_type "1" + event_flags "15" + subseq "10" + data [ + "codec1_out mo num_desc" + "codec1_out mo_size_desc" + "codec1_out mo" + ] + mixer [ + "media0_in mi Switch" + "dmic01_hifi_in mi Switch" + "codec0_in mi Switch" + ] +} +SectionWidget."codec1_out cpr 5" { + index"1" + type"pga" + no_pm "true" + event_type "4" + data [ + "codec1_out cpr 5 num_desc" + "codec1_out cpr 5_size_desc" + "codec1_out cpr 5" + ] +} +SectionWidget."codec1_out" { + index"1" + type"aif_out" + no_pm "true" +} +SectionWidget."hdmi1_pt_out cpr 6" { + index"1" + type"mixer" + no_pm "true" + event_type "3" + event_flags "9" + data [ + "hdmi1_pt_out cpr 6 num_desc" + "hdmi1_pt_out cpr 6_size_desc" + "hdmi1_pt_out cpr 6" + ] +} +SectionWidget."hdmi1_pt_out cpr 7" { + index"1" + type"pga" + no_pm "true" + event_type "4" + data [ + "hdmi1_pt_out cpr 7 num_desc" + "hdmi1_pt_out cpr 7_size_desc" + "hdmi1_pt_out cpr 7" + ] +} +SectionWidget."iDisp1_out" { + index"1" + type"aif_out" + no_pm "true" +} +SectionWidget."hdmi2_pt_out cpr 8" { + index"1" + type"mixer" + no_pm "true" + event_type "3" + event_flags "9" + data [ + "hdmi2_pt_out cpr 8 num_desc" + "hdmi2_pt_out cpr 8_size_desc" + "hdmi2_pt_out cpr 8" + ] +} +SectionWidget."hdmi2_pt_out cpr 9" { + index"1" + type"pga" + no_pm "true" + event_type "4" + data [ + "hdmi2_pt_out cpr 9 num_desc" + "hdmi2_pt_out cpr 9_size_desc" + "hdmi2_pt_out cpr 9" + ] +} +SectionWidget."iDisp2_out" { + index"1" + type"aif_out" + no_pm "true" +} +SectionWidget."hdmi3_pt_out cpr 10" { + index"1" + type"mixer" + no_pm "true" + event_type "3" + event_flags "9" + data [ + "hdmi3_pt_out cpr 10 num_desc" + "hdmi3_pt_out cpr 10_size_desc" + "hdmi3_pt_out cpr 10" + ] +} +SectionWidget."hdmi3_pt_out cpr 11" { + index"1" + type"pga" + no_pm "true" + event_type "4" + data [ + "hdmi3_pt_out cpr 11 num_desc" + "hdmi3_pt_out cpr 11_size_desc" + "hdmi3_pt_out cpr 11" + ] +} +SectionWidget."iDisp3_out" { + index"1" + type"aif_out" + no_pm "true" +} +SectionWidget."mch_cap_in cpr 12" { + index"1" + type"mixer" + no_pm "true" + event_type "3" + event_flags "9" + data [ + "mch_cap_in cpr 12 num_desc" + "mch_cap_in cpr 12_size_desc" + "mch_cap_in cpr 12" + ] +} +SectionWidget."mch_cap_in cpr 13" { + index"1" + type"pga" + no_pm "true" + event_type "4" + data [ + "mch_cap_in cpr 13 num_desc" + "mch_cap_in cpr 13_size_desc" + "mch_cap_in cpr 13" + ] +} +SectionManifest."lib_data" { + data [ + "lib_data num_desc" + "lib_data_size_desc" + "lib_data" + ] +} + +SectionGraph."Pipeline 1 Graph" { + index"1" + lines [ + "media0_in mi, , media0_in cpr 0" + "media0_in cpr 0, , System Playback" + "codec0_in mi, , codec0_in cpr 1" + "codec0_in cpr 1, , codec0_in" + "codec0_out mo, media0_in mi Switch, media0_in mi" + "codec0_out mo, dmic01_hifi_in mi Switch, dmic01_hifi_in mi" + "codec0_out mo, codec0_in mi Switch, codec0_in mi" + "codec0_out cpr 2, , codec0_out mo" + "codec0_out, , codec0_out cpr 2" + "media0_out mo, media0_in mi Switch, media0_in mi" + "media0_out mo, dmic01_hifi_in mi Switch, dmic01_hifi_in mi" + "media0_out mo, codec0_in mi Switch, codec0_in mi" + "media0_out cpr 3, , media0_out mo" + "System Capture, , media0_out cpr 3" + "dmic01_hifi_in mi, , dmic01_hifi_in cpr 4" + "dmic01_hifi_in cpr 4, , dmic01_hifi" + "codec1_out mo, media0_in mi Switch, media0_in mi" + "codec1_out mo, dmic01_hifi_in mi Switch, dmic01_hifi_in mi" + "codec1_out mo, codec0_in mi Switch, codec0_in mi" + "codec1_out cpr 5, , codec1_out mo" + "codec1_out, , codec1_out cpr 5" + "hdmi1_pt_out cpr 7, , hdmi1_pt_out cpr 6" + "hdmi1_pt_out cpr 6, , HDMI1 Playback" + "iDisp1_out, , hdmi1_pt_out cpr 7" + "hdmi2_pt_out cpr 9, , hdmi2_pt_out cpr 8" + "hdmi2_pt_out cpr 8, , HDMI2 Playback" + "iDisp2_out, , hdmi2_pt_out cpr 9" + "hdmi3_pt_out cpr 11, , hdmi3_pt_out cpr 10" + "hdmi3_pt_out cpr 10, , HDMI3 Playback" + "iDisp3_out, , hdmi3_pt_out cpr 11" + "mch_cap_in cpr 13, , mch_cap_in cpr 12" + "DMIC Capture, , mch_cap_in cpr 13" + "mch_cap_in cpr 12, , dmic01_hifi" + ] +} +
participants (1)
-
Vinod Koul