A write sequencer is a sequence of register addresses and values executed by some Cirrus DSPs following power-up or exit from hibernation, used for avoiding the overhead of bus transactions.

Add support for Cirrus drivers to update or add to a write sequencer present in firmware.

Signed-off-by: James Ogletree jogletre@opensource.cirrus.com --- drivers/firmware/cirrus/cs_dsp.c | 261 +++++++++++++++++++++++++ include/linux/firmware/cirrus/cs_dsp.h | 28 +++ 2 files changed, 289 insertions(+)

diff --git a/drivers/firmware/cirrus/cs_dsp.c b/drivers/firmware/cirrus/cs_dsp.c index 79d4254d1f9b..31a999f42e84 100644 --- a/drivers/firmware/cirrus/cs_dsp.c +++ b/drivers/firmware/cirrus/cs_dsp.c @@ -275,6 +275,15 @@ #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff #define HALO_MPU_VIO_ERR_SRC_SHIFT 0

+/* + * Write Sequencer + */ +#define WSEQ_OP_FULL_WORDS 3 +#define WSEQ_OP_X16_WORDS 2 +#define WSEQ_OP_END_WORDS 1 +#define WSEQ_OP_UNLOCK_WORDS 1 +#define WSEQ_END_OF_SCRIPT 0xFFFFFF + struct cs_dsp_ops { bool (*validate_version)(struct cs_dsp *dsp, unsigned int version); unsigned int (*parse_sizes)(struct cs_dsp *dsp, @@ -2233,6 +2242,111 @@ static int cs_dsp_create_name(struct cs_dsp *dsp) return 0; }

+struct cs_dsp_wseq_op { + struct list_head list; + u32 words[3]; + u32 address; + u32 data; + u16 offset; + u8 operation; +}; + +static int cs_dsp_populate_wseq(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq) +{ + struct cs_dsp_wseq_op *op = NULL; + struct cs_dsp_chunk ch; + int i, num_words, ret; + u32 *words; + + if (wseq->size <= 0 || !wseq->reg) + return -EINVAL; + + words = kcalloc(wseq->size, sizeof(u32), GFP_KERNEL); + if (!words) + return -ENOMEM; + + INIT_LIST_HEAD(&wseq->ops); + + ret = regmap_raw_read(dsp->regmap, wseq->reg, words, + wseq->size * sizeof(u32)); + if (ret) + goto err_free; + + ch = cs_dsp_chunk(words, wseq->size * sizeof(u32)); + + for (i = 0; i < wseq->size; i += num_words) { + op = devm_kzalloc(dsp->dev, sizeof(*op), GFP_KERNEL); + if (!op) { + ret = -ENOMEM; + goto err_free; + } + + op->offset = ch.bytes; + op->operation = cs_dsp_chunk_read(&ch, 8); + + switch (op->operation) { + case CS_DSP_WSEQ_END: + num_words = WSEQ_OP_END_WORDS; + break; + case CS_DSP_WSEQ_UNLOCK: + num_words = WSEQ_OP_UNLOCK_WORDS; + op->address = 0; + op->data = cs_dsp_chunk_read(&ch, 16); + break; + case CS_DSP_WSEQ_ADDR8: + case CS_DSP_WSEQ_H16: + case CS_DSP_WSEQ_L16: + num_words = WSEQ_OP_X16_WORDS; + op->address = cs_dsp_chunk_read(&ch, 24); + op->data = cs_dsp_chunk_read(&ch, 16); + break; + case CS_DSP_WSEQ_FULL: + num_words = WSEQ_OP_FULL_WORDS; + op->address = cs_dsp_chunk_read(&ch, 32); + op->data = cs_dsp_chunk_read(&ch, 32); + break; + default: + ret = -EINVAL; + cs_dsp_err(dsp, "Unsupported op: %u\n", op->operation); + goto err_free; + } + + list_add(&op->list, &wseq->ops); + + if (op->operation == CS_DSP_WSEQ_END) + break; + } + + if (op && op->operation != CS_DSP_WSEQ_END) + ret = -ENOENT; +err_free: + kfree(words); + + return ret; +} + +/** + * cs_dsp_wseq_init() - Initialize write sequences contained within the loaded DSP firmware + * @dsp: pointer to DSP structure + * @wseqs: list of write sequences to initialize + * @num_wseqs: number of write sequences to initialize + * + * Return: Zero for success, a negative number on error. + */ +int cs_dsp_wseq_init(struct cs_dsp *dsp, struct cs_dsp_wseq *wseqs, unsigned int num_wseqs) +{ + int i, ret; + + for (i = 0; i < num_wseqs; i++) { + ret = cs_dsp_populate_wseq(dsp, &wseqs[i]); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cs_dsp_wseq_init); + static int cs_dsp_common_init(struct cs_dsp *dsp) { int ret; @@ -3339,6 +3453,153 @@ int cs_dsp_chunk_read(struct cs_dsp_chunk *ch, int nbits) } EXPORT_SYMBOL_NS_GPL(cs_dsp_chunk_read, FW_CS_DSP);

+static struct cs_dsp_wseq_op *cs_dsp_wseq_find_op(u8 op_code, u32 addr, + struct list_head *wseq_ops) +{ + struct cs_dsp_wseq_op *op; + + list_for_each_entry(op, wseq_ops, list) { + if (op->operation == op_code && op->address == addr) + return op; + } + + return NULL; +} + +/** + * cs_dsp_wseq_write() - Add or update an entry in a write sequence + * @dsp: Pointer to a DSP structure + * @wseq: Write sequence to write to + * @addr: Address of the register to be written to + * @data: Data to be written + * @update: If true, searches for the first entry in the Write Sequencer with + * the same address and op_code, and replaces it. If false, creates a new entry + * at the tail. + * @op_code: The type of operation of the new entry + * + * This function formats register address and value pairs into the format + * required for write sequence entries, and either updates or adds the + * new entry into the write sequence. + * + * Return: Zero for success, a negative number on error. + */ +int cs_dsp_wseq_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, + u32 addr, u32 data, bool update, u8 op_code) +{ + struct cs_dsp_wseq_op *op_end, *op_new; + struct cs_dsp_chunk ch; + u32 wseq_bytes; + int new_op_size, ret; + + if (update) { + op_new = cs_dsp_wseq_find_op(op_code, addr, &wseq->ops); + if (!op_new) + return -EINVAL; + } else { + op_new = devm_kzalloc(dsp->dev, sizeof(*op_new), GFP_KERNEL); + if (!op_new) + return -ENOMEM; + + op_new->operation = op_code; + op_new->address = addr; + } + + op_new->data = data; + + ch = cs_dsp_chunk((void *) op_new->words, + WSEQ_OP_FULL_WORDS * sizeof(u32)); + cs_dsp_chunk_write(&ch, 8, op_new->operation); + switch (op_code) { + case CS_DSP_WSEQ_FULL: + cs_dsp_chunk_write(&ch, 32, op_new->address); + cs_dsp_chunk_write(&ch, 32, op_new->data); + break; + case CS_DSP_WSEQ_L16: + case CS_DSP_WSEQ_H16: + cs_dsp_chunk_write(&ch, 24, op_new->address); + cs_dsp_chunk_write(&ch, 16, op_new->data); + break; + default: + ret = -EINVAL; + goto op_new_free; + } + + new_op_size = cs_dsp_chunk_bytes(&ch); + + op_end = cs_dsp_wseq_find_op(CS_DSP_WSEQ_END, 0, &wseq->ops); + if (!op_end) { + cs_dsp_err(dsp, "Missing write sequencer list terminator\n"); + ret = -EINVAL; + goto op_new_free; + } + + wseq_bytes = wseq->size * sizeof(u32); + + if (wseq_bytes - op_end->offset < new_op_size) { + cs_dsp_err(dsp, "Not enough memory in Write Sequencer for entry\n"); + ret = -ENOMEM; + goto op_new_free; + } + + if (!update) { + op_new->offset = op_end->offset; + op_end->offset += new_op_size; + } + + ret = regmap_raw_write(dsp->regmap, wseq->reg + op_new->offset, + op_new->words, new_op_size); + if (ret) + goto op_new_free; + + if (!update) { + ret = regmap_write(dsp->regmap, wseq->reg + op_end->offset, + WSEQ_END_OF_SCRIPT); + if (ret) + goto op_new_free; + + list_add(&op_new->list, &wseq->ops); + } + + return 0; + +op_new_free: + devm_kfree(dsp->dev, op_new); + + return ret; +} +EXPORT_SYMBOL_GPL(cs_dsp_wseq_write); + +/** + * cs_dsp_wseq_multi_write() - Add or update multiple entries in the write sequence + * @dsp: Pointer to a DSP structure + * @wseq: Write sequence to write to + * @reg_seq: List of address-data pairs + * @num_regs: Number of address-data pairs + * @update: If true, searches for the first entry in the write sequence with the same + * address and op code, and replaces it. If false, creates a new entry at the tail. + * @op_code: The types of operations of the new entries + * + * This function calls cs_dsp_wseq_write() for multiple address-data pairs. + * + * Return: Zero for success, a negative number on error. + */ +int cs_dsp_wseq_multi_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, + const struct reg_sequence *reg_seq, + int num_regs, bool update, u8 op_code) +{ + int ret, i; + + for (i = 0; i < num_regs; i++) { + ret = cs_dsp_wseq_write(dsp, wseq, reg_seq[i].reg, + reg_seq[i].def, update, op_code); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cs_dsp_wseq_multi_write); + MODULE_DESCRIPTION("Cirrus Logic DSP Support"); MODULE_AUTHOR("Simon Trimmer simont@opensource.cirrus.com"); MODULE_LICENSE("GPL v2"); diff --git a/include/linux/firmware/cirrus/cs_dsp.h b/include/linux/firmware/cirrus/cs_dsp.h index 29cd11d5a3cf..d674fc061e9d 100644 --- a/include/linux/firmware/cirrus/cs_dsp.h +++ b/include/linux/firmware/cirrus/cs_dsp.h @@ -42,6 +42,16 @@ #define CS_DSP_ACKED_CTL_MIN_VALUE 0 #define CS_DSP_ACKED_CTL_MAX_VALUE 0xFFFFFF

+/* + * Write sequencer operation codes + */ +#define CS_DSP_WSEQ_FULL 0x00 +#define CS_DSP_WSEQ_ADDR8 0x02 +#define CS_DSP_WSEQ_L16 0x04 +#define CS_DSP_WSEQ_H16 0x05 +#define CS_DSP_WSEQ_UNLOCK 0xFD +#define CS_DSP_WSEQ_END 0xFF + /** * struct cs_dsp_region - Describes a logical memory region in DSP address space * @type: Memory region type @@ -107,6 +117,18 @@ struct cs_dsp_coeff_ctl { struct cs_dsp_ops; struct cs_dsp_client_ops;

+/** + * struct cs_dsp_wseq - Describes a write sequence + * @reg: Address of the head of the write sequence register + * @size: Size of the write sequence in words + * @ops: Operations contained within the write sequence + */ +struct cs_dsp_wseq { + unsigned int reg; + unsigned int size; + struct list_head ops; +}; + /** * struct cs_dsp - Configuration and state of a Cirrus Logic DSP * @name: The name of the DSP instance @@ -254,6 +276,12 @@ struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp, int type, unsigned int id);

const char *cs_dsp_mem_region_name(unsigned int type); +int cs_dsp_wseq_init(struct cs_dsp *dsp, struct cs_dsp_wseq *wseqs, unsigned int num_wseqs); +int cs_dsp_wseq_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, u32 addr, u32 data, + bool update, u8 op_code); +int cs_dsp_wseq_multi_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, + const struct reg_sequence *reg_seq, + int num_regs, bool update, u8 op_code);

/** * struct cs_dsp_chunk - Describes a buffer holding data formatted for the DSP

The CS40L50 is a haptic driver with waveform memory, integrated DSP, and closed-loop algorithms.

Add a YAML DT binding document for this device.

Reviewed-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org Signed-off-by: James Ogletree jogletre@opensource.cirrus.com --- .../bindings/input/cirrus,cs40l50.yaml | 70 +++++++++++++++++++ MAINTAINERS | 8 +++ 2 files changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml

diff --git a/Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml b/Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml new file mode 100644 index 000000000000..6a5bdafed56b --- /dev/null +++ b/Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/cirrus,cs40l50.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS40L50 Advanced Haptic Driver + +maintainers: + - James Ogletree james.ogletree@cirrus.com + +description: + CS40L50 is a haptic driver with waveform memory, + integrated DSP, and closed-loop algorithms. + +properties: + compatible: + enum: + - cirrus,cs40l50 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + va-supply: + description: Power supply for internal analog circuits. + + vp-supply: + description: Power supply for always-on circuits. + + vio-supply: + description: Power supply for digital input/output. + + vamp-supply: + description: Power supply for the Class D amplifier. + +required: + - compatible + - reg + - interrupts + - reset-gpios + - vp-supply + - vio-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + haptic-driver@34 { + compatible = "cirrus,cs40l50"; + reg = <0x34>; + interrupt-parent = <&gpio>; + interrupts = <113 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio 112 GPIO_ACTIVE_LOW>; + vp-supply = <&vreg>; + vio-supply = <&vreg>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index dd5de540ec0b..b71017a187f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4933,6 +4933,14 @@ F: sound/pci/hda/cs* F: sound/pci/hda/hda_cs_dsp_ctl.* F: sound/soc/codecs/cs*

+CIRRUS LOGIC HAPTIC DRIVERS +M: James Ogletree james.ogletree@cirrus.com +M: Fred Treven fred.treven@cirrus.com +M: Ben Bright ben.bright@cirrus.com +L: patches@opensource.cirrus.com +S: Supported +F: Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml + CIRRUS LOGIC DSP FIRMWARE DRIVER M: Simon Trimmer simont@opensource.cirrus.com M: Charles Keepax ckeepax@opensource.cirrus.com

Introduce support for Cirrus Logic Device CS40L50: a haptic driver with waveform memory, integrated DSP, and closed-loop algorithms.

The input driver provides the interface for control of haptic effects through the device.

Signed-off-by: James Ogletree jogletre@opensource.cirrus.com --- MAINTAINERS | 1 + drivers/input/misc/Kconfig | 10 + drivers/input/misc/Makefile | 1 + drivers/input/misc/cs40l50-vibra.c | 572 +++++++++++++++++++++++++++++ 4 files changed, 584 insertions(+) create mode 100644 drivers/input/misc/cs40l50-vibra.c

diff --git a/MAINTAINERS b/MAINTAINERS index 69a9e0a3b968..24cfb4f017bb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4940,6 +4940,7 @@ M: Ben Bright ben.bright@cirrus.com L: patches@opensource.cirrus.com S: Supported F: Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml +F: drivers/input/misc/cs40l* F: drivers/mfd/cs40l* F: include/linux/mfd/cs40l*

diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 6ba984d7f0b1..ee45dbb0636e 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -140,6 +140,16 @@ config INPUT_BMA150 To compile this driver as a module, choose M here: the module will be called bma150.

+config INPUT_CS40L50_VIBRA + tristate "CS40L50 Haptic Driver support" + depends on MFD_CS40L50_CORE + help + Say Y here to enable support for Cirrus Logic's CS40L50 + haptic driver. + + To compile this driver as a module, choose M here: the + module will be called cs40l50-vibra. + config INPUT_E3X0_BUTTON tristate "NI Ettus Research USRP E3xx Button support." default n diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index 04296a4abe8e..88279de6d3d5 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_INPUT_CMA3000) += cma3000_d0x.o obj-$(CONFIG_INPUT_CMA3000_I2C) += cma3000_d0x_i2c.o obj-$(CONFIG_INPUT_COBALT_BTNS) += cobalt_btns.o obj-$(CONFIG_INPUT_CPCAP_PWRBUTTON) += cpcap-pwrbutton.o +obj-$(CONFIG_INPUT_CS40L50_VIBRA) += cs40l50-vibra.o obj-$(CONFIG_INPUT_DA7280_HAPTICS) += da7280.o obj-$(CONFIG_INPUT_DA9052_ONKEY) += da9052_onkey.o obj-$(CONFIG_INPUT_DA9055_ONKEY) += da9055_onkey.o diff --git a/drivers/input/misc/cs40l50-vibra.c b/drivers/input/misc/cs40l50-vibra.c new file mode 100644 index 000000000000..cd3c2bf132da --- /dev/null +++ b/drivers/input/misc/cs40l50-vibra.c @@ -0,0 +1,572 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CS40L50 Advanced Haptic Driver with waveform memory, + * integrated DSP, and closed-loop algorithms + * + * Copyright 2023 Cirrus Logic, Inc. + * + * Author: James Ogletree james.ogletree@cirrus.com + */ + +#include <linux/input.h> +#include <linux/mfd/cs40l50.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> + +/* Wavetables */ +#define CS40L50_RAM_INDEX_START 0x1000000 +#define CS40L50_RAM_INDEX_END 0x100007F +#define CS40L50_RTH_INDEX_START 0x1400000 +#define CS40L50_RTH_INDEX_END 0x1400001 +#define CS40L50_ROM_INDEX_START 0x1800000 +#define CS40L50_ROM_INDEX_END 0x180001A +#define CS40L50_OWT_HEADER_SIZE 12 +#define CS40L50_OWT_TYPE_PCM 8 +#define CS40L50_OWT_TYPE_PWLE 12 +#define CS40L50_OWT_PCM_ID 0x0 +#define CS40L50_OWT_CUSTOM_DATA_SIZE 2 + +/* DSP */ +#define CS40L50_GPIO_BASE 0x2804140 +#define CS40L50_OWT_BASE 0x2805C34 +#define CS40L50_OWT_SIZE 0x2805C38 +#define CS40L50_OWT_NEXT 0x2805C3C + +/* GPIO */ +#define CS40L50_GPIO_NUM_MASK GENMASK(14, 12) +#define CS40L50_GPIO_EDGE_MASK BIT(15) +#define CS40L50_GPIO_MAPPING_INVALID 0 +#define CS40L50_GPIO_DISABLE 0x1FF + +enum vibra_bank_type { + WVFRM_BANK_RAM, + WVFRM_BANK_ROM, + WVFRM_BANK_OWT, + WVFRM_BANK_NUM, +}; + +/* Describes an area in DSP memory populated by effects */ +struct vibra_bank { + enum vibra_bank_type bank; + u32 base_index; + u32 max_index; +}; + +struct vibra_effect { + enum vibra_bank_type bank; + struct list_head list; + u32 gpio_mapping; + u32 index; + int id; +}; + +/* Describes haptic interface of loaded DSP firmware */ +struct vibra_dsp { + struct vibra_bank *banks; + u32 gpio_base_reg; + u32 owt_offset_reg; + u32 owt_size_reg; + u32 owt_base_reg; + u32 mailbox_reg; + u32 push_owt_cmd; + u32 delete_owt_cmd; + u32 stop_cmd; +}; + +/* Describes configuration and state of haptic operations */ +struct vibra_info { + struct device *dev; + struct regmap *regmap; + struct input_dev *input; + struct mutex lock; + struct workqueue_struct *vibe_wq; + struct work_struct vibe_start_work; + struct work_struct vibe_stop_work; + struct work_struct erase_work; + struct work_struct add_work; + struct ff_effect *start_effect; + struct ff_effect *erase_effect; + struct ff_effect add_effect; + struct list_head effect_head; + struct vibra_dsp dsp; + int erase_error; + int add_error; +}; + +static struct vibra_effect *vibra_find_effect(int id, struct list_head *effect_head) +{ + struct vibra_effect *effect; + + list_for_each_entry(effect, effect_head, list) + if (effect->id == id) + return effect; + + return NULL; +} + +static int vibra_effect_bank_set(struct vibra_info *info, + struct vibra_effect *effect, + struct ff_periodic_effect add_effect) +{ + s16 bank = add_effect.custom_data[0] & 0xffffu; + unsigned int len = add_effect.custom_len; + + if (bank >= WVFRM_BANK_NUM) { + dev_err(info->dev, "Invalid waveform bank: %d\n", bank); + return -EINVAL; + } + + effect->bank = len > CS40L50_OWT_CUSTOM_DATA_SIZE ? WVFRM_BANK_OWT : bank; + + return 0; +} + +static int vibra_effect_mapping_set(struct vibra_info *info, u16 button, + struct vibra_effect *effect) +{ + u32 gpio_num, gpio_edge; + + if (button) { + gpio_num = FIELD_GET(CS40L50_GPIO_NUM_MASK, button); + gpio_edge = FIELD_GET(CS40L50_GPIO_EDGE_MASK, button); + effect->gpio_mapping = info->dsp.gpio_base_reg + + (gpio_num * 8) - gpio_edge; + + return regmap_write(info->regmap, effect->gpio_mapping, button); + } + + effect->gpio_mapping = CS40L50_GPIO_MAPPING_INVALID; + + return 0; +} + +static int vibra_effect_index_set(struct vibra_info *info, + struct vibra_effect *effect, + struct ff_periodic_effect add_effect) +{ + struct vibra_effect *owt_effect; + u32 base_index, max_index; + + base_index = info->dsp.banks[effect->bank].base_index; + max_index = info->dsp.banks[effect->bank].max_index; + + effect->index = base_index; + + switch (effect->bank) { + case WVFRM_BANK_OWT: + list_for_each_entry(owt_effect, &info->effect_head, list) + if (owt_effect->bank == WVFRM_BANK_OWT) + effect->index++; + break; + case WVFRM_BANK_ROM: + case WVFRM_BANK_RAM: + effect->index += add_effect.custom_data[1] & 0xffffu; + break; + default: + dev_err(info->dev, "Bank not supported: %d\n", effect->bank); + return -EINVAL; + } + + if (effect->index > max_index || effect->index < base_index) { + dev_err(info->dev, "Index out of bounds: %u\n", effect->index); + return -ENOSPC; + } + + return 0; +} + +/* Describes a header for an effect in the OWT bank */ +struct owt_header { + u32 type; + u32 data_words; + u32 offset; +} __packed; + +static int vibra_upload_owt(struct vibra_info *info, struct vibra_effect *effect, + struct ff_periodic_effect add_effect) +{ + u32 len, wt_offset, wt_size; + struct owt_header header; + u8 *out_data; + int error; + + error = regmap_read(info->regmap, info->dsp.owt_offset_reg, &wt_offset); + if (error) + return error; + + error = regmap_read(info->regmap, info->dsp.owt_size_reg, &wt_size); + if (error) + return error; + + len = 2 * add_effect.custom_len; + + if ((wt_size * sizeof(u32)) < CS40L50_OWT_HEADER_SIZE + len) + return -ENOSPC; + + out_data = kzalloc(CS40L50_OWT_HEADER_SIZE + len, GFP_KERNEL); + if (!out_data) + return -ENOMEM; + + header.type = add_effect.custom_data[0] == CS40L50_OWT_PCM_ID ? CS40L50_OWT_TYPE_PCM : + CS40L50_OWT_TYPE_PWLE; + header.offset = CS40L50_OWT_HEADER_SIZE / sizeof(u32); + header.data_words = len / sizeof(u32); + + memcpy(out_data, &header, sizeof(header)); + memcpy(out_data + CS40L50_OWT_HEADER_SIZE, add_effect.custom_data, len); + + error = regmap_bulk_write(info->regmap, info->dsp.owt_base_reg + + (wt_offset * sizeof(u32)), out_data, + CS40L50_OWT_HEADER_SIZE + len); + if (error) + goto err_free; + + error = regmap_write(info->regmap, info->dsp.mailbox_reg, + info->dsp.push_owt_cmd); + +err_free: + kfree(out_data); + + return error; +} + +static void vibra_add_worker(struct work_struct *work) +{ + struct vibra_info *info = container_of(work, struct vibra_info, add_work); + struct ff_effect add_effect = info->add_effect; + struct vibra_effect *effect; + bool is_new = false; + int error; + + error = pm_runtime_resume_and_get(info->dev); + if (error < 0) { + info->add_error = error; + return; + } + + mutex_lock(&info->lock); + + effect = vibra_find_effect(add_effect.id, &info->effect_head); + if (!effect) { + effect = kzalloc(sizeof(*effect), GFP_KERNEL); + if (!effect) { + error = -ENOMEM; + goto err_mutex; + } + effect->id = add_effect.id; + is_new = true; + } + + error = vibra_effect_bank_set(info, effect, add_effect.u.periodic); + if (error) + goto err_free; + + error = vibra_effect_index_set(info, effect, add_effect.u.periodic); + if (error) + goto err_free; + + error = vibra_effect_mapping_set(info, add_effect.trigger.button, effect); + if (error) + goto err_free; + + if (effect->bank == WVFRM_BANK_OWT) + error = vibra_upload_owt(info, effect, add_effect.u.periodic); + +err_free: + if (is_new) { + if (error) + kfree(effect); + else + list_add(&effect->list, &info->effect_head); + } + +err_mutex: + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + + info->add_error = error; +} + +static int vibra_add(struct input_dev *dev, struct ff_effect *effect, + struct ff_effect *old) +{ + struct vibra_info *info = input_get_drvdata(dev); + u32 len = effect->u.periodic.custom_len; + + if (effect->type != FF_PERIODIC || effect->u.periodic.waveform != FF_CUSTOM) { + dev_err(info->dev, "Type (%#X) or waveform (%#X) unsupported\n", + effect->type, effect->u.periodic.waveform); + return -EINVAL; + } + + memcpy(&info->add_effect, effect, sizeof(struct ff_effect)); + + info->add_effect.u.periodic.custom_data = kcalloc(len, sizeof(s16), GFP_KERNEL); + if (!info->add_effect.u.periodic.custom_data) + return -ENOMEM; + + if (copy_from_user(info->add_effect.u.periodic.custom_data, + effect->u.periodic.custom_data, sizeof(s16) * len)) { + info->add_error = -EFAULT; + goto out_free; + } + + queue_work(info->vibe_wq, &info->add_work); + flush_work(&info->add_work); +out_free: + kfree(info->add_effect.u.periodic.custom_data); + info->add_effect.u.periodic.custom_data = NULL; + + return info->add_error; +} + +static void vibra_start_worker(struct work_struct *work) +{ + struct vibra_info *info = container_of(work, struct vibra_info, + vibe_start_work); + struct vibra_effect *effect; + + if (pm_runtime_resume_and_get(info->dev) < 0) + return; + + mutex_lock(&info->lock); + + effect = vibra_find_effect(info->start_effect->id, &info->effect_head); + if (effect) + regmap_write(info->regmap, info->dsp.mailbox_reg, effect->index); + + mutex_unlock(&info->lock); + + if (!effect) + dev_err(info->dev, "Effect to play not found\n"); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); +} + +static void vibra_stop_worker(struct work_struct *work) +{ + struct vibra_info *info = container_of(work, struct vibra_info, + vibe_stop_work); + + if (pm_runtime_resume_and_get(info->dev) < 0) + return; + + mutex_lock(&info->lock); + + regmap_write(info->regmap, info->dsp.mailbox_reg, info->dsp.stop_cmd); + + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); +} + +static int vibra_playback(struct input_dev *dev, int effect_id, int val) +{ + struct vibra_info *info = input_get_drvdata(dev); + + if (val > 0) { + info->start_effect = &dev->ff->effects[effect_id]; + queue_work(info->vibe_wq, &info->vibe_start_work); + } else { + queue_work(info->vibe_wq, &info->vibe_stop_work); + } + + return 0; +} + +static void vibra_erase_worker(struct work_struct *work) +{ + struct vibra_info *info = container_of(work, struct vibra_info, + erase_work); + struct vibra_effect *owt_effect, *erase_effect; + int error; + + error = pm_runtime_resume_and_get(info->dev); + if (error < 0) { + info->erase_error = error; + return; + } + + mutex_lock(&info->lock); + + erase_effect = vibra_find_effect(info->erase_effect->id, + &info->effect_head); + if (!erase_effect) { + dev_err(info->dev, "Effect to erase not found\n"); + error = -EINVAL; + goto err_mutex; + } + + if (erase_effect->gpio_mapping != CS40L50_GPIO_MAPPING_INVALID) { + error = regmap_write(info->regmap, erase_effect->gpio_mapping, + CS40L50_GPIO_DISABLE); + if (error) + goto err_mutex; + } + + if (erase_effect->bank == WVFRM_BANK_OWT) { + error = regmap_write(info->regmap, info->dsp.mailbox_reg, + info->dsp.delete_owt_cmd | erase_effect->index); + if (error) + goto err_mutex; + + list_for_each_entry(owt_effect, &info->effect_head, list) + if (owt_effect->bank == WVFRM_BANK_OWT && + owt_effect->index > erase_effect->index) + owt_effect->index--; + } + + list_del(&erase_effect->list); + kfree(erase_effect); + +err_mutex: + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + + info->erase_error = error; +} + +static int vibra_erase(struct input_dev *dev, int effect_id) +{ + struct vibra_info *info = input_get_drvdata(dev); + + info->erase_effect = &dev->ff->effects[effect_id]; + + queue_work(info->vibe_wq, &info->erase_work); + flush_work(&info->erase_work); + + return info->erase_error; +} + +static struct vibra_bank cs40l50_banks[] = { + { + .bank = WVFRM_BANK_RAM, + .base_index = CS40L50_RAM_INDEX_START, + .max_index = CS40L50_RAM_INDEX_END, + }, + { + .bank = WVFRM_BANK_ROM, + .base_index = CS40L50_ROM_INDEX_START, + .max_index = CS40L50_ROM_INDEX_END, + }, + { + .bank = WVFRM_BANK_OWT, + .base_index = CS40L50_RTH_INDEX_START, + .max_index = CS40L50_RTH_INDEX_END, + }, +}; + +static struct vibra_dsp cs40l50_dsp = { + .banks = cs40l50_banks, + .gpio_base_reg = CS40L50_GPIO_BASE, + .owt_base_reg = CS40L50_OWT_BASE, + .owt_offset_reg = CS40L50_OWT_NEXT, + .owt_size_reg = CS40L50_OWT_SIZE, + .mailbox_reg = CS40L50_DSP_QUEUE, + .push_owt_cmd = CS40L50_OWT_PUSH, + .delete_owt_cmd = CS40L50_OWT_DELETE, + .stop_cmd = CS40L50_STOP_PLAYBACK, +}; + +static void vibra_input_unregister(void *data) +{ + input_unregister_device((struct input_dev *)data); +} + +static void vibra_remove_wq(void *data) +{ + struct vibra_info *info = data; + + flush_workqueue(info->vibe_wq); + destroy_workqueue(info->vibe_wq); +} + +static int cs40l50_vibra_probe(struct platform_device *pdev) +{ + struct cs40l50 *cs40l50 = dev_get_drvdata(pdev->dev.parent); + struct vibra_info *info; + int error; + + info = devm_kzalloc(pdev->dev.parent, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev = cs40l50->dev; + info->regmap = cs40l50->regmap; + + info->input = devm_input_allocate_device(info->dev); + if (!info->input) + return -ENOMEM; + + info->input->id.product = cs40l50->devid & 0xFFFF; + info->input->id.version = cs40l50->revid; + info->input->name = "cs40l50_vibra"; + + input_set_drvdata(info->input, info); + input_set_capability(info->input, EV_FF, FF_PERIODIC); + input_set_capability(info->input, EV_FF, FF_CUSTOM); + + error = input_ff_create(info->input, FF_MAX_EFFECTS); + if (error) { + dev_err(info->dev, "Failed to create input device\n"); + return error; + } + + info->input->ff->upload = vibra_add; + info->input->ff->playback = vibra_playback; + info->input->ff->erase = vibra_erase; + + INIT_LIST_HEAD(&info->effect_head); + + info->dsp = cs40l50_dsp; + + info->vibe_wq = alloc_ordered_workqueue("vibe_wq", 0); + if (!info->vibe_wq) + return -ENOMEM; + + error = devm_add_action_or_reset(info->dev, vibra_remove_wq, info); + if (error) + return error; + + mutex_init(&info->lock); + + INIT_WORK(&info->vibe_start_work, vibra_start_worker); + INIT_WORK(&info->vibe_stop_work, vibra_stop_worker); + INIT_WORK(&info->erase_work, vibra_erase_worker); + INIT_WORK(&info->add_work, vibra_add_worker); + + error = input_register_device(info->input); + if (error) { + dev_err(info->dev, "Failed to register input device\n"); + input_free_device(info->input); + return error; + } + + return devm_add_action_or_reset(info->dev, vibra_input_unregister, + info->input); +} + +static const struct platform_device_id vibra_id_match[] = { + { "cs40l50-vibra", }, + {} +}; +MODULE_DEVICE_TABLE(platform, vibra_id_match); + +static struct platform_driver cs40l50_vibra_driver = { + .probe = cs40l50_vibra_probe, + .id_table = vibra_id_match, + .driver = { + .name = "cs40l50-vibra", + }, +}; +module_platform_driver(cs40l50_vibra_driver); + +MODULE_DESCRIPTION("CS40L50 Advanced Haptic Driver"); +MODULE_AUTHOR("James Ogletree, Cirrus Logic Inc. james.ogletree@cirrus.com"); +MODULE_LICENSE("GPL");

Introduce support for Cirrus Logic Device CS40L50: a haptic driver with waveform memory, integrated DSP, and closed-loop algorithms.

The ASoC driver enables I2S streaming to the device.

Signed-off-by: James Ogletree jogletre@opensource.cirrus.com --- MAINTAINERS | 1 + sound/soc/codecs/Kconfig | 11 ++ sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cs40l50-codec.c | 304 +++++++++++++++++++++++++++++++ 4 files changed, 318 insertions(+) create mode 100644 sound/soc/codecs/cs40l50-codec.c

diff --git a/MAINTAINERS b/MAINTAINERS index 24cfb4f017bb..fca2454a7a38 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4943,6 +4943,7 @@ F: Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml F: drivers/input/misc/cs40l* F: drivers/mfd/cs40l* F: include/linux/mfd/cs40l* +F: sound/soc/codecs/cs40l*

CIRRUS LOGIC DSP FIRMWARE DRIVER M: Simon Trimmer simont@opensource.cirrus.com diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index f1e1dbc509f6..9338a36c4c85 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -73,6 +73,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_CS35L56_I2C imply SND_SOC_CS35L56_SPI imply SND_SOC_CS35L56_SDW + imply SND_SOC_CS40L50 imply SND_SOC_CS42L42 imply SND_SOC_CS42L42_SDW imply SND_SOC_CS42L43 @@ -800,6 +801,16 @@ config SND_SOC_CS35L56_SDW help Enable support for Cirrus Logic CS35L56 boosted amplifier with SoundWire control

+config SND_SOC_CS40L50 + tristate "Cirrus Logic CS40L50 CODEC" + depends on MFD_CS40L50_CORE + help + This option enables support for I2S streaming to Cirrus Logic CS40L50. + + CS40L50 is a haptic driver with waveform memory, an integrated + DSP, and closed-loop algorithms. If built as a module, it will be + called snd-soc-cs40l50. + config SND_SOC_CS42L42_CORE tristate

diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index a87e56938ce5..7e31f000774a 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -74,6 +74,7 @@ snd-soc-cs35l56-shared-objs := cs35l56-shared.o snd-soc-cs35l56-i2c-objs := cs35l56-i2c.o snd-soc-cs35l56-spi-objs := cs35l56-spi.o snd-soc-cs35l56-sdw-objs := cs35l56-sdw.o +snd-soc-cs40l50-objs := cs40l50-codec.o snd-soc-cs42l42-objs := cs42l42.o snd-soc-cs42l42-i2c-objs := cs42l42-i2c.o snd-soc-cs42l42-sdw-objs := cs42l42-sdw.o @@ -460,6 +461,7 @@ obj-$(CONFIG_SND_SOC_CS35L56_SHARED) += snd-soc-cs35l56-shared.o obj-$(CONFIG_SND_SOC_CS35L56_I2C) += snd-soc-cs35l56-i2c.o obj-$(CONFIG_SND_SOC_CS35L56_SPI) += snd-soc-cs35l56-spi.o obj-$(CONFIG_SND_SOC_CS35L56_SDW) += snd-soc-cs35l56-sdw.o +obj-$(CONFIG_SND_SOC_CS40L50) += snd-soc-cs40l50.o obj-$(CONFIG_SND_SOC_CS42L42_CORE) += snd-soc-cs42l42.o obj-$(CONFIG_SND_SOC_CS42L42) += snd-soc-cs42l42-i2c.o obj-$(CONFIG_SND_SOC_CS42L42_SDW) += snd-soc-cs42l42-sdw.o diff --git a/sound/soc/codecs/cs40l50-codec.c b/sound/soc/codecs/cs40l50-codec.c new file mode 100644 index 000000000000..c4035719cf04 --- /dev/null +++ b/sound/soc/codecs/cs40l50-codec.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CS40L50 Advanced Haptic Driver with waveform memory, + * integrated DSP, and closed-loop algorithms + * + * Copyright 2023 Cirrus Logic, Inc. + * + * Author: James Ogletree james.ogletree@cirrus.com + */ + +#include <linux/mfd/cs40l50.h> +#include <linux/pm_runtime.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> + +#define CS40L50_REFCLK_INPUT 0x2C04 +#define CS40L50_ASP_CONTROL2 0x4808 +#define CS40L50_ASP_DATA_CONTROL5 0x4840 + +/* PLL Config */ +#define CS40L50_PLL_CLK_CFG_32768 0x00 +#define CS40L50_PLL_CLK_CFG_1536000 0x1B +#define CS40L50_PLL_CLK_CFG_3072000 0x21 +#define CS40L50_PLL_CLK_CFG_6144000 0x28 +#define CS40L50_PLL_CLK_CFG_9600000 0x30 +#define CS40L50_PLL_CLK_CFG_12288000 0x33 +#define CS40L50_PLL_CLK_FRQ_32768 32768 +#define CS40L50_PLL_CLK_FRQ_1536000 1536000 +#define CS40L50_PLL_CLK_FRQ_3072000 3072000 +#define CS40L50_PLL_CLK_FRQ_6144000 6144000 +#define CS40L50_PLL_CLK_FRQ_9600000 9600000 +#define CS40L50_PLL_CLK_FRQ_12288000 12288000 +#define CS40L50_PLL_REFCLK_BCLK 0x0 +#define CS40L50_PLL_REFCLK_MCLK 0x5 +#define CS40L50_PLL_REFCLK_LOOP_MASK BIT(11) +#define CS40L50_PLL_REFCLK_OPEN_LOOP 1 +#define CS40L50_PLL_REFCLK_CLOSED_LOOP 0 +#define CS40L50_PLL_REFCLK_LOOP_SHIFT 11 +#define CS40L50_PLL_REFCLK_FREQ_MASK GENMASK(10, 5) +#define CS40L50_PLL_REFCLK_FREQ_SHIFT 5 +#define CS40L50_PLL_REFCLK_SEL_MASK GENMASK(2, 0) + +/* ASP Config */ +#define CS40L50_ASP_RX_WIDTH_SHIFT 24 +#define CS40L50_ASP_RX_WIDTH_MASK GENMASK(31, 24) +#define CS40L50_ASP_RX_WL_MASK GENMASK(5, 0) +#define CS40L50_ASP_FSYNC_INV_MASK BIT(2) +#define CS40L50_ASP_BCLK_INV_MASK BIT(6) +#define CS40L50_ASP_FMT_MASK GENMASK(10, 8) +#define CS40L50_ASP_FMT_I2S 0x2 +#define CS40L50_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) + +struct cs40l50_pll_sysclk_config { + unsigned int freq; + unsigned int clk_cfg; +}; + +struct cs40l50_codec { + struct device *dev; + struct regmap *regmap; + unsigned int sysclk_rate; + unsigned int daifmt; +}; + +static const struct cs40l50_pll_sysclk_config cs40l50_pll_sysclk[] = { + {CS40L50_PLL_CLK_FRQ_32768, CS40L50_PLL_CLK_CFG_32768}, + {CS40L50_PLL_CLK_FRQ_1536000, CS40L50_PLL_CLK_CFG_1536000}, + {CS40L50_PLL_CLK_FRQ_3072000, CS40L50_PLL_CLK_CFG_3072000}, + {CS40L50_PLL_CLK_FRQ_6144000, CS40L50_PLL_CLK_CFG_6144000}, + {CS40L50_PLL_CLK_FRQ_9600000, CS40L50_PLL_CLK_CFG_9600000}, + {CS40L50_PLL_CLK_FRQ_12288000, CS40L50_PLL_CLK_CFG_12288000}, +}; + +static int cs40l50_get_clk_config(unsigned int freq, unsigned int *clk_cfg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs40l50_pll_sysclk); i++) { + if (cs40l50_pll_sysclk[i].freq == freq) { + *clk_cfg = cs40l50_pll_sysclk[i].clk_cfg; + return 0; + } + } + + return -EINVAL; +} + +static int cs40l50_swap_ext_clk(struct cs40l50_codec *codec, unsigned int clk_src) +{ + unsigned int clk_cfg; + int ret; + + switch (clk_src) { + case CS40L50_PLL_REFCLK_BCLK: + ret = cs40l50_get_clk_config(codec->sysclk_rate, &clk_cfg); + if (ret) + return ret; + break; + case CS40L50_PLL_REFCLK_MCLK: + clk_cfg = CS40L50_PLL_CLK_CFG_32768; + break; + default: + return -EINVAL; + } + + ret = regmap_update_bits(codec->regmap, CS40L50_REFCLK_INPUT, + CS40L50_PLL_REFCLK_LOOP_MASK, + CS40L50_PLL_REFCLK_OPEN_LOOP << + CS40L50_PLL_REFCLK_LOOP_SHIFT); + if (ret) + return ret; + + ret = regmap_update_bits(codec->regmap, CS40L50_REFCLK_INPUT, + CS40L50_PLL_REFCLK_FREQ_MASK | + CS40L50_PLL_REFCLK_SEL_MASK, + (clk_cfg << CS40L50_PLL_REFCLK_FREQ_SHIFT) | clk_src); + if (ret) + return ret; + + return regmap_update_bits(codec->regmap, CS40L50_REFCLK_INPUT, + CS40L50_PLL_REFCLK_LOOP_MASK, + CS40L50_PLL_REFCLK_CLOSED_LOOP << + CS40L50_PLL_REFCLK_LOOP_SHIFT); +} + +static int cs40l50_clk_en(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(comp); + int ret; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + ret = regmap_write(codec->regmap, CS40L50_DSP_QUEUE, CS40L50_STOP_PLAYBACK); + if (ret) + return ret; + + ret = regmap_write(codec->regmap, CS40L50_DSP_QUEUE, CS40L50_START_I2S); + if (ret) + return ret; + + ret = cs40l50_swap_ext_clk(codec, CS40L50_PLL_REFCLK_BCLK); + if (ret) + return ret; + break; + case SND_SOC_DAPM_PRE_PMD: + ret = cs40l50_swap_ext_clk(codec, CS40L50_PLL_REFCLK_MCLK); + if (ret) + return ret; + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct snd_soc_dapm_widget cs40l50_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY_S("ASP PLL", 0, SND_SOC_NOPM, 0, 0, cs40l50_clk_en, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_OUTPUT("OUT"), +}; + +static const struct snd_soc_dapm_route cs40l50_dapm_routes[] = { + { "ASP Playback", NULL, "ASP PLL" }, + { "ASPRX1", NULL, "ASP Playback" }, + { "ASPRX2", NULL, "ASP Playback" }, + + { "OUT", NULL, "ASPRX1" }, + { "OUT", NULL, "ASPRX2" }, +}; + +static int cs40l50_component_set_sysclk(struct snd_soc_component *component, + int clk_id, int source, unsigned int freq, int dir) +{ + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(component); + + codec->sysclk_rate = freq; + + return 0; +} + +static int cs40l50_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(codec_dai->component); + + if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) + return -EINVAL; + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + codec->daifmt = 0; + break; + case SND_SOC_DAIFMT_NB_IF: + codec->daifmt = CS40L50_ASP_FSYNC_INV_MASK; + break; + case SND_SOC_DAIFMT_IB_NF: + codec->daifmt = CS40L50_ASP_BCLK_INV_MASK; + break; + case SND_SOC_DAIFMT_IB_IF: + codec->daifmt = CS40L50_ASP_FSYNC_INV_MASK | CS40L50_ASP_BCLK_INV_MASK; + break; + default: + return -EINVAL; + } + + if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S) + codec->daifmt |= FIELD_PREP(CS40L50_ASP_FMT_MASK, CS40L50_ASP_FMT_I2S); + + return 0; +} + +static int cs40l50_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(dai->component); + unsigned int asp_rx_wl = params_width(params); + int ret; + + ret = regmap_update_bits(codec->regmap, CS40L50_ASP_DATA_CONTROL5, + CS40L50_ASP_RX_WL_MASK, asp_rx_wl); + if (ret) + return ret; + + codec->daifmt |= (asp_rx_wl << CS40L50_ASP_RX_WIDTH_SHIFT); + + return regmap_update_bits(codec->regmap, CS40L50_ASP_CONTROL2, + CS40L50_ASP_FSYNC_INV_MASK | + CS40L50_ASP_BCLK_INV_MASK | + CS40L50_ASP_FMT_MASK | + CS40L50_ASP_RX_WIDTH_MASK, codec->daifmt); +} + +static const struct snd_soc_dai_ops cs40l50_dai_ops = { + .set_fmt = cs40l50_set_dai_fmt, + .hw_params = cs40l50_hw_params, +}; + +static struct snd_soc_dai_driver cs40l50_dai[] = { + { + .name = "cs40l50-pcm", + .id = 0, + .playback = { + .stream_name = "ASP Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .formats = CS40L50_FORMATS, + }, + .ops = &cs40l50_dai_ops, + .symmetric_rate = 1, + }, +}; + +static int cs40l50_codec_probe(struct snd_soc_component *component) +{ + struct cs40l50_codec *codec = snd_soc_component_get_drvdata(component); + + codec->sysclk_rate = CS40L50_PLL_CLK_FRQ_1536000; + + return 0; +} + +static const struct snd_soc_component_driver soc_codec_dev_cs40l50 = { + .probe = cs40l50_codec_probe, + .set_sysclk = cs40l50_component_set_sysclk, + .dapm_widgets = cs40l50_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs40l50_dapm_widgets), + .dapm_routes = cs40l50_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(cs40l50_dapm_routes), +}; + +static int cs40l50_codec_driver_probe(struct platform_device *pdev) +{ + struct cs40l50 *cs40l50 = dev_get_drvdata(pdev->dev.parent); + struct cs40l50_codec *codec; + + codec = devm_kzalloc(&pdev->dev, sizeof(*codec), GFP_KERNEL); + if (!codec) + return -ENOMEM; + + codec->regmap = cs40l50->regmap; + codec->dev = &pdev->dev; + + return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_cs40l50, + cs40l50_dai, ARRAY_SIZE(cs40l50_dai)); +} + +static struct platform_driver cs40l50_codec_driver = { + .probe = cs40l50_codec_driver_probe, + .driver = { + .name = "cs40l50-codec", + }, +}; +module_platform_driver(cs40l50_codec_driver); + +MODULE_DESCRIPTION("ASoC CS40L50 driver"); +MODULE_AUTHOR("James Ogletree james.ogletree@cirrus.com"); +MODULE_LICENSE("GPL");