[alsa-devel] [PATCH v2 0/2] ASoC: fsl_sai: Add bus clock and mclks with clock controls
This series of patches add clock controls to fsl_sai driver and updates the vf610.dtsi accordingly.
Changelog v2: * Appended two extra mclks to the driver since SAI actually has three. * Renamed clock name to 'bus' and 'mclk' according to the reference manual.
Nicolin Chen (2): ASoC: fsl_sai: Add clock controls for SAI ARM: dts: Append clock bindings for sai2 on VF610 platform
.../devicetree/bindings/sound/fsl-sai.txt | 8 ++-- arch/arm/boot/dts/vf610.dtsi | 6 ++- sound/soc/fsl/fsl_sai.c | 50 ++++++++++++++++++++-- sound/soc/fsl/fsl_sai.h | 4 ++ 4 files changed, 59 insertions(+), 9 deletions(-)
The SAI mainly has the following clocks: bus clock control and configuration registers and to generate synchronous interrupts and DMA requests.
mclk1, mclk2, mclk3 to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock.
So this patch adds these clocks to the driver and their clock controls.
Signed-off-by: Nicolin Chen Guangyu.Chen@freescale.com --- .../devicetree/bindings/sound/fsl-sai.txt | 8 ++-- sound/soc/fsl/fsl_sai.c | 50 ++++++++++++++++++++-- sound/soc/fsl/fsl_sai.h | 4 ++ 3 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 35c09fe..8a273bc 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -10,7 +10,8 @@ Required properties: - compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai". - reg: Offset and length of the register set for the device. - clocks: Must contain an entry for each entry in clock-names. -- clock-names : Must include the "sai" entry. +- clock-names : Must include the "bus" for register access and "mclk1" "mclk2" + "mclk3" for bit clock and frame clock providing. - dmas : Generic dma devicetree binding as described in Documentation/devicetree/bindings/dma/dma.txt. - dma-names : Two dmas have to be defined, "tx" and "rx". @@ -30,8 +31,9 @@ sai2: sai@40031000 { reg = <0x40031000 0x1000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2_1>; - clocks = <&clks VF610_CLK_SAI2>; - clock-names = "sai"; + clocks = <&clks VF610_CLK_SAI2>, <&clks VF610_CLK_SAI2> + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 9cd1764..99051c7 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -401,7 +401,22 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); - u32 reg; + struct device *dev = &sai->pdev->dev; + u32 reg, ret, i; + + ret = clk_prepare_enable(sai->bus_clk); + if (ret) { + dev_err(dev, "failed to enable bus clock\n"); + return ret; + } + + for (i = 0; i < FSL_SAI_MCLK_MAX; i++) { + ret = clk_prepare_enable(sai->mclk_clk[i]); + if (ret) { + dev_err(dev, "failed to enable mclk%d clock\n", i + 1); + goto err; + } + }
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) reg = FSL_SAI_TCR3; @@ -412,13 +427,20 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream, FSL_SAI_CR3_TRCE);
return 0; + +err: + for (; i > 0; i--) + clk_disable_unprepare(sai->mclk_clk[i - 1]); + clk_disable_unprepare(sai->bus_clk); + + return ret; }
static void fsl_sai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); - u32 reg; + u32 reg, i;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) reg = FSL_SAI_TCR3; @@ -427,6 +449,10 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE, ~FSL_SAI_CR3_TRCE); + + for (i = 0; i < FSL_SAI_MCLK_MAX; i++) + clk_disable_unprepare(sai->mclk_clk[i]); + clk_disable_unprepare(sai->bus_clk); }
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { @@ -559,7 +585,8 @@ static int fsl_sai_probe(struct platform_device *pdev) struct fsl_sai *sai; struct resource *res; void __iomem *base; - int irq, ret; + char tmp[8]; + int irq, ret, i;
sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); if (!sai) @@ -582,12 +609,27 @@ static int fsl_sai_probe(struct platform_device *pdev) return PTR_ERR(base);
sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, - "sai", base, &fsl_sai_regmap_config); + "bus", base, &fsl_sai_regmap_config); if (IS_ERR(sai->regmap)) { dev_err(&pdev->dev, "regmap init failed\n"); return PTR_ERR(sai->regmap); }
+ sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); + if (IS_ERR(sai->bus_clk)) { + dev_err(&pdev->dev, "failed to get bus clock\n"); + return PTR_ERR(sai->bus_clk); + } + + for (i = 0; i < FSL_SAI_MCLK_MAX; i++) { + sprintf(tmp, "mclk%d", i + 1); + sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); + if (IS_ERR(sai->mclk_clk[i])) { + dev_err(&pdev->dev, "failed to get mclk%d clock\n", i + 1); + return PTR_ERR(sai->mclk_clk[i]); + } + } + irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 677670d..0e6c9f5 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -119,6 +119,8 @@ #define FSL_SAI_CLK_MAST2 2 #define FSL_SAI_CLK_MAST3 3
+#define FSL_SAI_MCLK_MAX 3 + /* SAI data transfer numbers per DMA request */ #define FSL_SAI_MAXBURST_TX 6 #define FSL_SAI_MAXBURST_RX 6 @@ -126,6 +128,8 @@ struct fsl_sai { struct platform_device *pdev; struct regmap *regmap; + struct clk *bus_clk; + struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
bool big_endian_regs; bool big_endian_data;
On Wed, Apr 02, 2014 at 06:10:19PM +0800, Nicolin Chen wrote:
-- clock-names : Must include the "sai" entry. +- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
- "mclk3" for bit clock and frame clock providing.
This breaks compatibilty with old DTs - it just removes the "sai" name. It's OK to deprecate the "sai" clock name but you need to keep support for DTs that only specify that, there's no code for that left in the driver.
On Mon, Apr 14, 2014 at 09:43:31PM +0100, Mark Brown wrote:
On Wed, Apr 02, 2014 at 06:10:19PM +0800, Nicolin Chen wrote:
-- clock-names : Must include the "sai" entry. +- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
- "mclk3" for bit clock and frame clock providing.
This breaks compatibilty with old DTs - it just removes the "sai" name. It's OK to deprecate the "sai" clock name but you need to keep support for DTs that only specify that, there's no code for that left in the driver.
Sir, you've already applied the v6 of this patch last week :) And I can still find it in topic/fsl-sai.
ca3e35c ASoC: fsl_sai: Add clock controls for SAI
And regarding the old DTs compatibilty, Shawn has already reminded me in his comments against one of the version. I took his advice and made the patch compatible with the old 'sai' clock binding within that v6.
Thank you, Nicolin
Since we added fours clock to the DT binding, we should update the current SAI dts/dtsi so as not to break their functions.
Signed-off-by: Nicolin Chen Guangyu.Chen@freescale.com --- arch/arm/boot/dts/vf610.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index d31ce1b..9fd0007 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -139,8 +139,10 @@ compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; interrupts = <0 86 0x04>; - clocks = <&clks VF610_CLK_SAI2>; - clock-names = "sai"; + clocks = <&clks VF610_CLK_SAI2>, + <&clks VF610_CLK_SAI2>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; status = "disabled"; };
On Wed, Apr 02, 2014 at 06:10:20PM +0800, Nicolin Chen wrote:
Since we added fours clock to the DT binding, we should update the current SAI dts/dtsi so as not to break their functions.
Signed-off-by: Nicolin Chen Guangyu.Chen@freescale.com
arch/arm/boot/dts/vf610.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index d31ce1b..9fd0007 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -139,8 +139,10 @@ compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; interrupts = <0 86 0x04>;
clocks = <&clks VF610_CLK_SAI2>;clock-names = "sai";
clocks = <&clks VF610_CLK_SAI2>,<&clks VF610_CLK_SAI2>,<&clks 0>, <&clks 0>;
So it seems that SAI on vf610 does work with only one clock. So the driver change will break old DTB for vf610? If that's case, we will have to need a new compatible for cases where 4 clocks are needed.
Shawn
clock-names = "bus", "mclk1", "mclk2", "mclk3"; status = "disabled"; };-- 1.8.4
Hi Shawn,
Thanks for the comments, but...
On Wed, Apr 02, 2014 at 09:03:04PM +0800, Shawn Guo wrote:
On Wed, Apr 02, 2014 at 06:10:20PM +0800, Nicolin Chen wrote:
Since we added fours clock to the DT binding, we should update the current SAI dts/dtsi so as not to break their functions.
Signed-off-by: Nicolin Chen Guangyu.Chen@freescale.com
arch/arm/boot/dts/vf610.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index d31ce1b..9fd0007 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -139,8 +139,10 @@ compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; interrupts = <0 86 0x04>;
clocks = <&clks VF610_CLK_SAI2>;clock-names = "sai";
clocks = <&clks VF610_CLK_SAI2>,<&clks VF610_CLK_SAI2>,<&clks 0>, <&clks 0>;So it seems that SAI on vf610 does work with only one clock. So the driver change will break old DTB for vf610? If that's case, we will have to need a new compatible for cases where 4 clocks are needed.
According to Vybrid's RM Chapter 9.11.12 SAI clocking, the SoC actually connects SAI with two clocks: SAI_CLK and Platform Bus Clock. So the DT binding here still needs to be corrected even if ignoring driver change.
Besides, I've checked both SAI on imx and vf610 and found that they are seemly identical, especially for the clock part -- "The transmitter and receiver can independently select between the bus clock and up to three audio master clocks to generate the bit clock." And the driver that was designed for vf610 already contains the code to switch the clock between Bus Clock and Three MCLKs. What I want to say is, even if SAI on vf610 does work with only one clock, it still doesn't have the full function on vf610 -- driving clock from Platform Bus Clock unless we make this improvement to the DT binding.
So I think it's fair to complete the code here for both platforms, even though we might take the risk of merging conflict. And I understand your point to avoid function break on those platform both of us aren't convenient to test. But I've already involved Xiubo in the list. And we can wait for his test result.
Hope you can understand the circumstance, Nicolin
Subject: Re: [PATCH v2 2/2] ARM: dts: Append clock bindings for sai2 on VF610 platform
Hi Shawn,
Thanks for the comments, but...
On Wed, Apr 02, 2014 at 09:03:04PM +0800, Shawn Guo wrote:
On Wed, Apr 02, 2014 at 06:10:20PM +0800, Nicolin Chen wrote:
Since we added fours clock to the DT binding, we should update the current SAI dts/dtsi so as not to break their functions.
Signed-off-by: Nicolin Chen Guangyu.Chen@freescale.com
arch/arm/boot/dts/vf610.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index d31ce1b..9fd0007 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -139,8 +139,10 @@ compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; interrupts = <0 86 0x04>;
clocks = <&clks VF610_CLK_SAI2>;clock-names = "sai";
clocks = <&clks VF610_CLK_SAI2>,<&clks VF610_CLK_SAI2>,<&clks 0>, <&clks 0>;So it seems that SAI on vf610 does work with only one clock. So the driver change will break old DTB for vf610? If that's case, we will have to need a new compatible for cases where 4 clocks are needed.
According to Vybrid's RM Chapter 9.11.12 SAI clocking, the SoC actually connects SAI with two clocks: SAI_CLK and Platform Bus Clock. So the DT binding here still needs to be corrected even if ignoring driver change.
Besides, I've checked both SAI on imx and vf610 and found that they are seemly identical, especially for the clock part -- "The transmitter and receiver can independently select between the bus clock and up to three audio master clocks to generate the bit clock." And the driver that was designed for vf610 already contains the code to switch the clock between Bus Clock and Three MCLKs. What I want to say is, even if SAI on vf610 does work with only one clock, it still doesn't have the full function on vf610 -- driving clock from Platform Bus Clock unless we make this improvement to the DT binding.
So I think it's fair to complete the code here for both platforms, even though we might take the risk of merging conflict. And I understand your point to avoid function break on those platform both of us aren't convenient to test. But I've already involved Xiubo in the list. And we can wait for his test result.
This has been test on my Vybird-TWR board and it's fine.
Thanks,
Brs Xiubo
Hope you can understand the circumstance, Nicolin
On Wed, Apr 02, 2014 at 06:10:20PM +0800, Nicolin Chen wrote:
Since we added fours clock to the DT binding, we should update the current SAI dts/dtsi so as not to break their functions.
This doesn't apply against v3.15-rc1, can you please check and resend?
On Mon, Apr 14, 2014 at 09:38:51PM +0100, Mark Brown wrote:
On Wed, Apr 02, 2014 at 06:10:20PM +0800, Nicolin Chen wrote:
Since we added fours clock to the DT binding, we should update the current SAI dts/dtsi so as not to break their functions.
This doesn't apply against v3.15-rc1, can you please check and resend?
Please disregard this patch, since my v6 patch was compatible with the old binding, the patch here is provisionally useless and I can later send it via Shawn's tree.
Thank you, Nicolin
participants (4)
-
Li.Xiubo＠freescale.com -
Mark Brown -
Nicolin Chen -
Shawn Guo