[PATCH 0/3] ASoC: codecs: qcom: tx-macro: minor cleanups
Hi,
Few minor cleanups. The series will conflict with my series: https://lore.kernel.org/alsa-devel/20240129143534.109196-1-krzysztof.kozlows...
Depending what will come in first, I will rebase the other patchset.
Best regards, Krzysztof
Krzysztof Kozlowski (3): ASoC: codecs: tx-macro: Drop unimplemented DMIC clock divider ASoC: codecs: tx-macro: Mark AMIC control registers as volatile ASoC: codecs: tx-macro: Simplify setting AMIC control
sound/soc/codecs/lpass-tx-macro.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-)
Downstream driver configures DMIC clock rate through the divider register but only parts of this code ended up in the upstream driver: we always write the same value 0, so DIV2. Same default value is used also for the AMIC rate control.
Let's make it obvious and drop unneeded parts of the code.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- sound/soc/codecs/lpass-tx-macro.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c index 124c2e144f33..cdceccf64ac8 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c @@ -38,6 +38,8 @@ #define CDC_TX_TOP_CSR_I2S_RESET (0x00AC) #define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4) #define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0) +/* Default divider for AMIC and DMIC clock: DIV2 */ +#define CDC_TX_SWR_MIC_CLK_DEFAULT 0 #define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1) #define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4) #define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8) @@ -270,7 +272,6 @@ struct tx_macro { struct clk_hw hw; bool dec_active[NUM_DECIMATORS]; int tx_mclk_users; - u16 dmic_clk_div; bool bcs_enable; int dec_mode[NUM_DECIMATORS]; struct lpass_macro *pds; @@ -743,7 +744,6 @@ static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, unsigned int val, dmic; u16 mic_sel_reg; u16 dmic_clk_reg; - struct tx_macro *tx = snd_soc_component_get_drvdata(component);
val = ucontrol->value.enumerated.item[0]; if (val >= e->items) @@ -793,7 +793,7 @@ static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); snd_soc_component_write_field(component, dmic_clk_reg, CDC_TX_SWR_DMIC_CLK_SEL_MASK, - tx->dmic_clk_div); + CDC_TX_SWR_MIC_CLK_DEFAULT); } }
@@ -882,7 +882,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
snd_soc_component_write_field(component, dmic_clk_reg, CDC_TX_SWR_DMIC_CLK_SEL_MASK, - tx->dmic_clk_div); + CDC_TX_SWR_MIC_CLK_DEFAULT); } } snd_soc_component_write_field(component, dec_cfg_reg,
Just like DMIC, the AMIC control registers are volatile.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- sound/soc/codecs/lpass-tx-macro.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c index cdceccf64ac8..2d4f6c04332b 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c @@ -432,6 +432,8 @@ static bool tx_is_volatile_register(struct device *dev, unsigned int reg) case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: + case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: + case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: return true; } return false;
When updating all bits in AMIC control registers (mask 0xff), use more obvious snd_soc_component_write(). Replace also hard-coded value 0x00 with a define.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- sound/soc/codecs/lpass-tx-macro.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c index 2d4f6c04332b..7e51212d4503 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c @@ -1850,8 +1850,10 @@ static int tx_macro_component_probe(struct snd_soc_component *comp) snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F, 0x0A); /* Enable swr mic0 and mic1 clock */ - snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00); - snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00); + snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, + CDC_TX_SWR_MIC_CLK_DEFAULT); + snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, + CDC_TX_SWR_MIC_CLK_DEFAULT);
return 0; }
On Fri, 02 Feb 2024 16:41:31 +0100, Krzysztof Kozlowski wrote:
Few minor cleanups. The series will conflict with my series: https://lore.kernel.org/alsa-devel/20240129143534.109196-1-krzysztof.kozlows...
Depending what will come in first, I will rebase the other patchset.
Best regards, Krzysztof
[...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/3] ASoC: codecs: tx-macro: Drop unimplemented DMIC clock divider commit: 58cef044e6ec88eef6f10565df8257138e2085ec [2/3] ASoC: codecs: tx-macro: Mark AMIC control registers as volatile commit: b396071681ca65e66f2a8fce240cde26a6db5931 [3/3] ASoC: codecs: tx-macro: Simplify setting AMIC control commit: fd236653ab60bf64fde341ed9c940c04a542483a
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
participants (2)
-
Krzysztof Kozlowski -
Mark Brown