[PATCH v4 0/7] Add SC7280 audioreach device tree nodes
Add SC7280 audioreach device tree nodes and extract audio specific dtsi nodes and add them in new file.
This patch series depends on: -- https://patchwork.kernel.org/project/linux-clk/list/?series=713587 Corresponding dt-bindings not mainlined yet. -- https://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git/commit/...
Changes Since v3: -- Remove deleting digital codecs in crd-rev3 board specific dtsi and upadate them using phandle. -- Update commit message in "Update lpass_tlmm node" patch. -- Change the position of status property in LPASS PIL node. -- Update commit message in "Add sound node" patch. Changes Since v2: -- Remove Patch related to Add CGCR reset property. -- Remove Patch related to Disable legacy path clock nodes. -- Add dt-bindings for missing properties. -- Change the order of nodes. -- Move digictal codec macro nodes to root node from soc node. -- Add adsp-pil-mode property in required clock nodes. Changes Since v1: -- Move remoteproc node to soc dtsi file. -- Add qcom, adsp-pil-mode reg property in lpasscc node. -- Fix typo errors. -- Remove redundant status properties.
Srinivasa Rao Mandadapu (7): arm64: dts: qcom: sc7280: Extract audio nodes from common idp dtsi file arm64: dts: qcom: sc7280: Add sound node for crd-rev3 board arm64: dts: qcom: sc7280: Add LPASS PIL node arm64: dts: qcom: sc7280: Update VA/RX/TX macro clock nodes arm64: dts: qcom: sc7280: Update lpass_tlmm node arm64: dts: qcom: sc7280: Update qcom,adsp-pil-mode property dt-bindings: remoteproc: qcom: sc7280-adsp-pil: Add missing properties
.../bindings/remoteproc/qcom,sc7280-adsp-pil.yaml | 30 +++- arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi | 135 ++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 24 +-- .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 171 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 126 --------------- arch/arm64/boot/dts/qcom/sc7280.dtsi | 96 ++++++++++++ 6 files changed, 429 insertions(+), 153 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
Split common idp dtsi file into audio specific dtsi and common idp dtsi file.
It is required to isolate idp and crd-rev3 platform device tree nodes and convert crd-rev3 platform device tree nodes into audioreach specific device tree nodes.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Tested-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi | 135 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 126 ----------------------- 3 files changed, 136 insertions(+), 126 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi new file mode 100644 index 0000000..614fb06 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 Audio IDP board device tree source (common between SKU1 and SKU2) + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +/{ + /* BOARD-SPECIFIC TOP LEVEL NODES */ + sound: sound { + compatible = "google,sc7280-herobrine"; + model = "sc7280-wcd938x-max98360a-1mic"; + + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + + dai-link@0 { + link-name = "MAX98360A"; + reg = <0>; + + cpu { + sound-dai = <&lpass_cpu MI2S_SECONDARY>; + }; + + codec { + sound-dai = <&max98360a>; + }; + }; + + dai-link@1 { + link-name = "DisplayPort"; + reg = <1>; + + cpu { + sound-dai = <&lpass_cpu LPASS_DP_RX>; + }; + + codec { + sound-dai = <&mdss_dp>; + }; + }; + + dai-link@2 { + link-name = "WCD9385 Playback"; + reg = <2>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>; + }; + + codec { + sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + }; + + dai-link@3 { + link-name = "WCD9385 Capture"; + reg = <3>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>; + }; + + codec { + sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + }; + + dai-link@4 { + link-name = "DMIC"; + reg = <4>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>; + }; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + }; + }; +}; + +&lpass_cpu { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; + + dai-link@1 { + reg = <MI2S_SECONDARY>; + qcom,playback-sd-lines = <0>; + }; + + dai-link@5 { + reg = <LPASS_DP_RX>; + }; + + dai-link@6 { + reg = <LPASS_CDC_DMA_RX0>; + }; + + dai-link@19 { + reg = <LPASS_CDC_DMA_TX3>; + }; + + dai-link@25 { + reg = <LPASS_CDC_DMA_VA_TX0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index 1185141..b024626 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -8,6 +8,7 @@ /dts-v1/;
#include "sc7280-idp.dtsi" +#include "sc7280-audio-idp.dtsi" #include "sc7280-idp-ec-h1.dtsi"
/ { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index fa10ddd..6b41574 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -87,104 +87,6 @@ pinctrl-names = "default"; pinctrl-0 = <&nvme_pwren>; }; - - sound: sound { - compatible = "google,sc7280-herobrine"; - model = "sc7280-wcd938x-max98360a-1mic"; - - audio-routing = - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC1", "MIC BIAS1", - "AMIC2", "MIC BIAS2", - "VA DMIC0", "MIC BIAS3", - "VA DMIC1", "MIC BIAS3", - "VA DMIC2", "MIC BIAS1", - "VA DMIC3", "MIC BIAS1", - "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC1", "ADC2_OUTPUT", - "TX SWR_ADC2", "ADC3_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT"; - - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; - - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - - dai-link@0 { - link-name = "MAX98360A"; - reg = <0>; - - cpu { - sound-dai = <&lpass_cpu MI2S_SECONDARY>; - }; - - codec { - sound-dai = <&max98360a>; - }; - }; - - dai-link@1 { - link-name = "DisplayPort"; - reg = <1>; - - cpu { - sound-dai = <&lpass_cpu LPASS_DP_RX>; - }; - - codec { - sound-dai = <&mdss_dp>; - }; - }; - - dai-link@2 { - link-name = "WCD9385 Playback"; - reg = <2>; - - cpu { - sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>; - }; - - codec { - sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>; - }; - }; - - dai-link@3 { - link-name = "WCD9385 Capture"; - reg = <3>; - - cpu { - sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>; - }; - - codec { - sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>; - }; - }; - - dai-link@4 { - link-name = "DMIC"; - reg = <4>; - - cpu { - sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>; - }; - - codec { - sound-dai = <&lpass_va_macro 0>; - }; - }; - }; };
&apps_rsc { @@ -377,34 +279,6 @@ status = "okay"; };
-&lpass_cpu { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; - - dai-link@1 { - reg = <MI2S_SECONDARY>; - qcom,playback-sd-lines = <0>; - }; - - dai-link@5 { - reg = <LPASS_DP_RX>; - }; - - dai-link@6 { - reg = <LPASS_CDC_DMA_RX0>; - }; - - dai-link@19 { - reg = <LPASS_CDC_DMA_TX3>; - }; - - dai-link@25 { - reg = <LPASS_CDC_DMA_VA_TX0>; - }; -}; - &lpass_rx_macro { status = "okay"; };
Add sound node for sc7280 ADSP based audioreach platforms such as crd-rev3 board.
Include audioreach dtsi into crd-rev3 platform specific dts file. Also remove phandle to sound node, as audio routing is same as audioreach specific dtsi file.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Tested-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 25 +---- .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 109 +++++++++++++++++++++ 2 files changed, 110 insertions(+), 24 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index b024626..aea8cbd 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -8,7 +8,7 @@ /dts-v1/;
#include "sc7280-idp.dtsi" -#include "sc7280-audio-idp.dtsi" +#include "sc7280-herobrine-audioreach-wcd9385.dtsi" #include "sc7280-idp-ec-h1.dtsi"
/ { @@ -88,29 +88,6 @@ ap_ts_pen_1v8: &i2c13 { pins = "gpio51"; };
-&sound { - audio-routing = - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC1", "MIC BIAS1", - "AMIC2", "MIC BIAS2", - "VA DMIC0", "MIC BIAS1", - "VA DMIC1", "MIC BIAS1", - "VA DMIC2", "MIC BIAS3", - "VA DMIC3", "MIC BIAS3", - "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC1", "ADC2_OUTPUT", - "TX SWR_ADC2", "ADC3_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT"; -}; - &wcd9385 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi new file mode 100644 index 0000000..7b3f7ee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 device tree source for boards using Max98360 and wcd9385 codec + * along with ADSP + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/sound/qcom,q6afe.h> + +/{ + /* BOARD-SPECIFIC TOP LEVEL NODES */ + sound: sound { + compatible = "google,sc7280-herobrine"; + model = "SC7280-AUDIOREACH"; + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "VA DMIC3", "MIC BIAS3", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; + + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + + dai-link@0 { + link-name = "WCD9385 Playback"; + reg = <0>; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dai-link@1 { + link-name = "WCD9385 Capture"; + reg = <1>; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dai-link@2 { + link-name = "Amplifier Playback"; + reg = <2>; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_RX>; + }; + + codec { + sound-dai = <&max98360a>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dai-link@3 { + link-name = "DMIC"; + reg = <3>; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; +};
Add LPASS PIL node for sc7280 based audioreach platforms.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Tested-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 4 + arch/arm64/boot/dts/qcom/sc7280.dtsi | 96 ++++++++++++++++++++++ 2 files changed, 100 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi index 7b3f7ee..81e0f3a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -107,3 +107,7 @@ }; }; }; + +&remoteproc_adsp { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 6908bca..42e8fd8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,dispcc-sc7280.h> #include <dt-bindings/clock/qcom,gcc-sc7280.h> #include <dt-bindings/clock/qcom,gpucc-sc7280.h> +#include <dt-bindings/clock/qcom,lpass-sc7280.h> #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> #include <dt-bindings/clock/qcom,rpmh.h> @@ -21,6 +22,7 @@ #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/reset/qcom,sdm845-pdc.h> +#include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,lpass.h> #include <dt-bindings/thermal/thermal.h> @@ -3439,6 +3441,100 @@ status = "disabled"; };
+ remoteproc_adsp: remoteproc@3000000 { + compatible = "qcom,sc7280-adsp-pil"; + reg = <0 0x03000000 0 0x5000>, <0 0x0355b000 0 0x10>; + reg-names = "qdsp6ss_base", "lpass_efuse"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 IRQ_TYPE_NONE>, + <&adsp_smp2p_in 1 IRQ_TYPE_NONE>, + <&adsp_smp2p_in 2 IRQ_TYPE_NONE>, + <&adsp_smp2p_in 3 IRQ_TYPE_NONE>, + <&adsp_smp2p_in 7 IRQ_TYPE_NONE>; + + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + qcom,qmp = <&aoss_qmp>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CFG_NOC_LPASS_CLK>; + + clock-names = "xo", "gcc_cfg_noc_lpass"; + + iommus = <&apps_smmu 0x1800 0x0>; + + power-domains = <&rpmhpd SC7280_CX>; + power-domain-names = "cx"; + + required-opps = <&rpmhpd_opp_nom>; + + resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>, + <&aoss_reset AOSS_CC_LPASS_RESTART>; + + reset-names = "pdc_sync", "cc_lpass"; + qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + remoteproc_wpss: remoteproc@8a00000 { compatible = "qcom,sc7280-wpss-pil"; reg = <0 0x08a00000 0 0x10000>;
Update VA, RX and TX macro and lpass_tlmm clock properties and enable them.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Tested-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi index 81e0f3a..0add125 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -108,6 +108,43 @@ }; };
+&lpass_rx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + status = "okay"; +}; + +&lpass_tx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + status = "okay"; +}; + +&lpass_va_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + + clock-names = "mclk", "macro", "dcodec"; + status = "okay"; +}; + &remoteproc_adsp { status = "okay"; };
Update lpass_tlmm clock properties, as different clock sources are required in ADSP enabled platforms. Also update LPASS_MCC register region. This is required to avoid memory region conflicts due to overlapping lpass_efuse Q6 regmap region used in LPASS PIL node.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Tested-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- .../arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi index 0add125..4def6b3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -121,6 +121,15 @@ status = "okay"; };
+&lpass_tlmm { + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + + clock-names = "core", "audio"; + reg = <0 0x033c0000 0x0 0x20000>, + <0 0x03550000 0x0 0xa100>; +}; + &lpass_tx_macro { /delete-property/ power-domains; /delete-property/ power-domain-names;
Add "qcom,adsp-pil-mode" property in clock nodes for herobrine crd revision 3 board specific device tree. This is to register clocks conditionally by differentiating ADSP based platforms and legacy path platforms.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Tested-by: Mohammad Rafi Shaik quic_mohs@quicinc.com --- .../boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi index 4def6b3..b95bfd1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi @@ -108,6 +108,14 @@ }; };
+&lpass_aon { + qcom,adsp-pil-mode; +}; + +&lpass_core { + qcom,adsp-pil-mode; +}; + &lpass_rx_macro { /delete-property/ power-domains; /delete-property/ power-domain-names; @@ -154,6 +162,10 @@ status = "okay"; };
+&lpasscc { + qcom,adsp-pil-mode; +}; + &remoteproc_adsp { status = "okay"; };
Add reg-names and power-domain-names for remoteproc ADSP pheripheral loader. Add firmware-name property to distinguish and load different firmware binaries of various vendors. Change qcom,halt-regs property phandle to tcsr_1 from tcsr_mutex. Also add required-opps property and change power domain from LCX to CX, which is actual PD to be controlled, for setting appropriate performance state. This is to make compatible with remoteproc ADSP PIL driver and latest device tree changes.
Fixes: 8490a99586ab ("dt-bindings: remoteproc: qcom: Add SC7280 ADSP support") Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Reviewed-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- .../bindings/remoteproc/qcom,sc7280-adsp-pil.yaml | 30 +++++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml index 94ca7a0..7addc7d 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml @@ -23,6 +23,11 @@ properties: - description: qdsp6ss register - description: efuse q6ss register
+ reg-names: + items: + - const: qdsp6ss_base + - const: lpass_efuse + iommus: items: - description: Phandle to apps_smmu node with sid mask @@ -57,7 +62,11 @@ properties:
power-domains: items: - - description: LCX power domain + - description: CX power domain + + power-domain-names: + items: + - const: cx
resets: items: @@ -73,6 +82,12 @@ properties: maxItems: 1 description: Reference to the reserved-memory for the Hexagon core
+ firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + The name of the firmware which should be loaded for this remote + processor. + qcom,halt-regs: $ref: /schemas/types.yaml#/definitions/phandle-array description: @@ -80,7 +95,7 @@ properties: four offsets within syscon for q6, modem, nc and qv6 halt registers. items: - items: - - description: phandle to TCSR_MUTEX registers + - description: phandle to TCSR_1 registers - description: offset to the Q6 halt register - description: offset to the modem halt register - description: offset to the nc halt register @@ -100,6 +115,10 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM.
+ required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + glink-edge: $ref: qcom,glink-edge.yaml# type: object @@ -167,13 +186,16 @@ examples: <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "xo", "gcc_cfg_noc_lpass";
- power-domains = <&rpmhpd SC7280_LCX>; + power-domains = <&rpmhpd SC7280_CX>; + power-domain-names = "cx"; + + required-opps = <&rpmhpd_opp_nom>;
resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>, <&aoss_reset AOSS_CC_LPASS_RESTART>; reset-names = "pdc_sync", "cc_lpass";
- qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; + qcom,halt-regs = <&tcsr_1 0x23000 0x25000 0x28000 0x33000>;
memory-region = <&adsp_mem>;
participants (1)
-
Srinivasa Rao Mandadapu