The existing FIELD_{GET,PREP}() macros are limited to compile-time constants. However, it is very common to prepare or extract bitfield elements where the bitfield mask is not a compile-time constant.

To avoid this limitation, the AT91 clock driver already has its own field_{prep,get}() macros. Make them available for general use by moving them to <linux/bitfield.h>, and improve them slightly: 1. Avoid evaluating macro parameters more than once, 2. Replace "ffs() - 1" by "__ffs()", as the latter operates on "unsigned long", just like BIT() and GENMASK().

Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be --- Using __ffs() actually reduces code size (16 bytes for each of drivers/clk/at91/clk-{generated,peripheral}.o), as __ffs() doesn't need to verify that the value passed is non-zero. --- drivers/clk/at91/clk-peripheral.c | 1 + drivers/clk/at91/pmc.h | 3 --- include/linux/bitfield.h | 30 ++++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index e14fa5ac734cead7..e2f33498139a1b8c 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 Boris BREZILLON b.brezillon@overkiz.com */

+#include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/clk-provider.h> #include <linux/clkdev.h> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 3a1bf6194c287d09..1256e1ab91526a25 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -114,9 +114,6 @@ struct at91_clk_pms { unsigned int parent; };

-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - #define ndck(a, s) (a[s - 1].id + 1) #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index 4e035aca6f7e6000..f03b0712e4babec1 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -156,4 +156,34 @@ __MAKE_OP(64) #undef __MAKE_OP #undef ____MAKE_OP

+/** + * field_prep() - prepare a bitfield element + * @_mask: shifted mask defining the field's length and position + * @_val: value to put in the field + * + * field_prep() masks and shifts up the value. The result should be + * combined with other fields of the bitfield using logical OR. + * Unlike FIELD_PREP(), @_mask is not limited to a compile-time constant. + */ +#define field_prep(_mask, _val) \ + ({ \ + typeof(_mask) ___mask = (_mask); \ + (((_val) << __ffs(___mask)) & (___mask)); \ + }) + +/** + * field_get() - extract a bitfield element + * @_mask: shifted mask defining the field's length and position + * @_reg: value of entire bitfield + * + * field_get() extracts the field specified by @_mask from the + * bitfield passed in as @_reg by masking and shifting it down. + * Unlike FIELD_GET(), @_mask is not limited to a compile-time constant. + */ +#define field_get(_mask, _reg) \ + ({ \ + typeof(_mask) ___mask = _mask; \ + (((_reg) & (___mask)) >> __ffs(___mask)); \ + }) + #endif

Use the FIELD_{GET,PREP}() and field_{get,prep}() helpers for const respective non-const bitfields, instead of open-coding the same operations.

Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be --- drivers/clk/renesas/clk-div6.c | 6 +++--- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 9 +++------ drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++++---------- 3 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c index 3abd6e5400aded6a..f7b827b5e9b2dd32 100644 --- a/drivers/clk/renesas/clk-div6.c +++ b/drivers/clk/renesas/clk-div6.c @@ -7,6 +7,7 @@ * Contact: Laurent Pinchart laurent.pinchart@ideasonboard.com */

+#include <linux/bitfield.h> #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/io.h> @@ -171,8 +172,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) if (clock->src_mask == 0) return 0;

- hw_index = (readl(clock->reg) & clock->src_mask) >> - __ffs(clock->src_mask); + hw_index = field_get(clock->src_mask, readl(clock->reg)); for (i = 0; i < clk_hw_get_num_parents(hw); i++) { if (clock->parents[i] == hw_index) return i; @@ -191,7 +191,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) if (index >= clk_hw_get_num_parents(hw)) return -EINVAL;

- src = clock->parents[index] << __ffs(clock->src_mask); + src = field_prep(clock->src_mask, clock->parents[index]); writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); return 0; } diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 7df86743c5491292..f716e739d138b722 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -302,11 +302,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); - unsigned int mult; - u32 val; - - val = readl(zclk->reg) & zclk->mask; - mult = 32 - (val >> __ffs(zclk->mask)); + unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg));

return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * zclk->fixed_div); @@ -357,7 +353,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY;

- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); + cpg_reg_modify(zclk->reg, zclk->mask, + field_prep(zclk->mask, 32 - mult));

/* * Set KICK bit in FRQCRB to update hardware setting and wait for diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index a9816b1beabb2582..30bbe8418e018153 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -54,10 +54,8 @@ static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); unsigned int mult; - u32 val;

- val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; - mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; + mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1;

return parent_rate * mult * pll_clk->fixed_mult; } @@ -94,7 +92,7 @@ static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,

val = readl(pll_clk->pllcr_reg); val &= ~CPG_PLLnCR_STC_MASK; - val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); + val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1); writel(val, pll_clk->pllcr_reg);

for (i = 1000; i; i--) { @@ -176,11 +174,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); - unsigned int mult; - u32 val; - - val = readl(zclk->reg) & zclk->mask; - mult = 32 - (val >> __ffs(zclk->mask)); + unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg));

return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * zclk->fixed_div); @@ -231,7 +225,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY;

- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); + cpg_reg_modify(zclk->reg, zclk->mask, + field_prep(zclk->mask, 32 - mult));

/* * Set KICK bit in FRQCRB to update hardware setting and wait for

Use the FIELD_{GET,PREP}() and field_{get,prep}() helpers for const respective non-const bitfields, instead of open-coding the same operations.

Remove the definitions of OMAP_POWERSTATEST_SHIFT and OMAP_POWERSTATE_SHIFT, as they are no longer used.

Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be --- Compile-tested only. Marked RFC, as this depends on [PATCH 01/17], but follows a different path to upstream. --- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 5 +- arch/arm/mach-omap2/cm2xxx.c | 11 ++--- arch/arm/mach-omap2/cm2xxx_3xxx.h | 9 +--- arch/arm/mach-omap2/cm33xx.c | 9 +--- arch/arm/mach-omap2/cm3xxx.c | 7 ++- arch/arm/mach-omap2/cminst44xx.c | 9 +--- arch/arm/mach-omap2/powerdomains3xxx_data.c | 3 +- arch/arm/mach-omap2/prm.h | 2 - arch/arm/mach-omap2/prm2xxx.c | 4 +- arch/arm/mach-omap2/prm2xxx_3xxx.c | 7 +-- arch/arm/mach-omap2/prm2xxx_3xxx.h | 9 +--- arch/arm/mach-omap2/prm33xx.c | 53 +++++++-------------- arch/arm/mach-omap2/prm3xxx.c | 3 +- arch/arm/mach-omap2/prm44xx.c | 53 +++++++-------------- arch/arm/mach-omap2/vc.c | 12 ++--- arch/arm/mach-omap2/vp.c | 11 +++-- 16 files changed, 77 insertions(+), 130 deletions(-)

diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 8a9983cb4733dfb1..6a61dc932b24f387 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -17,6 +17,7 @@ */ #undef DEBUG

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/clk.h> @@ -151,8 +152,8 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, mult = (rate / 1000000); done_rate = CORE_CLK_SRC_DPLL; } - tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); - tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); + tmpset.cm_clksel1_pll |= field_prep(dd->mult_mask, div); + tmpset.cm_clksel1_pll |= field_prep(dd->div1_mask, mult);

/* Worst case */ tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c index 0827acb605843778..59d35d4d43bec533 100644 --- a/arch/arm/mach-omap2/cm2xxx.c +++ b/arch/arm/mach-omap2/cm2xxx.c @@ -8,6 +8,7 @@ * Rajendra Nayak rnayak@ti.com */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/delay.h> @@ -46,7 +47,7 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)

v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); v &= ~mask; - v |= c << __ffs(mask); + v |= field_prep(mask, c); omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); }

@@ -54,9 +55,7 @@ static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask) { u32 v;

- v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); - v &= mask; - v >>= __ffs(mask); + v = field_get(mask, omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL));

return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; } @@ -81,7 +80,7 @@ static void _omap2xxx_set_dpll_autoidle(u8 m)

v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); v &= ~OMAP24XX_AUTO_DPLL_MASK; - v |= m << OMAP24XX_AUTO_DPLL_SHIFT; + v |= FIELD_PREP(OMAP24XX_AUTO_DPLL_MASK, m); omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); }

@@ -105,7 +104,7 @@ static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)

v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); v &= ~mask; - v |= m << __ffs(mask); + v |= field_prep(mask, m); omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); }

diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index 70944b94cc098d7f..e3214491f1b556fd 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -45,6 +45,7 @@

#ifndef __ASSEMBLER__

+#include <linux/bitfield.h> #include <linux/io.h>

static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) @@ -74,13 +75,7 @@ static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, /* Read a CM register, AND it, and shift the result down to bit 0 */ static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) { - u32 v; - - v = omap2_cm_read_mod_reg(domain, idx); - v &= mask; - v >>= __ffs(mask); - - return v; + return field_get(mask, omap2_cm_read_mod_reg(domain, idx)); }

static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index ac4882ebdca33fdf..5479b9587d688885 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/errno.h> @@ -74,13 +75,7 @@ static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)

static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) { - u32 v; - - v = am33xx_cm_read_reg(inst, idx); - v &= mask; - v >>= __ffs(mask); - - return v; + return field_get(mask, am33xx_cm_read_reg(inst, idx)); }

/** diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index b03b6123b8fcc8f2..951c6a9cee1e80ba 100644 --- a/arch/arm/mach-omap2/cm3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -8,6 +8,7 @@ * Rajendra Nayak rnayak@ti.com */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/delay.h> @@ -35,7 +36,7 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)

v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); v &= ~mask; - v |= c << __ffs(mask); + v |= field_prep(mask, c); omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); }

@@ -43,9 +44,7 @@ static bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask) { u32 v;

- v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); - v &= mask; - v >>= __ffs(mask); + v = field_get(mask, omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL));

return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; } diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index 46670521b27883ec..e9ca128b14349be2 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -12,6 +12,7 @@ * the PRM hardware module. What a mess... */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/errno.h> @@ -154,13 +155,7 @@ static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,

static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) { - u32 v; - - v = omap4_cminst_read_inst_reg(part, inst, idx); - v &= mask; - v >>= __ffs(mask); - - return v; + return field_get(mask, omap4_cminst_read_inst_reg(part, inst, idx)); }

/* diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 3564fade67e45061..08ae42ddb15b138e 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -8,6 +8,7 @@ * Paul Walmsley, Jouni Högander */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/bug.h> @@ -513,7 +514,7 @@ static struct powerdomain *powerdomains_ti816x[] __initdata = { static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, - (pwrst << OMAP_POWERSTATE_SHIFT), + FIELD_PREP(OMAP_POWERSTATE_MASK, pwrst), pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL); return 0; } diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 08df78810a5e39e9..c54991e7058e7cd7 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -67,7 +67,6 @@ int omap2_prcm_base_init(void); * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, * PM_PWSTST_NEON */ -#define OMAP_POWERSTATEST_SHIFT 0 #define OMAP_POWERSTATEST_MASK (0x3 << 0)

/* @@ -80,7 +79,6 @@ int omap2_prcm_base_init(void); * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, * PM_PWSTCTRL_NEON shared bits */ -#define OMAP_POWERSTATE_SHIFT 0 #define OMAP_POWERSTATE_MASK (0x3 << 0)

/* diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c index 35a58f54b528f335..e835e381a82b7685 100644 --- a/arch/arm/mach-omap2/prm2xxx.c +++ b/arch/arm/mach-omap2/prm2xxx.c @@ -9,6 +9,7 @@ * Rajendra Nayak rnayak@ti.com */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/err.h> @@ -165,7 +166,8 @@ static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) }

omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, - (omap24xx_pwrst << OMAP_POWERSTATE_SHIFT), + FIELD_PREP(OMAP_POWERSTATE_MASK, + omap24xx_pwrst), pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; } diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index d983efac6f4ff6f5..8a223ced2bcad25b 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -8,6 +8,7 @@ * Paul Walmsley */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/err.h> @@ -115,7 +116,7 @@ int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,

m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);

- omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + omap2_prm_rmw_mod_reg_bits(m, field_prep(m, pwrst), pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);

return 0; @@ -128,7 +129,7 @@ int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,

m = omap2_pwrdm_get_mem_bank_retst_mask(bank);

- omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + omap2_prm_rmw_mod_reg_bits(m, field_prep(m, pwrst), pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);

return 0; @@ -158,7 +159,7 @@ int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) { u32 v;

- v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK); + v = FIELD_PREP(OMAP_LOGICRETSTATE_MASK, pwrst); omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);

diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index 3d803f7182b98f04..5f438cca9f8a3584 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -46,6 +46,7 @@

#ifndef __ASSEMBLER__

+#include <linux/bitfield.h> #include <linux/io.h> #include "powerdomain.h"

@@ -77,13 +78,7 @@ static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, /* Read a PRM register, AND it, and shift the result down to bit 0 */ static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) { - u32 v; - - v = omap2_prm_read_mod_reg(domain, idx); - v &= mask; - v >>= __ffs(mask); - - return v; + return field_get(mask, omap2_prm_read_mod_reg(domain, idx)); }

static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c index 9144cc0479afe19c..864420e9c2102df5 100644 --- a/arch/arm/mach-omap2/prm33xx.c +++ b/arch/arm/mach-omap2/prm33xx.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/errno.h> @@ -149,37 +150,29 @@ static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, - (pwrst << OMAP_POWERSTATE_SHIFT), + FIELD_PREP(OMAP_POWERSTATE_MASK, pwrst), pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); return 0; }

static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) { - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - v &= OMAP_POWERSTATE_MASK; - v >>= OMAP_POWERSTATE_SHIFT; + u32 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);

- return v; + return FIELD_GET(OMAP_POWERSTATE_MASK, v); }

static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) { - u32 v; + u32 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);

- v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= OMAP_POWERSTATEST_MASK; - v >>= OMAP_POWERSTATEST_SHIFT; - - return v; + return FIELD_GET(OMAP_POWERSTATEST_MASK, v); }

static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) { am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, - (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), + FIELD_PREP(AM33XX_LOWPOWERSTATECHANGE_MASK, 1), pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); return 0; } @@ -200,21 +193,17 @@ static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) if (!m) return -EINVAL;

- am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + am33xx_prm_rmw_reg_bits(m, field_prep(m, pwrst), pwrdm->prcm_offs, + pwrdm->pwrstctrl_offs);

return 0; }

static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) { - u32 v; + u32 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);

- v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= AM33XX_LOGICSTATEST_MASK; - v >>= AM33XX_LOGICSTATEST_SHIFT; - - return v; + return FIELD_GET(AM33XX_LOGICSTATEST_MASK, v); }

static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) @@ -226,10 +215,8 @@ static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) return -EINVAL;

v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - v &= m; - v >>= __ffs(m);

- return v; + return field_get(m, v); }

static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, @@ -241,8 +228,8 @@ static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, if (!m) return -EINVAL;

- am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + am33xx_prm_rmw_reg_bits(m, field_prep(m, pwrst), pwrdm->prcm_offs, + pwrdm->pwrstctrl_offs);

return 0; } @@ -256,8 +243,8 @@ static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, if (!m) return -EINVAL;

- am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + am33xx_prm_rmw_reg_bits(m, field_prep(m, pwrst), pwrdm->prcm_offs, + pwrdm->pwrstctrl_offs);

return 0; } @@ -271,10 +258,8 @@ static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) return -EINVAL;

v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= m; - v >>= __ffs(m);

- return v; + return field_get(m, v); }

static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) @@ -286,10 +271,8 @@ static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) return -EINVAL;

v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - v &= m; - v >>= __ffs(m);

- return v; + return field_get(m, v); }

static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 1b442b1285693cd9..88c8963ff602589b 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -9,6 +9,7 @@ * Rajendra Nayak rnayak@ti.com */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/err.h> @@ -536,7 +537,7 @@ void omap3_prm_save_scratchpad_contents(u32 *ptr) static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, - (pwrst << OMAP_POWERSTATE_SHIFT), + FIELD_PREP(OMAP_POWERSTATE_MASK, pwrst), pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; } diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 25093c1e5b9ac927..629b0980d301e0a6 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -9,6 +9,7 @@ * Rajendra Nayak rnayak@ti.com */

+#include <linux/bitfield.h> #include <linux/cpu_pm.h> #include <linux/kernel.h> #include <linux/delay.h> @@ -316,10 +317,8 @@ static void omap44xx_prm_reconfigure_io_chain(void) inst, omap4_prcm_irq_setup.pm_ctrl); omap_test_timeout( - (((omap4_prm_read_inst_reg(inst, - omap4_prcm_irq_setup.pm_ctrl) & - OMAP4430_WUCLK_STATUS_MASK) >> - OMAP4430_WUCLK_STATUS_SHIFT) == 1), + (FIELD_GET(OMAP4430_WUCLK_STATUS_MASK, + omap4_prm_read_inst_reg(inst, omap4_prcm_irq_setup.pm_ctrl)) == 1), MAX_IOPAD_LATCH_TIME, i); if (i == MAX_IOPAD_LATCH_TIME) pr_warn("PRM: I/O chain clock line assertion timed out\n"); @@ -329,10 +328,8 @@ static void omap44xx_prm_reconfigure_io_chain(void) inst, omap4_prcm_irq_setup.pm_ctrl); omap_test_timeout( - (((omap4_prm_read_inst_reg(inst, - omap4_prcm_irq_setup.pm_ctrl) & - OMAP4430_WUCLK_STATUS_MASK) >> - OMAP4430_WUCLK_STATUS_SHIFT) == 0), + (FIELD_GET(OMAP4430_WUCLK_STATUS_MASK, + omap4_prm_read_inst_reg(inst, omap4_prcm_irq_setup.pm_ctrl)) == 0), MAX_IOPAD_LATCH_TIME, i); if (i == MAX_IOPAD_LATCH_TIME) pr_warn("PRM: I/O chain clock line deassertion timed out\n"); @@ -427,7 +424,7 @@ static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst, static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK, - (pwrst << OMAP_POWERSTATE_SHIFT), + FIELD_PREP(OMAP_POWERSTATE_MASK, pwrst), pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -439,10 +436,8 @@ static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)

v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); - v &= OMAP_POWERSTATE_MASK; - v >>= OMAP_POWERSTATE_SHIFT;

- return v; + return FIELD_GET(OMAP_POWERSTATE_MASK, v); }

static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) @@ -451,10 +446,8 @@ static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)

v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTST); - v &= OMAP_POWERSTATEST_MASK; - v >>= OMAP_POWERSTATEST_SHIFT;

- return v; + return FIELD_GET(OMAP_POWERSTATEST_MASK, v); }

static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) @@ -463,16 +456,14 @@ static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)

v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTST); - v &= OMAP4430_LASTPOWERSTATEENTERED_MASK; - v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;

- return v; + return FIELD_GET(OMAP4430_LASTPOWERSTATEENTERED_MASK, v); }

static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) { omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, - (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), + FIELD_PREP(OMAP4430_LOWPOWERSTATECHANGE_MASK, 1), pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -491,7 +482,7 @@ static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) { u32 v;

- v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); + v = FIELD_PREP(OMAP4430_LOGICRETSTATE_MASK, pwrst); omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); @@ -506,7 +497,7 @@ static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,

m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);

- omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), + omap4_prminst_rmw_inst_reg_bits(m, field_prep(m, pwrst), pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);

@@ -520,7 +511,7 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,

m = omap2_pwrdm_get_mem_bank_retst_mask(bank);

- omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), + omap4_prminst_rmw_inst_reg_bits(m, field_prep(m, pwrst), pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);

@@ -533,10 +524,8 @@ static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)

v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTST); - v &= OMAP4430_LOGICSTATEST_MASK; - v >>= OMAP4430_LOGICSTATEST_SHIFT;

- return v; + return FIELD_GET(OMAP4430_LOGICSTATEST_MASK, v); }

static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) @@ -545,10 +534,8 @@ static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)

v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); - v &= OMAP4430_LOGICRETSTATE_MASK; - v >>= OMAP4430_LOGICRETSTATE_SHIFT;

- return v; + return FIELD_GET(OMAP4430_LOGICRETSTATE_MASK, v); }

/** @@ -587,10 +574,7 @@ static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)

v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTST); - v &= m; - v >>= __ffs(m); - - return v; + return field_get(m, v); }

static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) @@ -601,10 +585,7 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)

v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); - v &= m; - v >>= __ffs(m); - - return v; + return field_get(m, v); }

/** diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 86f1ac4c24125ae2..1a836627eee2eaec 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -7,6 +7,7 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ +#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/delay.h> #include <linux/init.h> @@ -379,9 +380,8 @@ static void omap3_init_voltsetup1(struct voltagedomain *voltdm,

val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate; val *= voltdm->sys_clk.rate / 8 / 1000000 + 1; - val <<= __ffs(voltdm->vfsm->voltsetup_mask); c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask; - c->voltsetup1 |= val; + c->voltsetup1 |= field_prep(voltdm->vfsm->voltsetup_mask, val); }

/** @@ -772,7 +772,7 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) mcode = voltdm->pmic->i2c_mcode; if (mcode) voltdm->rmw(vc->common->i2c_mcode_mask, - mcode << __ffs(vc->common->i2c_mcode_mask), + field_prep(vc->common->i2c_mcode_mask, mcode), vc->common->i2c_cfg_reg);

if (cpu_is_omap44xx()) @@ -850,7 +850,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)

/* Configure the i2c slave address for this VC */ voltdm->rmw(vc->smps_sa_mask, - vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), + field_prep(vc->smps_sa_mask, vc->i2c_slave_addr), vc->smps_sa_reg); vc->cfg_channel |= vc_cfg_bits->sa;

@@ -858,13 +858,13 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) * Configure the PMIC register addresses. */ voltdm->rmw(vc->smps_volra_mask, - vc->volt_reg_addr << __ffs(vc->smps_volra_mask), + field_prep(vc->smps_volra_mask, vc->volt_reg_addr), vc->smps_volra_reg); vc->cfg_channel |= vc_cfg_bits->rav;

if (vc->cmd_reg_addr) { voltdm->rmw(vc->smps_cmdra_mask, - vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), + field_prep(vc->smps_cmdra_mask, vc->cmd_reg_addr), vc->smps_cmdra_reg); vc->cfg_channel |= vc_cfg_bits->rac; } diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c index a709655b978cbcc9..3071426a5ec116d7 100644 --- a/arch/arm/mach-omap2/vp.c +++ b/arch/arm/mach-omap2/vp.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/init.h>

@@ -22,7 +23,7 @@ static u32 _vp_set_init_voltage(struct voltagedomain *voltdm, u32 volt) vpconfig &= ~(vp->common->vpconfig_initvoltage_mask | vp->common->vpconfig_forceupdate | vp->common->vpconfig_initvdd); - vpconfig |= vsel << __ffs(vp->common->vpconfig_initvoltage_mask); + vpconfig |= field_prep(vp->common->vpconfig_initvoltage_mask, vsel); voltdm->write(vpconfig, vp->vpconfig);

/* Trigger initVDD value copy to voltage processor */ @@ -73,8 +74,8 @@ void __init omap_vp_init(struct voltagedomain *voltdm) * VP_CONFIG: error gain is not set here, it will be updated * on each scale, based on OPP. */ - val = (voltdm->pmic->vp_erroroffset << - __ffs(voltdm->vp->common->vpconfig_erroroffset_mask)) | + val = field_prep(voltdm->vp->common->vpconfig_erroroffset_mask, + voltdm->pmic->vp_erroroffset) | vp->common->vpconfig_timeouten; voltdm->write(val, vp->vpconfig);

@@ -110,8 +111,8 @@ int omap_vp_update_errorgain(struct voltagedomain *voltdm,

/* Setting vp errorgain based on the voltage */ voltdm->rmw(voltdm->vp->common->vpconfig_errorgain_mask, - volt_data->vp_errgain << - __ffs(voltdm->vp->common->vpconfig_errorgain_mask), + field_prep(voltdm->vp->common->vpconfig_errorgain_mask, + volt_data->vp_errgain), voltdm->vp->vpconfig);

return 0;

Use the field_{get,prep}() helpers, instead of open-coding the same operations.

Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be --- Compile-tested only. Marked RFC, as this depends on [PATCH 01/17], but follows a different path to upstream. --- drivers/clk/ti/apll.c | 25 +++++------- drivers/clk/ti/dpll3xxx.c | 81 +++++++++++++++++---------------------- 2 files changed, 44 insertions(+), 62 deletions(-)

diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c index ac5bc8857a51456e..145a42ff050f076b 100644 --- a/drivers/clk/ti/apll.c +++ b/drivers/clk/ti/apll.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */

+#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/module.h> @@ -62,7 +63,7 @@ static int dra7_apll_enable(struct clk_hw *hw)

v = ti_clk_ll_ops->clk_readl(&ad->control_reg); v &= ~ad->enable_mask; - v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); + v |= field_prep(ad->enable_mask, APLL_FORCE_LOCK); ti_clk_ll_ops->clk_writel(v, &ad->control_reg);

state <<= __ffs(ad->idlest_mask); @@ -101,7 +102,7 @@ static void dra7_apll_disable(struct clk_hw *hw)

v = ti_clk_ll_ops->clk_readl(&ad->control_reg); v &= ~ad->enable_mask; - v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); + v |= field_prep(ad->enable_mask, APLL_AUTO_IDLE); ti_clk_ll_ops->clk_writel(v, &ad->control_reg); }

@@ -114,11 +115,8 @@ static int dra7_apll_is_enabled(struct clk_hw *hw) ad = clk->dpll_data;

v = ti_clk_ll_ops->clk_readl(&ad->control_reg); - v &= ad->enable_mask;

- v >>= __ffs(ad->enable_mask); - - return v == APLL_AUTO_IDLE ? 0 : 1; + return field_get(ad->enable_mask, v) == APLL_AUTO_IDLE ? 0 : 1; }

static u8 dra7_init_apll_parent(struct clk_hw *hw) @@ -242,14 +240,9 @@ static int omap2_apll_is_enabled(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct dpll_data *ad = clk->dpll_data; - u32 v; - - v = ti_clk_ll_ops->clk_readl(&ad->control_reg); - v &= ad->enable_mask; - - v >>= __ffs(ad->enable_mask); + u32 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);

- return v == OMAP2_EN_APLL_LOCKED ? 1 : 0; + return field_get(ad->enable_mask, v) == OMAP2_EN_APLL_LOCKED ? 1 : 0; }

static unsigned long omap2_apll_recalc(struct clk_hw *hw, @@ -272,7 +265,7 @@ static int omap2_apll_enable(struct clk_hw *hw)

v = ti_clk_ll_ops->clk_readl(&ad->control_reg); v &= ~ad->enable_mask; - v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask); + v |= field_prep(ad->enable_mask, OMAP2_EN_APLL_LOCKED); ti_clk_ll_ops->clk_writel(v, &ad->control_reg);

while (1) { @@ -302,7 +295,7 @@ static void omap2_apll_disable(struct clk_hw *hw)

v = ti_clk_ll_ops->clk_readl(&ad->control_reg); v &= ~ad->enable_mask; - v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask); + v |= field_prep(ad->enable_mask, OMAP2_EN_APLL_STOPPED); ti_clk_ll_ops->clk_writel(v, &ad->control_reg); }

@@ -320,7 +313,7 @@ static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)

v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg); v &= ~ad->autoidle_mask; - v |= val << __ffs(ad->autoidle_mask); + v |= field_prep(ad->autoidle_mask, val); ti_clk_ll_ops->clk_writel(v, &ad->control_reg); }

diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index e32b3515f9e76b67..21c94d758eed92b7 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -15,6 +15,7 @@ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/device.h> #include <linux/list.h> @@ -53,7 +54,7 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)

v = ti_clk_ll_ops->clk_readl(&dd->control_reg); v &= ~dd->enable_mask; - v |= clken_bits << __ffs(dd->enable_mask); + v |= field_prep(dd->enable_mask, clken_bits); ti_clk_ll_ops->clk_writel(v, &dd->control_reg); }

@@ -333,8 +334,8 @@ static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk)

v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg); v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask); - v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask); - v |= exponent << __ffs(dd->ssc_modfreq_exp_mask); + v |= field_prep(dd->ssc_modfreq_mant_mask, mantissa); + v |= field_prep(dd->ssc_modfreq_exp_mask, exponent); ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg);

deltam_step = dd->last_rounded_m * dd->ssc_deltam; @@ -348,8 +349,7 @@ static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk) if (deltam_step > 0xFFFFF) deltam_step = 0xFFFFF;

- deltam_ceil = (deltam_step & dd->ssc_deltam_int_mask) >> - __ffs(dd->ssc_deltam_int_mask); + deltam_ceil = field_get(dd->ssc_deltam_int_mask, deltam_step); if (deltam_step & dd->ssc_deltam_frac_mask) deltam_ceil++;

@@ -363,8 +363,8 @@ static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk)

v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg); v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask); - v |= deltam_step << __ffs(dd->ssc_deltam_int_mask | - dd->ssc_deltam_frac_mask); + v |= field_prep(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask, + deltam_step); ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg); } else { ctrl &= ~dd->ssc_enable_mask; @@ -398,7 +398,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { v = ti_clk_ll_ops->clk_readl(&dd->control_reg); v &= ~dd->freqsel_mask; - v |= freqsel << __ffs(dd->freqsel_mask); + v |= field_prep(dd->freqsel_mask, freqsel); ti_clk_ll_ops->clk_writel(v, &dd->control_reg); }

@@ -414,20 +414,20 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) }

v &= ~(dd->mult_mask | dd->div1_mask); - v |= dd->last_rounded_m << __ffs(dd->mult_mask); - v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); + v |= field_prep(dd->mult_mask, dd->last_rounded_m); + v |= field_prep(dd->div1_mask, dd->last_rounded_n - 1);

/* Configure dco and sd_div for dplls that have these fields */ if (dd->dco_mask) { _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); v &= ~(dd->dco_mask); - v |= dco << __ffs(dd->dco_mask); + v |= field_prep(dd->dco_mask, dco); } if (dd->sddiv_mask) { _lookup_sddiv(clk, &sd_div, dd->last_rounded_m, dd->last_rounded_n); v &= ~(dd->sddiv_mask); - v |= sd_div << __ffs(dd->sddiv_mask); + v |= field_prep(dd->sddiv_mask, sd_div); }

/* @@ -728,7 +728,6 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) { const struct dpll_data *dd; - u32 v;

if (!clk || !clk->dpll_data) return -EINVAL; @@ -738,11 +737,8 @@ static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) if (!dd->autoidle_mask) return -EINVAL;

- v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); - v &= dd->autoidle_mask; - v >>= __ffs(dd->autoidle_mask); - - return v; + return field_get(dd->autoidle_mask, + ti_clk_ll_ops->clk_readl(&dd->autoidle_reg)); }

/** @@ -774,7 +770,7 @@ static void omap3_dpll_allow_idle(struct clk_hw_omap *clk) */ v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); v &= ~dd->autoidle_mask; - v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); + v |= field_prep(dd->autoidle_mask, DPLL_AUTOIDLE_LOW_POWER_STOP); ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg); }

@@ -799,7 +795,7 @@ static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)

v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); v &= ~dd->autoidle_mask; - v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); + v |= field_prep(dd->autoidle_mask, DPLL_AUTOIDLE_DISABLE); ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg); }

@@ -857,8 +853,8 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,

WARN_ON(!dd->enable_mask);

- v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask; - v >>= __ffs(dd->enable_mask); + v = field_get(dd->enable_mask, + ti_clk_ll_ops->clk_readl(&dd->control_reg)); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) rate = parent_rate; else @@ -877,19 +873,17 @@ int omap3_core_dpll_save_context(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct dpll_data *dd; - u32 v;

dd = clk->dpll_data;

- v = ti_clk_ll_ops->clk_readl(&dd->control_reg); - clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask); + clk->context = field_get(dd->enable_mask, + ti_clk_ll_ops->clk_readl(&dd->control_reg));

if (clk->context == DPLL_LOCKED) { - v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); - dd->last_rounded_m = (v & dd->mult_mask) >> - __ffs(dd->mult_mask); - dd->last_rounded_n = ((v & dd->div1_mask) >> - __ffs(dd->div1_mask)) + 1; + u32 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); + + dd->last_rounded_m = field_get(dd->mult_mask, v); + dd->last_rounded_n = field_get(dd->div1_mask, v) + 1; }

return 0; @@ -916,8 +910,8 @@ void omap3_core_dpll_restore_context(struct clk_hw *hw)

v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); v &= ~(dd->mult_mask | dd->div1_mask); - v |= dd->last_rounded_m << __ffs(dd->mult_mask); - v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); + v |= field_prep(dd->mult_mask, dd->last_rounded_m); + v |= field_prep(dd->div1_mask, dd->last_rounded_n - 1); ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);

_omap3_dpll_write_clken(clk, DPLL_LOCKED); @@ -938,19 +932,17 @@ int omap3_noncore_dpll_save_context(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct dpll_data *dd; - u32 v;

dd = clk->dpll_data;

- v = ti_clk_ll_ops->clk_readl(&dd->control_reg); - clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask); + clk->context = field_get(dd->enable_mask, + ti_clk_ll_ops->clk_readl(&dd->control_reg));

if (clk->context == DPLL_LOCKED) { - v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); - dd->last_rounded_m = (v & dd->mult_mask) >> - __ffs(dd->mult_mask); - dd->last_rounded_n = ((v & dd->div1_mask) >> - __ffs(dd->div1_mask)) + 1; + u32 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); + + dd->last_rounded_m = field_get(dd->mult_mask, v); + dd->last_rounded_n = field_get(dd->div1_mask, v) + 1; }

return 0; @@ -974,12 +966,9 @@ void omap3_noncore_dpll_restore_context(struct clk_hw *hw) ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);

- if (clk->context == ((ctrl & dd->enable_mask) >> - __ffs(dd->enable_mask)) && - dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >> - __ffs(dd->mult_mask)) && - dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >> - __ffs(dd->div1_mask)) + 1) { + if (clk->context == field_get(dd->enable_mask, ctrl) && + dd->last_rounded_m == field_get(dd->mult_mask, mult_div1) && + dd->last_rounded_n == field_get(dd->div1_mask, mult_div1) + 1) { /* nothing to be done */ return; }

Use the field_prep() helper, instead of defining a custom macro, or open-coding the same operation.

Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be --- Compile-tested only. Marked RFC, as this depends on [PATCH 01/17], but follows a different path to upstream. --- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 1 - .../iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c | 7 +-- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 45 +++++++++---------- drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c | 11 ++--- 4 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h index 6ac4eac36458aa23..5282bdb0942e8d71 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -62,7 +62,6 @@ enum st_lsm6dsx_hw_id { ST_LSM6DSX_SAMPLE_SIZE) #define ST_LSM6DSX_MAX_TAGGED_WORD_LEN ((32 / ST_LSM6DSX_TAGGED_SAMPLE_SIZE) \ * ST_LSM6DSX_TAGGED_SAMPLE_SIZE) -#define ST_LSM6DSX_SHIFT_VAL(val, mask) (((val) << __ffs(mask)) & (mask))

#define ST_LSM6DSX_CHANNEL_ACC(chan_type, addr, mod, scan_idx) \ { \ diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c index 16730a7809643695..80c763b837bfde01 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c @@ -29,6 +29,7 @@ * Lorenzo Bianconi lorenzo.bianconi@st.com * Denis Ciocca denis.ciocca@st.com */ +#include <linux/bitfield.h> #include <linux/module.h> #include <linux/iio/kfifo_buf.h> #include <linux/iio/iio.h> @@ -155,7 +156,7 @@ static int st_lsm6dsx_update_decimators(struct st_lsm6dsx_hw *hw)

dec_reg = &hw->settings->decimator[sensor->id]; if (dec_reg->addr) { - int val = ST_LSM6DSX_SHIFT_VAL(data, dec_reg->mask); + int val = field_prep(dec_reg->mask, data);

err = st_lsm6dsx_update_bits_locked(hw, dec_reg->addr, dec_reg->mask, @@ -177,7 +178,7 @@ static int st_lsm6dsx_update_decimators(struct st_lsm6dsx_hw *hw) if (ts_dec_reg->addr) { int val, ts_dec = !!hw->ts_sip;

- val = ST_LSM6DSX_SHIFT_VAL(ts_dec, ts_dec_reg->mask); + val = field_prep(ts_dec_reg->mask, ts_dec); err = st_lsm6dsx_update_bits_locked(hw, ts_dec_reg->addr, ts_dec_reg->mask, val); } @@ -215,7 +216,7 @@ static int st_lsm6dsx_set_fifo_odr(struct st_lsm6dsx_sensor *sensor, } else { data = 0; } - val = ST_LSM6DSX_SHIFT_VAL(data, batch_reg->mask); + val = field_prep(batch_reg->mask, data); return st_lsm6dsx_update_bits_locked(hw, batch_reg->addr, batch_reg->mask, val); } else { diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c index f2cbbc756459b1cb..f7f6783f8842ed98 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c @@ -46,6 +46,7 @@ * Denis Ciocca denis.ciocca@st.com */

+#include <linux/bitfield.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/delay.h> @@ -1159,7 +1160,7 @@ int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable) int err;

hub_settings = &hw->settings->shub_settings; - data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask); + data = field_prep(hub_settings->page_mux.mask, enable); err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr, hub_settings->page_mux.mask, data); usleep_range(100, 150); @@ -1220,8 +1221,7 @@ static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor, if (i == fs_table->fs_len) return -EINVAL;

- data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val, - fs_table->reg.mask); + data = field_prep(fs_table->reg.mask, fs_table->fs_avl[i].val); err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr, fs_table->reg.mask, data); if (err < 0) @@ -1319,7 +1319,7 @@ st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u32 req_odr) }

reg = &hw->settings->odr_table[ref_sensor->id].reg; - data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); + data = field_prep(reg->mask, val); return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); }

@@ -1473,7 +1473,7 @@ static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state)

reg = &hw->settings->event_settings.enable_reg; if (reg->addr) { - data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask); + data = field_prep(reg->mask, state); err = st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); if (err < 0) @@ -1481,7 +1481,7 @@ static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state) }

/* Enable wakeup interrupt */ - data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); + data = field_prep(hw->irq_routing->mask, state); return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, hw->irq_routing->mask, data); } @@ -1526,7 +1526,7 @@ st_lsm6dsx_write_event(struct iio_dev *iio_dev, return -EINVAL;

reg = &hw->settings->event_settings.wakeup_reg; - data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); + data = field_prep(reg->mask, val); err = st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); if (err < 0) @@ -1786,7 +1786,7 @@ static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw) return err; }

- data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask); + data = field_prep(hub_settings->pullup_en.mask, 1); err = regmap_update_bits(hw->regmap, hub_settings->pullup_en.addr, hub_settings->pullup_en.mask, data); @@ -1804,7 +1804,7 @@ static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw) if (err < 0) return err;

- data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask); + data = field_prep(hub_settings->aux_sens.mask, 3); err = regmap_update_bits(hw->regmap, hub_settings->aux_sens.addr, hub_settings->aux_sens.mask, data); @@ -1816,7 +1816,7 @@ static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw) }

if (hub_settings->emb_func.addr) { - data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->emb_func.mask); + data = field_prep(hub_settings->emb_func.mask, 1); err = regmap_update_bits(hw->regmap, hub_settings->emb_func.addr, hub_settings->emb_func.mask, data); @@ -1833,7 +1833,7 @@ static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw) ts_settings = &hw->settings->ts_settings; /* enable hw timestamp generation if necessary */ if (ts_settings->timer_en.addr) { - val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask); + val = field_prep(ts_settings->timer_en.mask, 1); err = regmap_update_bits(hw->regmap, ts_settings->timer_en.addr, ts_settings->timer_en.mask, val); @@ -1843,7 +1843,7 @@ static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw)

/* enable high resolution for hw ts timer if necessary */ if (ts_settings->hr_timer.addr) { - val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask); + val = field_prep(ts_settings->hr_timer.mask, 1); err = regmap_update_bits(hw->regmap, ts_settings->hr_timer.addr, ts_settings->hr_timer.mask, val); @@ -1853,7 +1853,7 @@ static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw)

/* enable ts queueing in FIFO if necessary */ if (ts_settings->fifo_en.addr) { - val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask); + val = field_prep(ts_settings->fifo_en.mask, 1); err = regmap_update_bits(hw->regmap, ts_settings->fifo_en.addr, ts_settings->fifo_en.mask, val); @@ -1899,7 +1899,7 @@ static int st_lsm6dsx_reset_device(struct st_lsm6dsx_hw *hw) /* device sw reset */ reg = &hw->settings->reset; err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, - ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); + field_prep(reg->mask, 1)); if (err < 0) return err;

@@ -1908,7 +1908,7 @@ static int st_lsm6dsx_reset_device(struct st_lsm6dsx_hw *hw) /* reload trimming parameter */ reg = &hw->settings->boot; err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, - ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); + field_prep(reg->mask, 1)); if (err < 0) return err;

@@ -1929,7 +1929,7 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) /* enable Block Data Update */ reg = &hw->settings->bdu; err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, - ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); + field_prep(reg->mask, 1)); if (err < 0) return err;

@@ -1939,7 +1939,7 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) return err;

err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, - ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); + field_prep(reg->mask, 1)); if (err < 0) return err;

@@ -1947,7 +1947,7 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) if (hw->settings->irq_config.lir.addr) { reg = &hw->settings->irq_config.lir; err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, - ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); + field_prep(reg->mask, 1)); if (err < 0) return err;

@@ -1956,7 +1956,7 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) reg = &hw->settings->irq_config.clear_on_read; err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, - ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); + field_prep(reg->mask, 1)); if (err < 0) return err; } @@ -1966,7 +1966,7 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) if (hw->settings->drdy_mask.addr) { reg = &hw->settings->drdy_mask; err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, - ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); + field_prep(reg->mask, 1)); if (err < 0) return err; } @@ -2131,8 +2131,7 @@ static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw)

reg = &hw->settings->irq_config.hla; err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, - ST_LSM6DSX_SHIFT_VAL(irq_active_low, - reg->mask)); + field_prep(reg->mask, irq_active_low)); if (err < 0) return err;

@@ -2141,7 +2140,7 @@ static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw) (pdata && pdata->open_drain)) { reg = &hw->settings->irq_config.od; err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, - ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); + field_prep(reg->mask, 1)); if (err < 0) return err;

diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c index 99562ba85ee43098..ea0e568c042b4b43 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c @@ -22,6 +22,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ +#include <linux/bitfield.h> #include <linux/module.h> #include <linux/regmap.h> #include <linux/iio/iio.h> @@ -263,7 +264,7 @@ static int st_lsm6dsx_shub_master_enable(struct st_lsm6dsx_sensor *sensor, goto out; }

- data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->master_en.mask); + data = field_prep(hub_settings->master_en.mask, enable); err = regmap_update_bits(hw->regmap, hub_settings->master_en.addr, hub_settings->master_en.mask, data);

@@ -296,7 +297,7 @@ st_lsm6dsx_shub_read(struct st_lsm6dsx_sensor *sensor, u8 addr, aux_sens = &hw->settings->shub_settings.aux_sens; /* do not overwrite aux_sens */ if (slv_addr + 2 == aux_sens->addr) - slv_config = ST_LSM6DSX_SHIFT_VAL(3, aux_sens->mask); + slv_config = field_prep(aux_sens->mask, 3);

config[0] = (sensor->ext_info.addr << 1) | 1; config[1] = addr; @@ -346,7 +347,7 @@ st_lsm6dsx_shub_write(struct st_lsm6dsx_sensor *sensor, u8 addr, if (hub_settings->wr_once.addr) { unsigned int data;

- data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->wr_once.mask); + data = field_prep(hub_settings->wr_once.mask, 1); err = st_lsm6dsx_shub_write_reg_with_mask(hw, hub_settings->wr_once.addr, hub_settings->wr_once.mask, @@ -395,7 +396,7 @@ st_lsm6dsx_shub_write_with_mask(struct st_lsm6dsx_sensor *sensor, if (err < 0) return err;

- data = ((data & ~mask) | (val << __ffs(mask) & mask)); + data = (data & ~mask) | field_prep(mask, val);

return st_lsm6dsx_shub_write(sensor, addr, &data, sizeof(data)); } @@ -835,7 +836,7 @@ st_lsm6dsx_shub_check_wai(struct st_lsm6dsx_hw *hw, u8 *i2c_addr, slv_addr = ST_LSM6DSX_SLV_ADDR(0, hub_settings->slv0_addr); /* do not overwrite aux_sens */ if (slv_addr + 2 == aux_sens->addr) - slv_config = ST_LSM6DSX_SHIFT_VAL(3, aux_sens->mask); + slv_config = field_prep(aux_sens->mask, 3);

for (i = 0; i < ARRAY_SIZE(settings->i2c_addr); i++) { if (!settings->i2c_addr[i])

Use the field_prep() helper, instead open-coding the same operation.

Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be --- Compile-tested only. Marked RFC, as this depends on [PATCH 01/17], but follows a different path to upstream. --- drivers/mmc/host/sdhci-of-aspeed.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 6e4e132903a6346b..26ac73aafb2ed55d 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -2,6 +2,7 @@ /* Copyright (C) 2019 ASPEED Technology Inc. */ /* Copyright (C) 2019 IBM Corp. */

+#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> @@ -131,8 +132,8 @@ aspeed_sdc_set_phase_tap(const struct aspeed_sdhci_tap_desc *desc, { reg &= ~(desc->enable_mask | desc->tap_mask); if (enable) { - reg |= tap << __ffs(desc->tap_mask); - reg |= desc->enable_value << __ffs(desc->enable_mask); + reg |= field_prep(desc->tap_mask, tap); + reg |= field_prep(desc->enable_mask, desc->enable_value); }

return reg;

Use the field_{get,prep}() helpers, instead of defining a custom function, or open-coding the same operations.

Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be --- Compile-tested only. Marked RFC, as this depends on [PATCH 01/17], but follows a different path to upstream. --- drivers/pinctrl/ti/pinctrl-ti-iodelay.c | 35 +++++++------------------ 1 file changed, 10 insertions(+), 25 deletions(-)

diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index 4e2382778d38f557..b220dcd9215520db 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -9,6 +9,7 @@ * warranty of any kind, whether express or implied. */

+#include <linux/bitfield.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> @@ -155,18 +156,6 @@ struct ti_iodelay_device { struct ti_iodelay_reg_values reg_init_conf_values; };

-/** - * ti_iodelay_extract() - extract bits for a field - * @val: Register value - * @mask: Mask - * - * Return: extracted value which is appropriately shifted - */ -static inline u32 ti_iodelay_extract(u32 val, u32 mask) -{ - return (val & mask) >> __ffs(mask); -} - /** * ti_iodelay_compute_dpe() - Compute equation for delay parameter * @period: Period to use @@ -233,10 +222,10 @@ static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, }

reg_mask = reg->signature_mask; - reg_val = reg->signature_value << __ffs(reg->signature_mask); + reg_val = field_prep(reg->signature_mask, reg->signature_value);

reg_mask |= reg->binary_data_coarse_mask; - tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask); + tmp_val = field_prep(reg->binary_data_coarse_mask, c_elements); if (tmp_val & ~reg->binary_data_coarse_mask) { dev_err(dev, "Masking overflow of coarse elements %08x\n", tmp_val); @@ -245,7 +234,7 @@ static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, reg_val |= tmp_val;

reg_mask |= reg->binary_data_fine_mask; - tmp_val = f_elements << __ffs(reg->binary_data_fine_mask); + tmp_val = field_prep(reg->binary_data_fine_mask, f_elements); if (tmp_val & ~reg->binary_data_fine_mask) { dev_err(dev, "Masking overflow of fine elements %08x\n", tmp_val); @@ -260,7 +249,7 @@ static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, * impacting iodelay configuration. Use with care! */ reg_mask |= reg->lock_mask; - reg_val |= reg->unlock_val << __ffs(reg->lock_mask); + reg_val |= field_prep(reg->lock_mask, reg->unlock_val); r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val);

dev_dbg(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n", @@ -296,16 +285,14 @@ static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod) r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val); if (r) return r; - ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask); + ival->ref_clk_period = field_get(reg->refclk_period_mask, val); dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period);

r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val); if (r) return r; - ival->coarse_ref_count = - ti_iodelay_extract(val, reg->coarse_ref_count_mask); - ival->coarse_delay_count = - ti_iodelay_extract(val, reg->coarse_delay_count_mask); + ival->coarse_ref_count = field_get(reg->coarse_ref_count_mask, val); + ival->coarse_delay_count = field_get(reg->coarse_delay_count_mask, val); if (!ival->coarse_delay_count) { dev_err(dev, "Invalid Coarse delay count (0) (reg=0x%08x)\n", val); @@ -326,10 +313,8 @@ static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod) r = regmap_read(iod->regmap, reg->reg_fine_offset, &val); if (r) return r; - ival->fine_ref_count = - ti_iodelay_extract(val, reg->fine_ref_count_mask); - ival->fine_delay_count = - ti_iodelay_extract(val, reg->fine_delay_count_mask); + ival->fine_ref_count = field_get(reg->fine_ref_count_mask, val); + ival->fine_delay_count = field_get(reg->fine_delay_count_mask, val); if (!ival->fine_delay_count) { dev_err(dev, "Invalid Fine delay count (0) (reg=0x%08x)\n", val);

Use the field_{get,prep}() helpers, instead of open-coding the same operations.

Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be --- Compile-tested only. Marked RFC, as this depends on [PATCH 01/17], but follows a different path to upstream. --- drivers/regulator/ti-abb-regulator.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/regulator/ti-abb-regulator.c b/drivers/regulator/ti-abb-regulator.c index 2931a0b89bffbf7a..3bc6ca5c382a4273 100644 --- a/drivers/regulator/ti-abb-regulator.c +++ b/drivers/regulator/ti-abb-regulator.c @@ -17,6 +17,7 @@ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> @@ -132,7 +133,7 @@ static inline u32 ti_abb_rmw(u32 mask, u32 value, void __iomem *reg)

val = readl(reg); val &= ~mask; - val |= (value << __ffs(mask)) & mask; + val |= field_prep(mask, value); writel(val, reg);

return val; @@ -229,7 +230,7 @@ static void ti_abb_program_ldovbb(struct device *dev, const struct ti_abb *abb, case TI_ABB_SLOW_OPP: case TI_ABB_FAST_OPP: val |= abb->ldovbb_override_mask; - val |= info->vset << __ffs(abb->ldovbb_vset_mask); + val |= field_prep(abb->ldovbb_vset_mask, info->vset); break; }

@@ -606,7 +607,7 @@ static int ti_abb_init_table(struct device *dev, struct ti_abb *abb, pname, *volt_table, vset_mask); continue; } - info->vset = (efuse_val & vset_mask) >> __ffs(vset_mask); + info->vset = field_get(vset_mask, efuse_val); dev_dbg(dev, "[%d]v=%d vset=%x\n", i, *volt_table, info->vset); check_abb: switch (info->opp_sel) {

Use the field_{get,prep}() helpers, instead of open-coding the same operations.

Signed-off-by: Geert Uytterhoeven geert+renesas@glider.be --- Compile-tested only. Marked RFC, as this depends on [PATCH 01/17], but follows a different path to upstream. --- drivers/thermal/ti-soc-thermal/ti-bandgap.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/thermal/ti-soc-thermal/ti-bandgap.c b/drivers/thermal/ti-soc-thermal/ti-bandgap.c index ea0603b59309f5f0..83a34d698414b177 100644 --- a/drivers/thermal/ti-soc-thermal/ti-bandgap.c +++ b/drivers/thermal/ti-soc-thermal/ti-bandgap.c @@ -9,6 +9,7 @@ * Eduardo Valentin eduardo.valentin@ti.com */

+#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/cpu_pm.h> #include <linux/device.h> @@ -80,10 +81,10 @@ do { \ struct temp_sensor_registers *t; \ u32 r; \ \ - t = bgp->conf->sensors[(id)].registers; \ + t = bgp->conf->sensors[(id)].registers; \ r = ti_bandgap_readl(bgp, t->reg); \ r &= ~t->mask; \ - r |= (val) << __ffs(t->mask); \ + r |= field_prep(t->mask, val); \ ti_bandgap_writel(bgp, r, t->reg); \ } while (0)

@@ -342,8 +343,7 @@ static void ti_bandgap_read_counter(struct ti_bandgap *bgp, int id,

tsr = bgp->conf->sensors[id].registers; time = ti_bandgap_readl(bgp, tsr->bgap_counter); - time = (time & tsr->counter_mask) >> - __ffs(tsr->counter_mask); + time = field_get(tsr->counter_mask, time); time = time * 1000 / bgp->clk_rate; *interval = time; } @@ -363,8 +363,7 @@ static void ti_bandgap_read_counter_delay(struct ti_bandgap *bgp, int id, tsr = bgp->conf->sensors[id].registers;

reg_val = ti_bandgap_readl(bgp, tsr->bgap_mask_ctrl); - reg_val = (reg_val & tsr->mask_counter_delay_mask) >> - __ffs(tsr->mask_counter_delay_mask); + reg_val = field_get(tsr->mask_counter_delay_mask, reg_val); switch (reg_val) { case 0: *interval = 0;