[alsa-devel] [PATCH 0/5] OMAP4: Fix CLKR/FSR mux for port with 6 pin mode
Hello,
This series will fix the CLKR/FSR signal mux configuration for OMAP4 devices. McBSP4 has 6 pin configuration on McBSP4 port while OMAP2/3 has the same capability on McBSP1 port. The API for mux control will be simplified for the mcbsp users (ASoC).
The series depends on earlier series sent for mcbsp: OMAP4: McBSP: Fix clock reparenting
I think the ASoC patch can go via linux-omap, since we do not have other changes for McBSP coming via sound tree.
Regards, Peter --- Peter Ujfalusi (5): OMAP2/3: mcbsp: Check McBSP port number in CLKR/FSR mux callback OMAP: mcbsp: Signle function for CLKR/FSR source mux configuration ASoC: omap-mcbsp: Use the new interface for configuring CLKR/FSR mux OMAP: mcbsp: Remove old CLKR/FSR mux functions OMAP4: mcbsp: Callback function for McBSP4 CLKR/FSR mux selection
arch/arm/mach-omap2/mcbsp.c | 47 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 15 ++++------ arch/arm/plat-omap/mcbsp.c | 49 +++++++++++++++---------------- sound/soc/omap/omap-mcbsp.c | 12 +++++-- 4 files changed, 85 insertions(+), 38 deletions(-)
CLKR/FSR mux is only possible on port 1. Make sure that we only change the mux if the call is made with the correct mcbsp device.
Signed-off-by: Peter Ujfalusi peter.ujfalusi@ti.com --- arch/arm/mach-omap2/mcbsp.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 829f4c7..269765c 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -38,8 +38,13 @@ static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal, const char *src) { + struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); u32 v;
+ /* Only McBSP1 have 6 pin configuration (CLKR/FSR source selectable) */ + if (mcbsp->id != 0) + return -EINVAL; + v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
if (!strcmp(signal, "clkr")) {
Use single function to configure the CLKR/FSR mux configuration. OMAP2/3 has 6 pin configuration on McBSP1 instance, while on OMAP4 McBSP4 instance have the 6 pin configuration.
Signed-off-by: Peter Ujfalusi peter.ujfalusi@ti.com --- arch/arm/plat-omap/include/plat/mcbsp.h | 13 +++++------ arch/arm/plat-omap/mcbsp.c | 35 +++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 8fa74e2..7f9a745 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -242,13 +242,11 @@ enum { #define RFSREN 0x0002 #define RSYNCERREN 0x0001
-/* CLKR signal muxing options */ -#define CLKR_SRC_CLKR 0 -#define CLKR_SRC_CLKX 1 - -/* FSR signal muxing options */ -#define FSR_SRC_FSR 0 -#define FSR_SRC_FSX 1 +/* Clock signal muxing options */ +#define CLKR_SRC_CLKR 0 /* CLKR signal is from the CLKR pin */ +#define CLKR_SRC_CLKX 1 /* CLKR signal is from the CLKX pin */ +#define FSR_SRC_FSR 2 /* FSR signal is from the FSR pin */ +#define FSR_SRC_FSX 3 /* FSR signal is from the FSX pin */
/* McBSP functional clock sources */ #define MCBSP_CLKS_PRCM_SRC 0 @@ -381,6 +379,7 @@ extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id); /* McBSP signal muxing API */ void omap2_mcbsp1_mux_clkr_src(u8 mux); void omap2_mcbsp1_mux_fsr_src(u8 mux); +int omap_mcbsp_6pin_src_mux(unsigned int id, u8 mux);
int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index f2eb1bb..501c6d1 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -957,6 +957,41 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux) } EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
+int omap_mcbsp_6pin_src_mux(unsigned int id, u8 mux) +{ + struct omap_mcbsp *mcbsp; + const char *signal, *src; + int ret = 0; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); + return -EINVAL; + } + + mcbsp = id_to_mcbsp_ptr(id); + + if (mux == CLKR_SRC_CLKR) { + signal = "clkr"; + src = "clkr"; + } else if (mux == CLKR_SRC_CLKX) { + signal = "clkr"; + src = "clkx"; + } else if (mux == FSR_SRC_FSR) { + signal = "fsr"; + src = "fsr"; + } else if (mux == FSR_SRC_FSX) { + signal = "fsr"; + src = "fsx"; + } else + return -EINVAL; + + if (mcbsp->pdata->mux_signal) + ret = mcbsp->pdata->mux_signal(mcbsp->dev, signal, src); + + return ret; +} +EXPORT_SYMBOL(omap_mcbsp_6pin_src_mux); + #define max_thres(m) (mcbsp->pdata->buffer_size) #define valid_threshold(m, val) ((val) <= max_thres(m)) #define THRESHOLD_PROP_BUILDER(prop) \
Switch using the new API to configure the 6 pin port's CLKR/FSR mux configuration.
Signed-off-by: Peter Ujfalusi peter.ujfalusi@ti.com --- sound/soc/omap/omap-mcbsp.c | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index 0173719..b9b0a9b 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -575,22 +575,26 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, case OMAP_MCBSP_CLKR_SRC_CLKR: if (cpu_class_is_omap1()) break; - omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKR); + err = omap_mcbsp_6pin_src_mux(mcbsp_data->bus_id, + CLKR_SRC_CLKR); break; case OMAP_MCBSP_CLKR_SRC_CLKX: if (cpu_class_is_omap1()) break; - omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKX); + err = omap_mcbsp_6pin_src_mux(mcbsp_data->bus_id, + CLKR_SRC_CLKX); break; case OMAP_MCBSP_FSR_SRC_FSR: if (cpu_class_is_omap1()) break; - omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSR); + err = omap_mcbsp_6pin_src_mux(mcbsp_data->bus_id, + FSR_SRC_FSR); break; case OMAP_MCBSP_FSR_SRC_FSX: if (cpu_class_is_omap1()) break; - omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSX); + err = omap_mcbsp_6pin_src_mux(mcbsp_data->bus_id, + FSR_SRC_FSX); break; default: err = -ENODEV;
On Thu, Dec 22, 2011 at 07:31:44PM +0200, Peter Ujfalusi wrote:
Switch using the new API to configure the 6 pin port's CLKR/FSR mux configuration.
Acked-by: Mark Brown broonie@opensource.wolfsonmicro.com
New, single function has replaced the old mux configuration API for CLKR/FSR configuration. Remove the unused code.
Signed-off-by: Peter Ujfalusi peter.ujfalusi@ti.com --- arch/arm/plat-omap/include/plat/mcbsp.h | 2 - arch/arm/plat-omap/mcbsp.c | 36 ------------------------------- 2 files changed, 0 insertions(+), 38 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 7f9a745..89aa33b 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -377,8 +377,6 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx); extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
/* McBSP signal muxing API */ -void omap2_mcbsp1_mux_clkr_src(u8 mux); -void omap2_mcbsp1_mux_fsr_src(u8 mux); int omap_mcbsp_6pin_src_mux(unsigned int id, u8 mux);
int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 501c6d1..c48d974 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -921,42 +921,6 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) } EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
-void omap2_mcbsp1_mux_clkr_src(u8 mux) -{ - struct omap_mcbsp *mcbsp; - const char *src; - - if (mux == CLKR_SRC_CLKR) - src = "clkr"; - else if (mux == CLKR_SRC_CLKX) - src = "clkx"; - else - return; - - mcbsp = id_to_mcbsp_ptr(0); - if (mcbsp->pdata->mux_signal) - mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src); -} -EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src); - -void omap2_mcbsp1_mux_fsr_src(u8 mux) -{ - struct omap_mcbsp *mcbsp; - const char *src; - - if (mux == FSR_SRC_FSR) - src = "fsr"; - else if (mux == FSR_SRC_FSX) - src = "fsx"; - else - return; - - mcbsp = id_to_mcbsp_ptr(0); - if (mcbsp->pdata->mux_signal) - mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src); -} -EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src); - int omap_mcbsp_6pin_src_mux(unsigned int id, u8 mux) { struct omap_mcbsp *mcbsp;
On OMAP4 McBSP4 has 6 pin mode. The configuration of the CLKR/FSR source can be done via the CONTROL_MCBSPLP register which only has two valid bits (30: CLKR mux, 31: FSR mux).
Signed-off-by: Peter Ujfalusi peter.ujfalusi@ti.com --- arch/arm/mach-omap2/mcbsp.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 269765c..d5fbe9a 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -70,6 +70,46 @@ static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal, return 0; }
+#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31) +#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30) +static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal, + const char *src) +{ + struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); + u32 v; + + /* Only McBSP4 have 6 pin configuration (CLKR/FSR source selectable) */ + if (mcbsp->id != 3) + return -EINVAL; + + /* + * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR + * mux) is used */ + v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP); + + if (!strcmp(signal, "clkr")) { + if (!strcmp(src, "clkr")) + v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX; + else if (!strcmp(src, "clkx")) + v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX; + else + return -EINVAL; + } else if (!strcmp(signal, "fsr")) { + if (!strcmp(src, "fsr")) + v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX; + else if (!strcmp(src, "fsx")) + v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX; + else + return -EINVAL; + } else { + return -EINVAL; + } + + omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP); + + return 0; +} + static int omap2_mcbsp_reparent_clk(struct device *dev, struct clk *clk, char *fck_src_name) { @@ -209,6 +249,8 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
if (oh->class->rev == MCBSP_CONFIG_TYPE4) pdata->set_clk_src = omap4_mcbsp_set_clk_src; + if (id == 4) + pdata->mux_signal = omap4_mcbsp4_mux_rx_clk; else { pdata->set_clk_src = omap2_mcbsp_set_clk_src; if (id == 1)
On 12/22/2011 07:31 PM, Peter Ujfalusi wrote:
Hello,
This series will fix the CLKR/FSR signal mux configuration for OMAP4 devices. McBSP4 has 6 pin configuration on McBSP4 port while OMAP2/3 has the same capability on McBSP1 port. The API for mux control will be simplified for the mcbsp users (ASoC).
The series depends on earlier series sent for mcbsp: OMAP4: McBSP: Fix clock reparenting
I think the ASoC patch can go via linux-omap, since we do not have other changes for McBSP coming via sound tree.
Looks ok to me and you can have my ack if you plan to resend this after clock reparenting fix set. (Note small typo in 2/5 subject)
Acked-by: Jarkko Nikula jarkko.nikula@bitmer.com
participants (3)
-
Jarkko Nikula -
Mark Brown -
Peter Ujfalusi