G'day,

The rt5631 has a single serial data port shared by playback and capture at the same time, using I2S.

Sometimes on playback or capture the channels are swapped left for right. The swap starts as a stream starts. The swap continues until the stream stops.

The SoC is an Armada 610 with an SSPA peripheral.

A workaround is to remove a clock domain reset when a stream is started. This is a reset bit in a register of the SSPA.

My theory is that the clock domain reset in the SSPA while I2S is clocking interferes with LRCK (aka fsync) edge detection.

I'm wondering how this kind of problem should be solved properly; avoiding the clock domain reset while I2S is clocking seems right, but which codec and SoC driver ops should start I2S and/or reset the host port?

My post is probably incomplete and inadequate; please ask any questions. ;-)