[alsa-devel] [PATCH v3 00/12] ASoC: Add I2S support for Allwinner H3 SoCs
From: Marcus Cooper codekipper@gmail.com
Hi All, please find attached a series of patches to bring i2s support to the Allwinner H3 SoC. This has been tested with the following setups:
A20 Olimex EVB connected to a pcm5102 Orange Pi 2 connected to a uda1380 Orange Pi 2 hdmi audio playback Pine 64 connected to the audio DAC board
To get i2s working some additional patches are required which will be delivered later. For now they have been pushed here
https://github.com/codekipper/linux-sunxi/commits/sunxi-audio-h3
I don't own a A33 device which uses the i2s block for the audio codec so if someone could test against that it would be much appreciated.
I'm also wondering if there is a preferred way of setting the lrclk size in the dts?..currently it is set to the sample width but for example the pcm5102a wants it to be 32 bits whatever the sample rate.
Thanks in advance, CK
---
v3 changes compared to v2 are: - initial changes to prepare driver for newer SoCs has been broken down into smaller patches - reduce use of regmap fields to where just needed. - clkdiv expansion will be delivered later. - defines for H3 variant segregated. - fixed regmap config issue with SUN8I_I2S_FIFO_TX_REG.
v2 changes compared to v1 are: - massive refactoring to remove duplicate code making use of regmap_fields. - extending the clock divisors. - removed code that should be delivered when we support 20/24bits
---
Marcus Cooper (12): ASoC: sun4i-i2s: Extend quirks scope ASoC: sun4i-i2s: Add clkdiv offsets to quirks ASoC: sun4i-i2s: Add regmap config to quirks ASoC: sun4i-i2s: Add TX FIFO offset to quirks ASoC: sun4i-i2s: Add regmap fields for channels ASoC: sun4i-i2s: Add changes for wss and sr ASoC: sun4i-i2s: bclk and lrclk polarity tidyup ASoC: sun4i-i2s: Add mclk enable regmap field ASoC: sun4i-i2s: Add regmap field to set format ASoC: sun4i-i2s: Check for slave select bit ASoC: sun4i-i2s: Update global enable with bitmask ASoC: sun4i-i2s: Add support for H3
.../devicetree/bindings/sound/sun4i-i2s.txt | 2 + sound/soc/sunxi/sun4i-i2s.c | 460 ++++++++++++++++++--- 2 files changed, 398 insertions(+), 64 deletions(-)
From: Marcus Cooper codekipper@gmail.com
In preparation for the changes required to support newer SoCs then quirks has been moved and also added to the device structure.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 62b307b0c846..d7ee7a443e4e 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -90,6 +90,15 @@ #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
+/** + * struct sun4i_i2s_quirks - Differences between SoC variants. + * + * @has_reset: SoC needs reset deasserted. + */ +struct sun4i_i2s_quirks { + bool has_reset; +}; + struct sun4i_i2s { struct clk *bus_clk; struct clk *mod_clk; @@ -100,6 +109,8 @@ struct sun4i_i2s {
struct snd_dmaengine_dai_dma_data capture_dma_data; struct snd_dmaengine_dai_dma_data playback_dma_data; + + const struct sun4i_i2s_quirks *variant; };
struct sun4i_i2s_clk_div { @@ -654,10 +665,6 @@ static int sun4i_i2s_runtime_suspend(struct device *dev) return 0; }
-struct sun4i_i2s_quirks { - bool has_reset; -}; - static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, }; @@ -669,7 +676,6 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { static int sun4i_i2s_probe(struct platform_device *pdev) { struct sun4i_i2s *i2s; - const struct sun4i_i2s_quirks *quirks; struct resource *res; void __iomem *regs; int irq, ret; @@ -690,8 +696,8 @@ static int sun4i_i2s_probe(struct platform_device *pdev) return irq; }
- quirks = of_device_get_match_data(&pdev->dev); - if (!quirks) { + i2s->variant = of_device_get_match_data(&pdev->dev); + if (!i2s->variant) { dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); return -ENODEV; } @@ -715,7 +721,7 @@ static int sun4i_i2s_probe(struct platform_device *pdev) return PTR_ERR(i2s->mod_clk); }
- if (quirks->has_reset) { + if (i2s->variant->has_reset) { i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(i2s->rst)) { dev_err(&pdev->dev, "Failed to get reset control\n");
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
In preparation for the changes required to support newer SoCs then
typo? ^^^^
quirks has been moved and also added to the device structure.
Signed-off-by: Marcus Cooper codekipper@gmail.com
Otherwise,
Reviewed-by: Chen-Yu Tsai wens@csie.org
The patch
ASoC: sun4i-i2s: Extend quirks scope
has been applied to the asoc tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From 47bea0c836867b6b1cdb714d58f2bfc8e2f5c386 Mon Sep 17 00:00:00 2001
From: Marcus Cooper codekipper@gmail.com Date: Sat, 29 Jul 2017 16:17:42 +0200 Subject: [PATCH] ASoC: sun4i-i2s: Extend quirks scope
In preparation for the changes required to support newer SoCs then quirks has been moved and also added to the device structure.
Signed-off-by: Marcus Cooper codekipper@gmail.com Reviewed-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/sunxi/sun4i-i2s.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 62b307b0c846..d7ee7a443e4e 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -90,6 +90,15 @@ #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
+/** + * struct sun4i_i2s_quirks - Differences between SoC variants. + * + * @has_reset: SoC needs reset deasserted. + */ +struct sun4i_i2s_quirks { + bool has_reset; +}; + struct sun4i_i2s { struct clk *bus_clk; struct clk *mod_clk; @@ -100,6 +109,8 @@ struct sun4i_i2s {
struct snd_dmaengine_dai_dma_data capture_dma_data; struct snd_dmaengine_dai_dma_data playback_dma_data; + + const struct sun4i_i2s_quirks *variant; };
struct sun4i_i2s_clk_div { @@ -654,10 +665,6 @@ static int sun4i_i2s_runtime_suspend(struct device *dev) return 0; }
-struct sun4i_i2s_quirks { - bool has_reset; -}; - static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, }; @@ -669,7 +676,6 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { static int sun4i_i2s_probe(struct platform_device *pdev) { struct sun4i_i2s *i2s; - const struct sun4i_i2s_quirks *quirks; struct resource *res; void __iomem *regs; int irq, ret; @@ -690,8 +696,8 @@ static int sun4i_i2s_probe(struct platform_device *pdev) return irq; }
- quirks = of_device_get_match_data(&pdev->dev); - if (!quirks) { + i2s->variant = of_device_get_match_data(&pdev->dev); + if (!i2s->variant) { dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); return -ENODEV; } @@ -715,7 +721,7 @@ static int sun4i_i2s_probe(struct platform_device *pdev) return PTR_ERR(i2s->mod_clk); }
- if (quirks->has_reset) { + if (i2s->variant->has_reset) { i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(i2s->rst)) { dev_err(&pdev->dev, "Failed to get reset control\n");
From: Marcus Cooper codekipper@gmail.com
The BCLKDIV and MCLKDIV found on newer SoCs start from an offset of 1. Add the functionality to adjust the division values according to the needs to the device being used.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index d7ee7a443e4e..1d538de4e4d0 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -94,9 +94,13 @@ * struct sun4i_i2s_quirks - Differences between SoC variants. * * @has_reset: SoC needs reset deasserted. + * @mclk_offset: Value by which mclkdiv needs to be adjusted. + * @bclk_offset: Value by which bclkdiv needs to be adjusted. */ struct sun4i_i2s_quirks { bool has_reset; + unsigned int mclk_offset; + unsigned int bclk_offset; };
struct sun4i_i2s { @@ -149,7 +153,7 @@ static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
if (bdiv->div == div) - return bdiv->val; + return bdiv->val + i2s->variant->bclk_offset; }
return -EINVAL; @@ -167,7 +171,7 @@ static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
if (mdiv->div == div) - return mdiv->val; + return mdiv->val + i2s->variant->mclk_offset; }
return -EINVAL;
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
The BCLKDIV and MCLKDIV found on newer SoCs start from an offset of 1. Add the functionality to adjust the division values according to the needs to the device being used.
Signed-off-by: Marcus Cooper codekipper@gmail.com
sound/soc/sunxi/sun4i-i2s.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index d7ee7a443e4e..1d538de4e4d0 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -94,9 +94,13 @@
- struct sun4i_i2s_quirks - Differences between SoC variants.
- @has_reset: SoC needs reset deasserted.
- @mclk_offset: Value by which mclkdiv needs to be adjusted.
*/
- @bclk_offset: Value by which bclkdiv needs to be adjusted.
struct sun4i_i2s_quirks { bool has_reset;
unsigned int mclk_offset;unsigned int bclk_offset;};
struct sun4i_i2s { @@ -149,7 +153,7 @@ static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
if (bdiv->div == div)
return bdiv->val;
return bdiv->val + i2s->variant->bclk_offset;
The offset should best be applied when the value is written to the register, in sun4i_i2s_set_clk_rate(). sun4i_i2s_get_*_div() should do what the name says, that is calculate a divider based on the parameters it is given.
Regards ChenYu
} return -EINVAL;@@ -167,7 +171,7 @@ static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
if (mdiv->div == div)
return mdiv->val;
return mdiv->val + i2s->variant->mclk_offset; } return -EINVAL;-- 2.13.3
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On 1 August 2017 at 04:55, Chen-Yu Tsai wens@csie.org wrote:
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
The BCLKDIV and MCLKDIV found on newer SoCs start from an offset of 1. Add the functionality to adjust the division values according to the needs to the device being used.
Signed-off-by: Marcus Cooper codekipper@gmail.com
sound/soc/sunxi/sun4i-i2s.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index d7ee7a443e4e..1d538de4e4d0 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -94,9 +94,13 @@
- struct sun4i_i2s_quirks - Differences between SoC variants.
- @has_reset: SoC needs reset deasserted.
- @mclk_offset: Value by which mclkdiv needs to be adjusted.
*/
- @bclk_offset: Value by which bclkdiv needs to be adjusted.
struct sun4i_i2s_quirks { bool has_reset;
unsigned int mclk_offset;unsigned int bclk_offset;};
struct sun4i_i2s { @@ -149,7 +153,7 @@ static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
if (bdiv->div == div)
return bdiv->val;
return bdiv->val + i2s->variant->bclk_offset;The offset should best be applied when the value is written to the register, in sun4i_i2s_set_clk_rate(). sun4i_i2s_get_*_div() should do what the name says, that is calculate a divider based on the parameters it is given.
ACK, Thanks for the review, CK
Regards ChenYu
} return -EINVAL;@@ -167,7 +171,7 @@ static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
if (mdiv->div == div)
return mdiv->val;
return mdiv->val + i2s->variant->mclk_offset; } return -EINVAL;-- 2.13.3
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From: Marcus Cooper codekipper@gmail.com
The newer SoCs have a larger range than the original SoC that this driver was developed for. By adding the regmap config to the quirks then the driver can initialise the managed register map correctly.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 1d538de4e4d0..73e991f5a81e 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -94,11 +94,13 @@ * struct sun4i_i2s_quirks - Differences between SoC variants. * * @has_reset: SoC needs reset deasserted. + * @sun4i_i2s_regmap: regmap config to use. * @mclk_offset: Value by which mclkdiv needs to be adjusted. * @bclk_offset: Value by which bclkdiv needs to be adjusted. */ struct sun4i_i2s_quirks { bool has_reset; + const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset; unsigned int bclk_offset; }; @@ -670,11 +672,13 @@ static int sun4i_i2s_runtime_suspend(struct device *dev) }
static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { - .has_reset = false, + .has_reset = false, + .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, };
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { - .has_reset = true, + .has_reset = true, + .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, };
static int sun4i_i2s_probe(struct platform_device *pdev) @@ -713,7 +717,7 @@ static int sun4i_i2s_probe(struct platform_device *pdev) }
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, - &sun4i_i2s_regmap_config); + i2s->variant->sun4i_i2s_regmap); if (IS_ERR(i2s->regmap)) { dev_err(&pdev->dev, "Regmap initialisation failed\n"); return PTR_ERR(i2s->regmap);
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
The newer SoCs have a larger range than the original SoC that this driver was developed for. By adding the regmap config to the quirks then the driver can initialise the managed register map correctly.
Signed-off-by: Marcus Cooper codekipper@gmail.com
Reviewed-by: Chen-Yu Tsai wens@csie.org
From: Marcus Cooper codekipper@gmail.com
It has been seen that the newer SoCs have a different TX FIFO address. Add this to the quirks structure.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 73e991f5a81e..2a25df22c2f8 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -94,12 +94,14 @@ * struct sun4i_i2s_quirks - Differences between SoC variants. * * @has_reset: SoC needs reset deasserted. + * @reg_offset_txdata: offset of the tx fifo. * @sun4i_i2s_regmap: regmap config to use. * @mclk_offset: Value by which mclkdiv needs to be adjusted. * @bclk_offset: Value by which bclkdiv needs to be adjusted. */ struct sun4i_i2s_quirks { bool has_reset; + unsigned int reg_offset_txdata; /* TX FIFO */ const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset; unsigned int bclk_offset; @@ -673,11 +675,13 @@ static int sun4i_i2s_runtime_suspend(struct device *dev)
static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, + .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, };
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .has_reset = true, + .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, };
@@ -746,7 +750,8 @@ static int sun4i_i2s_probe(struct platform_device *pdev) } }
- i2s->playback_dma_data.addr = res->start + SUN4I_I2S_FIFO_TX_REG; + i2s->playback_dma_data.addr = res->start + + i2s->variant->reg_offset_txdata; i2s->playback_dma_data.maxburst = 8;
i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
It has been seen that the newer SoCs have a different TX FIFO address. Add this to the quirks structure.
Signed-off-by: Marcus Cooper codekipper@gmail.com
Reviewed-by: Chen-Yu Tsai wens@csie.org
From: Marcus Cooper codekipper@gmail.com
On the original i2s block the channel mapping and selection were configured for stereo audio by default: This is not the case with the newer SoCs and they are also located at different offsets.
To support the newer SoC then regmap fields have been added to the quirks and these are initialised to their correct settings during probing.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 80 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 72 insertions(+), 8 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 2a25df22c2f8..120f797a38e8 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -82,7 +82,7 @@ #define SUN4I_I2S_TX_CNT_REG 0x2c
#define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 -#define SUN4I_I2S_TX_CHAN_SEL(num_chan) (((num_chan) - 1) << 0) +#define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
#define SUN4I_I2S_TX_CHAN_MAP_REG 0x34 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2)) @@ -98,6 +98,10 @@ * @sun4i_i2s_regmap: regmap config to use. * @mclk_offset: Value by which mclkdiv needs to be adjusted. * @bclk_offset: Value by which bclkdiv needs to be adjusted. + * @field_txchanmap: location of the tx channel mapping register. + * @field_rxchanmap: location of the rx channel mapping register. + * @field_txchansel: location of the tx channel select bit fields. + * @field_rxchansel: location of the rx channel select bit fields. */ struct sun4i_i2s_quirks { bool has_reset; @@ -105,6 +109,12 @@ struct sun4i_i2s_quirks { const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset; unsigned int bclk_offset; + + /* Register fields for i2s */ + struct reg_field field_txchanmap; + struct reg_field field_rxchanmap; + struct reg_field field_txchansel; + struct reg_field field_rxchansel; };
struct sun4i_i2s { @@ -118,6 +128,12 @@ struct sun4i_i2s { struct snd_dmaengine_dai_dma_data capture_dma_data; struct snd_dmaengine_dai_dma_data playback_dma_data;
+ /* Register fields for i2s */ + struct regmap_field *field_txchanmap; + struct regmap_field *field_rxchanmap; + struct regmap_field *field_txchansel; + struct regmap_field *field_rxchansel; + const struct sun4i_i2s_quirks *variant; };
@@ -264,6 +280,18 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, if (params_channels(params) != 2) return -EINVAL;
+ /* Map the channels for playback and capture */ + regmap_field_write(i2s->field_txchanmap, 0x76543210); + regmap_field_write(i2s->field_rxchanmap, 0x00003210); + + /* Configure the channels */ + regmap_field_write(i2s->field_txchansel, + SUN4I_I2S_CHAN_SEL(params_channels(params))); + + regmap_field_write(i2s->field_rxchansel, + SUN4I_I2S_CHAN_SEL(params_channels(params))); + + switch (params_physical_width(params)) { case 16: width = DMA_SLAVE_BUSWIDTH_2_BYTES; @@ -486,13 +514,6 @@ static int sun4i_i2s_startup(struct snd_pcm_substream *substream, SUN4I_I2S_CTRL_SDO_EN_MASK, SUN4I_I2S_CTRL_SDO_EN(0));
- /* Enable the first two channels */ - regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG, - SUN4I_I2S_TX_CHAN_SEL(2)); - - /* Map them to the two first samples coming in */ - regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, - SUN4I_I2S_TX_CHAN_MAP(0, 0) | SUN4I_I2S_TX_CHAN_MAP(1, 1));
return clk_prepare_enable(i2s->mod_clk); } @@ -677,14 +698,51 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), + .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), };
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .has_reset = true, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), + .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), };
+static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2s) +{ + i2s->field_txchanmap = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_txchanmap); + if (IS_ERR(i2s->field_txchanmap)) + return PTR_ERR(i2s->field_txchanmap); + + i2s->field_rxchanmap = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_rxchanmap); + if (IS_ERR(i2s->field_rxchanmap)) + return PTR_ERR(i2s->field_rxchanmap); + + i2s->field_txchansel = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_txchansel); + if (IS_ERR(i2s->field_txchansel)) + return PTR_ERR(i2s->field_txchansel); + + i2s->field_rxchansel = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_rxchansel); + if (IS_ERR(i2s->field_rxchansel)) + return PTR_ERR(i2s->field_rxchansel); + + return 0; +} + static int sun4i_i2s_probe(struct platform_device *pdev) { struct sun4i_i2s *i2s; @@ -778,6 +836,12 @@ static int sun4i_i2s_probe(struct platform_device *pdev) goto err_suspend; }
+ ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); + if (ret) { + dev_err(&pdev->dev, "Could not initialise regmap fields\n"); + goto err_suspend; + } + return 0;
err_suspend:
Hi Marcus,
[auto build test WARNING on asoc/for-next] [also build test WARNING on next-20170728] [cannot apply to v4.13-rc2] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/codekipper-gmail-com/ASoC-Add-I2S-s... base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
coccinelle warnings: (new ones prefixed by >>)
sound/soc/sunxi/sun4i-i2s.c:740:1-3: WARNING: PTR_ERR_OR_ZERO can be used
Please review and possibly fold the followup patch.
--- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
sound/soc/sunxi/sun4i-i2s.c:740:1-3: WARNING: PTR_ERR_OR_ZERO can be used
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
Fixes: 298207690de9 ("ASoC: sun4i-i2s: Add regmap fields for channels") CC: Marcus Cooper codekipper@gmail.com Signed-off-by: Fengguang Wu fengguang.wu@intel.com ---
sun4i-i2s.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
--- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -737,10 +737,7 @@ static int sun4i_i2s_init_regmap_fields( i2s->field_rxchansel = devm_regmap_field_alloc(dev, i2s->regmap, i2s->variant->field_rxchansel); - if (IS_ERR(i2s->field_rxchansel)) - return PTR_ERR(i2s->field_rxchansel); - - return 0; + return PTR_ERR_OR_ZERO(i2s->field_rxchansel); }
static int sun4i_i2s_probe(struct platform_device *pdev)
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
On the original i2s block the channel mapping and selection were configured for stereo audio by default: This is not the case with the newer SoCs and they are also located at different offsets.
To support the newer SoC then regmap fields have been added to the quirks and these are initialised to their correct settings during probing.
Signed-off-by: Marcus Cooper codekipper@gmail.com
sound/soc/sunxi/sun4i-i2s.c | 80 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 72 insertions(+), 8 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 2a25df22c2f8..120f797a38e8 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -82,7 +82,7 @@ #define SUN4I_I2S_TX_CNT_REG 0x2c
#define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 -#define SUN4I_I2S_TX_CHAN_SEL(num_chan) (((num_chan) - 1) << 0) +#define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
#define SUN4I_I2S_TX_CHAN_MAP_REG 0x34 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2)) @@ -98,6 +98,10 @@
- @sun4i_i2s_regmap: regmap config to use.
- @mclk_offset: Value by which mclkdiv needs to be adjusted.
- @bclk_offset: Value by which bclkdiv needs to be adjusted.
- @field_txchanmap: location of the tx channel mapping register.
- @field_rxchanmap: location of the rx channel mapping register.
- @field_txchansel: location of the tx channel select bit fields.
*/
- @field_rxchansel: location of the rx channel select bit fields.
struct sun4i_i2s_quirks { bool has_reset; @@ -105,6 +109,12 @@ struct sun4i_i2s_quirks { const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset; unsigned int bclk_offset;
/* Register fields for i2s */struct reg_field field_txchanmap;struct reg_field field_rxchanmap;struct reg_field field_txchansel;struct reg_field field_rxchansel;};
struct sun4i_i2s { @@ -118,6 +128,12 @@ struct sun4i_i2s { struct snd_dmaengine_dai_dma_data capture_dma_data; struct snd_dmaengine_dai_dma_data playback_dma_data;
/* Register fields for i2s */struct regmap_field *field_txchanmap;struct regmap_field *field_rxchanmap;struct regmap_field *field_txchansel;struct regmap_field *field_rxchansel;const struct sun4i_i2s_quirks *variant;};
@@ -264,6 +280,18 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, if (params_channels(params) != 2) return -EINVAL;
/* Map the channels for playback and capture */regmap_field_write(i2s->field_txchanmap, 0x76543210);regmap_field_write(i2s->field_rxchanmap, 0x00003210);/* Configure the channels */regmap_field_write(i2s->field_txchansel,SUN4I_I2S_CHAN_SEL(params_channels(params)));regmap_field_write(i2s->field_rxchansel,SUN4I_I2S_CHAN_SEL(params_channels(params)));
Checkpatch says don't use multiple blank lines.
switch (params_physical_width(params)) { case 16: width = DMA_SLAVE_BUSWIDTH_2_BYTES;@@ -486,13 +514,6 @@ static int sun4i_i2s_startup(struct snd_pcm_substream *substream, SUN4I_I2S_CTRL_SDO_EN_MASK, SUN4I_I2S_CTRL_SDO_EN(0));
/* Enable the first two channels */regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG,SUN4I_I2S_TX_CHAN_SEL(2));/* Map them to the two first samples coming in */regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG,SUN4I_I2S_TX_CHAN_MAP(0, 0) | SUN4I_I2S_TX_CHAN_MAP(1, 1)); return clk_prepare_enable(i2s->mod_clk);} @@ -677,14 +698,51 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),};
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .has_reset = true, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),};
+static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2s)
This line is over 80 characters. Please wrap the line.
+{
i2s->field_txchanmap =devm_regmap_field_alloc(dev, i2s->regmap,i2s->variant->field_txchanmap);if (IS_ERR(i2s->field_txchanmap))return PTR_ERR(i2s->field_txchanmap);i2s->field_rxchanmap =devm_regmap_field_alloc(dev, i2s->regmap,i2s->variant->field_rxchanmap);if (IS_ERR(i2s->field_rxchanmap))return PTR_ERR(i2s->field_rxchanmap);i2s->field_txchansel =devm_regmap_field_alloc(dev, i2s->regmap,i2s->variant->field_txchansel);if (IS_ERR(i2s->field_txchansel))return PTR_ERR(i2s->field_txchansel);i2s->field_rxchansel =devm_regmap_field_alloc(dev, i2s->regmap,i2s->variant->field_rxchansel);if (IS_ERR(i2s->field_rxchansel))return PTR_ERR(i2s->field_rxchansel);return 0;
This seems to be the last "if (IS_ERR()) return PTR_ERR()" sequence. So it looks like you could apply the PTR_ERR_OR_ZERO hunk from the kbuild test robot. I wasn't aware of this preference before, and to be honest I'm fine either way.
Otherwise,
Reviewed-by: Chen-Yu Tsai wens@csie.org
+}
static int sun4i_i2s_probe(struct platform_device *pdev) { struct sun4i_i2s *i2s; @@ -778,6 +836,12 @@ static int sun4i_i2s_probe(struct platform_device *pdev) goto err_suspend; }
ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);if (ret) {dev_err(&pdev->dev, "Could not initialise regmap fields\n");goto err_suspend;}return 0;err_suspend:
2.13.3
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On 1 August 2017 at 10:31, Chen-Yu Tsai wens@csie.org wrote:
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
On the original i2s block the channel mapping and selection were configured for stereo audio by default: This is not the case with the newer SoCs and they are also located at different offsets.
To support the newer SoC then regmap fields have been added to the quirks and these are initialised to their correct settings during probing.
Signed-off-by: Marcus Cooper codekipper@gmail.com
sound/soc/sunxi/sun4i-i2s.c | 80 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 72 insertions(+), 8 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 2a25df22c2f8..120f797a38e8 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -82,7 +82,7 @@ #define SUN4I_I2S_TX_CNT_REG 0x2c
#define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 -#define SUN4I_I2S_TX_CHAN_SEL(num_chan) (((num_chan) - 1) << 0) +#define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
#define SUN4I_I2S_TX_CHAN_MAP_REG 0x34 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2)) @@ -98,6 +98,10 @@
- @sun4i_i2s_regmap: regmap config to use.
- @mclk_offset: Value by which mclkdiv needs to be adjusted.
- @bclk_offset: Value by which bclkdiv needs to be adjusted.
- @field_txchanmap: location of the tx channel mapping register.
- @field_rxchanmap: location of the rx channel mapping register.
- @field_txchansel: location of the tx channel select bit fields.
*/
- @field_rxchansel: location of the rx channel select bit fields.
struct sun4i_i2s_quirks { bool has_reset; @@ -105,6 +109,12 @@ struct sun4i_i2s_quirks { const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset; unsigned int bclk_offset;
/* Register fields for i2s */struct reg_field field_txchanmap;struct reg_field field_rxchanmap;struct reg_field field_txchansel;struct reg_field field_rxchansel;};
struct sun4i_i2s { @@ -118,6 +128,12 @@ struct sun4i_i2s { struct snd_dmaengine_dai_dma_data capture_dma_data; struct snd_dmaengine_dai_dma_data playback_dma_data;
/* Register fields for i2s */struct regmap_field *field_txchanmap;struct regmap_field *field_rxchanmap;struct regmap_field *field_txchansel;struct regmap_field *field_rxchansel;const struct sun4i_i2s_quirks *variant;};
@@ -264,6 +280,18 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, if (params_channels(params) != 2) return -EINVAL;
/* Map the channels for playback and capture */regmap_field_write(i2s->field_txchanmap, 0x76543210);regmap_field_write(i2s->field_rxchanmap, 0x00003210);/* Configure the channels */regmap_field_write(i2s->field_txchansel,SUN4I_I2S_CHAN_SEL(params_channels(params)));regmap_field_write(i2s->field_rxchansel,SUN4I_I2S_CHAN_SEL(params_channels(params)));Checkpatch says don't use multiple blank lines.
switch (params_physical_width(params)) { case 16: width = DMA_SLAVE_BUSWIDTH_2_BYTES;@@ -486,13 +514,6 @@ static int sun4i_i2s_startup(struct snd_pcm_substream *substream, SUN4I_I2S_CTRL_SDO_EN_MASK, SUN4I_I2S_CTRL_SDO_EN(0));
/* Enable the first two channels */regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG,SUN4I_I2S_TX_CHAN_SEL(2));/* Map them to the two first samples coming in */regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG,SUN4I_I2S_TX_CHAN_MAP(0, 0) | SUN4I_I2S_TX_CHAN_MAP(1, 1)); return clk_prepare_enable(i2s->mod_clk);} @@ -677,14 +698,51 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),};
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .has_reset = true, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),};
+static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2s)
This line is over 80 characters. Please wrap the line.
+{
i2s->field_txchanmap =devm_regmap_field_alloc(dev, i2s->regmap,i2s->variant->field_txchanmap);if (IS_ERR(i2s->field_txchanmap))return PTR_ERR(i2s->field_txchanmap);i2s->field_rxchanmap =devm_regmap_field_alloc(dev, i2s->regmap,i2s->variant->field_rxchanmap);if (IS_ERR(i2s->field_rxchanmap))return PTR_ERR(i2s->field_rxchanmap);i2s->field_txchansel =devm_regmap_field_alloc(dev, i2s->regmap,i2s->variant->field_txchansel);if (IS_ERR(i2s->field_txchansel))return PTR_ERR(i2s->field_txchansel);i2s->field_rxchansel =devm_regmap_field_alloc(dev, i2s->regmap,i2s->variant->field_rxchansel);if (IS_ERR(i2s->field_rxchansel))return PTR_ERR(i2s->field_rxchansel);return 0;This seems to be the last "if (IS_ERR()) return PTR_ERR()" sequence. So it looks like you could apply the PTR_ERR_OR_ZERO hunk from the kbuild test robot. I wasn't aware of this preference before, and to be honest I'm fine either way.
ACK, BR, CK
Otherwise,
Reviewed-by: Chen-Yu Tsai wens@csie.org
+}
static int sun4i_i2s_probe(struct platform_device *pdev) { struct sun4i_i2s *i2s; @@ -778,6 +836,12 @@ static int sun4i_i2s_probe(struct platform_device *pdev) goto err_suspend; }
ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);if (ret) {dev_err(&pdev->dev, "Could not initialise regmap fields\n");goto err_suspend;}return 0;err_suspend:
2.13.3
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From: Marcus Cooper codekipper@gmail.com
On newer SoCs the location of the slot width select and sample resolution are different and also there is a bigger range of support.
For the current supported rates then an offset is required.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 120f797a38e8..171df99a267e 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -98,6 +98,9 @@ * @sun4i_i2s_regmap: regmap config to use. * @mclk_offset: Value by which mclkdiv needs to be adjusted. * @bclk_offset: Value by which bclkdiv needs to be adjusted. + * @fmt_offset: Value by which wss and sr needs to be adjusted. + * @field_fmt_set_wss: regmap field to set word select size. + * @field_fmt_set_sr: regmap field to set sample resolution. * @field_txchanmap: location of the tx channel mapping register. * @field_rxchanmap: location of the rx channel mapping register. * @field_txchansel: location of the tx channel select bit fields. @@ -109,8 +112,11 @@ struct sun4i_i2s_quirks { const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset; unsigned int bclk_offset; + unsigned int fmt_offset;
/* Register fields for i2s */ + struct reg_field field_fmt_set_wss; + struct reg_field field_fmt_set_sr; struct reg_field field_txchanmap; struct reg_field field_rxchanmap; struct reg_field field_txchansel; @@ -129,6 +135,8 @@ struct sun4i_i2s { struct snd_dmaengine_dai_dma_data playback_dma_data;
/* Register fields for i2s */ + struct regmap_field *field_fmt_set_wss; + struct regmap_field *field_fmt_set_sr; struct regmap_field *field_txchanmap; struct regmap_field *field_rxchanmap; struct regmap_field *field_txchansel; @@ -311,9 +319,10 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, return -EINVAL; }
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, - SUN4I_I2S_FMT0_WSS_MASK | SUN4I_I2S_FMT0_SR_MASK, - SUN4I_I2S_FMT0_WSS(wss) | SUN4I_I2S_FMT0_SR(sr)); + regmap_field_write(i2s->field_fmt_set_wss, + wss + i2s->variant->fmt_offset); + regmap_field_write(i2s->field_fmt_set_sr, + sr + i2s->variant->fmt_offset);
return sun4i_i2s_set_clk_rate(i2s, params_rate(params), params_width(params)); @@ -698,6 +707,8 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), + .field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), @@ -708,6 +719,8 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .has_reset = true, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), + .field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), @@ -716,6 +729,18 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2s) { + i2s->field_fmt_set_wss = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_fmt_set_wss); + if (IS_ERR(i2s->field_fmt_set_wss)) + return PTR_ERR(i2s->field_fmt_set_wss); + + i2s->field_fmt_set_sr = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_fmt_set_sr); + if (IS_ERR(i2s->field_fmt_set_sr)) + return PTR_ERR(i2s->field_fmt_set_sr); + i2s->field_txchanmap = devm_regmap_field_alloc(dev, i2s->regmap, i2s->variant->field_txchanmap);
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
On newer SoCs the location of the slot width select and sample resolution are different and also there is a bigger range of support.
There is enough space to not use acronyms in the commit subject line.
ASoC: sun4i-i2s: Add regfields for word size select and sample resolution
would be much clearer.
For the current supported rates then an offset is required.
Signed-off-by: Marcus Cooper codekipper@gmail.com
Otherwise,
Reviewed-by: Chen-Yu Tsai wens@csie.org
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
On newer SoCs the location of the slot width select and sample resolution are different and also there is a bigger range of support.
For the current supported rates then an offset is required.
Signed-off-by: Marcus Cooper codekipper@gmail.com
sound/soc/sunxi/sun4i-i2s.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 120f797a38e8..171df99a267e 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -98,6 +98,9 @@
- @sun4i_i2s_regmap: regmap config to use.
- @mclk_offset: Value by which mclkdiv needs to be adjusted.
- @bclk_offset: Value by which bclkdiv needs to be adjusted.
- @fmt_offset: Value by which wss and sr needs to be adjusted.
- @field_fmt_set_wss: regmap field to set word select size.
- @field_fmt_set_sr: regmap field to set sample resolution.
One more thing. Is "_set_" necessary? "field_fmt_wss" seems fine and makes plenty of sense to me.
ChenYu
From: Marcus Cooper codekipper@gmail.com
On newer SoCs the bit fields for the blck and lrclk polarity are in a different locations. Use regmap fields to set the polarity bits as intended.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 45 ++++++++++++++++++++++++++++++++------------- 1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 171df99a267e..90daa974bd27 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -50,6 +50,8 @@ #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0) #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0) #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) +#define SUN4I_I2S_FMT0_POLARITY_INVERTED (1) +#define SUN4I_I2S_FMT0_POLARITY_NORMAL (0)
#define SUN4I_I2S_FMT1_REG 0x08 #define SUN4I_I2S_FIFO_TX_REG 0x0c @@ -101,6 +103,8 @@ * @fmt_offset: Value by which wss and sr needs to be adjusted. * @field_fmt_set_wss: regmap field to set word select size. * @field_fmt_set_sr: regmap field to set sample resolution. + * @field_fmt_set_bclk_polarity: regmap field to set clk polarity. + * @field_fmt_set_lrclk_polarity: regmap field to set frame polarity. * @field_txchanmap: location of the tx channel mapping register. * @field_rxchanmap: location of the rx channel mapping register. * @field_txchansel: location of the tx channel select bit fields. @@ -117,6 +121,8 @@ struct sun4i_i2s_quirks { /* Register fields for i2s */ struct reg_field field_fmt_set_wss; struct reg_field field_fmt_set_sr; + struct reg_field field_fmt_set_bclk_polarity; + struct reg_field field_fmt_set_lrclk_polarity; struct reg_field field_txchanmap; struct reg_field field_rxchanmap; struct reg_field field_txchansel; @@ -137,6 +143,8 @@ struct sun4i_i2s { /* Register fields for i2s */ struct regmap_field *field_fmt_set_wss; struct regmap_field *field_fmt_set_sr; + struct regmap_field *field_fmt_set_bclk_polarity; + struct regmap_field *field_fmt_set_lrclk_polarity; struct regmap_field *field_txchanmap; struct regmap_field *field_rxchanmap; struct regmap_field *field_txchansel; @@ -332,6 +340,8 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); u32 val; + u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; + u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
/* DAI Mode */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -356,32 +366,25 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_IB_IF: /* Invert both clocks */ - val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED | - SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED; + bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; + lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; break; case SND_SOC_DAIFMT_IB_NF: /* Invert bit clock */ - val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED | - SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL; + bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; break; case SND_SOC_DAIFMT_NB_IF: /* Invert frame clock */ - val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED | - SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL; + lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED; break; case SND_SOC_DAIFMT_NB_NF: - /* Nothing to do for both normal cases */ - val = SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL | - SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL; break; default: return -EINVAL; }
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, - SUN4I_I2S_FMT0_BCLK_POLARITY_MASK | - SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK, - val); + regmap_field_write(i2s->field_fmt_set_bclk_polarity, bclk_polarity); + regmap_field_write(i2s->field_fmt_set_lrclk_polarity, lrclk_polarity);
/* DAI clock master masks */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { @@ -709,6 +712,8 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, .field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), .field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), + .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), + .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), @@ -721,6 +726,8 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, .field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), .field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), + .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), + .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), @@ -741,6 +748,18 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2 if (IS_ERR(i2s->field_fmt_set_sr)) return PTR_ERR(i2s->field_fmt_set_sr);
+ i2s->field_fmt_set_bclk_polarity = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_fmt_set_bclk_polarity); + if (IS_ERR(i2s->field_fmt_set_bclk_polarity)) + return PTR_ERR(i2s->field_fmt_set_bclk_polarity); + + i2s->field_fmt_set_lrclk_polarity = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_fmt_set_lrclk_polarity); + if (IS_ERR(i2s->field_fmt_set_lrclk_polarity)) + return PTR_ERR(i2s->field_fmt_set_lrclk_polarity); + i2s->field_txchanmap = devm_regmap_field_alloc(dev, i2s->regmap, i2s->variant->field_txchanmap);
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
On newer SoCs the bit fields for the blck and lrclk polarity are in a different locations. Use regmap fields to set the polarity bits as intended.
Signed-off-by: Marcus Cooper codekipper@gmail.com
sound/soc/sunxi/sun4i-i2s.c | 45 ++++++++++++++++++++++++++++++++------------- 1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 171df99a267e..90daa974bd27 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -50,6 +50,8 @@ #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0) #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0) #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) +#define SUN4I_I2S_FMT0_POLARITY_INVERTED (1) +#define SUN4I_I2S_FMT0_POLARITY_NORMAL (0)
#define SUN4I_I2S_FMT1_REG 0x08 #define SUN4I_I2S_FIFO_TX_REG 0x0c @@ -101,6 +103,8 @@
- @fmt_offset: Value by which wss and sr needs to be adjusted.
- @field_fmt_set_wss: regmap field to set word select size.
- @field_fmt_set_sr: regmap field to set sample resolution.
- @field_fmt_set_bclk_polarity: regmap field to set clk polarity.
- @field_fmt_set_lrclk_polarity: regmap field to set frame polarity.
You can cut these down to "field_fmt_{b,lr}clk_pol". It still makes sense in this context, and you can make the lines fit under 80 characters in the last hunk.
ChenYu
From: Marcus Cooper codekipper@gmail.com
The location of the mclk output enable bit is different on newer SoCs. Use a regmap field to enable it.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 90daa974bd27..6d8d2c4a675b 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -74,7 +74,7 @@ #define SUN4I_I2S_INT_STA_REG 0x20
#define SUN4I_I2S_CLK_DIV_REG 0x24 -#define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7) +#define SUN4I_I2S_CLK_DIV_MCLK_EN 7 #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4) #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4) #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0) @@ -101,6 +101,7 @@ * @mclk_offset: Value by which mclkdiv needs to be adjusted. * @bclk_offset: Value by which bclkdiv needs to be adjusted. * @fmt_offset: Value by which wss and sr needs to be adjusted. + * @field_clkdiv_mclk_en: regmap field to enable mclk output. * @field_fmt_set_wss: regmap field to set word select size. * @field_fmt_set_sr: regmap field to set sample resolution. * @field_fmt_set_bclk_polarity: regmap field to set clk polarity. @@ -119,6 +120,7 @@ struct sun4i_i2s_quirks { unsigned int fmt_offset;
/* Register fields for i2s */ + struct reg_field field_clkdiv_mclk_en; struct reg_field field_fmt_set_wss; struct reg_field field_fmt_set_sr; struct reg_field field_fmt_set_bclk_polarity; @@ -141,6 +143,7 @@ struct sun4i_i2s { struct snd_dmaengine_dai_dma_data playback_dma_data;
/* Register fields for i2s */ + struct regmap_field *field_clkdiv_mclk_en; struct regmap_field *field_fmt_set_wss; struct regmap_field *field_fmt_set_sr; struct regmap_field *field_fmt_set_bclk_polarity; @@ -279,8 +282,9 @@ static int sun4i_i2s_set_clk_rate(struct sun4i_i2s *i2s,
regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, SUN4I_I2S_CLK_DIV_BCLK(bclk_div) | - SUN4I_I2S_CLK_DIV_MCLK(mclk_div) | - SUN4I_I2S_CLK_DIV_MCLK_EN); + SUN4I_I2S_CLK_DIV_MCLK(mclk_div)); + + regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
return 0; } @@ -710,6 +714,9 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, + SUN4I_I2S_CLK_DIV_MCLK_EN, + SUN4I_I2S_CLK_DIV_MCLK_EN), .field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), .field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), @@ -724,6 +731,9 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .has_reset = true, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, + SUN4I_I2S_CLK_DIV_MCLK_EN, + SUN4I_I2S_CLK_DIV_MCLK_EN), .field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), .field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), @@ -760,6 +770,12 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2 if (IS_ERR(i2s->field_fmt_set_lrclk_polarity)) return PTR_ERR(i2s->field_fmt_set_lrclk_polarity);
+ i2s->field_clkdiv_mclk_en = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_clkdiv_mclk_en); + if (IS_ERR(i2s->field_clkdiv_mclk_en)) + return PTR_ERR(i2s->field_clkdiv_mclk_en); + i2s->field_txchanmap = devm_regmap_field_alloc(dev, i2s->regmap, i2s->variant->field_txchanmap);
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
The location of the mclk output enable bit is different on newer SoCs. Use a regmap field to enable it.
Signed-off-by: Marcus Cooper codekipper@gmail.com
sound/soc/sunxi/sun4i-i2s.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 90daa974bd27..6d8d2c4a675b 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -74,7 +74,7 @@ #define SUN4I_I2S_INT_STA_REG 0x20
#define SUN4I_I2S_CLK_DIV_REG 0x24 -#define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7) +#define SUN4I_I2S_CLK_DIV_MCLK_EN 7 #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4) #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4) #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0) @@ -101,6 +101,7 @@
- @mclk_offset: Value by which mclkdiv needs to be adjusted.
- @bclk_offset: Value by which bclkdiv needs to be adjusted.
- @fmt_offset: Value by which wss and sr needs to be adjusted.
- @field_clkdiv_mclk_en: regmap field to enable mclk output.
- @field_fmt_set_wss: regmap field to set word select size.
- @field_fmt_set_sr: regmap field to set sample resolution.
- @field_fmt_set_bclk_polarity: regmap field to set clk polarity.
@@ -119,6 +120,7 @@ struct sun4i_i2s_quirks { unsigned int fmt_offset;
/* Register fields for i2s */
struct reg_field field_clkdiv_mclk_en; struct reg_field field_fmt_set_wss; struct reg_field field_fmt_set_sr; struct reg_field field_fmt_set_bclk_polarity;@@ -141,6 +143,7 @@ struct sun4i_i2s { struct snd_dmaengine_dai_dma_data playback_dma_data;
/* Register fields for i2s */
struct regmap_field *field_clkdiv_mclk_en; struct regmap_field *field_fmt_set_wss; struct regmap_field *field_fmt_set_sr; struct regmap_field *field_fmt_set_bclk_polarity;@@ -279,8 +282,9 @@ static int sun4i_i2s_set_clk_rate(struct sun4i_i2s *i2s,
regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
SUN4I_I2S_CLK_DIV_MCLK(mclk_div) |SUN4I_I2S_CLK_DIV_MCLK_EN);
SUN4I_I2S_CLK_DIV_MCLK(mclk_div));regmap_field_write(i2s->field_clkdiv_mclk_en, 1); return 0;} @@ -710,6 +714,9 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG,SUN4I_I2S_CLK_DIV_MCLK_EN,SUN4I_I2S_CLK_DIV_MCLK_EN),
Nit: just use raw number to match all the other lines. And you won't need to change the macro.
ChenYu
From: Marcus Cooper codekipper@gmail.com
On the newer SoCs the bits to configure the operational mode are located in a different register. Add a regmap field so that this location can be configured.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 6d8d2c4a675b..9e060d1b73d5 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -106,6 +106,7 @@ * @field_fmt_set_sr: regmap field to set sample resolution. * @field_fmt_set_bclk_polarity: regmap field to set clk polarity. * @field_fmt_set_lrclk_polarity: regmap field to set frame polarity. + * @field_fmt_set_mode: regmap field to set the operational mode. * @field_txchanmap: location of the tx channel mapping register. * @field_rxchanmap: location of the rx channel mapping register. * @field_txchansel: location of the tx channel select bit fields. @@ -125,6 +126,7 @@ struct sun4i_i2s_quirks { struct reg_field field_fmt_set_sr; struct reg_field field_fmt_set_bclk_polarity; struct reg_field field_fmt_set_lrclk_polarity; + struct reg_field field_fmt_set_mode; struct reg_field field_txchanmap; struct reg_field field_rxchanmap; struct reg_field field_txchansel; @@ -148,6 +150,7 @@ struct sun4i_i2s { struct regmap_field *field_fmt_set_sr; struct regmap_field *field_fmt_set_bclk_polarity; struct regmap_field *field_fmt_set_lrclk_polarity; + struct regmap_field *field_fmt_set_mode; struct regmap_field *field_txchanmap; struct regmap_field *field_rxchanmap; struct regmap_field *field_txchansel; @@ -362,9 +365,7 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; }
- regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, - SUN4I_I2S_FMT0_FMT_MASK, - val); + regmap_field_write(i2s->field_fmt_set_mode, val);
/* DAI clock polarity */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { @@ -721,6 +722,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), + .field_fmt_set_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), @@ -738,6 +740,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), + .field_fmt_set_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), @@ -770,6 +773,12 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2 if (IS_ERR(i2s->field_fmt_set_lrclk_polarity)) return PTR_ERR(i2s->field_fmt_set_lrclk_polarity);
+ i2s->field_fmt_set_mode = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_fmt_set_mode); + if (IS_ERR(i2s->field_fmt_set_mode)) + return PTR_ERR(i2s->field_fmt_set_mode); + i2s->field_clkdiv_mclk_en = devm_regmap_field_alloc(dev, i2s->regmap, i2s->variant->field_clkdiv_mclk_en);
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
On the newer SoCs the bits to configure the operational mode are
The subject says "format". Which is it? And please be clear what "mode" or "format" this configures. Is it the DAI controller's overall mode (PCM/I2S/Left-Justified/Right-Justified/TDM)? or the PCM mode (linear/u-law/a-law)?
located in a different register. Add a regmap field so that this location can be configured.
Signed-off-by: Marcus Cooper codekipper@gmail.com
sound/soc/sunxi/sun4i-i2s.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 6d8d2c4a675b..9e060d1b73d5 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -106,6 +106,7 @@
- @field_fmt_set_sr: regmap field to set sample resolution.
- @field_fmt_set_bclk_polarity: regmap field to set clk polarity.
- @field_fmt_set_lrclk_polarity: regmap field to set frame polarity.
- @field_fmt_set_mode: regmap field to set the operational mode.
Drop the "_set_" part.
ChenYu
From: Marcus Cooper codekipper@gmail.com
The newer SoCs do not have this setting. Instead they set the pin direction. Add a check to see if the bit is valid and if so set it accordingly.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 9e060d1b73d5..1c4d763e3a8e 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -96,6 +96,7 @@ * struct sun4i_i2s_quirks - Differences between SoC variants. * * @has_reset: SoC needs reset deasserted. + * @has_slave_select_bit: SoC has a bit to enable slave mode. * @reg_offset_txdata: offset of the tx fifo. * @sun4i_i2s_regmap: regmap config to use. * @mclk_offset: Value by which mclkdiv needs to be adjusted. @@ -114,6 +115,7 @@ */ struct sun4i_i2s_quirks { bool has_reset; + bool has_slave_select_bit; unsigned int reg_offset_txdata; /* TX FIFO */ const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset; @@ -391,30 +393,32 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) regmap_field_write(i2s->field_fmt_set_bclk_polarity, bclk_polarity); regmap_field_write(i2s->field_fmt_set_lrclk_polarity, lrclk_polarity);
- /* DAI clock master masks */ - switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { - case SND_SOC_DAIFMT_CBS_CFS: - /* BCLK and LRCLK master */ - val = SUN4I_I2S_CTRL_MODE_MASTER; - break; - case SND_SOC_DAIFMT_CBM_CFM: - /* BCLK and LRCLK slave */ - val = SUN4I_I2S_CTRL_MODE_SLAVE; - break; - default: - return -EINVAL; + if (i2s->variant->has_slave_select_bit) { + /* DAI clock master masks */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + /* BCLK and LRCLK master */ + val = SUN4I_I2S_CTRL_MODE_MASTER; + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* BCLK and LRCLK slave */ + val = SUN4I_I2S_CTRL_MODE_SLAVE; + break; + default: + return -EINVAL; + } + regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, + SUN4I_I2S_CTRL_MODE_MASK, + val); }
- regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, - SUN4I_I2S_CTRL_MODE_MASK, - val); - /* Set significant bits in our FIFOs */ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); + return 0; }
@@ -715,6 +719,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { .has_reset = false, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .has_slave_select_bit = true, .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, SUN4I_I2S_CLK_DIV_MCLK_EN, SUN4I_I2S_CLK_DIV_MCLK_EN), @@ -733,6 +738,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .has_reset = true, .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, + .has_slave_select_bit = true, .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, SUN4I_I2S_CLK_DIV_MCLK_EN, SUN4I_I2S_CLK_DIV_MCLK_EN),
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
The newer SoCs do not have this setting. Instead they set the pin direction. Add a check to see if the bit is valid and if so set it accordingly.
Signed-off-by: Marcus Cooper codekipper@gmail.com
sound/soc/sunxi/sun4i-i2s.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 9e060d1b73d5..1c4d763e3a8e 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -96,6 +96,7 @@
- struct sun4i_i2s_quirks - Differences between SoC variants.
- @has_reset: SoC needs reset deasserted.
- @has_slave_select_bit: SoC has a bit to enable slave mode.
- @reg_offset_txdata: offset of the tx fifo.
- @sun4i_i2s_regmap: regmap config to use.
- @mclk_offset: Value by which mclkdiv needs to be adjusted.
@@ -114,6 +115,7 @@ */ struct sun4i_i2s_quirks { bool has_reset;
bool has_slave_select_bit; unsigned int reg_offset_txdata; /* TX FIFO */ const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset;@@ -391,30 +393,32 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) regmap_field_write(i2s->field_fmt_set_bclk_polarity, bclk_polarity); regmap_field_write(i2s->field_fmt_set_lrclk_polarity, lrclk_polarity);
/* DAI clock master masks */switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {case SND_SOC_DAIFMT_CBS_CFS:/* BCLK and LRCLK master */val = SUN4I_I2S_CTRL_MODE_MASTER;break;case SND_SOC_DAIFMT_CBM_CFM:/* BCLK and LRCLK slave */val = SUN4I_I2S_CTRL_MODE_SLAVE;break;default:return -EINVAL;
if (i2s->variant->has_slave_select_bit) {/* DAI clock master masks */switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {case SND_SOC_DAIFMT_CBS_CFS:/* BCLK and LRCLK master */val = SUN4I_I2S_CTRL_MODE_MASTER;break;case SND_SOC_DAIFMT_CBM_CFM:/* BCLK and LRCLK slave */val = SUN4I_I2S_CTRL_MODE_SLAVE;break;default:return -EINVAL;}regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,SUN4I_I2S_CTRL_MODE_MASK,val); }
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,SUN4I_I2S_CTRL_MODE_MASK,val);/* Set significant bits in our FIFOs */ regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
Stray newline. Otherwise,
Reviewed-by: Chen-Yu Tsai wens@csie.org
From: Marcus Cooper codekipper@gmail.com
The default value of the config register is different on newer SoCs and therefore enabling/disabling with a register write will clear bits used to set the direction of the clock and frame pins.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- sound/soc/sunxi/sun4i-i2s.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 1c4d763e3a8e..d8bcd3d9c2b6 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -527,8 +527,8 @@ static int sun4i_i2s_startup(struct snd_pcm_substream *substream, struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
/* Enable the whole hardware block */ - regmap_write(i2s->regmap, SUN4I_I2S_CTRL_REG, - SUN4I_I2S_CTRL_GL_EN); + regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, + SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
/* Enable the first output line */ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, @@ -551,7 +551,8 @@ static void sun4i_i2s_shutdown(struct snd_pcm_substream *substream, SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
/* Disable the whole hardware block */ - regmap_write(i2s->regmap, SUN4I_I2S_CTRL_REG, 0); + regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, + SUN4I_I2S_CTRL_GL_EN, 0); }
static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
The default value of the config register is different on newer SoCs and therefore enabling/disabling with a register write will clear bits used to set the direction of the clock and frame pins.
Signed-off-by: Marcus Cooper codekipper@gmail.com
Reviewed-by: Chen-Yu Tsai wens@csie.org
This patch looks like it could be applied directly without any of the other preceding patches?
From: Marcus Cooper codekipper@gmail.com
The sun8i-h3 introduces a lot of changes to the i2s block such as different register locations, extended clock division and more operational modes. As we have to consider the earlier implementation then these changes need to be isolated.
Signed-off-by: Marcus Cooper codekipper@gmail.com --- .../devicetree/bindings/sound/sun4i-i2s.txt | 2 + sound/soc/sunxi/sun4i-i2s.c | 173 +++++++++++++++++++++ 2 files changed, 175 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt index ee21da865771..fc5da6080759 100644 --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt @@ -8,6 +8,7 @@ Required properties: - compatible: should be one of the following: - "allwinner,sun4i-a10-i2s" - "allwinner,sun6i-a31-i2s" + - "allwinner,sun8i-h3-i2s" - reg: physical base address of the controller and length of memory mapped region. - interrupts: should contain the I2S interrupt. @@ -22,6 +23,7 @@ Required properties:
Required properties for the following compatibles: - "allwinner,sun6i-a31-i2s" + - "allwinner,sun8i-h3-i2s" - resets: phandle to the reset line for this codec
Example: diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index d8bcd3d9c2b6..87dfb5017c25 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -92,11 +92,43 @@ #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
+/* Defines required for sun8i-h3 support */ +#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) +#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17) + +#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) +#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) (period << 8) + +#define SUN8I_I2S_INT_STA_REG 0x0c +#define SUN8I_I2S_FIFO_TX_REG 0x20 + +#define SUN8I_I2S_CLK_DIV_MCLK_EN 8 + +#define SUN8I_I2S_CHAN_CFG_REG 0x30 +#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4) +#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) (chan - 1) +#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0) +#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1) + +#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 +#define SUN8I_I2S_TX_CHAN_SEL_REG 0x34 +#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13,11) +#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) +#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) +#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4) + +#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 +#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 + /** * struct sun4i_i2s_quirks - Differences between SoC variants. * * @has_reset: SoC needs reset deasserted. * @has_slave_select_bit: SoC has a bit to enable slave mode. + * @has_fmt_set_lrck_period: SoC requires lrclk period to be set. + * @has_chcfg: tx and rx slot number need to be set. + * @has_chsel_tx_chen: requires lrclk period to be set. + * @has_chsel_offset: requires lrclk period to be set. * @reg_offset_txdata: offset of the tx fifo. * @sun4i_i2s_regmap: regmap config to use. * @mclk_offset: Value by which mclkdiv needs to be adjusted. @@ -116,6 +148,10 @@ struct sun4i_i2s_quirks { bool has_reset; bool has_slave_select_bit; + bool has_fmt_set_lrck_period; + bool has_chcfg; + bool has_chsel_tx_chen; + bool has_chsel_offset; unsigned int reg_offset_txdata; /* TX FIFO */ const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset; @@ -291,6 +327,12 @@ static int sun4i_i2s_set_clk_rate(struct sun4i_i2s *i2s,
regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
+ /* Set sync period */ + if (i2s->variant->has_fmt_set_lrck_period) + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, + SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, + SUN8I_I2S_FMT0_LRCK_PERIOD(0x1f)); + return 0; }
@@ -305,6 +347,15 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, if (params_channels(params) != 2) return -EINVAL;
+ if (i2s->variant->has_chcfg) { + regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, + SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, + SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(params_channels(params))); + regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, + SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, + SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(params_channels(params))); + } + /* Map the channels for playback and capture */ regmap_field_write(i2s->field_txchanmap, 0x76543210); regmap_field_write(i2s->field_rxchanmap, 0x00003210); @@ -316,6 +367,10 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, regmap_field_write(i2s->field_rxchansel, SUN4I_I2S_CHAN_SEL(params_channels(params)));
+ if (i2s->variant->has_chsel_tx_chen) + regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, + SUN8I_I2S_TX_CHAN_EN_MASK, + SUN8I_I2S_TX_CHAN_EN(params_channels(params)));
switch (params_physical_width(params)) { case 16: @@ -349,6 +404,7 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); u32 val; + u32 offset = 0; u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
@@ -356,6 +412,7 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: val = SUN4I_I2S_FMT0_FMT_I2S; + offset = 1; break; case SND_SOC_DAIFMT_LEFT_J: val = SUN4I_I2S_FMT0_FMT_LEFT_J; @@ -367,6 +424,21 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; }
+ if (i2s->variant->has_chsel_offset) { + /* + * offset being set indicates that we're connected to an i2s + * device, however offset is only used on the sun8i block and + * i2s shares the same setting with the LJ format. Increment + * val so that the bit to value to write is correct. + */ + if (offset > 0) + val++; + /* blck offset determines whether i2s or LJ */ + regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, + SUN8I_I2S_TX_CHAN_OFFSET_MASK, + SUN8I_I2S_TX_CHAN_OFFSET(offset)); + } + regmap_field_write(i2s->field_fmt_set_mode, val);
/* DAI clock polarity */ @@ -410,6 +482,29 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN4I_I2S_CTRL_MODE_MASK, val); + } else { + /* + * The newer i2s block does not have a slave select bit, + * instead the clk pins are configured as inputs. + */ + /* DAI clock master masks */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + /* BCLK and LRCLK master */ + val = SUN8I_I2S_CTRL_BCLK_OUT | + SUN8I_I2S_CTRL_LRCK_OUT; + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* BCLK and LRCLK slave */ + val = 0; + break; + default: + return -EINVAL; + } + regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, + SUN8I_I2S_CTRL_BCLK_OUT | + SUN8I_I2S_CTRL_LRCK_OUT, + val); }
/* Set significant bits in our FIFOs */ @@ -651,6 +746,28 @@ static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg) } }
+static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SUN8I_I2S_FIFO_TX_REG: + return false; + + default: + return true; + } +} + +static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) +{ + + if (reg == SUN8I_I2S_INT_STA_REG) + return true; + if (reg == SUN8I_I2S_FIFO_TX_REG) + return false; + + return sun4i_i2s_volatile_reg(dev, reg); +} + static const struct reg_default sun4i_i2s_reg_defaults[] = { { SUN4I_I2S_CTRL_REG, 0x00000000 }, { SUN4I_I2S_FMT0_REG, 0x0000000c }, @@ -664,6 +781,20 @@ static const struct reg_default sun4i_i2s_reg_defaults[] = { { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 }, };
+static const struct reg_default sun8i_i2s_reg_defaults[] = { + { SUN4I_I2S_CTRL_REG, 0x00060000 }, + { SUN4I_I2S_FMT0_REG, 0x00000033 }, + { SUN4I_I2S_FMT1_REG, 0x00000030 }, + { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, + { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, + { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, + { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, + { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 }, + { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 }, + { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 }, + { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 }, +}; + static const struct regmap_config sun4i_i2s_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -678,6 +809,19 @@ static const struct regmap_config sun4i_i2s_regmap_config = { .volatile_reg = sun4i_i2s_volatile_reg, };
+static const struct regmap_config sun8i_i2s_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = SUN8I_I2S_RX_CHAN_MAP_REG, + .cache_type = REGCACHE_FLAT, + .reg_defaults = sun8i_i2s_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults), + .writeable_reg = sun4i_i2s_wr_reg, + .readable_reg = sun8i_i2s_rd_reg, + .volatile_reg = sun8i_i2s_volatile_reg, +}; + static int sun4i_i2s_runtime_resume(struct device *dev) { struct sun4i_i2s *i2s = dev_get_drvdata(dev); @@ -754,6 +898,31 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), };
+static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { + .has_reset = true, + .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, + .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, + .mclk_offset = 1, + .bclk_offset = 2, + .fmt_offset = 3, + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, + SUN8I_I2S_CLK_DIV_MCLK_EN, + SUN8I_I2S_CLK_DIV_MCLK_EN), + .has_fmt_set_lrck_period = true, + .has_chcfg = true, + .has_chsel_tx_chen = true, + .has_chsel_offset = true, + .field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), + .field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), + .field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), + .field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), + .field_fmt_set_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5), + .field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31), + .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2), + .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2), +}; + static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2s) { i2s->field_fmt_set_wss = @@ -956,6 +1125,10 @@ static const struct of_device_id sun4i_i2s_match[] = { .compatible = "allwinner,sun6i-a31-i2s", .data = &sun6i_a31_i2s_quirks, }, + { + .compatible = "allwinner,sun8i-h3-i2s", + .data = &sun8i_h3_i2s_quirks, + }, {} }; MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
On Sat, Jul 29, 2017 at 10:17 PM, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
The sun8i-h3 introduces a lot of changes to the i2s block such as different register locations, extended clock division and more operational modes. As we have to consider the earlier implementation then these changes need to be isolated.
Can you describe which parts are already supported, and what remains to be done? For example, you don't seem to support the extended clock division, nor the new operational modes.
Please also leave TODO notes in the code.
Signed-off-by: Marcus Cooper codekipper@gmail.com
.../devicetree/bindings/sound/sun4i-i2s.txt | 2 + sound/soc/sunxi/sun4i-i2s.c | 173 +++++++++++++++++++++ 2 files changed, 175 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt index ee21da865771..fc5da6080759 100644 --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt @@ -8,6 +8,7 @@ Required properties:
- compatible: should be one of the following:
- "allwinner,sun4i-a10-i2s"
- "allwinner,sun6i-a31-i2s"
- "allwinner,sun8i-h3-i2s"
- reg: physical base address of the controller and length of memory mapped region.
- interrupts: should contain the I2S interrupt.
@@ -22,6 +23,7 @@ Required properties:
Required properties for the following compatibles: - "allwinner,sun6i-a31-i2s"
- "allwinner,sun8i-h3-i2s"
- resets: phandle to the reset line for this codec
Example: diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index d8bcd3d9c2b6..87dfb5017c25 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -92,11 +92,43 @@ #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
+/* Defines required for sun8i-h3 support */ +#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) +#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
+#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) +#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) (period << 8)
+#define SUN8I_I2S_INT_STA_REG 0x0c +#define SUN8I_I2S_FIFO_TX_REG 0x20
+#define SUN8I_I2S_CLK_DIV_MCLK_EN 8
+#define SUN8I_I2S_CHAN_CFG_REG 0x30 +#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4) +#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) (chan - 1) +#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0) +#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
+#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 +#define SUN8I_I2S_TX_CHAN_SEL_REG 0x34 +#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13,11) +#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) +#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) +#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
+#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 +#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
/**
- struct sun4i_i2s_quirks - Differences between SoC variants.
- @has_reset: SoC needs reset deasserted.
- @has_slave_select_bit: SoC has a bit to enable slave mode.
- @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
- @has_chcfg: tx and rx slot number need to be set.
- @has_chsel_tx_chen: requires lrclk period to be set.
- @has_chsel_offset: requires lrclk period to be set.
The last two descriptions don't match up.
- @reg_offset_txdata: offset of the tx fifo.
- @sun4i_i2s_regmap: regmap config to use.
- @mclk_offset: Value by which mclkdiv needs to be adjusted.
@@ -116,6 +148,10 @@ struct sun4i_i2s_quirks { bool has_reset; bool has_slave_select_bit;
bool has_fmt_set_lrck_period;bool has_chcfg;bool has_chsel_tx_chen;bool has_chsel_offset; unsigned int reg_offset_txdata; /* TX FIFO */ const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset;@@ -291,6 +327,12 @@ static int sun4i_i2s_set_clk_rate(struct sun4i_i2s *i2s,
regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
/* Set sync period */if (i2s->variant->has_fmt_set_lrck_period)regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,SUN8I_I2S_FMT0_LRCK_PERIOD(0x1f));
Please use the actual number (32) here, and let the macro handle the register value offset.
return 0;}
@@ -305,6 +347,15 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, if (params_channels(params) != 2) return -EINVAL;
if (i2s->variant->has_chcfg) {regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(params_channels(params)));regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(params_channels(params)));}/* Map the channels for playback and capture */ regmap_field_write(i2s->field_txchanmap, 0x76543210); regmap_field_write(i2s->field_rxchanmap, 0x00003210);@@ -316,6 +367,10 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, regmap_field_write(i2s->field_rxchansel, SUN4I_I2S_CHAN_SEL(params_channels(params)));
if (i2s->variant->has_chsel_tx_chen)regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,SUN8I_I2S_TX_CHAN_EN_MASK,SUN8I_I2S_TX_CHAN_EN(params_channels(params))); switch (params_physical_width(params)) { case 16:@@ -349,6 +404,7 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); u32 val;
u32 offset = 0; u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;@@ -356,6 +412,7 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: val = SUN4I_I2S_FMT0_FMT_I2S;
offset = 1; break; case SND_SOC_DAIFMT_LEFT_J: val = SUN4I_I2S_FMT0_FMT_LEFT_J;@@ -367,6 +424,21 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; }
if (i2s->variant->has_chsel_offset) {/** offset being set indicates that we're connected to an i2s* device, however offset is only used on the sun8i block and* i2s shares the same setting with the LJ format. Increment* val so that the bit to value to write is correct.*/if (offset > 0)val++;/* blck offset determines whether i2s or LJ */regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,SUN8I_I2S_TX_CHAN_OFFSET_MASK,SUN8I_I2S_TX_CHAN_OFFSET(offset));}regmap_field_write(i2s->field_fmt_set_mode, val); /* DAI clock polarity */@@ -410,6 +482,29 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, SUN4I_I2S_CTRL_MODE_MASK, val);
} else {/** The newer i2s block does not have a slave select bit,* instead the clk pins are configured as inputs.*//* DAI clock master masks */switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {case SND_SOC_DAIFMT_CBS_CFS:/* BCLK and LRCLK master */val = SUN8I_I2S_CTRL_BCLK_OUT |SUN8I_I2S_CTRL_LRCK_OUT;break;case SND_SOC_DAIFMT_CBM_CFM:/* BCLK and LRCLK slave */val = 0;break;default:return -EINVAL;}regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,SUN8I_I2S_CTRL_BCLK_OUT |SUN8I_I2S_CTRL_LRCK_OUT,val); } /* Set significant bits in our FIFOs */@@ -651,6 +746,28 @@ static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg) } }
+static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg) +{
switch (reg) {case SUN8I_I2S_FIFO_TX_REG:return false;default:return true;}+}
+static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) +{
if (reg == SUN8I_I2S_INT_STA_REG)return true;if (reg == SUN8I_I2S_FIFO_TX_REG)return false;return sun4i_i2s_volatile_reg(dev, reg);+}
static const struct reg_default sun4i_i2s_reg_defaults[] = { { SUN4I_I2S_CTRL_REG, 0x00000000 }, { SUN4I_I2S_FMT0_REG, 0x0000000c }, @@ -664,6 +781,20 @@ static const struct reg_default sun4i_i2s_reg_defaults[] = { { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 }, };
+static const struct reg_default sun8i_i2s_reg_defaults[] = {
{ SUN4I_I2S_CTRL_REG, 0x00060000 },{ SUN4I_I2S_FMT0_REG, 0x00000033 },{ SUN4I_I2S_FMT1_REG, 0x00000030 },{ SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },{ SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },{ SUN4I_I2S_CLK_DIV_REG, 0x00000000 },{ SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },{ SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },{ SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },{ SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },{ SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },+};
static const struct regmap_config sun4i_i2s_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -678,6 +809,19 @@ static const struct regmap_config sun4i_i2s_regmap_config = { .volatile_reg = sun4i_i2s_volatile_reg, };
+static const struct regmap_config sun8i_i2s_regmap_config = {
.reg_bits = 32,.reg_stride = 4,.val_bits = 32,.max_register = SUN8I_I2S_RX_CHAN_MAP_REG,.cache_type = REGCACHE_FLAT,.reg_defaults = sun8i_i2s_reg_defaults,.num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults),.writeable_reg = sun4i_i2s_wr_reg,.readable_reg = sun8i_i2s_rd_reg,.volatile_reg = sun8i_i2s_volatile_reg,+};
static int sun4i_i2s_runtime_resume(struct device *dev) { struct sun4i_i2s *i2s = dev_get_drvdata(dev); @@ -754,6 +898,31 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2), };
+static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.has_reset = true,.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,.sun4i_i2s_regmap = &sun8i_i2s_regmap_config,.mclk_offset = 1,.bclk_offset = 2,.fmt_offset = 3,.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG,SUN8I_I2S_CLK_DIV_MCLK_EN,SUN8I_I2S_CLK_DIV_MCLK_EN),.has_fmt_set_lrck_period = true,.has_chcfg = true,.has_chsel_tx_chen = true,.has_chsel_offset = true,.field_fmt_set_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),.field_fmt_set_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),.field_fmt_set_bclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),.field_fmt_set_lrclk_polarity = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),.field_fmt_set_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
Comments from previous patches also apply here.
Regards, ChenYu
.field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),.field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),.field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),.field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),+};
static int sun4i_i2s_init_regmap_fields(struct device *dev, struct sun4i_i2s *i2s) { i2s->field_fmt_set_wss = @@ -956,6 +1125,10 @@ static const struct of_device_id sun4i_i2s_match[] = { .compatible = "allwinner,sun6i-a31-i2s", .data = &sun6i_a31_i2s_quirks, },
{.compatible = "allwinner,sun8i-h3-i2s",.data = &sun8i_h3_i2s_quirks,}, {}}; MODULE_DEVICE_TABLE(of, sun4i_i2s_match); -- 2.13.3
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Hey Marcus,
On 29-07-17 16:17, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
Hi All, please find attached a series of patches to bring i2s support to the Allwinner H3 SoC. This has been tested with the following setups:
A20 Olimex EVB connected to a pcm5102
But that's not an H3 is it? :)
Orange Pi 2 connected to a uda1380 Orange Pi 2 hdmi audio playback Pine 64 connected to the audio DAC board
To get i2s working some additional patches are required which will be delivered later. For now they have been pushed here
https://github.com/codekipper/linux-sunxi/commits/sunxi-audio-h3
Since I want to use i2s on the A20, i'm trying out your patches. It would be helpfull if you could point out which patches are missing (and if the subject doesn't cover it why those are needed)
I don't own a A33 device which uses the i2s block for the audio codec so if someone could test against that it would be much appreciated.
I'm also wondering if there is a preferred way of setting the lrclk size in the dts?..currently it is set to the sample width but for example the pcm5102a wants it to be 32 bits whatever the sample rate.
Thanks in advance, CK
v3 changes compared to v2 are:
- initial changes to prepare driver for newer SoCs has been broken down into smaller patches
- reduce use of regmap fields to where just needed.
- clkdiv expansion will be delivered later.
- defines for H3 variant segregated.
- fixed regmap config issue with SUN8I_I2S_FIFO_TX_REG.
v2 changes compared to v1 are:
- massive refactoring to remove duplicate code making use of regmap_fields.
- extending the clock divisors.
- removed code that should be delivered when we support 20/24bits
Marcus Cooper (12): ASoC: sun4i-i2s: Extend quirks scope ASoC: sun4i-i2s: Add clkdiv offsets to quirks ASoC: sun4i-i2s: Add regmap config to quirks ASoC: sun4i-i2s: Add TX FIFO offset to quirks ASoC: sun4i-i2s: Add regmap fields for channels ASoC: sun4i-i2s: Add changes for wss and sr ASoC: sun4i-i2s: bclk and lrclk polarity tidyup ASoC: sun4i-i2s: Add mclk enable regmap field ASoC: sun4i-i2s: Add regmap field to set format ASoC: sun4i-i2s: Check for slave select bit ASoC: sun4i-i2s: Update global enable with bitmask ASoC: sun4i-i2s: Add support for H3
.../devicetree/bindings/sound/sun4i-i2s.txt | 2 + sound/soc/sunxi/sun4i-i2s.c | 460 ++++++++++++++++++--- 2 files changed, 398 insertions(+), 64 deletions(-)
On 31 July 2017 at 09:05, Olliver Schinagl oliver+list@schinagl.nl wrote:
Hey Marcus,
On 29-07-17 16:17, codekipper@gmail.com wrote:
From: Marcus Cooper codekipper@gmail.com
Hi All, please find attached a series of patches to bring i2s support to the Allwinner H3 SoC. This has been tested with the following setups:
A20 Olimex EVB connected to a pcm5102
But that's not an H3 is it? :)
Was it broken?.....No...Have you fucked with it?....Yes....Is it now broken?...well better test!
Orange Pi 2 connected to a uda1380 Orange Pi 2 hdmi audio playback Pine 64 connected to the audio DAC board
To get i2s working some additional patches are required which will be delivered later. For now they have been pushed here
https://github.com/codekipper/linux-sunxi/commits/sunxi-audio-h3
Since I want to use i2s on the A20, i'm trying out your patches. It would be helpfull if you could point out which patches are missing (and if the subject doesn't cover it why those are needed)
Mainline currently supports A20...just needs pins to be added to the dtsi and codec specific added to the board dts. If you're having problems check pin connections to your external board and make sure the codec is being compiled. Good luck, CK
I don't own a A33 device which uses the i2s block for the audio codec so if someone could test against that it would be much appreciated.
I'm also wondering if there is a preferred way of setting the lrclk size in the dts?..currently it is set to the sample width but for example the pcm5102a wants it to be 32 bits whatever the sample rate.
Thanks in advance, CK
v3 changes compared to v2 are:
- initial changes to prepare driver for newer SoCs has been broken down into smaller patches
- reduce use of regmap fields to where just needed.
- clkdiv expansion will be delivered later.
- defines for H3 variant segregated.
- fixed regmap config issue with SUN8I_I2S_FIFO_TX_REG.
v2 changes compared to v1 are:
- massive refactoring to remove duplicate code making use of
regmap_fields.
- extending the clock divisors.
- removed code that should be delivered when we support 20/24bits
Marcus Cooper (12): ASoC: sun4i-i2s: Extend quirks scope ASoC: sun4i-i2s: Add clkdiv offsets to quirks ASoC: sun4i-i2s: Add regmap config to quirks ASoC: sun4i-i2s: Add TX FIFO offset to quirks ASoC: sun4i-i2s: Add regmap fields for channels ASoC: sun4i-i2s: Add changes for wss and sr ASoC: sun4i-i2s: bclk and lrclk polarity tidyup ASoC: sun4i-i2s: Add mclk enable regmap field ASoC: sun4i-i2s: Add regmap field to set format ASoC: sun4i-i2s: Check for slave select bit ASoC: sun4i-i2s: Update global enable with bitmask ASoC: sun4i-i2s: Add support for H3
.../devicetree/bindings/sound/sun4i-i2s.txt | 2 + sound/soc/sunxi/sun4i-i2s.c | 460 ++++++++++++++++++--- 2 files changed, 398 insertions(+), 64 deletions(-)
participants (6)
-
Chen-Yu Tsai -
Code Kipper -
codekipper＠gmail.com
-
kbuild test robot -
Mark Brown -
Olliver Schinagl