Add ACP IP register header file for ACP7.0 platform.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- include/sound/acp70_chip_offset_byte.h | 484 +++++++++++++++++++++++++ 1 file changed, 484 insertions(+) create mode 100644 include/sound/acp70_chip_offset_byte.h

diff --git a/include/sound/acp70_chip_offset_byte.h b/include/sound/acp70_chip_offset_byte.h new file mode 100644 index 000000000000..c0d51a0e012e --- /dev/null +++ b/include/sound/acp70_chip_offset_byte.h @@ -0,0 +1,484 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AMD ACP 7.0 Register Documentation + * + * Copyright 2024 Advanced Micro Devices, Inc. + */ + +#ifndef _acp_ip_OFFSET_HEADER +#define _acp_ip_OFFSET_HEADER + +/* Registers from ACP_AXI2AXIATU block */ +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C00 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C04 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C08 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C10 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C14 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C18 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C20 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C24 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C28 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C30 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C34 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C38 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C +#define ACPAXI2AXI_ATU_CTRL 0x0000C40 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C44 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C48 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C50 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C54 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C58 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80 + +/* Registers from ACP_CLKRST block */ +#define ACP_SOFT_RESET 0x0001000 +#define ACP_CONTROL 0x0001004 +#define ACP_STATUS 0x0001008 +#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010 +#define ACP_ZSC_DSP_CTRL 0x0001014 +#define ACP_ZSC_STS 0x0001018 +#define ACP_PGFSM_CONTROL 0x0001024 +#define ACP_PGFSM_STATUS 0x0001028 +#define ACP_CLKMUX_SEL 0x000102C +#define ACP_SW0_48MHZ_CLK_SEL 0x0001030 + +/* Registers from ACP_AON block */ +#define ACP_PME_EN 0x0001400 +#define ACP_DEVICE_STATE 0x0001404 +#define AZ_DEVICE_STATE 0x0001408 +#define SW_DEVICE_STATE 0x0001430 +#define ACP_PIN_CONFIG 0x0001440 +#define ACP_PAD_PULLUP_CTRL 0x0001444 +#define ACP_PAD_PULLDOWN_CTRL 0x0001448 +#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C +#define ACP_PAD_SCHMEN_CTRL 0x0001450 +#define ACP_SW_PAD_KEEPER_EN 0x0001454 +#define ACP_SW0_WAKE_EN 0x0001458 +#define ACP_I2S_WAKE_EN 0x000145C +#define ACP_SW1_WAKE_EN 0x0001460 +#define ACP_PAD_DISABLE_OE_CTRL 0x0001468 + +/* Registers from ACP_MISC block */ +#define ACP_SW0_I2S_ERROR_REASON 0x00018B4 +#define ACP_SW0_POS_TRACK_AUDIO0_TX_CTRL 0x00018B8 +#define ACP_SW0_AUDIO0_TX_DMA_POS 0x00018BC +#define ACP_SW0_POS_TRACK_AUDIO1_TX_CTRL 0x00018C0 +#define ACP_SW0_AUDIO1_TX_DMA_POS 0x00018C4 +#define ACP_SW0_POS_TRACK_AUDIO2_TX_CTRL 0x00018C8 +#define ACP_SW0_AUDIO2_TX_DMA_POS 0x00018CC +#define ACP_SW0_POS_TRACK_AUDIO0_RX_CTRL 0x00018D0 +#define ACP_SW0_AUDIO0_DMA_POS 0x00018D4 +#define ACP_SW0_POS_TRACK_AUDIO1_RX_CTRL 0x00018D8 +#define ACP_SW0_AUDIO1_RX_DMA_POS 0x00018DC +#define ACP_SW0_POS_TRACK_AUDIO2_RX_CTRL 0x00018E0 +#define ACP_SW0_AUDIO2_RX_DMA_POS 0x00018E4 +#define ACP_ERROR_INTR_MASK1 0x0001974 +#define ACP_ERROR_INTR_MASK2 0x0001978 +#define ACP_ERROR_INTR_MASK3 0x000197C + +/* Registers from ACP_P1_MISC block */ +#define ACP_EXTERNAL_INTR_ENB 0x0001A00 +#define ACP_EXTERNAL_INTR_CNTL 0x0001A04 +#define ACP_EXTERNAL_INTR_CNTL1 0x0001A08 +#define ACP_EXTERNAL_INTR_STAT 0x0001A0C +#define ACP_EXTERNAL_INTR_STAT1 0x0001A10 +#define ACP_ERROR_STATUS 0x0001A4C +#define ACP_SW1_I2S_ERROR_REASON 0x0001A50 +#define ACP_SW1_POS_TRACK_AUDIO0_TX_CTRL 0x0001A6C +#define ACP_SW1_AUDIO0_TX_DMA_POS 0x0001A70 +#define ACP_SW1_POS_TRACK_AUDIO0_RX_CTRL 0x0001A74 +#define ACP_SW1_AUDIO0_RX_DMA_POS 0x0001A78 +#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C +#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80 +#define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84 +#define ACP_SW1_POS_TRACK_AUDIO1_TX_CTRL 0x0001A88 +#define ACP_SW1_AUDIO1_TX_DMA_POS 0x0001A8C +#define ACP_SW1_POS_TRACK_AUDIO2_TX_CTRL 0x0001A90 +#define ACP_SW1_AUDIO2_TX_DMA_POS 0x0001A94 +#define ACP_SW1_POS_TRACK_AUDIO1_RX_CTRL 0x0001A98 +#define ACP_SW1_AUDIO1_RX_DMA_POS 0x0001A9C +#define ACP_SW1_POS_TRACK_AUDIO2_RX_CTRL 0x0001AA0 +#define ACP_SW1_AUDIO2_RX_DMA_POS 0x0001AA4 +#define ACP_ERROR_INTR_MASK4 0x0001AEC +#define ACP_ERROR_INTR_MASK5 0x0001AF0 +#define ACP_ERROR_STATUS1 0x0001B28 + +/* Registers from ACP_AUDIO_BUFFERS block */ +#define ACP_AUDIO0_RX_RINGBUFADDR 0x0002000 +#define ACP_AUDIO0_RX_RINGBUFSIZE 0x0002004 +#define ACP_AUDIO0_RX_LINKPOSITIONCNTR 0x0002008 +#define ACP_AUDIO0_RX_FIFOADDR 0x000200C +#define ACP_AUDIO0_RX_FIFOSIZE 0x0002010 +#define ACP_AUDIO0_RX_DMA_SIZE 0x0002014 +#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0002018 +#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x000201C +#define ACP_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0002020 +#define ACP_AUDIO0_TX_RINGBUFADDR 0x0002024 +#define ACP_AUDIO0_TX_RINGBUFSIZE 0x0002028 +#define ACP_AUDIO0_TX_LINKPOSITIONCNTR 0x000202C +#define ACP_AUDIO0_TX_FIFOADDR 0x0002030 +#define ACP_AUDIO0_TX_FIFOSIZE 0x0002034 +#define ACP_AUDIO0_TX_DMA_SIZE 0x0002038 +#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x000203C +#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0002040 +#define ACP_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0002044 +#define ACP_AUDIO1_RX_RINGBUFADDR 0x0002048 +#define ACP_AUDIO1_RX_RINGBUFSIZE 0x000204C +#define ACP_AUDIO1_RX_LINKPOSITIONCNTR 0x0002050 +#define ACP_AUDIO1_RX_FIFOADDR 0x0002054 +#define ACP_AUDIO1_RX_FIFOSIZE 0x0002058 +#define ACP_AUDIO1_RX_DMA_SIZE 0x000205C +#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0002060 +#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0002064 +#define ACP_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0002068 +#define ACP_AUDIO1_TX_RINGBUFADDR 0x000206C +#define ACP_AUDIO1_TX_RINGBUFSIZE 0x0002070 +#define ACP_AUDIO1_TX_LINKPOSITIONCNTR 0x0002074 +#define ACP_AUDIO1_TX_FIFOADDR 0x0002078 +#define ACP_AUDIO1_TX_FIFOSIZE 0x000207C +#define ACP_AUDIO1_TX_DMA_SIZE 0x0002080 +#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0002084 +#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0002088 +#define ACP_AUDIO1_TX_INTR_WATERMARK_SIZE 0x000208C +#define ACP_AUDIO2_RX_RINGBUFADDR 0x0002090 +#define ACP_AUDIO2_RX_RINGBUFSIZE 0x0002094 +#define ACP_AUDIO2_RX_LINKPOSITIONCNTR 0x0002098 +#define ACP_AUDIO2_RX_FIFOADDR 0x000209C +#define ACP_AUDIO2_RX_FIFOSIZE 0x00020A0 +#define ACP_AUDIO2_RX_DMA_SIZE 0x00020A4 +#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8 +#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x00020AC +#define ACP_AUDIO2_RX_INTR_WATERMARK_SIZE 0x00020B0 +#define ACP_AUDIO2_TX_RINGBUFADDR 0x00020B4 +#define ACP_AUDIO2_TX_RINGBUFSIZE 0x00020B8 +#define ACP_AUDIO2_TX_LINKPOSITIONCNTR 0x00020BC +#define ACP_AUDIO2_TX_FIFOADDR 0x00020C0 +#define ACP_AUDIO2_TX_FIFOSIZE 0x00020C4 +#define ACP_AUDIO2_TX_DMA_SIZE 0x00020C8 +#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC +#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x00020D0 +#define ACP_AUDIO2_TX_INTR_WATERMARK_SIZE 0x00020D4 + +/* Registers from ACP_I2S_TDM block */ +#define ACP_I2STDM_IER 0x0002400 +#define ACP_I2STDM_IRER 0x0002404 +#define ACP_I2STDM_RXFRMT 0x0002408 +#define ACP_I2STDM_ITER 0x000240C +#define ACP_I2STDM_TXFRMT 0x0002410 +#define ACP_I2STDM0_MSTRCLKGEN 0x0002414 +#define ACP_I2STDM1_MSTRCLKGEN 0x0002418 +#define ACP_I2STDM2_MSTRCLKGEN 0x000241C +#define ACP_I2STDM_REFCLKGEN 0x0002420 + +/* Registers from ACP_BT_TDM block */ +#define ACP_BTTDM_IER 0x0002800 +#define ACP_BTTDM_IRER 0x0002804 +#define ACP_BTTDM_RXFRMT 0x0002808 +#define ACP_BTTDM_ITER 0x000280C +#define ACP_BTTDM_TXFRMT 0x0002810 +#define ACP_HSTDM_IER 0x0002814 +#define ACP_HSTDM_IRER 0x0002818 +#define ACP_HSTDM_RXFRMT 0x000281C +#define ACP_HSTDM_ITER 0x0002820 +#define ACP_HSTDM_TXFRMT 0x0002824 + +/* Registers from ACP_WOV block */ +#define ACP_WOV_PDM_ENABLE 0x0002C04 +#define ACP_WOV_PDM_DMA_ENABLE 0x0002C08 +#define ACP_WOV_RX_RINGBUFADDR 0x0002C0C +#define ACP_WOV_RX_RINGBUFSIZE 0x0002C10 +#define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14 +#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18 +#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C +#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20 +#define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24 +#define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28 +#define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C +#define ACP_WOV_PDM_VAD_CTRL 0x0002C30 +#define ACP_WOV_WAKE 0x0002C54 +#define ACP_WOV_BUFFER_STATUS 0x0002C58 +#define ACP_WOV_MISC_CTRL 0x0002C5C +#define ACP_WOV_CLK_CTRL 0x0002C60 +#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64 +#define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68 +#define ACP_PDM_CLKDIV 0x0002C6C + +/* Registers from ACP_SW0_SWCLK block */ +#define ACP_SW0_EN 0x0003000 +#define ACP_SW0_EN_STATUS 0x0003004 +#define ACP_SW0_FRAMESIZE 0x0003008 +#define ACP_SW0_SSP_COUNTER 0x000300C +#define ACP_SW0_AUDIO0_TX_EN 0x0003010 +#define ACP_SW0_AUDIO0_TX_EN_STATUS 0x0003014 +#define ACP_SW0_AUDIO0_TX_FRAME_FORMAT 0x0003018 +#define ACP_SW0_AUDIO0_TX_SAMPLEINTERVAL 0x000301C +#define ACP_SW0_AUDIO0_TX_HCTRL_DP0 0x0003020 +#define ACP_SW0_AUDIO0_TX_HCTRL_DP1 0x0003024 +#define ACP_SW0_AUDIO0_TX_HCTRL_DP2 0x0003028 +#define ACP_SW0_AUDIO0_TX_HCTRL_DP3 0x000302C +#define ACP_SW0_AUDIO0_TX_OFFSET_DP0 0x0003030 +#define ACP_SW0_AUDIO0_TX_OFFSET_DP1 0x0003034 +#define ACP_SW0_AUDIO0_TX_OFFSET_DP2 0x0003038 +#define ACP_SW0_AUDIO0_TX_OFFSET_DP3 0x000303C +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP0 0x0003040 +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP1 0x0003044 +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP2 0x0003048 +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP3 0x000304C +#define ACP_SW0_AUDIO1_TX_EN 0x0003050 +#define ACP_SW0_AUDIO1_TX_EN_STATUS 0x0003054 +#define ACP_SW0_AUDIO1_TX_FRAME_FORMAT 0x0003058 +#define ACP_SW0_AUDIO1_TX_SAMPLEINTERVAL 0x000305C +#define ACP_SW0_AUDIO1_TX_HCTRL 0x0003060 +#define ACP_SW0_AUDIO1_TX_OFFSET 0x0003064 +#define ACP_SW0_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003068 +#define ACP_SW0_AUDIO2_TX_EN 0x000306C +#define ACP_SW0_AUDIO2_TX_EN_STATUS 0x0003070 +#define ACP_SW0_AUDIO2_TX_FRAME_FORMAT 0x0003074 +#define ACP_SW0_AUDIO2_TX_SAMPLEINTERVAL 0x0003078 +#define ACP_SW0_AUDIO2_TX_HCTRL 0x000307C +#define ACP_SW0_AUDIO2_TX_OFFSET 0x0003080 +#define ACP_SW0_AUDIO2_TX_CHANNEL_ENABLE_DP0 0x0003084 +#define ACP_SW0_AUDIO0_RX_EN 0x0003088 +#define ACP_SW0_AUDIO0_RX_EN_STATUS 0x000308C +#define ACP_SW0_AUDIO0_RX_FRAME_FORMAT 0x0003090 +#define ACP_SW0_AUDIO0_RX_SAMPLEINTERVAL 0x0003094 +#define ACP_SW0_AUDIO0_RX_HCTRL_DP0 0x0003098 +#define ACP_SW0_AUDIO0_RX_HCTRL_DP1 0x000309C +#define ACP_SW0_AUDIO0_RX_HCTRL_DP2 0x0003100 +#define ACP_SW0_AUDIO0_RX_HCTRL_DP3 0x0003104 +#define ACP_SW0_AUDIO0_RX_OFFSET_DP0 0x0003108 +#define ACP_SW0_AUDIO0_RX_OFFSET_DP1 0x000310C +#define ACP_SW0_AUDIO0_RX_OFFSET_DP2 0x0003110 +#define ACP_SW0_AUDIO0_RX_OFFSET_DP3 0x0003114 +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP0 0x0003118 +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP1 0x000311C +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP2 0x0003120 +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP3 0x0003124 +#define ACP_SW0_AUDIO1_RX_EN 0x0003128 +#define ACP_SW0_AUDIO1_RX_EN_STATUS 0x000312C +#define ACP_SW0_AUDIO1_RX_FRAME_FORMAT 0x0003130 +#define ACP_SW0_AUDIO1_RX_SAMPLEINTERVAL 0x0003134 +#define ACP_SW0_AUDIO1_RX_HCTRL 0x0003138 +#define ACP_SW0_AUDIO1_RX_OFFSET 0x000313C +#define ACP_SW0_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003140 +#define ACP_SW0_AUDIO2_RX_EN 0x0003144 +#define ACP_SW0_AUDIO2_RX_EN_STATUS 0x0003148 +#define ACP_SW0_AUDIO2_RX_FRAME_FORMAT 0x000314C +#define ACP_SW0_AUDIO2_RX_SAMPLEINTERVAL 0x0003150 +#define ACP_SW0_AUDIO2_RX_HCTRL 0x0003154 +#define ACP_SW0_AUDIO2_RX_OFFSET 0x0003158 +#define ACP_SW0_AUDIO2_RX_CHANNEL_ENABLE_DP0 0x000315C +#define ACP_SW0_BPT_PORT_EN 0x0003160 +#define ACP_SW0_BPT_PORT_EN_STATUS 0x0003164 +#define ACP_SW0_BPT_PORT_FRAME_FORMAT 0x0003168 +#define ACP_SW0_BPT_PORT_SAMPLEINTERVAL 0x000316C +#define ACP_SW0_BPT_PORT_HCTRL 0x0003170 +#define ACP_SW0_BPT_PORT_OFFSET 0x0003174 +#define ACP_SW0_BPT_PORT_CHANNEL_ENABLE 0x0003178 +#define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR 0x000317C +#define ACP_SW0_CLK_RESUME_CTRL 0x0003180 +#define ACP_SW0_CLK_RESUME_DELAY_CNTR 0x0003184 +#define ACP_SW0_BUS_RESET_CTRL 0x0003188 +#define ACP_SW0_PRBS_ERR_STATUS 0x000318C + +/* Registers from ACP_SW0_ACLK block */ +#define ACP_SW0_CORB_BASE_ADDRESS 0x0003200 +#define ACP_SW0_CORB_WRITE_POINTER 0x0003204 +#define ACP_SW0_CORB_READ_POINTER 0x0003208 +#define ACP_SW0_CORB_CONTROL 0x000320C +#define ACP_SW0_CORB_SIZE 0x0003214 +#define ACP_SW0_RIRB_BASE_ADDRESS 0x0003218 +#define ACP_SW0_RIRB_WRITE_POINTER 0x000321C +#define ACP_SW0_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003220 +#define ACP_SW0_RIRB_CONTROL 0x0003224 +#define ACP_SW0_RIRB_SIZE 0x0003228 +#define ACP_SW0_RIRB_FIFO_MIN_THDL 0x000322C +#define ACP_SW0_IMM_CMD_UPPER_WORD 0x0003230 +#define ACP_SW0_IMM_CMD_LOWER_QWORD 0x0003234 +#define ACP_SW0_IMM_RESP_UPPER_WORD 0x0003238 +#define ACP_SW0_IMM_RESP_LOWER_QWORD 0x000323C +#define ACP_SW0_IMM_CMD_STS 0x0003240 +#define ACP_SW0_BRA_BASE_ADDRESS 0x0003244 +#define ACP_SW0_BRA_TRANSFER_SIZE 0x0003248 +#define ACP_SW0_BRA_DMA_BUSY 0x000324C +#define ACP_SW0_BRA_RESP 0x0003250 +#define ACP_SW0_BRA_RESP_FRAME_ADDR 0x0003254 +#define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE 0x0003258 +#define ACP_SW0_STATECHANGE_STATUS_0TO7 0x000325C +#define ACP_SW0_STATECHANGE_STATUS_8TO11 0x0003260 +#define ACP_SW0_STATECHANGE_STATUS_MASK_0TO7 0x0003264 +#define ACP_SW0_STATECHANGE_STATUS_MASK_8TO11 0x0003268 +#define ACP_SW0_CLK_FREQUENCY_CTRL 0x000326C +#define ACP_SW0_ERROR_INTR_MASK 0x0003270 +#define ACP_SW0_PHY_TEST_MODE_DATA_OFF 0x0003274 + +/* Registers from ACP_P1_AUDIO_BUFFERS block */ +#define ACP_P1_AUDIO0_RX_RINGBUFADDR 0x0003A00 +#define ACP_P1_AUDIO0_RX_RINGBUFSIZE 0x0003A04 +#define ACP_P1_AUDIO0_RX_LINKPOSITIONCNTR 0x0003A08 +#define ACP_P1_AUDIO0_RX_FIFOADDR 0x0003A0C +#define ACP_P1_AUDIO0_RX_FIFOSIZE 0x0003A10 +#define ACP_P1_AUDIO0_RX_DMA_SIZE 0x0003A14 +#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18 +#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C +#define ACP_P1_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0003A20 +#define ACP_P1_AUDIO0_TX_RINGBUFADDR 0x0003A24 +#define ACP_P1_AUDIO0_TX_RINGBUFSIZE 0x0003A28 +#define ACP_P1_AUDIO0_TX_LINKPOSITIONCNTR 0x0003A2C +#define ACP_P1_AUDIO0_TX_FIFOADDR 0x0003A30 +#define ACP_P1_AUDIO0_TX_FIFOSIZE 0x0003A34 +#define ACP_P1_AUDIO0_TX_DMA_SIZE 0x0003A38 +#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C +#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0003A40 +#define ACP_P1_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0003A44 +#define ACP_P1_AUDIO1_RX_RINGBUFADDR 0x0003A48 +#define ACP_P1_AUDIO1_RX_RINGBUFSIZE 0x0003A4C +#define ACP_P1_AUDIO1_RX_LINKPOSITIONCNTR 0x0003A50 +#define ACP_P1_AUDIO1_RX_FIFOADDR 0x0003A54 +#define ACP_P1_AUDIO1_RX_FIFOSIZE 0x0003A58 +#define ACP_P1_AUDIO1_RX_DMA_SIZE 0x0003A5C +#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60 +#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0003A64 +#define ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0003A68 +#define ACP_P1_AUDIO1_TX_RINGBUFADDR 0x0003A6C +#define ACP_P1_AUDIO1_TX_RINGBUFSIZE 0x0003A70 +#define ACP_P1_AUDIO1_TX_LINKPOSITIONCNTR 0x0003A74 +#define ACP_P1_AUDIO1_TX_FIFOADDR 0x0003A78 +#define ACP_P1_AUDIO1_TX_FIFOSIZE 0x0003A7C +#define ACP_P1_AUDIO1_TX_DMA_SIZE 0x0003A80 +#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84 +#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0003A88 +#define ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE 0x0003A8C +#define ACP_P1_AUDIO2_RX_RINGBUFADDR 0x0003A90 +#define ACP_P1_AUDIO2_RX_RINGBUFSIZE 0x0003A94 +#define ACP_P1_AUDIO2_RX_LINKPOSITIONCNTR 0x0003A98 +#define ACP_P1_AUDIO2_RX_FIFOADDR 0x0003A9C +#define ACP_P1_AUDIO2_RX_FIFOSIZE 0x0003AA0 +#define ACP_P1_AUDIO2_RX_DMA_SIZE 0x0003AA4 +#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8 +#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC +#define ACP_P1_AUDIO2_RX_INTR_WATERMARK_SIZE 0x0003AB0 +#define ACP_P1_AUDIO2_TX_RINGBUFADDR 0x0003AB4 +#define ACP_P1_AUDIO2_TX_RINGBUFSIZE 0x0003AB8 +#define ACP_P1_AUDIO2_TX_LINKPOSITIONCNTR 0x0003ABC +#define ACP_P1_AUDIO2_TX_FIFOADDR 0x0003AC0 +#define ACP_P1_AUDIO2_TX_FIFOSIZE 0x0003AC4 +#define ACP_P1_AUDIO2_TX_DMA_SIZE 0x0003AC8 +#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC +#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0 +#define ACP_P1_AUDIO2_TX_INTR_WATERMARK_SIZE 0x0003AD4 + +/* Registers from ACP_SW1_SWCLK block */ +#define ACP_SW1_EN 0x0003C00 +#define ACP_SW1_EN_STATUS 0x0003C04 +#define ACP_SW1_FRAMESIZE 0x0003C08 +#define ACP_SW1_SSP_COUNTER 0x0003C0C +#define ACP_SW1_AUDIO0_TX_EN 0x0003C10 +#define ACP_SW1_AUDIO0_TX_EN_STATUS 0x0003C14 +#define ACP_SW1_AUDIO0_TX_FRAME_FORMAT 0x0003C18 +#define ACP_SW1_AUDIO0_TX_SAMPLEINTERVAL 0x0003C1C +#define ACP_SW1_AUDIO0_TX_HCTRL_DP0 0x0003C20 +#define ACP_SW1_AUDIO0_TX_HCTRL_DP1 0x0003C24 +#define ACP_SW1_AUDIO0_TX_OFFSET_DP0 0x0003C30 +#define ACP_SW1_AUDIO0_TX_OFFSET_DP1 0x0003C34 +#define ACP_SW1_AUDIO0_TX_CHANNEL_ENABLE_DP0 0x0003C40 +#define ACP_SW1_AUDIO0_TX_CHANNEL_ENABLE_DP1 0x0003C44 +#define ACP_SW1_AUDIO1_TX_EN 0x0003C50 +#define ACP_SW1_AUDIO1_TX_EN_STATUS 0x0003C54 +#define ACP_SW1_AUDIO1_TX_FRAME_FORMAT 0x0003C58 +#define ACP_SW1_AUDIO1_TX_SAMPLEINTERVAL 0x0003C5C +#define ACP_SW1_AUDIO1_TX_HCTRL 0x0003C60 +#define ACP_SW1_AUDIO1_TX_OFFSET 0x0003C64 +#define ACP_SW1_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003C68 +#define ACP_SW1_AUDIO2_TX_EN 0x0003C6C +#define ACP_SW1_AUDIO2_TX_EN_STATUS 0x0003C70 +#define ACP_SW1_AUDIO2_TX_FRAME_FORMAT 0x0003C74 +#define ACP_SW1_AUDIO2_TX_SAMPLEINTERVAL 0x0003C78 +#define ACP_SW1_AUDIO2_TX_HCTRL 0x0003C7C +#define ACP_SW1_AUDIO2_TX_OFFSET 0x0003C80 +#define ACP_SW1_AUDIO2_TX_CHANNEL_ENABLE_DP0 0x0003C84 +#define ACP_SW1_AUDIO0_RX_EN 0x0003C88 +#define ACP_SW1_AUDIO0_RX_EN_STATUS 0x0003C8C +#define ACP_SW1_AUDIO0_RX_FRAME_FORMAT 0x0003C90 +#define ACP_SW1_AUDIO0_RX_SAMPLEINTERVAL 0x0003C94 +#define ACP_SW1_AUDIO0_RX_HCTRL_DP0 0x0003C98 +#define ACP_SW1_AUDIO0_RX_HCTRL_DP1 0x0003C9C +#define ACP_SW1_AUDIO0_RX_OFFSET_DP0 0x0003D08 +#define ACP_SW1_AUDIO0_RX_OFFSET_DP1 0x0003D0C +#define ACP_SW1_AUDIO0_RX_CHANNEL_ENABLE_DP0 0x0003D18 +#define ACP_SW1_AUDIO0_RX_CHANNEL_ENABLE_DP1 0x0003D1C +#define ACP_SW1_AUDIO1_RX_EN 0x0003D28 +#define ACP_SW1_AUDIO1_RX_EN_STATUS 0x0003D2C +#define ACP_SW1_AUDIO1_RX_FRAME_FORMAT 0x0003D30 +#define ACP_SW1_AUDIO1_RX_SAMPLEINTERVAL 0x0003D34 +#define ACP_SW1_AUDIO1_RX_HCTRL 0x0003D38 +#define ACP_SW1_AUDIO1_RX_OFFSET 0x0003D3C +#define ACP_SW1_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003D40 +#define ACP_SW1_AUDIO2_RX_EN 0x0003D44 +#define ACP_SW1_AUDIO2_RX_EN_STATUS 0x0003D48 +#define ACP_SW1_AUDIO2_RX_FRAME_FORMAT 0x0003D4C +#define ACP_SW1_AUDIO2_RX_SAMPLEINTERVAL 0x0003D50 +#define ACP_SW1_AUDIO2_RX_HCTRL 0x0003D54 +#define ACP_SW1_AUDIO2_RX_OFFSET 0x0003D58 +#define ACP_SW1_AUDIO2_RX_CHANNEL_ENABLE_DP0 0x0003D5C +#define ACP_SW1_BPT_PORT_EN 0x0003D60 +#define ACP_SW1_BPT_PORT_EN_STATUS 0x0003D64 +#define ACP_SW1_BPT_PORT_FRAME_FORMAT 0x0003D68 +#define ACP_SW1_BPT_PORT_SAMPLEINTERVAL 0x0003D6C +#define ACP_SW1_BPT_PORT_HCTRL 0x0003D70 +#define ACP_SW1_BPT_PORT_OFFSET 0x0003D74 +#define ACP_SW1_BPT_PORT_CHANNEL_ENABLE 0x0003D78 +#define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C +#define ACP_SW1_CLK_RESUME_CTRL 0x0003D80 +#define ACP_SW1_CLK_RESUME_DELAY_CNTR 0x0003D84 +#define ACP_SW1_BUS_RESET_CTRL 0x0003D88 +#define ACP_SW1_PRBS_ERR_STATUS 0x0003D8C + +/* Registers from ACP_SW1_ACLK block */ +#define ACP_SW1_CORB_BASE_ADDRESS 0x0003E00 +#define ACP_SW1_CORB_WRITE_POINTER 0x0003E04 +#define ACP_SW1_CORB_READ_POINTER 0x0003E08 +#define ACP_SW1_CORB_CONTROL 0x0003E0C +#define ACP_SW1_CORB_SIZE 0x0003E14 +#define ACP_SW1_RIRB_BASE_ADDRESS 0x0003E18 +#define ACP_SW1_RIRB_WRITE_POINTER 0x0003E1C +#define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20 +#define ACP_SW1_RIRB_CONTROL 0x0003E24 +#define ACP_SW1_RIRB_SIZE 0x0003E28 +#define ACP_SW1_RIRB_FIFO_MIN_THDL 0x0003E2C +#define ACP_SW1_IMM_CMD_UPPER_WORD 0x0003E30 +#define ACP_SW1_IMM_CMD_LOWER_QWORD 0x0003E34 +#define ACP_SW1_IMM_RESP_UPPER_WORD 0x0003E38 +#define ACP_SW1_IMM_RESP_LOWER_QWORD 0x0003E3C +#define ACP_SW1_IMM_CMD_STS 0x0003E40 +#define ACP_SW1_BRA_BASE_ADDRESS 0x0003E44 +#define ACP_SW1_BRA_TRANSFER_SIZE 0x0003E48 +#define ACP_SW1_BRA_DMA_BUSY 0x0003E4C +#define ACP_SW1_BRA_RESP 0x0003E50 +#define ACP_SW1_BRA_RESP_FRAME_ADDR 0x0003E54 +#define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE 0x0003E58 +#define ACP_SW1_STATECHANGE_STATUS_0TO7 0x0003E5C +#define ACP_SW1_STATECHANGE_STATUS_8TO11 0x0003E60 +#define ACP_SW1_STATECHANGE_STATUS_MASK_0TO7 0x0003E64 +#define ACP_SW1_STATECHANGE_STATUS_MASK_8TO11 0x0003E68 +#define ACP_SW1_CLK_FREQUENCY_CTRL 0x0003E6C +#define ACP_SW1_ERROR_INTR_MASK 0x0003E70 +#define ACP_SW1_PHY_TEST_MODE_DATA_OFF 0x0003E74 + +/* Registers from ACP_SCRATCH block */ +#define ACP_SCRATCH_REG_0 0x0010000 + +#endif

Based on acp pin configuration, add logic for scanning child devices under acp pci device acpi scope.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70.h | 43 +++++++++++++ sound/soc/amd/acp70/pci-acp70.c | 103 ++++++++++++++++++++++++++++++++ 2 files changed, 146 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index b6f0f75de91d..1b20de75876a 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -5,6 +5,7 @@ * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. */

+#include <linux/soundwire/sdw_amd.h> #include <sound/acp70_chip_offset_byte.h>

#define ACP_DEVICE_ID 0x15E2 @@ -28,21 +29,63 @@ #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF #define ACP_ERROR_IRQ BIT(29)

+#define ACP_DMIC_DEV 2 +#define ACP70_DMIC_ADDR 2 +#define ACP70_SDW_ADDR 5 +#define AMD_SDW_MAX_MANAGERS 2 + +enum acp_config { + ACP_CONFIG_0 = 0, + ACP_CONFIG_1, + ACP_CONFIG_2, + ACP_CONFIG_3, + ACP_CONFIG_4, + ACP_CONFIG_5, + ACP_CONFIG_6, + ACP_CONFIG_7, + ACP_CONFIG_8, + ACP_CONFIG_9, + ACP_CONFIG_10, + ACP_CONFIG_11, + ACP_CONFIG_12, + ACP_CONFIG_13, + ACP_CONFIG_14, + ACP_CONFIG_15, + ACP_CONFIG_16, + ACP_CONFIG_17, + ACP_CONFIG_18, + ACP_CONFIG_19, + ACP_CONFIG_20, +}; + /** * struct acp70_dev_data - acp pci driver context * @acp70_base: acp mmio base * @acp_lock: used to protect acp common registers + * @info: SoundWire AMD information found in ACPI tables + * @sdw: SoundWire context for all SoundWire manager instances * @addr: pci ioremap address * @reg_range: ACP reigister range * @acp_rev : ACP PCI revision id + * @is_sdw_dev: flag set to true when any SoundWire manager instances are available + * @is_pdm_dev: flag set to true when ACP PDM controller exists + * @is_pdm_config: flat set to true when PDM configuration is selected from BIOS + * @is_sdw_config: flag set to true when SDW configuration is selected from BIOS */

struct acp70_dev_data { void __iomem *acp70_base; struct mutex acp_lock; /* protect shared registers */ + struct sdw_amd_acpi_info info; + /* sdw context allocated by SoundWire driver */ + struct sdw_amd_ctx *sdw; u32 addr; u32 reg_range; u32 acp_rev; + bool is_sdw_dev; + bool is_pdm_dev; + bool is_pdm_config; + bool is_sdw_config; };

int snd_amd_acp_find_config(struct pci_dev *pci); diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index a98407fa2cd2..d360dfc396ad 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -5,6 +5,8 @@ * Copyright 2024 Advanced Micro Devices, Inc. */

+#include <linux/acpi.h> +#include <linux/bitops.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/iopoll.h> @@ -93,6 +95,99 @@ static int acp70_deinit(void __iomem *acp_base, struct device *dev) return 0; }

+#if IS_ENABLED(CONFIG_SND_SOC_AMD_SOUNDWIRE) +static int acp_scan_sdw_devices(struct device *dev, u64 addr) +{ + struct acpi_device *sdw_dev; + struct acp70_dev_data *acp_data; + + acp_data = dev_get_drvdata(dev); + if (!addr) + return -ENODEV; + + sdw_dev = acpi_find_child_device(ACPI_COMPANION(dev), addr, 0); + if (!sdw_dev) { + pr_err("%s No SoundWire devices found\n", __func__); + return -ENODEV; + } + + acp_data->info.handle = sdw_dev->handle; + acp_data->info.count = AMD_SDW_MAX_MANAGERS; + return amd_sdw_scan_controller(&acp_data->info); +} +#else +static int acp_scan_sdw_devices(struct device *dev, u64 addr) +{ + return 0; +} +#endif + +static int get_acp70_device_config(struct pci_dev *pci, struct acp70_dev_data *acp_data) +{ + struct acpi_device *pdm_dev; + const union acpi_object *obj; + u32 config; + int ret; + bool is_dmic_dev = false; + bool is_sdw_dev = false; + + config = readl(acp_data->acp70_base + ACP_PIN_CONFIG); + dev_dbg(&pci->dev, "ACP_PIN_CONFIG:0x%x\n", config); + switch (config) { + case ACP_CONFIG_4: + case ACP_CONFIG_5: + case ACP_CONFIG_10: + case ACP_CONFIG_11: + case ACP_CONFIG_20: + acp_data->is_pdm_config = true; + break; + case ACP_CONFIG_2: + case ACP_CONFIG_3: + case ACP_CONFIG_16: + acp_data->is_sdw_config = true; + break; + case ACP_CONFIG_6: + case ACP_CONFIG_7: + case ACP_CONFIG_12: + case ACP_CONFIG_8: + case ACP_CONFIG_13: + case ACP_CONFIG_14: + case ACP_CONFIG_17: + case ACP_CONFIG_18: + case ACP_CONFIG_19: + acp_data->is_pdm_config = true; + acp_data->is_sdw_config = true; + break; + default: + break; + } + + if (acp_data->is_pdm_config) { + pdm_dev = acpi_find_child_device(ACPI_COMPANION(&pci->dev), ACP70_DMIC_ADDR, 0); + if (pdm_dev) { + /* is_dmic_dev flag will be set when ACP PDM controller device exists */ + if (!acpi_dev_get_property(pdm_dev, "acp-audio-device-type", + ACPI_TYPE_INTEGER, &obj) && + obj->integer.value == ACP_DMIC_DEV) + is_dmic_dev = true; + } + } + + if (acp_data->is_sdw_config) { + ret = acp_scan_sdw_devices(&pci->dev, ACP70_SDW_ADDR); + if (!ret && acp_data->info.link_mask) + is_sdw_dev = true; + } + + acp_data->is_pdm_dev = is_dmic_dev; + acp_data->is_sdw_dev = is_sdw_dev; + dev_dbg(&pci->dev, "is_pdm_dev:%d is_sdw_dev:%d\n", is_dmic_dev, is_sdw_dev); + if (!is_dmic_dev && !is_sdw_dev) { + dev_dbg(&pci->dev, "No PDM or SoundWire manager devices found\n"); + return -ENODEV; + } + return 0; +} static int snd_acp70_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { @@ -148,6 +243,13 @@ static int snd_acp70_probe(struct pci_dev *pci, if (ret) goto release_regions;

+ ret = get_acp70_device_config(pci, adata); + /* ACP PCI driver probe should be continued even PDM or SoundWire Devices are not found */ + if (ret) { + dev_dbg(&pci->dev, "get acp device config failed:%d\n", ret); + goto skip_pdev_creation; + } +skip_pdev_creation: return 0; release_regions: pci_release_regions(pci); @@ -189,4 +291,5 @@ module_pci_driver(ps_acp70_driver);

MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); MODULE_DESCRIPTION("AMD ACP7.0 PCI driver"); +MODULE_IMPORT_NS("SND_AMD_SOUNDWIRE_ACPI"); MODULE_LICENSE("GPL");

Add Config options for ACP7.0 platform and Make file to trigger ACP7.0 driver build.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/Kconfig | 10 ++++++++++ sound/soc/amd/Makefile | 1 + sound/soc/amd/acp70/Makefile | 5 +++++ 3 files changed, 16 insertions(+) create mode 100644 sound/soc/amd/acp70/Makefile

diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig index c7590d4989bb..9d8114909eb5 100644 --- a/sound/soc/amd/Kconfig +++ b/sound/soc/amd/Kconfig @@ -184,4 +184,14 @@ config SND_SOC_AMD_PS_MACH Say m if you have such a device. If unsure select "N".

+config SND_SOC_AMD_ACP70 + tristate "AMD Audio Coprocessor-v7.0 SoundWire support" + select SND_SOC_AMD_SOUNDWIRE_LINK_BASELINE + depends on X86 && PCI && ACPI + help + This option enables Audio Coprocessor i.e ACP v7.0 support. + By enabling this flag build will be triggered for ACP PCI driver. + Say m if you have such a device. + If unsure select "N". + endif diff --git a/sound/soc/amd/Makefile b/sound/soc/amd/Makefile index 4f89d962cce2..d71f74f957ff 100644 --- a/sound/soc/amd/Makefile +++ b/sound/soc/amd/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_SND_AMD_ACP_CONFIG) += acp/ obj-$(CONFIG_SND_AMD_ACP_CONFIG) += snd-acp-config.o obj-$(CONFIG_SND_SOC_AMD_RPL_ACP6x) += rpl/ obj-$(CONFIG_SND_SOC_AMD_PS) += ps/ +obj-$(CONFIG_SND_SOC_AMD_ACP70) += acp70/ diff --git a/sound/soc/amd/acp70/Makefile b/sound/soc/amd/acp70/Makefile new file mode 100644 index 000000000000..5e553de6c772 --- /dev/null +++ b/sound/soc/amd/acp70/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +# ACP 7.0 platform Support +snd-pci-acp70-y := pci-acp70.o + +obj-$(CONFIG_SND_SOC_AMD_ACP70) += snd-pci-acp70.o

Add acp pdm driver dma ops and dai ops for ACP7.0 & ACP7.1 platforms.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70-pdm-dma.c | 319 ++++++++++++++++++++++++++++ sound/soc/amd/acp70/acp70.h | 32 +++ 2 files changed, 351 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70-pdm-dma.c b/sound/soc/amd/acp70/acp70-pdm-dma.c index fd31e31a02a6..197214e68489 100644 --- a/sound/soc/amd/acp70/acp70-pdm-dma.c +++ b/sound/soc/amd/acp70/acp70-pdm-dma.c @@ -18,6 +18,319 @@

#define DRV_NAME "acp70_pdm_dma"

+static int pdm_gain = 3; +module_param(pdm_gain, int, 0644); +MODULE_PARM_DESC(pdm_gain, "Gain control (0-3)"); + +static const struct snd_pcm_hardware acp70_pdm_hardware_capture = { + .info = SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, + .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, + .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, + .periods_min = CAPTURE_MIN_NUM_PERIODS, + .periods_max = CAPTURE_MAX_NUM_PERIODS, +}; + +static void acp70_init_pdm_ring_buffer(u32 physical_addr, u32 buffer_size, + u32 watermark_size, void __iomem *acp_base) +{ + writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR); + writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE); + writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE); + writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL); +} + +static void acp70_enable_pdm_clock(void __iomem *acp_base) +{ + u32 pdm_clk_enable, pdm_ctrl; + + pdm_clk_enable = ACP_PDM_CLK_FREQ_MASK; + pdm_ctrl = 0x00; + + writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL); + pdm_ctrl = readl(acp_base + ACP_WOV_MISC_CTRL); + pdm_ctrl &= ~ACP_WOV_GAIN_CONTROL; + pdm_ctrl |= FIELD_PREP(ACP_WOV_GAIN_CONTROL, clamp(pdm_gain, 0, 3)); + writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL); +} + +static void acp70_enable_pdm_interrupts(struct pdm_dev_data *adata) +{ + u32 ext_int_ctrl; + + mutex_lock(adata->acp_lock); + ext_int_ctrl = readl(adata->acp70_base + ACP_EXTERNAL_INTR_CNTL); + ext_int_ctrl |= PDM_DMA_INTR_MASK; + writel(ext_int_ctrl, adata->acp70_base + ACP_EXTERNAL_INTR_CNTL); + mutex_unlock(adata->acp_lock); +} + +static void acp70_disable_pdm_interrupts(struct pdm_dev_data *adata) +{ + u32 ext_int_ctrl; + + mutex_lock(adata->acp_lock); + ext_int_ctrl = readl(adata->acp70_base + ACP_EXTERNAL_INTR_CNTL); + ext_int_ctrl &= ~PDM_DMA_INTR_MASK; + writel(ext_int_ctrl, adata->acp70_base + ACP_EXTERNAL_INTR_CNTL); + mutex_unlock(adata->acp_lock); +} + +static bool acp70_check_pdm_dma_status(void __iomem *acp_base) +{ + bool pdm_dma_status; + u32 pdm_enable, pdm_dma_enable; + + pdm_dma_status = false; + pdm_enable = readl(acp_base + ACP_WOV_PDM_ENABLE); + pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE); + if ((pdm_enable & ACP_PDM_ENABLE) && (pdm_dma_enable & ACP_PDM_DMA_EN_STATUS)) + pdm_dma_status = true; + + return pdm_dma_status; +} + +static int acp70_start_pdm_dma(void __iomem *acp_base) +{ + u32 pdm_enable; + u32 pdm_dma_enable; + int timeout; + + pdm_enable = 0x01; + pdm_dma_enable = 0x01; + + acp70_enable_pdm_clock(acp_base); + writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE); + writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE); + timeout = 0; + while (++timeout < ACP_COUNTER) { + pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE); + if ((pdm_dma_enable & 0x02) == ACP_PDM_DMA_EN_STATUS) + return 0; + udelay(DELAY_US); + } + return -ETIMEDOUT; +} + +static int acp70_stop_pdm_dma(void __iomem *acp_base) +{ + u32 pdm_enable, pdm_dma_enable; + int timeout; + + pdm_enable = 0x00; + pdm_dma_enable = 0x00; + + pdm_enable = readl(acp_base + ACP_WOV_PDM_ENABLE); + pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE); + if (pdm_dma_enable & 0x01) { + pdm_dma_enable = 0x02; + writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE); + timeout = 0; + while (++timeout < ACP_COUNTER) { + pdm_dma_enable = readl(acp_base + ACP_WOV_PDM_DMA_ENABLE); + if ((pdm_dma_enable & 0x02) == 0x00) + break; + udelay(DELAY_US); + } + if (timeout == ACP_COUNTER) + return -ETIMEDOUT; + } + if (pdm_enable == ACP_PDM_ENABLE) { + pdm_enable = ACP_PDM_DISABLE; + writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE); + } + writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH); + return 0; +} + +static void acp70_config_dma(struct pdm_stream_instance *rtd, int direction) +{ + u16 page_idx; + u32 low, high, val; + dma_addr_t addr; + + addr = rtd->dma_addr; + val = PDM_PTE_OFFSET; + + /* Group Enable */ + writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp70_base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1); + writel(PAGE_SIZE_4K_ENABLE, rtd->acp70_base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1); + for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) { + /* Load the low address of page int ACP SRAM through SRBM */ + low = lower_32_bits(addr); + high = upper_32_bits(addr); + + writel(low, rtd->acp70_base + ACP_SCRATCH_REG_0 + val); + high |= BIT(31); + writel(high, rtd->acp70_base + ACP_SCRATCH_REG_0 + val + 4); + val += 8; + addr += PAGE_SIZE; + } +} + +static int acp70_pdm_dma_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime; + struct pdm_dev_data *adata; + struct pdm_stream_instance *pdm_data; + int ret; + + runtime = substream->runtime; + adata = dev_get_drvdata(component->dev); + pdm_data = kzalloc(sizeof(*pdm_data), GFP_KERNEL); + if (!pdm_data) + return -EINVAL; + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + runtime->hw = acp70_pdm_hardware_capture; + + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) { + dev_err(component->dev, "set integer constraint failed\n"); + kfree(pdm_data); + return ret; + } + + acp70_enable_pdm_interrupts(adata); + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + adata->capture_stream = substream; + + pdm_data->acp70_base = adata->acp70_base; + runtime->private_data = pdm_data; + return ret; +} + +static int acp70_pdm_dma_hw_params(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct pdm_stream_instance *rtd; + size_t size, period_bytes; + + rtd = substream->runtime->private_data; + if (!rtd) + return -EINVAL; + size = params_buffer_bytes(params); + period_bytes = params_period_bytes(params); + rtd->dma_addr = substream->runtime->dma_addr; + rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT); + acp70_config_dma(rtd, substream->stream); + acp70_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, size, + period_bytes, rtd->acp70_base); + return 0; +} + +static u64 acp70_pdm_get_byte_count(struct pdm_stream_instance *rtd, + int direction) +{ + u32 high, low; + u64 byte_count; + + high = readl(rtd->acp70_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH); + byte_count = high; + low = readl(rtd->acp70_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW); + byte_count = (byte_count << 32) | low; + return byte_count; +} + +static snd_pcm_uframes_t acp70_pdm_dma_pointer(struct snd_soc_component *comp, + struct snd_pcm_substream *stream) +{ + struct pdm_stream_instance *rtd; + u32 pos, buffersize; + u64 bytescount; + + rtd = stream->runtime->private_data; + buffersize = frames_to_bytes(stream->runtime, + stream->runtime->buffer_size); + bytescount = acp70_pdm_get_byte_count(rtd, stream->stream); + if (bytescount > rtd->bytescount) + bytescount -= rtd->bytescount; + pos = do_div(bytescount, buffersize); + return bytes_to_frames(stream->runtime, pos); +} + +static int acp70_pdm_dma_new(struct snd_soc_component *component, + struct snd_soc_pcm_runtime *rtd) +{ + struct device *parent = component->dev->parent; + + snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, + parent, MIN_BUFFER, MAX_BUFFER); + return 0; +} + +static int acp70_pdm_dma_close(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + struct pdm_dev_data *adata = dev_get_drvdata(component->dev); + struct snd_pcm_runtime *runtime = substream->runtime; + + acp70_disable_pdm_interrupts(adata); + adata->capture_stream = NULL; + kfree(runtime->private_data); + return 0; +} + +static int acp70_pdm_dai_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct pdm_stream_instance *rtd; + int ret; + bool pdm_status; + unsigned int ch_mask; + + rtd = substream->runtime->private_data; + ret = 0; + switch (substream->runtime->channels) { + case TWO_CH: + ch_mask = 0x00; + break; + default: + return -EINVAL; + } + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + writel(ch_mask, rtd->acp70_base + ACP_WOV_PDM_NO_OF_CHANNELS); + writel(PDM_DECIMATION_FACTOR, rtd->acp70_base + ACP_WOV_PDM_DECIMATION_FACTOR); + rtd->bytescount = acp70_pdm_get_byte_count(rtd, substream->stream); + pdm_status = acp70_check_pdm_dma_status(rtd->acp70_base); + if (!pdm_status) + ret = acp70_start_pdm_dma(rtd->acp70_base); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + pdm_status = acp70_check_pdm_dma_status(rtd->acp70_base); + if (pdm_status) + ret = acp70_stop_pdm_dma(rtd->acp70_base); + break; + default: + ret = -EINVAL; + break; + } + return ret; +} + +static const struct snd_soc_dai_ops acp70_pdm_dai_ops = { + .trigger = acp70_pdm_dai_trigger, +}; + static struct snd_soc_dai_driver acp70_pdm_dai_driver = { .name = "acp_acp70_pdm_dma.0", .capture = { @@ -28,10 +341,16 @@ static struct snd_soc_dai_driver acp70_pdm_dai_driver = { .rate_min = 48000, .rate_max = 48000, }, + .ops = &acp70_pdm_dai_ops, };

static const struct snd_soc_component_driver acp70_pdm_component = { .name = DRV_NAME, + .open = acp70_pdm_dma_open, + .close = acp70_pdm_dma_close, + .hw_params = acp70_pdm_dma_hw_params, + .pointer = acp70_pdm_dma_pointer, + .pcm_construct = acp70_pdm_dma_new, };

static int acp70_pdm_audio_probe(struct platform_device *pdev) diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index c7cabb98cc1a..d6c99d43ed4f 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -34,6 +34,30 @@ #define ACP70_SDW_ADDR 5 #define AMD_SDW_MAX_MANAGERS 2

+#define PDM_DMA_STAT 0x10 +#define PDM_DMA_INTR_MASK 0x10000 +#define ACP_ERROR_STAT 29 +#define PDM_DECIMATION_FACTOR 2 +#define ACP_PDM_CLK_FREQ_MASK 7 +#define ACP_WOV_GAIN_CONTROL GENMASK(4, 3) +#define ACP_PDM_ENABLE 1 +#define ACP_PDM_DISABLE 0 +#define ACP_PDM_DMA_EN_STATUS 2 +#define TWO_CH 2 + +#define ACP_SRAM_PTE_OFFSET 0x03800000 +#define PAGE_SIZE_4K_ENABLE 2 +#define PDM_PTE_OFFSET 0 +#define PDM_MEM_WINDOW_START 0x4000000 + +#define CAPTURE_MIN_NUM_PERIODS 4 +#define CAPTURE_MAX_NUM_PERIODS 4 +#define CAPTURE_MAX_PERIOD_SIZE 8192 +#define CAPTURE_MIN_PERIOD_SIZE 4096 + +#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS) +#define MIN_BUFFER MAX_BUFFER + enum acp_config { ACP_CONFIG_0 = 0, ACP_CONFIG_1, @@ -58,6 +82,14 @@ enum acp_config { ACP_CONFIG_20, };

+struct pdm_stream_instance { + u16 num_pages; + u16 channels; + dma_addr_t dma_addr; + u64 bytescount; + void __iomem *acp70_base; +}; + struct pdm_dev_data { u32 pdm_irq; void __iomem *acp70_base;

Update Kconfig option description for "SND_SOC_AMD_ACP70".

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig index 9d8114909eb5..57743bc4fcea 100644 --- a/sound/soc/amd/Kconfig +++ b/sound/soc/amd/Kconfig @@ -190,7 +190,8 @@ config SND_SOC_AMD_ACP70 depends on X86 && PCI && ACPI help This option enables Audio Coprocessor i.e ACP v7.0 support. - By enabling this flag build will be triggered for ACP PCI driver. + By enabling this flag build will be triggered for ACP PCI driver, + ACP PDM DMA driver, ACP SoundWire DMA driver. Say m if you have such a device. If unsure select "N".

Add interrupt handler for handling, below listed interrupts for ACP IP. - SoundWire dma driver interrupts - ACP PDM dma driver interrupts - SoundWire manager related interrupts - ACP error interrupts.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70.h | 4 + sound/soc/amd/acp70/pci-acp70.c | 161 +++++++++++++++++++++++++++++++- 2 files changed, 164 insertions(+), 1 deletion(-)

diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index a96b021e64da..d5ab606adedc 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -238,6 +238,8 @@ struct sdw_dma_dev_data { * @addr: pci ioremap address * @reg_range: ACP reigister range * @acp_rev : ACP PCI revision id + * @sdw0-dma_intr_stat: DMA interrupt status array for SoundWire manager-SW0 instance + * @sdw_dma_intr_stat: DMA interrupt status array for SoundWire manager-SW1 instance * @is_sdw_dev: flag set to true when any SoundWire manager instances are available * @is_pdm_dev: flag set to true when ACP PDM controller exists * @is_pdm_config: flat set to true when PDM configuration is selected from BIOS @@ -257,6 +259,8 @@ struct acp70_dev_data { u32 addr; u32 reg_range; u32 acp_rev; + u16 sdw0_dma_intr_stat[ACP70_SDW0_DMA_MAX_STREAMS]; + u16 sdw1_dma_intr_stat[ACP70_SDW1_DMA_MAX_STREAMS]; bool is_sdw_dev; bool is_pdm_dev; bool is_pdm_config; diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index a6812fa269b1..e732a680c092 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -8,11 +8,13 @@ #include <linux/acpi.h> #include <linux/bitops.h> #include <linux/delay.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/platform_device.h> +#include <sound/pcm_params.h> #include "../mach-config.h"

#include "acp70.h" @@ -96,6 +98,155 @@ static int acp70_deinit(void __iomem *acp_base, struct device *dev) return 0; }

+static irqreturn_t acp70_irq_thread(int irq, void *context) +{ + struct sdw_dma_dev_data *sdw_dma_data; + struct acp70_dev_data *adata = context; + u32 stream_index; + + sdw_dma_data = dev_get_drvdata(&adata->sdw_dma_dev->dev); + + for (stream_index = 0; stream_index < ACP70_SDW0_DMA_MAX_STREAMS; stream_index++) { + if (adata->sdw0_dma_intr_stat[stream_index]) { + if (sdw_dma_data->sdw0_dma_stream[stream_index]) + snd_pcm_period_elapsed(sdw_dma_data->sdw0_dma_stream[stream_index]); + adata->sdw0_dma_intr_stat[stream_index] = 0; + } + } + for (stream_index = 0; stream_index < ACP70_SDW1_DMA_MAX_STREAMS; stream_index++) { + if (adata->sdw1_dma_intr_stat[stream_index]) { + if (sdw_dma_data->sdw1_dma_stream[stream_index]) + snd_pcm_period_elapsed(sdw_dma_data->sdw1_dma_stream[stream_index]); + adata->sdw1_dma_intr_stat[stream_index] = 0; + } + } + return IRQ_HANDLED; +} + +static irqreturn_t acp70_irq_handler(int irq, void *dev_id) +{ + struct acp70_dev_data *adata; + struct pdm_dev_data *ps_pdm_data; + struct amd_sdw_manager *amd_manager; + u32 ext_intr_stat, ext_intr_stat1; + u32 stream_id = 0; + u16 irq_flag = 0; + u16 sdw_dma_irq_flag = 0; + u16 index; + + adata = dev_id; + if (!adata) + return IRQ_NONE; + /* ACP interrupts will be cleared by reading particular bit and writing + * same value to the status register. writing zero's doesn't have any + * effect. + * Bit by bit checking of IRQ field is implemented. + */ + ext_intr_stat = readl(adata->acp70_base + ACP_EXTERNAL_INTR_STAT); + if (ext_intr_stat & ACP_SDW0_STAT) { + writel(ACP_SDW0_STAT, adata->acp70_base + ACP_EXTERNAL_INTR_STAT); + amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); + if (amd_manager) + schedule_work(&amd_manager->amd_sdw_irq_thread); + irq_flag = 1; + } + + ext_intr_stat1 = readl(adata->acp70_base + ACP_EXTERNAL_INTR_STAT1); + if (ext_intr_stat1 & ACP_SDW1_STAT) { + writel(ACP_SDW1_STAT, adata->acp70_base + ACP_EXTERNAL_INTR_STAT1); + amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); + if (amd_manager) + schedule_work(&amd_manager->amd_sdw_irq_thread); + irq_flag = 1; + } + + if (ext_intr_stat & ACP_ERROR_IRQ) { + writel(ACP_ERROR_IRQ, adata->acp70_base + ACP_EXTERNAL_INTR_STAT); + writel(0, adata->acp70_base + ACP_SW0_I2S_ERROR_REASON); + writel(0, adata->acp70_base + ACP_SW1_I2S_ERROR_REASON); + writel(0, adata->acp70_base + ACP_ERROR_STATUS); + irq_flag = 1; + } + + if (ext_intr_stat & BIT(PDM_DMA_STAT)) { + ps_pdm_data = dev_get_drvdata(&adata->pdm_dev->dev); + writel(BIT(PDM_DMA_STAT), adata->acp70_base + ACP_EXTERNAL_INTR_STAT); + if (ps_pdm_data->capture_stream) + snd_pcm_period_elapsed(ps_pdm_data->capture_stream); + irq_flag = 1; + } + + if (ext_intr_stat & ACP_SDW_DMA_IRQ_MASK) { + for (index = ACP_AUDIO2_RX_THRESHOLD; index <= ACP_AUDIO0_TX_THRESHOLD; index++) { + if (ext_intr_stat & BIT(index)) { + writel(BIT(index), adata->acp70_base + ACP_EXTERNAL_INTR_STAT); + switch (index) { + case ACP_AUDIO0_TX_THRESHOLD: + stream_id = ACP_SDW0_AUDIO0_TX; + break; + case ACP_AUDIO1_TX_THRESHOLD: + stream_id = ACP_SDW0_AUDIO1_TX; + break; + case ACP_AUDIO2_TX_THRESHOLD: + stream_id = ACP_SDW0_AUDIO2_TX; + break; + case ACP_AUDIO0_RX_THRESHOLD: + stream_id = ACP_SDW0_AUDIO0_RX; + break; + case ACP_AUDIO1_RX_THRESHOLD: + stream_id = ACP_SDW0_AUDIO1_RX; + break; + case ACP_AUDIO2_RX_THRESHOLD: + stream_id = ACP_SDW0_AUDIO2_RX; + break; + } + + adata->sdw0_dma_intr_stat[stream_id] = 1; + sdw_dma_irq_flag = 1; + } + } + } + + if (ext_intr_stat1 & ACP_P1_SDW_DMA_IRQ_MASK) { + for (index = ACP_P1_AUDIO2_RX_THRESHOLD; index <= ACP_P1_AUDIO0_TX_THRESHOLD; index++) { + if (ext_intr_stat1 & BIT(index)) { + writel(BIT(index), adata->acp70_base + ACP_EXTERNAL_INTR_STAT1); + switch (index) { + case ACP_P1_AUDIO0_TX_THRESHOLD: + stream_id = ACP_SDW1_AUDIO0_TX; + break; + case ACP_P1_AUDIO1_TX_THRESHOLD: + stream_id = ACP_SDW1_AUDIO1_TX; + break; + case ACP_P1_AUDIO2_TX_THRESHOLD: + stream_id = ACP_SDW1_AUDIO2_TX; + break; + case ACP_P1_AUDIO0_RX_THRESHOLD: + stream_id = ACP_SDW1_AUDIO0_RX; + break; + case ACP_P1_AUDIO1_RX_THRESHOLD: + stream_id = ACP_SDW1_AUDIO1_RX; + break; + case ACP_P1_AUDIO2_RX_THRESHOLD: + stream_id = ACP_SDW1_AUDIO2_RX; + break; + } + + adata->sdw1_dma_intr_stat[stream_id] = 1; + sdw_dma_irq_flag = 1; + } + } + } + + if (sdw_dma_irq_flag) + return IRQ_WAKE_THREAD; + + if (irq_flag) + return IRQ_HANDLED; + else + return IRQ_NONE; +} + #if IS_ENABLED(CONFIG_SND_SOC_AMD_SOUNDWIRE) static int acp_scan_sdw_devices(struct device *dev, u64 addr) { @@ -333,8 +484,11 @@ static int snd_acp70_probe(struct pci_dev *pci, { struct acp70_dev_data *adata; u32 addr, flag; + u32 irqflags; int ret;

+ irqflags = IRQF_SHARED; + /* Return if acp config flag is defined */ flag = snd_amd_acp_find_config(pci); if (flag) @@ -382,7 +536,12 @@ static int snd_acp70_probe(struct pci_dev *pci, ret = acp70_init(adata->acp70_base, &pci->dev); if (ret) goto release_regions; - + ret = devm_request_threaded_irq(&pci->dev, pci->irq, acp70_irq_handler, + acp70_irq_thread, irqflags, "ACP_PCI_IRQ", adata); + if (ret) { + dev_err(&pci->dev, "ACP PCI IRQ request failed\n"); + goto de_init; + } ret = get_acp70_device_config(pci, adata); /* ACP PCI driver probe should be continued even PDM or SoundWire Devices are not found */ if (ret) {

Add pm ops support for SoundWire dma driver for ACP7.0 and ACP7.1 platforms.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70-sdw-dma.c | 92 +++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70-sdw-dma.c b/sound/soc/amd/acp70/acp70-sdw-dma.c index 2c01f60cf3b9..183db176725f 100644 --- a/sound/soc/amd/acp70/acp70-sdw-dma.c +++ b/sound/soc/amd/acp70/acp70-sdw-dma.c @@ -13,6 +13,7 @@ #include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/soc-dai.h> +#include <linux/pm_runtime.h> #include <linux/soundwire/sdw_amd.h> #include "acp70.h"

@@ -128,6 +129,29 @@ static const struct snd_pcm_hardware acp70_sdw_hardware_capture = { .periods_max = SDW_CAPTURE_MAX_NUM_PERIODS, };

+static void acp70_enable_disable_sdw_dma_interrupts(void __iomem *acp_base, bool enable) +{ + u32 ext_intr_cntl, ext_intr_cntl1; + u32 irq_mask = ACP_SDW_DMA_IRQ_MASK; + u32 irq_mask1 = ACP_P1_SDW_DMA_IRQ_MASK; + + if (enable) { + ext_intr_cntl = readl(acp_base + ACP_EXTERNAL_INTR_CNTL); + ext_intr_cntl |= irq_mask; + writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL); + ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1); + ext_intr_cntl1 |= irq_mask1; + writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1); + } else { + ext_intr_cntl = readl(acp_base + ACP_EXTERNAL_INTR_CNTL); + ext_intr_cntl &= ~irq_mask; + writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL); + ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1); + ext_intr_cntl1 &= ~irq_mask1; + writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1); + } +} + static void acp70_config_dma(struct acp_sdw_dma_stream *stream, void __iomem *acp_base, u32 stream_id) { @@ -476,13 +500,81 @@ static int acp70_sdw_platform_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Fail to register sdw dma component\n"); return status; } + pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); return 0; }

+static void acp70_sdw_platform_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); +} + +static int acp_restore_sdw_dma_config(struct sdw_dma_dev_data *sdw_data) +{ + struct acp_sdw_dma_stream *stream; + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + u32 period_bytes, buf_size, water_mark_size_reg; + u32 stream_count; + int index, instance, ret; + + for (instance = 0; instance < AMD_SDW_MAX_MANAGERS; instance++) { + if (instance == ACP_SDW0) + stream_count = ACP70_SDW0_DMA_MAX_STREAMS; + else + stream_count = ACP70_SDW1_DMA_MAX_STREAMS; + + for (index = 0; index < stream_count; index++) { + if (instance == ACP_SDW0) { + substream = sdw_data->sdw0_dma_stream[index]; + water_mark_size_reg = + sdw0_dma_ring_buf_reg[index].water_mark_size_reg; + } else { + substream = sdw_data->sdw1_dma_stream[index]; + water_mark_size_reg = + sdw1_dma_ring_buf_reg[index].water_mark_size_reg; + } + + if (substream && substream->runtime) { + runtime = substream->runtime; + stream = runtime->private_data; + period_bytes = frames_to_bytes(runtime, runtime->period_size); + buf_size = frames_to_bytes(runtime, runtime->buffer_size); + acp70_config_dma(stream, sdw_data->acp_base, index); + ret = acp70_configure_sdw_ringbuffer(sdw_data->acp_base, index, + buf_size, instance); + if (ret) + return ret; + writel(period_bytes, sdw_data->acp_base + water_mark_size_reg); + } + } + } + acp70_enable_disable_sdw_dma_interrupts(sdw_data->acp_base, true); + return 0; +} + +static int __maybe_unused acp70_sdw_pcm_resume(struct device *dev) +{ + struct sdw_dma_dev_data *sdw_data; + + sdw_data = dev_get_drvdata(dev); + return acp_restore_sdw_dma_config(sdw_data); +} + +static const struct dev_pm_ops acp70_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(NULL, acp70_sdw_pcm_resume) +}; + static struct platform_driver acp70_sdw_dma_driver = { .probe = acp70_sdw_platform_probe, + .remove = acp70_sdw_platform_remove, .driver = { .name = "amd_acp70_sdw_dma", + .pm = &acp70_pm_ops, }, };

Enable wake capability for acp pci driver for ACP7.0 & ACP7.1 platforms.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/pci-acp70.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index 3cca18612ef1..5e0f7bb68eb8 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -555,6 +555,7 @@ static int snd_acp70_probe(struct pci_dev *pci, goto de_init; } skip_pdev_creation: + device_set_wakeup_enable(&pci->dev, true); pm_runtime_set_autosuspend_delay(&pci->dev, ACP_SUSPEND_DELAY_MS); pm_runtime_use_autosuspend(&pci->dev); pm_runtime_put_noidle(&pci->dev);

Add SoundWire machine register logic for ACP7.0 platform to create device node for SoundWire machine driver.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70.h | 4 ++ sound/soc/amd/acp70/pci-acp70.c | 72 +++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index 9774db1ac537..c7dec130f27f 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -239,9 +239,11 @@ struct sdw_dma_dev_data { * @pdm_dev: ACP PDM controller platform device * @dmic_codec: platform device for DMIC Codec * sdw_dma_dev: platform device for SoundWire DMA controller + * @mach_dev: platform device for machine driver to support ACP PDM/SoundWire configuration * @acp_lock: used to protect acp common registers * @info: SoundWire AMD information found in ACPI tables * @sdw: SoundWire context for all SoundWire manager instances + * @machine: ACPI machines for SoundWire interface * @addr: pci ioremap address * @reg_range: ACP reigister range * @acp_rev : ACP PCI revision id @@ -260,10 +262,12 @@ struct acp70_dev_data { struct platform_device *pdm_dev; struct platform_device *dmic_codec_dev; struct platform_device *sdw_dma_dev; + struct platform_device *mach_dev; struct mutex acp_lock; /* protect shared registers */ struct sdw_amd_acpi_info info; /* sdw context allocated by SoundWire driver */ struct sdw_amd_ctx *sdw; + struct snd_soc_acpi_mach *machines; u32 addr; u32 reg_range; u32 acp_rev; diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index 6884e8516a2c..ae19187fe695 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -317,6 +317,42 @@ static int amd_sdw_exit(struct acp70_dev_data *acp_data)

return 0; } + +static struct snd_soc_acpi_mach *acp70_sdw_machine_select(struct device *dev) +{ + struct snd_soc_acpi_mach *mach; + const struct snd_soc_acpi_link_adr *link; + struct acp70_dev_data *acp_data = dev_get_drvdata(dev); + int ret, i; + + if (acp_data->info.count) { + ret = sdw_amd_get_slave_info(acp_data->sdw); + if (ret) { + dev_dbg(dev, "failed to read slave information\n"); + return NULL; + } + for (mach = acp_data->machines; mach; mach++) { + if (!mach->links) + break; + link = mach->links; + for (i = 0; i < acp_data->info.count && link->num_adr; link++, i++) { + if (!snd_soc_acpi_sdw_link_slaves_found(dev, link, + acp_data->sdw->peripherals)) + break; + } + if (i == acp_data->info.count || !link->num_adr) + break; + } + if (mach && mach->link_mask) { + mach->mach_params.links = mach->links; + mach->mach_params.link_mask = mach->link_mask; + mach->mach_params.subsystem_rev = acp_data->acp_rev; + return mach; + } + } + dev_dbg(dev, "No SoundWire machine driver found\n"); + return NULL; +} #else static int acp_scan_sdw_devices(struct device *dev, u64 addr) { @@ -332,8 +368,36 @@ static int amd_sdw_exit(struct acp70_dev_data *acp_data) { return 0; } + +static struct snd_soc_acpi_mach *acp70_sdw_machine_select(struct device *dev) +{ + return NULL; +} #endif

+static int acp70_machine_register(struct device *dev) +{ + struct snd_soc_acpi_mach *mach; + struct acp70_dev_data *adata = dev_get_drvdata(dev); + int size; + + if (adata->is_sdw_dev && adata->is_sdw_config) { + size = sizeof(*adata->machines); + mach = acp70_sdw_machine_select(dev); + if (mach) { + adata->mach_dev = platform_device_register_data(dev, mach->drv_name, + PLATFORM_DEVID_NONE, mach, + size); + if (IS_ERR(adata->mach_dev)) { + dev_err(dev, + "cannot register Machine device for SoundWire Interface\n"); + return PTR_ERR(adata->mach_dev); + } + } + } + return 0; +} + static int get_acp70_device_config(struct pci_dev *pci, struct acp70_dev_data *acp_data) { struct acpi_device *pdm_dev; @@ -570,6 +634,12 @@ static int snd_acp70_probe(struct pci_dev *pci, dev_err(&pci->dev, "ACP platform devices creation failed\n"); goto de_init; } + ret = acp70_machine_register(&pci->dev); + if (ret) { + dev_err(&pci->dev, "ACP machine register failed\n"); + goto de_init; + } + skip_pdev_creation: device_set_wakeup_enable(&pci->dev, true); pm_runtime_set_autosuspend_delay(&pci->dev, ACP_SUSPEND_DELAY_MS); @@ -698,6 +768,8 @@ static void snd_acp70_remove(struct pci_dev *pci) platform_device_unregister(adata->pdm_dev); platform_device_unregister(adata->dmic_codec_dev); } + if (adata->mach_dev) + platform_device_unregister(adata->mach_dev); ret = acp70_deinit(adata->acp70_base, &pci->dev); if (ret) dev_err(&pci->dev, "ACP de-init failed\n");

Add support for corresponding codecs on ACP7.0 platform hardware configuration.

SDW0: RT711 Jack SDW0: RT1316 Left Speaker SDW0: RT1316 Right Speaker SDW1: RT714 DMIC

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/Kconfig | 1 + sound/soc/amd/acp/Makefile | 2 +- sound/soc/amd/acp/amd-acp70-acpi-match.c | 88 ++++++++++++++++++++++++ sound/soc/amd/acp70/pci-acp70.c | 1 + sound/soc/amd/mach-config.h | 1 + 5 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 sound/soc/amd/acp/amd-acp70-acpi-match.c

diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig index 57743bc4fcea..de55fc7642c8 100644 --- a/sound/soc/amd/Kconfig +++ b/sound/soc/amd/Kconfig @@ -187,6 +187,7 @@ config SND_SOC_AMD_PS_MACH config SND_SOC_AMD_ACP70 tristate "AMD Audio Coprocessor-v7.0 SoundWire support" select SND_SOC_AMD_SOUNDWIRE_LINK_BASELINE + select SND_SOC_ACPI_AMD_MATCH depends on X86 && PCI && ACPI help This option enables Audio Coprocessor i.e ACP v7.0 support. diff --git a/sound/soc/amd/acp/Makefile b/sound/soc/amd/acp/Makefile index bb2702036338..7c75892e678b 100644 --- a/sound/soc/amd/acp/Makefile +++ b/sound/soc/amd/acp/Makefile @@ -22,7 +22,7 @@ snd-acp70-y := acp70.o snd-acp-mach-y := acp-mach-common.o snd-acp-legacy-mach-y := acp-legacy-mach.o acp3x-es83xx/acp3x-es83xx.o snd-acp-sof-mach-y := acp-sof-mach.o -snd-soc-acpi-amd-match-y := amd-acp63-acpi-match.o +snd-soc-acpi-amd-match-y := amd-acp63-acpi-match.o amd-acp70-acpi-match.o snd-acp-sdw-mach-y := acp-sdw-mach-common.o snd-acp-sdw-sof-mach-y += acp-sdw-sof-mach.o snd-acp-sdw-legacy-mach-y += acp-sdw-legacy-mach.o diff --git a/sound/soc/amd/acp/amd-acp70-acpi-match.c b/sound/soc/amd/acp/amd-acp70-acpi-match.c new file mode 100644 index 000000000000..1f30adb6c02a --- /dev/null +++ b/sound/soc/amd/acp/amd-acp70-acpi-match.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * amd-acp70-acpi-match.c - tables and support for ACP 7.0 platform + * ACPI enumeration. + * + * Copyright 2024 Advanced Micro Devices, Inc. + */ + +#include <sound/soc-acpi.h> +#include "../mach-config.h" + +static const struct snd_soc_acpi_endpoint single_endpoint = { + .num = 0, + .aggregated = 0, + .group_position = 0, + .group_id = 0 +}; + +static const struct snd_soc_acpi_endpoint spk_l_endpoint = { + .num = 0, + .aggregated = 1, + .group_position = 0, + .group_id = 1 +}; + +static const struct snd_soc_acpi_endpoint spk_r_endpoint = { + .num = 0, + .aggregated = 1, + .group_position = 1, + .group_id = 1 +}; + +static const struct snd_soc_acpi_adr_device rt711_rt1316_group_adr[] = { + { + .adr = 0x000030025D071101ull, + .num_endpoints = 1, + .endpoints = &single_endpoint, + .name_prefix = "rt711" + }, + { + .adr = 0x000030025D131601ull, + .num_endpoints = 1, + .endpoints = &spk_l_endpoint, + .name_prefix = "rt1316-1" + }, + { + .adr = 0x000032025D131601ull, + .num_endpoints = 1, + .endpoints = &spk_r_endpoint, + .name_prefix = "rt1316-2" + }, +}; + +static const struct snd_soc_acpi_adr_device rt714_adr[] = { + { + .adr = 0x130025d071401ull, + .num_endpoints = 1, + .endpoints = &single_endpoint, + .name_prefix = "rt714" + } +}; + +static const struct snd_soc_acpi_link_adr acp70_4_in_1_sdca[] = { + { .mask = BIT(0), + .num_adr = ARRAY_SIZE(rt711_rt1316_group_adr), + .adr_d = rt711_rt1316_group_adr, + }, + { + .mask = BIT(1), + .num_adr = ARRAY_SIZE(rt714_adr), + .adr_d = rt714_adr, + }, + {} +}; + +struct snd_soc_acpi_mach snd_soc_acpi_amd_acp70_sdw_machines[] = { + { + .link_mask = BIT(0) | BIT(1), + .links = acp70_4_in_1_sdca, + .drv_name = "amd_sdw", + }, + {}, +}; +EXPORT_SYMBOL(snd_soc_acpi_amd_acp70_sdw_machines); + +MODULE_DESCRIPTION("AMD ACP7.0 tables and support for ACPI enumeration"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index ae19187fe695..d873e90e16d1 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -611,6 +611,7 @@ static int snd_acp70_probe(struct pci_dev *pci, adata->addr = addr; adata->reg_range = ACP70_REG_END - ACP70_REG_START; adata->acp_rev = pci->revision; + adata->machines = snd_soc_acpi_amd_acp70_sdw_machines; pci_set_master(pci); pci_set_drvdata(pci, adata); mutex_init(&adata->acp_lock); diff --git a/sound/soc/amd/mach-config.h b/sound/soc/amd/mach-config.h index a86c76f781f9..fdf016a64bbf 100644 --- a/sound/soc/amd/mach-config.h +++ b/sound/soc/amd/mach-config.h @@ -26,6 +26,7 @@ extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_sof_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_sdw_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_sof_sdw_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp70_sof_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp70_sdw_machines[];

struct config_entry { u32 flags;