Add ACP IP register header file for ACP7.0 platform.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- include/sound/acp70_chip_offset_byte.h | 484 +++++++++++++++++++++++++ 1 file changed, 484 insertions(+) create mode 100644 include/sound/acp70_chip_offset_byte.h

diff --git a/include/sound/acp70_chip_offset_byte.h b/include/sound/acp70_chip_offset_byte.h new file mode 100644 index 000000000000..c0d51a0e012e --- /dev/null +++ b/include/sound/acp70_chip_offset_byte.h @@ -0,0 +1,484 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AMD ACP 7.0 Register Documentation + * + * Copyright 2024 Advanced Micro Devices, Inc. + */ + +#ifndef _acp_ip_OFFSET_HEADER +#define _acp_ip_OFFSET_HEADER + +/* Registers from ACP_AXI2AXIATU block */ +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C00 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C04 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C08 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C10 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C14 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C18 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C20 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C24 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C28 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C30 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C34 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C38 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C +#define ACPAXI2AXI_ATU_CTRL 0x0000C40 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C44 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C48 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C50 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C54 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C58 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80 + +/* Registers from ACP_CLKRST block */ +#define ACP_SOFT_RESET 0x0001000 +#define ACP_CONTROL 0x0001004 +#define ACP_STATUS 0x0001008 +#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010 +#define ACP_ZSC_DSP_CTRL 0x0001014 +#define ACP_ZSC_STS 0x0001018 +#define ACP_PGFSM_CONTROL 0x0001024 +#define ACP_PGFSM_STATUS 0x0001028 +#define ACP_CLKMUX_SEL 0x000102C +#define ACP_SW0_48MHZ_CLK_SEL 0x0001030 + +/* Registers from ACP_AON block */ +#define ACP_PME_EN 0x0001400 +#define ACP_DEVICE_STATE 0x0001404 +#define AZ_DEVICE_STATE 0x0001408 +#define SW_DEVICE_STATE 0x0001430 +#define ACP_PIN_CONFIG 0x0001440 +#define ACP_PAD_PULLUP_CTRL 0x0001444 +#define ACP_PAD_PULLDOWN_CTRL 0x0001448 +#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C +#define ACP_PAD_SCHMEN_CTRL 0x0001450 +#define ACP_SW_PAD_KEEPER_EN 0x0001454 +#define ACP_SW0_WAKE_EN 0x0001458 +#define ACP_I2S_WAKE_EN 0x000145C +#define ACP_SW1_WAKE_EN 0x0001460 +#define ACP_PAD_DISABLE_OE_CTRL 0x0001468 + +/* Registers from ACP_MISC block */ +#define ACP_SW0_I2S_ERROR_REASON 0x00018B4 +#define ACP_SW0_POS_TRACK_AUDIO0_TX_CTRL 0x00018B8 +#define ACP_SW0_AUDIO0_TX_DMA_POS 0x00018BC +#define ACP_SW0_POS_TRACK_AUDIO1_TX_CTRL 0x00018C0 +#define ACP_SW0_AUDIO1_TX_DMA_POS 0x00018C4 +#define ACP_SW0_POS_TRACK_AUDIO2_TX_CTRL 0x00018C8 +#define ACP_SW0_AUDIO2_TX_DMA_POS 0x00018CC +#define ACP_SW0_POS_TRACK_AUDIO0_RX_CTRL 0x00018D0 +#define ACP_SW0_AUDIO0_DMA_POS 0x00018D4 +#define ACP_SW0_POS_TRACK_AUDIO1_RX_CTRL 0x00018D8 +#define ACP_SW0_AUDIO1_RX_DMA_POS 0x00018DC +#define ACP_SW0_POS_TRACK_AUDIO2_RX_CTRL 0x00018E0 +#define ACP_SW0_AUDIO2_RX_DMA_POS 0x00018E4 +#define ACP_ERROR_INTR_MASK1 0x0001974 +#define ACP_ERROR_INTR_MASK2 0x0001978 +#define ACP_ERROR_INTR_MASK3 0x000197C + +/* Registers from ACP_P1_MISC block */ +#define ACP_EXTERNAL_INTR_ENB 0x0001A00 +#define ACP_EXTERNAL_INTR_CNTL 0x0001A04 +#define ACP_EXTERNAL_INTR_CNTL1 0x0001A08 +#define ACP_EXTERNAL_INTR_STAT 0x0001A0C +#define ACP_EXTERNAL_INTR_STAT1 0x0001A10 +#define ACP_ERROR_STATUS 0x0001A4C +#define ACP_SW1_I2S_ERROR_REASON 0x0001A50 +#define ACP_SW1_POS_TRACK_AUDIO0_TX_CTRL 0x0001A6C +#define ACP_SW1_AUDIO0_TX_DMA_POS 0x0001A70 +#define ACP_SW1_POS_TRACK_AUDIO0_RX_CTRL 0x0001A74 +#define ACP_SW1_AUDIO0_RX_DMA_POS 0x0001A78 +#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C +#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80 +#define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84 +#define ACP_SW1_POS_TRACK_AUDIO1_TX_CTRL 0x0001A88 +#define ACP_SW1_AUDIO1_TX_DMA_POS 0x0001A8C +#define ACP_SW1_POS_TRACK_AUDIO2_TX_CTRL 0x0001A90 +#define ACP_SW1_AUDIO2_TX_DMA_POS 0x0001A94 +#define ACP_SW1_POS_TRACK_AUDIO1_RX_CTRL 0x0001A98 +#define ACP_SW1_AUDIO1_RX_DMA_POS 0x0001A9C +#define ACP_SW1_POS_TRACK_AUDIO2_RX_CTRL 0x0001AA0 +#define ACP_SW1_AUDIO2_RX_DMA_POS 0x0001AA4 +#define ACP_ERROR_INTR_MASK4 0x0001AEC +#define ACP_ERROR_INTR_MASK5 0x0001AF0 +#define ACP_ERROR_STATUS1 0x0001B28 + +/* Registers from ACP_AUDIO_BUFFERS block */ +#define ACP_AUDIO0_RX_RINGBUFADDR 0x0002000 +#define ACP_AUDIO0_RX_RINGBUFSIZE 0x0002004 +#define ACP_AUDIO0_RX_LINKPOSITIONCNTR 0x0002008 +#define ACP_AUDIO0_RX_FIFOADDR 0x000200C +#define ACP_AUDIO0_RX_FIFOSIZE 0x0002010 +#define ACP_AUDIO0_RX_DMA_SIZE 0x0002014 +#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0002018 +#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x000201C +#define ACP_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0002020 +#define ACP_AUDIO0_TX_RINGBUFADDR 0x0002024 +#define ACP_AUDIO0_TX_RINGBUFSIZE 0x0002028 +#define ACP_AUDIO0_TX_LINKPOSITIONCNTR 0x000202C +#define ACP_AUDIO0_TX_FIFOADDR 0x0002030 +#define ACP_AUDIO0_TX_FIFOSIZE 0x0002034 +#define ACP_AUDIO0_TX_DMA_SIZE 0x0002038 +#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x000203C +#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0002040 +#define ACP_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0002044 +#define ACP_AUDIO1_RX_RINGBUFADDR 0x0002048 +#define ACP_AUDIO1_RX_RINGBUFSIZE 0x000204C +#define ACP_AUDIO1_RX_LINKPOSITIONCNTR 0x0002050 +#define ACP_AUDIO1_RX_FIFOADDR 0x0002054 +#define ACP_AUDIO1_RX_FIFOSIZE 0x0002058 +#define ACP_AUDIO1_RX_DMA_SIZE 0x000205C +#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0002060 +#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0002064 +#define ACP_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0002068 +#define ACP_AUDIO1_TX_RINGBUFADDR 0x000206C +#define ACP_AUDIO1_TX_RINGBUFSIZE 0x0002070 +#define ACP_AUDIO1_TX_LINKPOSITIONCNTR 0x0002074 +#define ACP_AUDIO1_TX_FIFOADDR 0x0002078 +#define ACP_AUDIO1_TX_FIFOSIZE 0x000207C +#define ACP_AUDIO1_TX_DMA_SIZE 0x0002080 +#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0002084 +#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0002088 +#define ACP_AUDIO1_TX_INTR_WATERMARK_SIZE 0x000208C +#define ACP_AUDIO2_RX_RINGBUFADDR 0x0002090 +#define ACP_AUDIO2_RX_RINGBUFSIZE 0x0002094 +#define ACP_AUDIO2_RX_LINKPOSITIONCNTR 0x0002098 +#define ACP_AUDIO2_RX_FIFOADDR 0x000209C +#define ACP_AUDIO2_RX_FIFOSIZE 0x00020A0 +#define ACP_AUDIO2_RX_DMA_SIZE 0x00020A4 +#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8 +#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x00020AC +#define ACP_AUDIO2_RX_INTR_WATERMARK_SIZE 0x00020B0 +#define ACP_AUDIO2_TX_RINGBUFADDR 0x00020B4 +#define ACP_AUDIO2_TX_RINGBUFSIZE 0x00020B8 +#define ACP_AUDIO2_TX_LINKPOSITIONCNTR 0x00020BC +#define ACP_AUDIO2_TX_FIFOADDR 0x00020C0 +#define ACP_AUDIO2_TX_FIFOSIZE 0x00020C4 +#define ACP_AUDIO2_TX_DMA_SIZE 0x00020C8 +#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC +#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x00020D0 +#define ACP_AUDIO2_TX_INTR_WATERMARK_SIZE 0x00020D4 + +/* Registers from ACP_I2S_TDM block */ +#define ACP_I2STDM_IER 0x0002400 +#define ACP_I2STDM_IRER 0x0002404 +#define ACP_I2STDM_RXFRMT 0x0002408 +#define ACP_I2STDM_ITER 0x000240C +#define ACP_I2STDM_TXFRMT 0x0002410 +#define ACP_I2STDM0_MSTRCLKGEN 0x0002414 +#define ACP_I2STDM1_MSTRCLKGEN 0x0002418 +#define ACP_I2STDM2_MSTRCLKGEN 0x000241C +#define ACP_I2STDM_REFCLKGEN 0x0002420 + +/* Registers from ACP_BT_TDM block */ +#define ACP_BTTDM_IER 0x0002800 +#define ACP_BTTDM_IRER 0x0002804 +#define ACP_BTTDM_RXFRMT 0x0002808 +#define ACP_BTTDM_ITER 0x000280C +#define ACP_BTTDM_TXFRMT 0x0002810 +#define ACP_HSTDM_IER 0x0002814 +#define ACP_HSTDM_IRER 0x0002818 +#define ACP_HSTDM_RXFRMT 0x000281C +#define ACP_HSTDM_ITER 0x0002820 +#define ACP_HSTDM_TXFRMT 0x0002824 + +/* Registers from ACP_WOV block */ +#define ACP_WOV_PDM_ENABLE 0x0002C04 +#define ACP_WOV_PDM_DMA_ENABLE 0x0002C08 +#define ACP_WOV_RX_RINGBUFADDR 0x0002C0C +#define ACP_WOV_RX_RINGBUFSIZE 0x0002C10 +#define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14 +#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18 +#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C +#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20 +#define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24 +#define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28 +#define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C +#define ACP_WOV_PDM_VAD_CTRL 0x0002C30 +#define ACP_WOV_WAKE 0x0002C54 +#define ACP_WOV_BUFFER_STATUS 0x0002C58 +#define ACP_WOV_MISC_CTRL 0x0002C5C +#define ACP_WOV_CLK_CTRL 0x0002C60 +#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64 +#define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68 +#define ACP_PDM_CLKDIV 0x0002C6C + +/* Registers from ACP_SW0_SWCLK block */ +#define ACP_SW0_EN 0x0003000 +#define ACP_SW0_EN_STATUS 0x0003004 +#define ACP_SW0_FRAMESIZE 0x0003008 +#define ACP_SW0_SSP_COUNTER 0x000300C +#define ACP_SW0_AUDIO0_TX_EN 0x0003010 +#define ACP_SW0_AUDIO0_TX_EN_STATUS 0x0003014 +#define ACP_SW0_AUDIO0_TX_FRAME_FORMAT 0x0003018 +#define ACP_SW0_AUDIO0_TX_SAMPLEINTERVAL 0x000301C +#define ACP_SW0_AUDIO0_TX_HCTRL_DP0 0x0003020 +#define ACP_SW0_AUDIO0_TX_HCTRL_DP1 0x0003024 +#define ACP_SW0_AUDIO0_TX_HCTRL_DP2 0x0003028 +#define ACP_SW0_AUDIO0_TX_HCTRL_DP3 0x000302C +#define ACP_SW0_AUDIO0_TX_OFFSET_DP0 0x0003030 +#define ACP_SW0_AUDIO0_TX_OFFSET_DP1 0x0003034 +#define ACP_SW0_AUDIO0_TX_OFFSET_DP2 0x0003038 +#define ACP_SW0_AUDIO0_TX_OFFSET_DP3 0x000303C +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP0 0x0003040 +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP1 0x0003044 +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP2 0x0003048 +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP3 0x000304C +#define ACP_SW0_AUDIO1_TX_EN 0x0003050 +#define ACP_SW0_AUDIO1_TX_EN_STATUS 0x0003054 +#define ACP_SW0_AUDIO1_TX_FRAME_FORMAT 0x0003058 +#define ACP_SW0_AUDIO1_TX_SAMPLEINTERVAL 0x000305C +#define ACP_SW0_AUDIO1_TX_HCTRL 0x0003060 +#define ACP_SW0_AUDIO1_TX_OFFSET 0x0003064 +#define ACP_SW0_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003068 +#define ACP_SW0_AUDIO2_TX_EN 0x000306C +#define ACP_SW0_AUDIO2_TX_EN_STATUS 0x0003070 +#define ACP_SW0_AUDIO2_TX_FRAME_FORMAT 0x0003074 +#define ACP_SW0_AUDIO2_TX_SAMPLEINTERVAL 0x0003078 +#define ACP_SW0_AUDIO2_TX_HCTRL 0x000307C +#define ACP_SW0_AUDIO2_TX_OFFSET 0x0003080 +#define ACP_SW0_AUDIO2_TX_CHANNEL_ENABLE_DP0 0x0003084 +#define ACP_SW0_AUDIO0_RX_EN 0x0003088 +#define ACP_SW0_AUDIO0_RX_EN_STATUS 0x000308C +#define ACP_SW0_AUDIO0_RX_FRAME_FORMAT 0x0003090 +#define ACP_SW0_AUDIO0_RX_SAMPLEINTERVAL 0x0003094 +#define ACP_SW0_AUDIO0_RX_HCTRL_DP0 0x0003098 +#define ACP_SW0_AUDIO0_RX_HCTRL_DP1 0x000309C +#define ACP_SW0_AUDIO0_RX_HCTRL_DP2 0x0003100 +#define ACP_SW0_AUDIO0_RX_HCTRL_DP3 0x0003104 +#define ACP_SW0_AUDIO0_RX_OFFSET_DP0 0x0003108 +#define ACP_SW0_AUDIO0_RX_OFFSET_DP1 0x000310C +#define ACP_SW0_AUDIO0_RX_OFFSET_DP2 0x0003110 +#define ACP_SW0_AUDIO0_RX_OFFSET_DP3 0x0003114 +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP0 0x0003118 +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP1 0x000311C +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP2 0x0003120 +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP3 0x0003124 +#define ACP_SW0_AUDIO1_RX_EN 0x0003128 +#define ACP_SW0_AUDIO1_RX_EN_STATUS 0x000312C +#define ACP_SW0_AUDIO1_RX_FRAME_FORMAT 0x0003130 +#define ACP_SW0_AUDIO1_RX_SAMPLEINTERVAL 0x0003134 +#define ACP_SW0_AUDIO1_RX_HCTRL 0x0003138 +#define ACP_SW0_AUDIO1_RX_OFFSET 0x000313C +#define ACP_SW0_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003140 +#define ACP_SW0_AUDIO2_RX_EN 0x0003144 +#define ACP_SW0_AUDIO2_RX_EN_STATUS 0x0003148 +#define ACP_SW0_AUDIO2_RX_FRAME_FORMAT 0x000314C +#define ACP_SW0_AUDIO2_RX_SAMPLEINTERVAL 0x0003150 +#define ACP_SW0_AUDIO2_RX_HCTRL 0x0003154 +#define ACP_SW0_AUDIO2_RX_OFFSET 0x0003158 +#define ACP_SW0_AUDIO2_RX_CHANNEL_ENABLE_DP0 0x000315C +#define ACP_SW0_BPT_PORT_EN 0x0003160 +#define ACP_SW0_BPT_PORT_EN_STATUS 0x0003164 +#define ACP_SW0_BPT_PORT_FRAME_FORMAT 0x0003168 +#define ACP_SW0_BPT_PORT_SAMPLEINTERVAL 0x000316C +#define ACP_SW0_BPT_PORT_HCTRL 0x0003170 +#define ACP_SW0_BPT_PORT_OFFSET 0x0003174 +#define ACP_SW0_BPT_PORT_CHANNEL_ENABLE 0x0003178 +#define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR 0x000317C +#define ACP_SW0_CLK_RESUME_CTRL 0x0003180 +#define ACP_SW0_CLK_RESUME_DELAY_CNTR 0x0003184 +#define ACP_SW0_BUS_RESET_CTRL 0x0003188 +#define ACP_SW0_PRBS_ERR_STATUS 0x000318C + +/* Registers from ACP_SW0_ACLK block */ +#define ACP_SW0_CORB_BASE_ADDRESS 0x0003200 +#define ACP_SW0_CORB_WRITE_POINTER 0x0003204 +#define ACP_SW0_CORB_READ_POINTER 0x0003208 +#define ACP_SW0_CORB_CONTROL 0x000320C +#define ACP_SW0_CORB_SIZE 0x0003214 +#define ACP_SW0_RIRB_BASE_ADDRESS 0x0003218 +#define ACP_SW0_RIRB_WRITE_POINTER 0x000321C +#define ACP_SW0_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003220 +#define ACP_SW0_RIRB_CONTROL 0x0003224 +#define ACP_SW0_RIRB_SIZE 0x0003228 +#define ACP_SW0_RIRB_FIFO_MIN_THDL 0x000322C +#define ACP_SW0_IMM_CMD_UPPER_WORD 0x0003230 +#define ACP_SW0_IMM_CMD_LOWER_QWORD 0x0003234 +#define ACP_SW0_IMM_RESP_UPPER_WORD 0x0003238 +#define ACP_SW0_IMM_RESP_LOWER_QWORD 0x000323C +#define ACP_SW0_IMM_CMD_STS 0x0003240 +#define ACP_SW0_BRA_BASE_ADDRESS 0x0003244 +#define ACP_SW0_BRA_TRANSFER_SIZE 0x0003248 +#define ACP_SW0_BRA_DMA_BUSY 0x000324C +#define ACP_SW0_BRA_RESP 0x0003250 +#define ACP_SW0_BRA_RESP_FRAME_ADDR 0x0003254 +#define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE 0x0003258 +#define ACP_SW0_STATECHANGE_STATUS_0TO7 0x000325C +#define ACP_SW0_STATECHANGE_STATUS_8TO11 0x0003260 +#define ACP_SW0_STATECHANGE_STATUS_MASK_0TO7 0x0003264 +#define ACP_SW0_STATECHANGE_STATUS_MASK_8TO11 0x0003268 +#define ACP_SW0_CLK_FREQUENCY_CTRL 0x000326C +#define ACP_SW0_ERROR_INTR_MASK 0x0003270 +#define ACP_SW0_PHY_TEST_MODE_DATA_OFF 0x0003274 + +/* Registers from ACP_P1_AUDIO_BUFFERS block */ +#define ACP_P1_AUDIO0_RX_RINGBUFADDR 0x0003A00 +#define ACP_P1_AUDIO0_RX_RINGBUFSIZE 0x0003A04 +#define ACP_P1_AUDIO0_RX_LINKPOSITIONCNTR 0x0003A08 +#define ACP_P1_AUDIO0_RX_FIFOADDR 0x0003A0C +#define ACP_P1_AUDIO0_RX_FIFOSIZE 0x0003A10 +#define ACP_P1_AUDIO0_RX_DMA_SIZE 0x0003A14 +#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18 +#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C +#define ACP_P1_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0003A20 +#define ACP_P1_AUDIO0_TX_RINGBUFADDR 0x0003A24 +#define ACP_P1_AUDIO0_TX_RINGBUFSIZE 0x0003A28 +#define ACP_P1_AUDIO0_TX_LINKPOSITIONCNTR 0x0003A2C +#define ACP_P1_AUDIO0_TX_FIFOADDR 0x0003A30 +#define ACP_P1_AUDIO0_TX_FIFOSIZE 0x0003A34 +#define ACP_P1_AUDIO0_TX_DMA_SIZE 0x0003A38 +#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C +#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0003A40 +#define ACP_P1_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0003A44 +#define ACP_P1_AUDIO1_RX_RINGBUFADDR 0x0003A48 +#define ACP_P1_AUDIO1_RX_RINGBUFSIZE 0x0003A4C +#define ACP_P1_AUDIO1_RX_LINKPOSITIONCNTR 0x0003A50 +#define ACP_P1_AUDIO1_RX_FIFOADDR 0x0003A54 +#define ACP_P1_AUDIO1_RX_FIFOSIZE 0x0003A58 +#define ACP_P1_AUDIO1_RX_DMA_SIZE 0x0003A5C +#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60 +#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0003A64 +#define ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0003A68 +#define ACP_P1_AUDIO1_TX_RINGBUFADDR 0x0003A6C +#define ACP_P1_AUDIO1_TX_RINGBUFSIZE 0x0003A70 +#define ACP_P1_AUDIO1_TX_LINKPOSITIONCNTR 0x0003A74 +#define ACP_P1_AUDIO1_TX_FIFOADDR 0x0003A78 +#define ACP_P1_AUDIO1_TX_FIFOSIZE 0x0003A7C +#define ACP_P1_AUDIO1_TX_DMA_SIZE 0x0003A80 +#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84 +#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0003A88 +#define ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE 0x0003A8C +#define ACP_P1_AUDIO2_RX_RINGBUFADDR 0x0003A90 +#define ACP_P1_AUDIO2_RX_RINGBUFSIZE 0x0003A94 +#define ACP_P1_AUDIO2_RX_LINKPOSITIONCNTR 0x0003A98 +#define ACP_P1_AUDIO2_RX_FIFOADDR 0x0003A9C +#define ACP_P1_AUDIO2_RX_FIFOSIZE 0x0003AA0 +#define ACP_P1_AUDIO2_RX_DMA_SIZE 0x0003AA4 +#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8 +#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC +#define ACP_P1_AUDIO2_RX_INTR_WATERMARK_SIZE 0x0003AB0 +#define ACP_P1_AUDIO2_TX_RINGBUFADDR 0x0003AB4 +#define ACP_P1_AUDIO2_TX_RINGBUFSIZE 0x0003AB8 +#define ACP_P1_AUDIO2_TX_LINKPOSITIONCNTR 0x0003ABC +#define ACP_P1_AUDIO2_TX_FIFOADDR 0x0003AC0 +#define ACP_P1_AUDIO2_TX_FIFOSIZE 0x0003AC4 +#define ACP_P1_AUDIO2_TX_DMA_SIZE 0x0003AC8 +#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC +#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0 +#define ACP_P1_AUDIO2_TX_INTR_WATERMARK_SIZE 0x0003AD4 + +/* Registers from ACP_SW1_SWCLK block */ +#define ACP_SW1_EN 0x0003C00 +#define ACP_SW1_EN_STATUS 0x0003C04 +#define ACP_SW1_FRAMESIZE 0x0003C08 +#define ACP_SW1_SSP_COUNTER 0x0003C0C +#define ACP_SW1_AUDIO0_TX_EN 0x0003C10 +#define ACP_SW1_AUDIO0_TX_EN_STATUS 0x0003C14 +#define ACP_SW1_AUDIO0_TX_FRAME_FORMAT 0x0003C18 +#define ACP_SW1_AUDIO0_TX_SAMPLEINTERVAL 0x0003C1C +#define ACP_SW1_AUDIO0_TX_HCTRL_DP0 0x0003C20 +#define ACP_SW1_AUDIO0_TX_HCTRL_DP1 0x0003C24 +#define ACP_SW1_AUDIO0_TX_OFFSET_DP0 0x0003C30 +#define ACP_SW1_AUDIO0_TX_OFFSET_DP1 0x0003C34 +#define ACP_SW1_AUDIO0_TX_CHANNEL_ENABLE_DP0 0x0003C40 +#define ACP_SW1_AUDIO0_TX_CHANNEL_ENABLE_DP1 0x0003C44 +#define ACP_SW1_AUDIO1_TX_EN 0x0003C50 +#define ACP_SW1_AUDIO1_TX_EN_STATUS 0x0003C54 +#define ACP_SW1_AUDIO1_TX_FRAME_FORMAT 0x0003C58 +#define ACP_SW1_AUDIO1_TX_SAMPLEINTERVAL 0x0003C5C +#define ACP_SW1_AUDIO1_TX_HCTRL 0x0003C60 +#define ACP_SW1_AUDIO1_TX_OFFSET 0x0003C64 +#define ACP_SW1_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003C68 +#define ACP_SW1_AUDIO2_TX_EN 0x0003C6C +#define ACP_SW1_AUDIO2_TX_EN_STATUS 0x0003C70 +#define ACP_SW1_AUDIO2_TX_FRAME_FORMAT 0x0003C74 +#define ACP_SW1_AUDIO2_TX_SAMPLEINTERVAL 0x0003C78 +#define ACP_SW1_AUDIO2_TX_HCTRL 0x0003C7C +#define ACP_SW1_AUDIO2_TX_OFFSET 0x0003C80 +#define ACP_SW1_AUDIO2_TX_CHANNEL_ENABLE_DP0 0x0003C84 +#define ACP_SW1_AUDIO0_RX_EN 0x0003C88 +#define ACP_SW1_AUDIO0_RX_EN_STATUS 0x0003C8C +#define ACP_SW1_AUDIO0_RX_FRAME_FORMAT 0x0003C90 +#define ACP_SW1_AUDIO0_RX_SAMPLEINTERVAL 0x0003C94 +#define ACP_SW1_AUDIO0_RX_HCTRL_DP0 0x0003C98 +#define ACP_SW1_AUDIO0_RX_HCTRL_DP1 0x0003C9C +#define ACP_SW1_AUDIO0_RX_OFFSET_DP0 0x0003D08 +#define ACP_SW1_AUDIO0_RX_OFFSET_DP1 0x0003D0C +#define ACP_SW1_AUDIO0_RX_CHANNEL_ENABLE_DP0 0x0003D18 +#define ACP_SW1_AUDIO0_RX_CHANNEL_ENABLE_DP1 0x0003D1C +#define ACP_SW1_AUDIO1_RX_EN 0x0003D28 +#define ACP_SW1_AUDIO1_RX_EN_STATUS 0x0003D2C +#define ACP_SW1_AUDIO1_RX_FRAME_FORMAT 0x0003D30 +#define ACP_SW1_AUDIO1_RX_SAMPLEINTERVAL 0x0003D34 +#define ACP_SW1_AUDIO1_RX_HCTRL 0x0003D38 +#define ACP_SW1_AUDIO1_RX_OFFSET 0x0003D3C +#define ACP_SW1_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003D40 +#define ACP_SW1_AUDIO2_RX_EN 0x0003D44 +#define ACP_SW1_AUDIO2_RX_EN_STATUS 0x0003D48 +#define ACP_SW1_AUDIO2_RX_FRAME_FORMAT 0x0003D4C +#define ACP_SW1_AUDIO2_RX_SAMPLEINTERVAL 0x0003D50 +#define ACP_SW1_AUDIO2_RX_HCTRL 0x0003D54 +#define ACP_SW1_AUDIO2_RX_OFFSET 0x0003D58 +#define ACP_SW1_AUDIO2_RX_CHANNEL_ENABLE_DP0 0x0003D5C +#define ACP_SW1_BPT_PORT_EN 0x0003D60 +#define ACP_SW1_BPT_PORT_EN_STATUS 0x0003D64 +#define ACP_SW1_BPT_PORT_FRAME_FORMAT 0x0003D68 +#define ACP_SW1_BPT_PORT_SAMPLEINTERVAL 0x0003D6C +#define ACP_SW1_BPT_PORT_HCTRL 0x0003D70 +#define ACP_SW1_BPT_PORT_OFFSET 0x0003D74 +#define ACP_SW1_BPT_PORT_CHANNEL_ENABLE 0x0003D78 +#define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C +#define ACP_SW1_CLK_RESUME_CTRL 0x0003D80 +#define ACP_SW1_CLK_RESUME_DELAY_CNTR 0x0003D84 +#define ACP_SW1_BUS_RESET_CTRL 0x0003D88 +#define ACP_SW1_PRBS_ERR_STATUS 0x0003D8C + +/* Registers from ACP_SW1_ACLK block */ +#define ACP_SW1_CORB_BASE_ADDRESS 0x0003E00 +#define ACP_SW1_CORB_WRITE_POINTER 0x0003E04 +#define ACP_SW1_CORB_READ_POINTER 0x0003E08 +#define ACP_SW1_CORB_CONTROL 0x0003E0C +#define ACP_SW1_CORB_SIZE 0x0003E14 +#define ACP_SW1_RIRB_BASE_ADDRESS 0x0003E18 +#define ACP_SW1_RIRB_WRITE_POINTER 0x0003E1C +#define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20 +#define ACP_SW1_RIRB_CONTROL 0x0003E24 +#define ACP_SW1_RIRB_SIZE 0x0003E28 +#define ACP_SW1_RIRB_FIFO_MIN_THDL 0x0003E2C +#define ACP_SW1_IMM_CMD_UPPER_WORD 0x0003E30 +#define ACP_SW1_IMM_CMD_LOWER_QWORD 0x0003E34 +#define ACP_SW1_IMM_RESP_UPPER_WORD 0x0003E38 +#define ACP_SW1_IMM_RESP_LOWER_QWORD 0x0003E3C +#define ACP_SW1_IMM_CMD_STS 0x0003E40 +#define ACP_SW1_BRA_BASE_ADDRESS 0x0003E44 +#define ACP_SW1_BRA_TRANSFER_SIZE 0x0003E48 +#define ACP_SW1_BRA_DMA_BUSY 0x0003E4C +#define ACP_SW1_BRA_RESP 0x0003E50 +#define ACP_SW1_BRA_RESP_FRAME_ADDR 0x0003E54 +#define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE 0x0003E58 +#define ACP_SW1_STATECHANGE_STATUS_0TO7 0x0003E5C +#define ACP_SW1_STATECHANGE_STATUS_8TO11 0x0003E60 +#define ACP_SW1_STATECHANGE_STATUS_MASK_0TO7 0x0003E64 +#define ACP_SW1_STATECHANGE_STATUS_MASK_8TO11 0x0003E68 +#define ACP_SW1_CLK_FREQUENCY_CTRL 0x0003E6C +#define ACP_SW1_ERROR_INTR_MASK 0x0003E70 +#define ACP_SW1_PHY_TEST_MODE_DATA_OFF 0x0003E74 + +/* Registers from ACP_SCRATCH block */ +#define ACP_SCRATCH_REG_0 0x0010000 + +#endif

Add acp init and deinit functions for ACP7.0 platform.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70.h | 15 ++++++ sound/soc/amd/acp70/pci-acp70.c | 92 +++++++++++++++++++++++++++++++++ 2 files changed, 107 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index 28a46f0c2026..b6f0f75de91d 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -12,6 +12,21 @@ #define ACP70_REG_END 0x125C000 #define ACP70_PCI_REV 0x70 #define ACP71_PCI_REV 0x71 +#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001 +#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x1F +#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0 +#define ACP_PGFSM_STATUS_MASK 0xFF +#define ACP_POWERED_ON 0 +#define ACP_POWER_ON_IN_PROGRESS 1 +#define ACP_POWERED_OFF 2 +#define ACP_POWER_OFF_IN_PROGRESS 3 +#define DELAY_US 5 +#define ACP_COUNTER 20000 +/* time in ms for acp timeout */ +#define ACP_TIMEOUT 2000 + +#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF +#define ACP_ERROR_IRQ BIT(29)

/** * struct acp70_dev_data - acp pci driver context diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index 23e47f619bd7..a98407fa2cd2 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -5,13 +5,94 @@ * Copyright 2024 Advanced Micro Devices, Inc. */

+#include <linux/delay.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/module.h> #include <linux/pci.h> #include "../mach-config.h"

#include "acp70.h"

+static int acp70_power_on(void __iomem *acp_base) +{ + u32 val = 0; + + val = readl(acp_base + ACP_PGFSM_STATUS); + + if (!val) + return 0; + if (val & ACP_PGFSM_STATUS_MASK) + writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL); + + return readl_poll_timeout(acp_base + ACP_PGFSM_STATUS, val, !val, DELAY_US, ACP_TIMEOUT); +} + +static int acp70_reset(void __iomem *acp_base) +{ + u32 val; + int ret; + + writel(1, acp_base + ACP_SOFT_RESET); + + ret = readl_poll_timeout(acp_base + ACP_SOFT_RESET, val, + val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK, + DELAY_US, ACP_TIMEOUT); + if (ret) + return ret; + + writel(0, acp_base + ACP_SOFT_RESET); + + return readl_poll_timeout(acp_base + ACP_SOFT_RESET, val, !val, DELAY_US, ACP_TIMEOUT); +} + +static void acp70_enable_interrupts(void __iomem *acp_base) +{ + writel(1, acp_base + ACP_EXTERNAL_INTR_ENB); + writel(ACP_ERROR_IRQ, acp_base + ACP_EXTERNAL_INTR_CNTL); +} + +static void acp70_disable_interrupts(void __iomem *acp_base) +{ + writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base + ACP_EXTERNAL_INTR_STAT); + writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL); + writel(0, acp_base + ACP_EXTERNAL_INTR_ENB); +} + +static int acp70_init(void __iomem *acp_base, struct device *dev) +{ + int ret; + + ret = acp70_power_on(acp_base); + if (ret) { + dev_err(dev, "ACP power on failed\n"); + return ret; + } + writel(0x01, acp_base + ACP_CONTROL); + ret = acp70_reset(acp_base); + if (ret) { + dev_err(dev, "ACP reset failed\n"); + return ret; + } + writel(0, acp_base + ACP_ZSC_DSP_CTRL); + acp70_enable_interrupts(acp_base); + return 0; +} + +static int acp70_deinit(void __iomem *acp_base, struct device *dev) +{ + int ret; + + acp70_disable_interrupts(acp_base); + ret = acp70_reset(acp_base); + if (ret) { + dev_err(dev, "ACP reset failed\n"); + return ret; + } + writel(0x01, acp_base + ACP_ZSC_DSP_CTRL); + return 0; +} + static int snd_acp70_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { @@ -63,6 +144,10 @@ static int snd_acp70_probe(struct pci_dev *pci, pci_set_master(pci); pci_set_drvdata(pci, adata); mutex_init(&adata->acp_lock); + ret = acp70_init(adata->acp70_base, &pci->dev); + if (ret) + goto release_regions; + return 0; release_regions: pci_release_regions(pci); @@ -74,6 +159,13 @@ static int snd_acp70_probe(struct pci_dev *pci,

static void snd_acp70_remove(struct pci_dev *pci) { + struct acp70_dev_data *adata; + int ret; + + adata = pci_get_drvdata(pci); + ret = acp70_deinit(adata->acp70_base, &pci->dev); + if (ret) + dev_err(&pci->dev, "ACP de-init failed\n"); pci_release_regions(pci); pci_disable_device(pci); }

Create platform devices for ACP child nodes(ACP PDM controller, DMIC codec, SoundWire DMA driver, SoundWire manager instances).

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70.h | 8 ++ sound/soc/amd/acp70/pci-acp70.c | 157 ++++++++++++++++++++++++++++++++ 2 files changed, 165 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index 1b20de75876a..68035fbf23d1 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -61,6 +61,10 @@ enum acp_config { /** * struct acp70_dev_data - acp pci driver context * @acp70_base: acp mmio base + * @res: resource + * @pdm_dev: ACP PDM controller platform device + * @dmic_codec: platform device for DMIC Codec + * sdw_dma_dev: platform device for SoundWire DMA controller * @acp_lock: used to protect acp common registers * @info: SoundWire AMD information found in ACPI tables * @sdw: SoundWire context for all SoundWire manager instances @@ -75,6 +79,10 @@ enum acp_config {

struct acp70_dev_data { void __iomem *acp70_base; + struct resource *res; + struct platform_device *pdm_dev; + struct platform_device *dmic_codec_dev; + struct platform_device *sdw_dma_dev; struct mutex acp_lock; /* protect shared registers */ struct sdw_amd_acpi_info info; /* sdw context allocated by SoundWire driver */ diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index d360dfc396ad..a6812fa269b1 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -12,6 +12,7 @@ #include <linux/iopoll.h> #include <linux/module.h> #include <linux/pci.h> +#include <linux/platform_device.h> #include "../mach-config.h"

#include "acp70.h" @@ -115,11 +116,54 @@ static int acp_scan_sdw_devices(struct device *dev, u64 addr) acp_data->info.count = AMD_SDW_MAX_MANAGERS; return amd_sdw_scan_controller(&acp_data->info); } + +static int amd_sdw_probe(struct device *dev) +{ + struct acp70_dev_data *acp_data; + struct sdw_amd_res sdw_res; + int ret; + + acp_data = dev_get_drvdata(dev); + memset(&sdw_res, 0, sizeof(sdw_res)); + sdw_res.addr = acp_data->addr; + sdw_res.reg_range = acp_data->reg_range; + sdw_res.handle = acp_data->info.handle; + sdw_res.parent = dev; + sdw_res.dev = dev; + sdw_res.acp_lock = &acp_data->acp_lock; + sdw_res.count = acp_data->info.count; + sdw_res.mmio_base = acp_data->acp70_base; + sdw_res.link_mask = acp_data->info.link_mask; + sdw_res.acp_rev = acp_data->acp_rev; + ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); + if (ret) + dev_err(dev, "error: SoundWire probe failed\n"); + return ret; +} + +static int amd_sdw_exit(struct acp70_dev_data *acp_data) +{ + if (acp_data->sdw) + sdw_amd_exit(acp_data->sdw); + acp_data->sdw = NULL; + + return 0; +} #else static int acp_scan_sdw_devices(struct device *dev, u64 addr) { return 0; } + +static int amd_sdw_probe(struct device *dev) +{ + return 0; +} + +static int amd_sdw_exit(struct acp70_dev_data *acp_data) +{ + return 0; +} #endif

static int get_acp70_device_config(struct pci_dev *pci, struct acp70_dev_data *acp_data) @@ -188,6 +232,102 @@ static int get_acp70_device_config(struct pci_dev *pci, struct acp70_dev_data *a } return 0; } + +static void acp70_fill_platform_dev_info(struct platform_device_info *pdevinfo, + struct device *parent, + struct fwnode_handle *fw_node, + char *name, unsigned int id, + const struct resource *res, + unsigned int num_res, + const void *data, + size_t size_data) +{ + pdevinfo->name = name; + pdevinfo->id = id; + pdevinfo->parent = parent; + pdevinfo->num_res = num_res; + pdevinfo->res = res; + pdevinfo->data = data; + pdevinfo->size_data = size_data; + pdevinfo->fwnode = fw_node; +} + +static int create_acp70_platform_devs(struct pci_dev *pci, struct acp70_dev_data *adata, u32 addr) +{ + struct platform_device_info pdevinfo; + struct device *parent; + int ret; + + parent = &pci->dev; + + if (adata->is_sdw_dev || adata->is_pdm_dev) { + adata->res = devm_kzalloc(&pci->dev, sizeof(struct resource), GFP_KERNEL); + if (!adata->res) { + ret = -ENOMEM; + goto de_init; + } + adata->res->flags = IORESOURCE_MEM; + adata->res->start = addr; + adata->res->end = addr + (ACP70_REG_END - ACP70_REG_START); + memset(&pdevinfo, 0, sizeof(pdevinfo)); + } + + if (adata->is_pdm_dev && adata->is_pdm_config) { + acp70_fill_platform_dev_info(&pdevinfo, parent, NULL, "acp70_pdm_dma", + 0, adata->res, 1, NULL, 0); + + adata->pdm_dev = platform_device_register_full(&pdevinfo); + if (IS_ERR(adata->pdm_dev)) { + dev_err(&pci->dev, + "cannot register %s device\n", pdevinfo.name); + ret = PTR_ERR(adata->pdm_dev); + goto de_init; + } + memset(&pdevinfo, 0, sizeof(pdevinfo)); + acp70_fill_platform_dev_info(&pdevinfo, parent, NULL, "dmic-codec", + 0, NULL, 0, NULL, 0); + adata->dmic_codec_dev = platform_device_register_full(&pdevinfo); + if (IS_ERR(adata->dmic_codec_dev)) { + dev_err(&pci->dev, + "cannot register %s device\n", pdevinfo.name); + ret = PTR_ERR(adata->dmic_codec_dev); + goto unregister_pdm_dev; + } + } + if (adata->is_sdw_dev && adata->is_sdw_config) { + ret = amd_sdw_probe(&pci->dev); + if (ret) { + if (adata->is_pdm_dev) + goto unregister_dmic_codec_dev; + else + goto de_init; + } + memset(&pdevinfo, 0, sizeof(pdevinfo)); + acp70_fill_platform_dev_info(&pdevinfo, parent, NULL, "amd_acp70_sdw_dma", + 0, adata->res, 1, NULL, 0); + + adata->sdw_dma_dev = platform_device_register_full(&pdevinfo); + if (IS_ERR(adata->sdw_dma_dev)) { + dev_err(&pci->dev, + "cannot register %s device\n", pdevinfo.name); + ret = PTR_ERR(adata->sdw_dma_dev); + if (adata->is_pdm_dev) + goto unregister_dmic_codec_dev; + else + goto de_init; + } + } + return 0; +unregister_dmic_codec_dev: + platform_device_unregister(adata->dmic_codec_dev); +unregister_pdm_dev: + platform_device_unregister(adata->pdm_dev); +de_init: + if (acp70_deinit(adata->acp70_base, &pci->dev)) + dev_err(&pci->dev, "ACP de-init failed\n"); + return ret; +} + static int snd_acp70_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { @@ -249,8 +389,16 @@ static int snd_acp70_probe(struct pci_dev *pci, dev_dbg(&pci->dev, "get acp device config failed:%d\n", ret); goto skip_pdev_creation; } + ret = create_acp70_platform_devs(pci, adata, addr); + if (ret < 0) { + dev_err(&pci->dev, "ACP platform devices creation failed\n"); + goto de_init; + } skip_pdev_creation: return 0; +de_init: + if (acp70_deinit(adata->acp70_base, &pci->dev)) + dev_err(&pci->dev, "ACP de-init failed\n"); release_regions: pci_release_regions(pci); disable_pci: @@ -265,6 +413,14 @@ static void snd_acp70_remove(struct pci_dev *pci) int ret;

adata = pci_get_drvdata(pci); + if (adata->sdw) { + amd_sdw_exit(adata); + platform_device_unregister(adata->sdw_dma_dev); + } + if (adata->is_pdm_dev) { + platform_device_unregister(adata->pdm_dev); + platform_device_unregister(adata->dmic_codec_dev); + } ret = acp70_deinit(adata->acp70_base, &pci->dev); if (ret) dev_err(&pci->dev, "ACP de-init failed\n"); @@ -291,5 +447,6 @@ module_pci_driver(ps_acp70_driver);

MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); MODULE_DESCRIPTION("AMD ACP7.0 PCI driver"); +MODULE_IMPORT_NS("SOUNDWIRE_AMD_INIT"); MODULE_IMPORT_NS("SND_AMD_SOUNDWIRE_ACPI"); MODULE_LICENSE("GPL");

PDM platform driver binds to the platform device created by ACP7.0 PCI device. PDM driver registers ALSA DMA and CPU DAI components with ASoC framework.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/Makefile | 2 + sound/soc/amd/acp70/acp70-pdm-dma.c | 87 +++++++++++++++++++++++++++++ sound/soc/amd/acp70/acp70.h | 7 +++ 3 files changed, 96 insertions(+) create mode 100644 sound/soc/amd/acp70/acp70-pdm-dma.c

diff --git a/sound/soc/amd/acp70/Makefile b/sound/soc/amd/acp70/Makefile index 5e553de6c772..778bdf268731 100644 --- a/sound/soc/amd/acp70/Makefile +++ b/sound/soc/amd/acp70/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only # ACP 7.0 platform Support snd-pci-acp70-y := pci-acp70.o +snd-acp70-pdm-dma-y := acp70-pdm-dma.o

obj-$(CONFIG_SND_SOC_AMD_ACP70) += snd-pci-acp70.o +obj-$(CONFIG_SND_SOC_AMD_ACP70) += snd-acp70-pdm-dma.o diff --git a/sound/soc/amd/acp70/acp70-pdm-dma.c b/sound/soc/amd/acp70/acp70-pdm-dma.c new file mode 100644 index 000000000000..fd31e31a02a6 --- /dev/null +++ b/sound/soc/amd/acp70/acp70-pdm-dma.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD ALSA SoC ACP 7.0 PDM Driver + * + * Copyright 2024 Advanced Micro Devices, Inc. + */ + +#include <linux/bitfield.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dai.h> + +#include "acp70.h" + +#define DRV_NAME "acp70_pdm_dma" + +static struct snd_soc_dai_driver acp70_pdm_dai_driver = { + .name = "acp_acp70_pdm_dma.0", + .capture = { + .rates = SNDRV_PCM_RATE_48000, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 2, + .rate_min = 48000, + .rate_max = 48000, + }, +}; + +static const struct snd_soc_component_driver acp70_pdm_component = { + .name = DRV_NAME, +}; + +static int acp70_pdm_audio_probe(struct platform_device *pdev) +{ + struct resource *res; + struct pdm_dev_data *adata; + struct acp70_dev_data *acp_data; + struct device *parent; + int status; + + parent = pdev->dev.parent; + acp_data = dev_get_drvdata(parent); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n"); + return -ENODEV; + } + + adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL); + if (!adata) + return -ENOMEM; + + adata->acp70_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!adata->acp70_base) + return -ENOMEM; + + adata->capture_stream = NULL; + adata->acp_lock = &acp_data->acp_lock; + dev_set_drvdata(&pdev->dev, adata); + status = devm_snd_soc_register_component(&pdev->dev, + &acp70_pdm_component, + &acp70_pdm_dai_driver, 1); + if (status) { + dev_err(&pdev->dev, "Fail to register acp pdm dai\n"); + + return -ENODEV; + } + return 0; +} + +static struct platform_driver acp70_pdm_dma_driver = { + .probe = acp70_pdm_audio_probe, + .driver = { + .name = "acp70_pdm_dma", + }, +}; + +module_platform_driver(acp70_pdm_dma_driver); + +MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); +MODULE_DESCRIPTION("AMD ACP 7.0 PDM Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index 68035fbf23d1..c7cabb98cc1a 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -58,6 +58,13 @@ enum acp_config { ACP_CONFIG_20, };

+struct pdm_dev_data { + u32 pdm_irq; + void __iomem *acp70_base; + struct mutex *acp_lock; /* mutex to protect acp common register access */ + struct snd_pcm_substream *capture_stream; +}; + /** * struct acp70_dev_data - acp pci driver context * @acp70_base: acp mmio base

SoundWire DMA platform driver binds to the platform device created by ACP PCI device. SoundWire DMA driver registers ALSA DMA component with ASoC framework. Add common SoundWire dma driver for ACP7.0 and ACP7.1 platforms.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/Makefile | 2 + sound/soc/amd/acp70/acp70-sdw-dma.c | 74 +++++++++++++++++++++++++++++ sound/soc/amd/acp70/acp70.h | 5 ++ 3 files changed, 81 insertions(+) create mode 100644 sound/soc/amd/acp70/acp70-sdw-dma.c

diff --git a/sound/soc/amd/acp70/Makefile b/sound/soc/amd/acp70/Makefile index 778bdf268731..f3e47635558b 100644 --- a/sound/soc/amd/acp70/Makefile +++ b/sound/soc/amd/acp70/Makefile @@ -2,6 +2,8 @@ # ACP 7.0 platform Support snd-pci-acp70-y := pci-acp70.o snd-acp70-pdm-dma-y := acp70-pdm-dma.o +snd-acp70-sdw-dma-y := acp70-sdw-dma.o

obj-$(CONFIG_SND_SOC_AMD_ACP70) += snd-pci-acp70.o obj-$(CONFIG_SND_SOC_AMD_ACP70) += snd-acp70-pdm-dma.o +obj-$(CONFIG_SND_SOC_AMD_ACP70) += snd-acp70-sdw-dma.o diff --git a/sound/soc/amd/acp70/acp70-sdw-dma.c b/sound/soc/amd/acp70/acp70-sdw-dma.c new file mode 100644 index 000000000000..6d748b295cb0 --- /dev/null +++ b/sound/soc/amd/acp70/acp70-sdw-dma.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD ALSA SoC common SoundWire DMA Driver for ACP 7.0 and + * ACP 7.1 platforms. + * + * Copyright 2024 Advanced Micro Devices, Inc. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dai.h> +#include <linux/soundwire/sdw_amd.h> +#include "acp70.h" + +#define DRV_NAME "amd_acp70_sdw_dma" + +static const struct snd_soc_component_driver acp70_sdw_component = { + .name = DRV_NAME, + .use_dai_pcm_id = true, +}; + +static int acp70_sdw_platform_probe(struct platform_device *pdev) +{ + struct resource *res; + struct sdw_dma_dev_data *sdw_data; + struct acp70_dev_data *acp_data; + struct device *parent; + int status; + + parent = pdev->dev.parent; + acp_data = dev_get_drvdata(parent); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n"); + return -ENODEV; + } + + sdw_data = devm_kzalloc(&pdev->dev, sizeof(*sdw_data), GFP_KERNEL); + if (!sdw_data) + return -ENOMEM; + + sdw_data->acp_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!sdw_data->acp_base) + return -ENOMEM; + + sdw_data->acp_lock = &acp_data->acp_lock; + dev_set_drvdata(&pdev->dev, sdw_data); + status = devm_snd_soc_register_component(&pdev->dev, + &acp70_sdw_component, + NULL, 0); + if (status) { + dev_err(&pdev->dev, "Fail to register sdw dma component\n"); + return status; + } + return 0; +} + +static struct platform_driver acp70_sdw_dma_driver = { + .probe = acp70_sdw_platform_probe, + .driver = { + .name = "amd_acp70_sdw_dma", + }, +}; + +module_platform_driver(acp70_sdw_dma_driver); + +MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); +MODULE_DESCRIPTION("AMD ACP7.0 SDW DMA Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index d6c99d43ed4f..c707c10c4be4 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -97,6 +97,11 @@ struct pdm_dev_data { struct snd_pcm_substream *capture_stream; };

+struct sdw_dma_dev_data { + void __iomem *acp_base; + struct mutex *acp_lock; /* used to protect acp common register access */ +}; + /** * struct acp70_dev_data - acp pci driver context * @acp70_base: acp mmio base

Add SoundWire dma driver dma ops for ACP7.0 and ACP7.1 platforms.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70-sdw-dma.c | 420 ++++++++++++++++++++++++++++ sound/soc/amd/acp70/acp70.h | 123 ++++++++ 2 files changed, 543 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70-sdw-dma.c b/sound/soc/amd/acp70/acp70-sdw-dma.c index 6d748b295cb0..2c01f60cf3b9 100644 --- a/sound/soc/amd/acp70/acp70-sdw-dma.c +++ b/sound/soc/amd/acp70/acp70-sdw-dma.c @@ -18,8 +18,428 @@

#define DRV_NAME "amd_acp70_sdw_dma"

+static struct sdw_dma_ring_buf_reg sdw0_dma_ring_buf_reg[ACP70_SDW0_DMA_MAX_STREAMS] = { + {ACP_AUDIO0_TX_DMA_SIZE, ACP_AUDIO0_TX_FIFOADDR, ACP_AUDIO0_TX_FIFOSIZE, + ACP_AUDIO0_TX_RINGBUFSIZE, ACP_AUDIO0_TX_RINGBUFADDR, ACP_AUDIO0_TX_INTR_WATERMARK_SIZE, + ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH}, + {ACP_AUDIO1_TX_DMA_SIZE, ACP_AUDIO1_TX_FIFOADDR, ACP_AUDIO1_TX_FIFOSIZE, + ACP_AUDIO1_TX_RINGBUFSIZE, ACP_AUDIO1_TX_RINGBUFADDR, ACP_AUDIO1_TX_INTR_WATERMARK_SIZE, + ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH}, + {ACP_AUDIO2_TX_DMA_SIZE, ACP_AUDIO2_TX_FIFOADDR, ACP_AUDIO2_TX_FIFOSIZE, + ACP_AUDIO2_TX_RINGBUFSIZE, ACP_AUDIO2_TX_RINGBUFADDR, ACP_AUDIO2_TX_INTR_WATERMARK_SIZE, + ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH}, + {ACP_AUDIO0_RX_DMA_SIZE, ACP_AUDIO0_RX_FIFOADDR, ACP_AUDIO0_RX_FIFOSIZE, + ACP_AUDIO0_RX_RINGBUFSIZE, ACP_AUDIO0_RX_RINGBUFADDR, ACP_AUDIO0_RX_INTR_WATERMARK_SIZE, + ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH}, + {ACP_AUDIO1_RX_DMA_SIZE, ACP_AUDIO1_RX_FIFOADDR, ACP_AUDIO1_RX_FIFOSIZE, + ACP_AUDIO1_RX_RINGBUFSIZE, ACP_AUDIO1_RX_RINGBUFADDR, ACP_AUDIO1_RX_INTR_WATERMARK_SIZE, + ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH}, + {ACP_AUDIO2_RX_DMA_SIZE, ACP_AUDIO2_RX_FIFOADDR, ACP_AUDIO2_RX_FIFOSIZE, + ACP_AUDIO2_RX_RINGBUFSIZE, ACP_AUDIO2_RX_RINGBUFADDR, ACP_AUDIO2_RX_INTR_WATERMARK_SIZE, + ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH} +}; + +static struct sdw_dma_ring_buf_reg sdw1_dma_ring_buf_reg[ACP70_SDW1_DMA_MAX_STREAMS] = { + {ACP_P1_AUDIO0_TX_DMA_SIZE, ACP_P1_AUDIO0_TX_FIFOADDR, ACP_P1_AUDIO0_TX_FIFOSIZE, + ACP_P1_AUDIO0_TX_RINGBUFSIZE, ACP_P1_AUDIO0_TX_RINGBUFADDR, + ACP_P1_AUDIO0_TX_INTR_WATERMARK_SIZE, + ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH}, + {ACP_P1_AUDIO1_TX_DMA_SIZE, ACP_P1_AUDIO1_TX_FIFOADDR, ACP_P1_AUDIO1_TX_FIFOSIZE, + ACP_P1_AUDIO1_TX_RINGBUFSIZE, ACP_P1_AUDIO1_TX_RINGBUFADDR, + ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE, + ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH}, + {ACP_P1_AUDIO2_TX_DMA_SIZE, ACP_P1_AUDIO2_TX_FIFOADDR, ACP_P1_AUDIO2_TX_FIFOSIZE, + ACP_P1_AUDIO2_TX_RINGBUFSIZE, ACP_P1_AUDIO2_TX_RINGBUFADDR, + ACP_P1_AUDIO2_TX_INTR_WATERMARK_SIZE, + ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH}, + {ACP_P1_AUDIO0_RX_DMA_SIZE, ACP_P1_AUDIO0_RX_FIFOADDR, ACP_P1_AUDIO0_RX_FIFOSIZE, + ACP_P1_AUDIO0_RX_RINGBUFSIZE, ACP_P1_AUDIO0_RX_RINGBUFADDR, + ACP_P1_AUDIO0_RX_INTR_WATERMARK_SIZE, + ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH}, + {ACP_P1_AUDIO1_RX_DMA_SIZE, ACP_P1_AUDIO1_RX_FIFOADDR, ACP_P1_AUDIO1_RX_FIFOSIZE, + ACP_P1_AUDIO1_RX_RINGBUFSIZE, ACP_P1_AUDIO1_RX_RINGBUFADDR, + ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE, + ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH}, + {ACP_P1_AUDIO2_RX_DMA_SIZE, ACP_P1_AUDIO2_RX_FIFOADDR, ACP_P1_AUDIO2_RX_FIFOSIZE, + ACP_P1_AUDIO2_RX_RINGBUFSIZE, ACP_P1_AUDIO2_RX_RINGBUFADDR, + ACP_P1_AUDIO2_RX_INTR_WATERMARK_SIZE, + ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH} +}; + +static u32 sdw0_dma_enable_reg[ACP70_SDW0_DMA_MAX_STREAMS] = { + ACP_SW0_AUDIO0_TX_EN, + ACP_SW0_AUDIO1_TX_EN, + ACP_SW0_AUDIO2_TX_EN, + ACP_SW0_AUDIO0_RX_EN, + ACP_SW0_AUDIO1_RX_EN, + ACP_SW0_AUDIO2_RX_EN, +}; + +#define ACP_SW1_AUDIO0_TX_EN 0x0003C10 +#define ACP_SW1_AUDIO2_TX_EN 0x0003C6C +#define ACP_SW1_AUDIO0_RX_EN 0x0003C88 +#define ACP_SW1_AUDIO2_RX_EN 0x0003D44 + +static u32 sdw1_dma_enable_reg[ACP70_SDW1_DMA_MAX_STREAMS] = { + ACP_SW1_AUDIO0_TX_EN, + ACP_SW1_AUDIO1_TX_EN, + ACP_SW1_AUDIO2_TX_EN, + ACP_SW1_AUDIO0_RX_EN, + ACP_SW1_AUDIO1_RX_EN, + ACP_SW1_AUDIO2_RX_EN, +}; + +static const struct snd_pcm_hardware acp70_sdw_hardware_playback = { + .info = SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .buffer_bytes_max = SDW_PLAYBACK_MAX_NUM_PERIODS * SDW_PLAYBACK_MAX_PERIOD_SIZE, + .period_bytes_min = SDW_PLAYBACK_MIN_PERIOD_SIZE, + .period_bytes_max = SDW_PLAYBACK_MAX_PERIOD_SIZE, + .periods_min = SDW_PLAYBACK_MIN_NUM_PERIODS, + .periods_max = SDW_PLAYBACK_MAX_NUM_PERIODS, +}; + +static const struct snd_pcm_hardware acp70_sdw_hardware_capture = { + .info = SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .rate_min = 48000, + .rate_max = 48000, + .buffer_bytes_max = SDW_CAPTURE_MAX_NUM_PERIODS * SDW_CAPTURE_MAX_PERIOD_SIZE, + .period_bytes_min = SDW_CAPTURE_MIN_PERIOD_SIZE, + .period_bytes_max = SDW_CAPTURE_MAX_PERIOD_SIZE, + .periods_min = SDW_CAPTURE_MIN_NUM_PERIODS, + .periods_max = SDW_CAPTURE_MAX_NUM_PERIODS, +}; + +static void acp70_config_dma(struct acp_sdw_dma_stream *stream, void __iomem *acp_base, + u32 stream_id) +{ + u16 page_idx; + u32 low, high, val; + u32 sdw_dma_pte_offset; + dma_addr_t addr; + + addr = stream->dma_addr; + sdw_dma_pte_offset = SDW_PTE_OFFSET(stream->instance); + val = sdw_dma_pte_offset + (stream_id * ACP_SDW_PTE_OFFSET); + + /* Group Enable */ + writel(ACP_SDW_SRAM_PTE_OFFSET | BIT(31), acp_base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_2); + writel(PAGE_SIZE_4K_ENABLE, acp_base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2); + for (page_idx = 0; page_idx < stream->num_pages; page_idx++) { + /* Load the low address of page int ACP SRAM through SRBM */ + low = lower_32_bits(addr); + high = upper_32_bits(addr); + + writel(low, acp_base + ACP_SCRATCH_REG_0 + val); + high |= BIT(31); + writel(high, acp_base + ACP_SCRATCH_REG_0 + val + 4); + val += 8; + addr += PAGE_SIZE; + } + writel(0x1, acp_base + ACPAXI2AXI_ATU_CTRL); +} + +static int acp70_configure_sdw_ringbuffer(void __iomem *acp_base, u32 stream_id, u32 size, + u32 manager_instance) +{ + u32 reg_dma_size; + u32 reg_fifo_addr; + u32 reg_fifo_size; + u32 reg_ring_buf_size; + u32 reg_ring_buf_addr; + u32 sdw_fifo_addr; + u32 sdw_fifo_offset; + u32 sdw_ring_buf_addr; + u32 sdw_ring_buf_size; + u32 sdw_mem_window_offset; + + switch (manager_instance) { + case ACP_SDW0: + reg_dma_size = sdw0_dma_ring_buf_reg[stream_id].reg_dma_size; + reg_fifo_addr = sdw0_dma_ring_buf_reg[stream_id].reg_fifo_addr; + reg_fifo_size = sdw0_dma_ring_buf_reg[stream_id].reg_fifo_size; + reg_ring_buf_size = sdw0_dma_ring_buf_reg[stream_id].reg_ring_buf_size; + reg_ring_buf_addr = sdw0_dma_ring_buf_reg[stream_id].reg_ring_buf_addr; + break; + case ACP_SDW1: + reg_dma_size = sdw1_dma_ring_buf_reg[stream_id].reg_dma_size; + reg_fifo_addr = sdw1_dma_ring_buf_reg[stream_id].reg_fifo_addr; + reg_fifo_size = sdw1_dma_ring_buf_reg[stream_id].reg_fifo_size; + reg_ring_buf_size = sdw1_dma_ring_buf_reg[stream_id].reg_ring_buf_size; + reg_ring_buf_addr = sdw1_dma_ring_buf_reg[stream_id].reg_ring_buf_addr; + break; + default: + return -EINVAL; + } + sdw_fifo_offset = ACP_SDW_FIFO_OFFSET(manager_instance); + sdw_mem_window_offset = SDW_MEM_WINDOW_START(manager_instance); + sdw_fifo_addr = sdw_fifo_offset + (stream_id * SDW_FIFO_OFFSET); + sdw_ring_buf_addr = sdw_mem_window_offset + (stream_id * ACP_SDW_RING_BUFF_ADDR_OFFSET); + sdw_ring_buf_size = size; + writel(sdw_ring_buf_size, acp_base + reg_ring_buf_size); + writel(sdw_ring_buf_addr, acp_base + reg_ring_buf_addr); + writel(sdw_fifo_addr, acp_base + reg_fifo_addr); + writel(SDW_DMA_SIZE, acp_base + reg_dma_size); + writel(SDW_FIFO_SIZE, acp_base + reg_fifo_size); + return 0; +} + +static int acp70_sdw_dma_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime; + struct acp_sdw_dma_stream *stream; + struct snd_soc_dai *cpu_dai; + struct amd_sdw_manager *amd_manager; + struct snd_soc_pcm_runtime *prtd = substream->private_data; + int ret; + + runtime = substream->runtime; + cpu_dai = snd_soc_rtd_to_cpu(prtd, 0); + amd_manager = snd_soc_dai_get_drvdata(cpu_dai); + stream = kzalloc(sizeof(*stream), GFP_KERNEL); + if (!stream) + return -ENOMEM; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + runtime->hw = acp70_sdw_hardware_playback; + else + runtime->hw = acp70_sdw_hardware_capture; + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) { + dev_err(component->dev, "set integer constraint failed\n"); + kfree(stream); + return ret; + } + + stream->stream_id = cpu_dai->id; + stream->instance = amd_manager->instance; + runtime->private_data = stream; + return ret; +} + +static int acp70_sdw_dma_hw_params(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct acp_sdw_dma_stream *stream; + struct sdw_dma_dev_data *sdw_data; + u32 period_bytes; + u32 water_mark_size_reg; + u32 irq_mask, ext_intr_ctrl; + u64 size; + u32 stream_id; + u32 acp_ext_intr_cntl_reg; + int ret; + + sdw_data = dev_get_drvdata(component->dev); + stream = substream->runtime->private_data; + if (!stream) + return -EINVAL; + stream_id = stream->stream_id; + switch (stream->instance) { + case ACP_SDW0: + sdw_data->sdw0_dma_stream[stream_id] = substream; + water_mark_size_reg = sdw0_dma_ring_buf_reg[stream_id].water_mark_size_reg; + acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL; + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + irq_mask = BIT(SDW0_DMA_TX_IRQ_MASK(stream_id)); + else + irq_mask = BIT(SDW0_DMA_RX_IRQ_MASK(stream_id)); + break; + case ACP_SDW1: + sdw_data->sdw1_dma_stream[stream_id] = substream; + acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL1; + water_mark_size_reg = sdw1_dma_ring_buf_reg[stream_id].water_mark_size_reg; + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + irq_mask = BIT(SDW1_DMA_TX_IRQ_MASK(stream_id)); + else + irq_mask = BIT(SDW1_DMA_RX_IRQ_MASK(stream_id)); + + break; + default: + return -EINVAL; + } + size = params_buffer_bytes(params); + period_bytes = params_period_bytes(params); + stream->dma_addr = substream->runtime->dma_addr; + stream->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT); + acp70_config_dma(stream, sdw_data->acp_base, stream_id); + ret = acp70_configure_sdw_ringbuffer(sdw_data->acp_base, stream_id, size, + stream->instance); + if (ret) { + dev_err(component->dev, "Invalid DMA channel\n"); + return -EINVAL; + } + ext_intr_ctrl = readl(sdw_data->acp_base + acp_ext_intr_cntl_reg); + ext_intr_ctrl |= irq_mask; + writel(ext_intr_ctrl, sdw_data->acp_base + acp_ext_intr_cntl_reg); + writel(period_bytes, sdw_data->acp_base + water_mark_size_reg); + return 0; +} + +static u64 acp70_sdw_get_byte_count(struct acp_sdw_dma_stream *stream, void __iomem *acp_base) +{ + union acp_sdw_dma_count byte_count; + u32 pos_low_reg, pos_high_reg; + + byte_count.bytescount = 0; + switch (stream->instance) { + case ACP_SDW0: + pos_low_reg = sdw0_dma_ring_buf_reg[stream->stream_id].pos_low_reg; + pos_high_reg = sdw0_dma_ring_buf_reg[stream->stream_id].pos_high_reg; + break; + case ACP_SDW1: + pos_low_reg = sdw1_dma_ring_buf_reg[stream->stream_id].pos_low_reg; + pos_high_reg = sdw1_dma_ring_buf_reg[stream->stream_id].pos_high_reg; + break; + default: + goto POINTER_RETURN_BYTES; + } + if (pos_low_reg) { + byte_count.bcount.high = readl(acp_base + pos_high_reg); + byte_count.bcount.low = readl(acp_base + pos_low_reg); + } +POINTER_RETURN_BYTES: + return byte_count.bytescount; +} + +static snd_pcm_uframes_t acp70_sdw_dma_pointer(struct snd_soc_component *comp, + struct snd_pcm_substream *substream) +{ + struct sdw_dma_dev_data *sdw_data; + struct acp_sdw_dma_stream *stream; + u32 pos, buffersize; + u64 bytescount; + + sdw_data = dev_get_drvdata(comp->dev); + stream = substream->runtime->private_data; + buffersize = frames_to_bytes(substream->runtime, + substream->runtime->buffer_size); + bytescount = acp70_sdw_get_byte_count(stream, sdw_data->acp_base); + if (bytescount > stream->bytescount) + bytescount -= stream->bytescount; + pos = do_div(bytescount, buffersize); + return bytes_to_frames(substream->runtime, pos); +} + +static int acp70_sdw_dma_new(struct snd_soc_component *component, + struct snd_soc_pcm_runtime *rtd) +{ + struct device *parent = component->dev->parent; + + snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, + parent, SDW_MIN_BUFFER, SDW_MAX_BUFFER); + return 0; +} + +static int acp70_sdw_dma_close(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + struct sdw_dma_dev_data *sdw_data; + struct acp_sdw_dma_stream *stream; + + sdw_data = dev_get_drvdata(component->dev); + stream = substream->runtime->private_data; + if (!stream) + return -EINVAL; + switch (stream->instance) { + case ACP_SDW0: + sdw_data->sdw0_dma_stream[stream->stream_id] = NULL; + break; + case ACP_SDW1: + sdw_data->sdw1_dma_stream[stream->stream_id] = NULL; + break; + default: + return -EINVAL; + } + kfree(stream); + return 0; +} + +static int acp70_sdw_dma_enable(struct snd_pcm_substream *substream, + void __iomem *acp_base, bool sdw_dma_enable) +{ + struct acp_sdw_dma_stream *stream; + u32 stream_id; + u32 sdw_dma_en_reg; + u32 sdw_dma_en_stat_reg; + u32 sdw_dma_stat; + u32 dma_enable; + + stream = substream->runtime->private_data; + stream_id = stream->stream_id; + switch (stream->instance) { + case ACP_SDW0: + sdw_dma_en_reg = sdw0_dma_enable_reg[stream_id]; + break; + case ACP_SDW1: + sdw_dma_en_reg = sdw1_dma_enable_reg[stream_id]; + break; + default: + return -EINVAL; + } + sdw_dma_en_stat_reg = sdw_dma_en_reg + 4; + dma_enable = sdw_dma_enable; + writel(dma_enable, acp_base + sdw_dma_en_reg); + return readl_poll_timeout(acp_base + sdw_dma_en_stat_reg, sdw_dma_stat, + (sdw_dma_stat == dma_enable), ACP_DELAY_US, ACP_COUNTER); +} + +static int acp70_sdw_dma_trigger(struct snd_soc_component *comp, + struct snd_pcm_substream *substream, + int cmd) +{ + struct sdw_dma_dev_data *sdw_data; + int ret; + + sdw_data = dev_get_drvdata(comp->dev); + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + case SNDRV_PCM_TRIGGER_RESUME: + ret = acp70_sdw_dma_enable(substream, sdw_data->acp_base, true); + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_STOP: + ret = acp70_sdw_dma_enable(substream, sdw_data->acp_base, false); + break; + default: + ret = -EINVAL; + } + if (ret) + dev_err(comp->dev, "trigger %d failed: %d", cmd, ret); + return ret; +} + static const struct snd_soc_component_driver acp70_sdw_component = { .name = DRV_NAME, + .open = acp70_sdw_dma_open, + .close = acp70_sdw_dma_close, + .hw_params = acp70_sdw_dma_hw_params, + .trigger = acp70_sdw_dma_trigger, + .pointer = acp70_sdw_dma_pointer, + .pcm_construct = acp70_sdw_dma_new, .use_dai_pcm_id = true, };

diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index c707c10c4be4..a96b021e64da 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -58,6 +58,81 @@ #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS) #define MIN_BUFFER MAX_BUFFER

+#define ACP_SDW0_STAT BIT(21) +#define ACP_SDW1_STAT BIT(2) +#define ACP_ERROR_IRQ BIT(29) + +#define ACP_AUDIO0_TX_THRESHOLD 0x1c +#define ACP_AUDIO1_TX_THRESHOLD 0x1a +#define ACP_AUDIO2_TX_THRESHOLD 0x18 +#define ACP_AUDIO0_RX_THRESHOLD 0x1b +#define ACP_AUDIO1_RX_THRESHOLD 0x19 +#define ACP_AUDIO2_RX_THRESHOLD 0x17 +#define ACP_P1_AUDIO0_TX_THRESHOLD 0x8 +#define ACP_P1_AUDIO1_TX_THRESHOLD 0x6 +#define ACP_P1_AUDIO2_TX_THRESHOLD 0x4 +#define ACP_P1_AUDIO0_RX_THRESHOLD 0x7 +#define ACP_P1_AUDIO1_RX_THRESHOLD 0x5 +#define ACP_P1_AUDIO2_RX_THRESHOLD 0x3 +#define ACP_SDW_DMA_IRQ_MASK 0x1F800000 +#define ACP_P1_SDW_DMA_IRQ_MASK 0x1F8 +#define ACP70_SDW0_DMA_MAX_STREAMS 6 +#define ACP70_SDW1_DMA_MAX_STREAMS 6 + +/* + * Below entries describes SDW0 instance DMA stream id and DMA irq bit mapping + * in ACP_EXTENAL_INTR_CNTL register. + * Stream id IRQ Bit + * 0 (SDW0_AUDIO0_TX) 28 + * 1 (SDW0_AUDIO1_TX) 26 + * 2 (SDW0_AUDIO2_TX) 24 + * 3 (SDW0_AUDIO0_RX) 27 + * 4 (SDW0_AUDIO1_RX) 25 + * 5 (SDW0_AUDIO2_RX) 23 + */ +#define SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i))) +#define SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3))) + +/* + * Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping + * in ACP_EXTENAL_INTR_CNTL1 register. + * Stream id IRQ Bit + * 0 (SDW1_AUDIO0_TX) 8 + * 1 (SDW1_AUDIO1_TX) 6 + * 2 (SDW1_AUDIO2_TX) 4 + * 3 (SDW1_AUDIO0_RX) 7 + * 4 (SDW1_AUDIO1_RX) 5 + * 5 (SDW1_AUDIO2_RX) 3 + */ +#define SDW1_DMA_TX_IRQ_MASK(i) (ACP_P1_AUDIO0_TX_THRESHOLD - (2 * (i))) +#define SDW1_DMA_RX_IRQ_MASK(i) (ACP_P1_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3))) + +#define ACP_DELAY_US 5 +#define ACP_SDW_RING_BUFF_ADDR_OFFSET (128 * 1024) +#define SDW0_MEM_WINDOW_START 0x4800000 +#define ACP_SDW_SRAM_PTE_OFFSET 0x03800400 +#define SDW0_PTE_OFFSET 0x400 +#define SDW_FIFO_SIZE 0x100 +#define SDW_DMA_SIZE 0x40 +#define ACP_SDW0_FIFO_OFFSET 0x100 +#define ACP_SDW_PTE_OFFSET 0x100 +#define SDW_FIFO_OFFSET 0x100 +#define SDW_PTE_OFFSET(i) (SDW0_PTE_OFFSET + ((i) * 0x600)) +#define ACP_SDW_FIFO_OFFSET(i) (ACP_SDW0_FIFO_OFFSET + ((i) * 0x500)) +#define SDW_MEM_WINDOW_START(i) (SDW0_MEM_WINDOW_START + ((i) * 0xC0000)) + +#define SDW_PLAYBACK_MIN_NUM_PERIODS 2 +#define SDW_PLAYBACK_MAX_NUM_PERIODS 8 +#define SDW_PLAYBACK_MAX_PERIOD_SIZE 8192 +#define SDW_PLAYBACK_MIN_PERIOD_SIZE 1024 +#define SDW_CAPTURE_MIN_NUM_PERIODS 2 +#define SDW_CAPTURE_MAX_NUM_PERIODS 8 +#define SDW_CAPTURE_MAX_PERIOD_SIZE 8192 +#define SDW_CAPTURE_MIN_PERIOD_SIZE 1024 + +#define SDW_MAX_BUFFER (SDW_PLAYBACK_MAX_PERIOD_SIZE * SDW_PLAYBACK_MAX_NUM_PERIODS) +#define SDW_MIN_BUFFER SDW_MAX_BUFFER + enum acp_config { ACP_CONFIG_0 = 0, ACP_CONFIG_1, @@ -82,6 +157,24 @@ enum acp_config { ACP_CONFIG_20, };

+enum amd_sdw0_channel { + ACP_SDW0_AUDIO0_TX = 0, + ACP_SDW0_AUDIO1_TX, + ACP_SDW0_AUDIO2_TX, + ACP_SDW0_AUDIO0_RX, + ACP_SDW0_AUDIO1_RX, + ACP_SDW0_AUDIO2_RX, +}; + +enum amd_sdw1_channel { + ACP_SDW1_AUDIO0_TX = 0, + ACP_SDW1_AUDIO1_TX, + ACP_SDW1_AUDIO2_TX, + ACP_SDW1_AUDIO0_RX, + ACP_SDW1_AUDIO1_RX, + ACP_SDW1_AUDIO2_RX, +}; + struct pdm_stream_instance { u16 num_pages; u16 channels; @@ -97,9 +190,39 @@ struct pdm_dev_data { struct snd_pcm_substream *capture_stream; };

+union acp_sdw_dma_count { + struct { + u32 low; + u32 high; + } bcount; + u64 bytescount; +}; + +struct acp_sdw_dma_stream { + u16 num_pages; + u16 channels; + u32 stream_id; + u32 instance; + dma_addr_t dma_addr; + u64 bytescount; +}; + +struct sdw_dma_ring_buf_reg { + u32 reg_dma_size; + u32 reg_fifo_addr; + u32 reg_fifo_size; + u32 reg_ring_buf_size; + u32 reg_ring_buf_addr; + u32 water_mark_size_reg; + u32 pos_low_reg; + u32 pos_high_reg; +}; + struct sdw_dma_dev_data { void __iomem *acp_base; struct mutex *acp_lock; /* used to protect acp common register access */ + struct snd_pcm_substream *sdw0_dma_stream[ACP70_SDW0_DMA_MAX_STREAMS]; + struct snd_pcm_substream *sdw1_dma_stream[ACP70_SDW1_DMA_MAX_STREAMS]; };

/**

Add acp pdm driver pm ops for ACP7.0 & ACP7.1 platforms.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70-pdm-dma.c | 57 +++++++++++++++++++++++++++++ sound/soc/amd/acp70/acp70.h | 3 ++ 2 files changed, 60 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70-pdm-dma.c b/sound/soc/amd/acp70/acp70-pdm-dma.c index 197214e68489..0d24c9ed917f 100644 --- a/sound/soc/amd/acp70/acp70-pdm-dma.c +++ b/sound/soc/amd/acp70/acp70-pdm-dma.c @@ -13,6 +13,7 @@ #include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/soc-dai.h> +#include <linux/pm_runtime.h>

#include "acp70.h"

@@ -388,13 +389,69 @@ static int acp70_pdm_audio_probe(struct platform_device *pdev)

return -ENODEV; } + pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); return 0; }

+static void acp70_pdm_audio_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); +} + +static int __maybe_unused acp70_pdm_resume(struct device *dev) +{ + struct pdm_dev_data *adata; + struct snd_pcm_runtime *runtime; + struct pdm_stream_instance *rtd; + u32 period_bytes, buffer_len; + + adata = dev_get_drvdata(dev); + if (adata->capture_stream && adata->capture_stream->runtime) { + runtime = adata->capture_stream->runtime; + rtd = runtime->private_data; + period_bytes = frames_to_bytes(runtime, runtime->period_size); + buffer_len = frames_to_bytes(runtime, runtime->buffer_size); + acp70_config_dma(rtd, SNDRV_PCM_STREAM_CAPTURE); + acp70_init_pdm_ring_buffer(PDM_MEM_WINDOW_START, buffer_len, + period_bytes, adata->acp70_base); + } + acp70_enable_pdm_interrupts(adata); + return 0; +} + +static int __maybe_unused acp70_pdm_suspend(struct device *dev) +{ + struct pdm_dev_data *adata; + + adata = dev_get_drvdata(dev); + acp70_disable_pdm_interrupts(adata); + return 0; +} + +static int __maybe_unused acp70_pdm_runtime_resume(struct device *dev) +{ + struct pdm_dev_data *adata; + + adata = dev_get_drvdata(dev); + acp70_enable_pdm_interrupts(adata); + return 0; +} + +static const struct dev_pm_ops acp70_pdm_pm_ops = { + SET_RUNTIME_PM_OPS(acp70_pdm_suspend, acp70_pdm_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(acp70_pdm_suspend, acp70_pdm_resume) +}; + static struct platform_driver acp70_pdm_dma_driver = { .probe = acp70_pdm_audio_probe, + .remove = acp70_pdm_audio_remove, .driver = { .name = "acp70_pdm_dma", + .pm = &acp70_pdm_pm_ops, }, };

diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index d5ab606adedc..1d8e670264fc 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -133,6 +133,9 @@ #define SDW_MAX_BUFFER (SDW_PLAYBACK_MAX_PERIOD_SIZE * SDW_PLAYBACK_MAX_NUM_PERIODS) #define SDW_MIN_BUFFER SDW_MAX_BUFFER

+/* time in ms for runtime suspend delay */ +#define ACP_SUSPEND_DELAY_MS 2000 + enum acp_config { ACP_CONFIG_0 = 0, ACP_CONFIG_1,

Add pm ops support for ACP7.0 PCI driver.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70.h | 4 ++ sound/soc/amd/acp70/pci-acp70.c | 106 ++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index 1d8e670264fc..1b5661a86352 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -60,6 +60,8 @@

#define ACP_SDW0_STAT BIT(21) #define ACP_SDW1_STAT BIT(2) +#define ACP_SDW0_PME_STAT BIT(26) +#define ACP_SDW1_PME_STAT BIT(27) #define ACP_ERROR_IRQ BIT(29)

#define ACP_AUDIO0_TX_THRESHOLD 0x1c @@ -247,6 +249,7 @@ struct sdw_dma_dev_data { * @is_pdm_dev: flag set to true when ACP PDM controller exists * @is_pdm_config: flat set to true when PDM configuration is selected from BIOS * @is_sdw_config: flag set to true when SDW configuration is selected from BIOS + * @sdw_en_stat: flag set to true when any one of the SoundWire manager instance is enabled */

struct acp70_dev_data { @@ -268,6 +271,7 @@ struct acp70_dev_data { bool is_pdm_dev; bool is_pdm_config; bool is_sdw_config; + bool sdw_en_stat; };

int snd_amd_acp_find_config(struct pci_dev *pci); diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index e732a680c092..3cca18612ef1 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -15,6 +15,7 @@ #include <linux/pci.h> #include <linux/platform_device.h> #include <sound/pcm_params.h> +#include <linux/pm_runtime.h> #include "../mach-config.h"

#include "acp70.h" @@ -554,6 +555,10 @@ static int snd_acp70_probe(struct pci_dev *pci, goto de_init; } skip_pdev_creation: + pm_runtime_set_autosuspend_delay(&pci->dev, ACP_SUSPEND_DELAY_MS); + pm_runtime_use_autosuspend(&pci->dev); + pm_runtime_put_noidle(&pci->dev); + pm_runtime_allow(&pci->dev); return 0; de_init: if (acp70_deinit(adata->acp70_base, &pci->dev)) @@ -566,6 +571,102 @@ static int snd_acp70_probe(struct pci_dev *pci, return ret; }

+static bool check_acp_sdw_enable_status(struct acp70_dev_data *adata) +{ + u32 sdw0_en, sdw1_en; + + sdw0_en = readl(adata->acp70_base + ACP_SW0_EN); + sdw1_en = readl(adata->acp70_base + ACP_SW1_EN); + return (sdw0_en || sdw1_en); +} + +static void handle_acp70_sdw_pme_event(struct device *dev) +{ + struct amd_sdw_manager *amd_manager; + struct acp70_dev_data *adata; + u32 ext_intr_stat1; + + adata = dev_get_drvdata(dev); + ext_intr_stat1 = readl(adata->acp70_base + ACP_EXTERNAL_INTR_STAT1); + dev_dbg(dev, "ext_intr_stat1: 0x%x\n", ext_intr_stat1); + if (ext_intr_stat1 & ACP_SDW0_PME_STAT) { + amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); + if (amd_manager) + pm_request_resume(amd_manager->dev); + } + + if (ext_intr_stat1 & ACP_SDW1_PME_STAT) { + amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); + if (amd_manager) + pm_request_resume(amd_manager->dev); + } +} + +static int __maybe_unused snd_acp70_suspend(struct device *dev) +{ + struct acp70_dev_data *adata; + int ret; + + adata = dev_get_drvdata(dev); + writel(0x1, adata->acp70_base + ACP_PME_EN); + if (adata->is_sdw_dev) { + adata->sdw_en_stat = check_acp_sdw_enable_status(adata); + if (adata->sdw_en_stat) + return 0; + } + ret = acp70_deinit(adata->acp70_base, dev); + if (ret) + dev_err(dev, "ACP de-init failed\n"); + + return ret; +} + +static int __maybe_unused snd_acp70_runtime_resume(struct device *dev) +{ + struct acp70_dev_data *adata; + int ret; + + adata = dev_get_drvdata(dev); + writel(0x1, adata->acp70_base + ACP_PME_EN); + + if (adata->sdw_en_stat) + return 0; + + ret = acp70_init(adata->acp70_base, dev); + if (ret) { + dev_err(dev, "ACP init failed\n"); + return ret; + } + + if (!adata->sdw_en_stat) + handle_acp70_sdw_pme_event(dev); + + return 0; +} + +static int __maybe_unused snd_acp70_resume(struct device *dev) +{ + struct acp70_dev_data *adata; + int ret; + + adata = dev_get_drvdata(dev); + writel(0x1, adata->acp70_base + ACP_PME_EN); + + if (adata->sdw_en_stat) + return 0; + + ret = acp70_init(adata->acp70_base, dev); + if (ret) + dev_err(dev, "ACP init failed\n"); + + return ret; +} + +static const struct dev_pm_ops acp70_pm_ops = { + SET_RUNTIME_PM_OPS(snd_acp70_suspend, snd_acp70_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(snd_acp70_suspend, snd_acp70_resume) +}; + static void snd_acp70_remove(struct pci_dev *pci) { struct acp70_dev_data *adata; @@ -583,6 +684,8 @@ static void snd_acp70_remove(struct pci_dev *pci) ret = acp70_deinit(adata->acp70_base, &pci->dev); if (ret) dev_err(&pci->dev, "ACP de-init failed\n"); + pm_runtime_forbid(&pci->dev); + pm_runtime_get_noresume(&pci->dev); pci_release_regions(pci); pci_disable_device(pci); } @@ -600,6 +703,9 @@ static struct pci_driver ps_acp70_driver = { .id_table = snd_acp70_ids, .probe = snd_acp70_probe, .remove = snd_acp70_remove, + .driver = { + .pm = &acp70_pm_ops, + } };

module_pci_driver(ps_acp70_driver);

When ACP is in D0 state and SoundWire manager instance is in D3 state, If SoundWire wake event is asserted, Soundwire host wake interrupt will be triggered for that SoundWire manager instance. In this case, ACP PCI driver should clear the host wake interrupt and queue up the runtime resume of the SoundWire manager instance.

Add code to handle SoundWire host wake interrupt in ACP7.0 interrupt handler.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70.h | 2 ++ sound/soc/amd/acp70/pci-acp70.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+)

diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index 1b5661a86352..9774db1ac537 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -60,6 +60,8 @@

#define ACP_SDW0_STAT BIT(21) #define ACP_SDW1_STAT BIT(2) +#define ACP_SDW0_HOST_WAKE_STAT BIT(24) +#define ACP_SDW1_HOST_WAKE_STAT BIT(25) #define ACP_SDW0_PME_STAT BIT(26) #define ACP_SDW1_PME_STAT BIT(27) #define ACP_ERROR_IRQ BIT(29) diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index 5e0f7bb68eb8..6884e8516a2c 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -169,6 +169,22 @@ static irqreturn_t acp70_irq_handler(int irq, void *dev_id) irq_flag = 1; }

+ if (ext_intr_stat1 & ACP_SDW0_HOST_WAKE_STAT) { + writel(ACP_SDW0_HOST_WAKE_STAT, adata->acp70_base + ACP_EXTERNAL_INTR_STAT1); + amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); + if (amd_manager) + pm_request_resume(amd_manager->dev); + irq_flag = 1; + } + + if (ext_intr_stat1 & ACP_SDW1_HOST_WAKE_STAT) { + writel(ACP_SDW1_HOST_WAKE_STAT, adata->acp70_base + ACP_EXTERNAL_INTR_STAT1); + amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); + if (amd_manager) + pm_request_resume(amd_manager->dev); + irq_flag = 1; + } + if (ext_intr_stat & BIT(PDM_DMA_STAT)) { ps_pdm_data = dev_get_drvdata(&adata->pdm_dev->dev); writel(BIT(PDM_DMA_STAT), adata->acp70_base + ACP_EXTERNAL_INTR_STAT);

Add SoundWire generic machine driver changes for legacy stack(No DSP) for ACP7.0 and ACP7.1 platforms.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp/acp-sdw-legacy-mach.c | 16 ++++++++++++ sound/soc/amd/acp/acp-sdw-mach-common.c | 34 +++++++++++++++++++++++++ sound/soc/amd/acp/soc_amd_sdw_common.h | 11 ++++++++ 3 files changed, 61 insertions(+)

diff --git a/sound/soc/amd/acp/acp-sdw-legacy-mach.c b/sound/soc/amd/acp/acp-sdw-legacy-mach.c index 9280cd30d19c..e27093d80cc6 100644 --- a/sound/soc/amd/acp/acp-sdw-legacy-mach.c +++ b/sound/soc/amd/acp/acp-sdw-legacy-mach.c @@ -122,6 +122,13 @@ static int create_sdw_dailink(struct snd_soc_card *card, if (ret) return ret; break; + case ACP70_PCI_REV: + case ACP71_PCI_REV: + ret = get_acp70_cpu_pin_id(ffs(soc_end->link_mask - 1), + *be_id, &cpu_pin_id, dev); + if (ret) + return ret; + break; default: return -EINVAL; } @@ -223,6 +230,10 @@ static int create_sdw_dailinks(struct snd_soc_card *card, case ACP63_PCI_REV: sdw_platform_component->name = "amd_ps_sdw_dma.0"; break; + case ACP70_PCI_REV: + case ACP71_PCI_REV: + sdw_platform_component->name = "amd_acp70_sdw_dma.0"; + break; default: return -EINVAL; } @@ -269,6 +280,11 @@ static int create_dmic_dailinks(struct snd_soc_card *card, pdm_cpu->name = "acp_ps_pdm_dma.0"; pdm_platform->name = "acp_ps_pdm_dma.0"; break; + case ACP70_PCI_REV: + case ACP71_PCI_REV: + pdm_cpu->name = "acp70_pdm_dma.0"; + pdm_platform->name = "acp70_pdm_dma.0"; + break; default: return -EINVAL; } diff --git a/sound/soc/amd/acp/acp-sdw-mach-common.c b/sound/soc/amd/acp/acp-sdw-mach-common.c index 6f5c39ed1a18..e5f394dc2f4c 100644 --- a/sound/soc/amd/acp/acp-sdw-mach-common.c +++ b/sound/soc/amd/acp/acp-sdw-mach-common.c @@ -59,6 +59,40 @@ int get_acp63_cpu_pin_id(u32 sdw_link_id, int be_id, int *cpu_pin_id, struct dev } EXPORT_SYMBOL_NS_GPL(get_acp63_cpu_pin_id, "SND_SOC_AMD_SDW_MACH");

+int get_acp70_cpu_pin_id(u32 sdw_link_id, int be_id, int *cpu_pin_id, struct device *dev) +{ + switch (sdw_link_id) { + case AMD_SDW0: + case AMD_SDW1: + switch (be_id) { + case SOC_SDW_JACK_OUT_DAI_ID: + *cpu_pin_id = ACP70_SW_AUDIO0_TX; + break; + case SOC_SDW_JACK_IN_DAI_ID: + *cpu_pin_id = ACP70_SW_AUDIO0_RX; + break; + case SOC_SDW_AMP_OUT_DAI_ID: + *cpu_pin_id = ACP70_SW_AUDIO1_TX; + break; + case SOC_SDW_AMP_IN_DAI_ID: + *cpu_pin_id = ACP70_SW_AUDIO1_RX; + break; + case SOC_SDW_DMIC_DAI_ID: + *cpu_pin_id = ACP70_SW_AUDIO2_RX; + break; + default: + dev_err(dev, "Invalid be id:%d\n", be_id); + return -EINVAL; + } + break; + default: + return -EINVAL; + } + dev_dbg(dev, "sdw_link_id:%d, be_id:%d, cpu_pin_id:%d\n", sdw_link_id, be_id, *cpu_pin_id); + return 0; +} +EXPORT_SYMBOL_NS_GPL(get_acp70_cpu_pin_id, "SND_SOC_AMD_SDW_MACH"); + MODULE_DESCRIPTION("AMD SoundWire Common Machine driver"); MODULE_AUTHOR("Vijendar Mukunda Vijendar.Mukunda@amd.com"); MODULE_LICENSE("GPL"); diff --git a/sound/soc/amd/acp/soc_amd_sdw_common.h b/sound/soc/amd/acp/soc_amd_sdw_common.h index b7bae107c13e..9bedccfe25a9 100644 --- a/sound/soc/amd/acp/soc_amd_sdw_common.h +++ b/sound/soc/amd/acp/soc_amd_sdw_common.h @@ -19,6 +19,8 @@

#define AMD_SDW_MAX_GROUPS 9 #define ACP63_PCI_REV 0x63 +#define ACP70_PCI_REV 0x70 +#define ACP71_PCI_REV 0x71 #define SOC_JACK_JDSRC(quirk) ((quirk) & GENMASK(3, 0)) #define ASOC_SDW_FOUR_SPK BIT(4) #define ASOC_SDW_ACP_DMIC BIT(5) @@ -38,11 +40,20 @@

#define ACP_DMIC_BE_ID 4

+#define ACP70_SW_AUDIO0_TX 0 +#define ACP70_SW_AUDIO1_TX 1 +#define ACP70_SW_AUDIO2_TX 2 + +#define ACP70_SW_AUDIO0_RX 3 +#define ACP70_SW_AUDIO1_RX 4 +#define ACP70_SW_AUDIO2_RX 5 + struct amd_mc_ctx { unsigned int acp_rev; unsigned int max_sdw_links; };

int get_acp63_cpu_pin_id(u32 sdw_link_id, int be_id, int *cpu_pin_id, struct device *dev); +int get_acp70_cpu_pin_id(u32 sdw_link_id, int be_id, int *cpu_pin_id, struct device *dev);

#endif

Patch adds driver data and match table for rt722 multi-function codec on acp7.0 and acp7.1 platforms at sdw link0 for legacy(NO DSP) stack.

Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp/amd-acp70-acpi-match.c | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+)

diff --git a/sound/soc/amd/acp/amd-acp70-acpi-match.c b/sound/soc/amd/acp/amd-acp70-acpi-match.c index 1f30adb6c02a..d31b681b19e2 100644 --- a/sound/soc/amd/acp/amd-acp70-acpi-match.c +++ b/sound/soc/amd/acp/amd-acp70-acpi-match.c @@ -73,7 +73,51 @@ static const struct snd_soc_acpi_link_adr acp70_4_in_1_sdca[] = { {} };

+static const struct snd_soc_acpi_endpoint rt722_endpoints[] = { + { + .num = 0, + .aggregated = 0, + .group_position = 0, + .group_id = 0, + }, + { + .num = 1, + .aggregated = 0, + .group_position = 0, + .group_id = 0, + }, + { + .num = 2, + .aggregated = 0, + .group_position = 0, + .group_id = 0, + }, +}; + +static const struct snd_soc_acpi_adr_device rt722_0_single_adr[] = { + { + .adr = 0x000030025d072201ull, + .num_endpoints = ARRAY_SIZE(rt722_endpoints), + .endpoints = rt722_endpoints, + .name_prefix = "rt722" + } +}; + +static const struct snd_soc_acpi_link_adr acp70_rt722_only[] = { + { + .mask = BIT(0), + .num_adr = ARRAY_SIZE(rt722_0_single_adr), + .adr_d = rt722_0_single_adr, + }, + {} +}; + struct snd_soc_acpi_mach snd_soc_acpi_amd_acp70_sdw_machines[] = { + { + .link_mask = BIT(0), + .links = acp70_rt722_only, + .drv_name = "amd_sdw", + }, { .link_mask = BIT(0) | BIT(1), .links = acp70_4_in_1_sdca,