[alsa-devel] [PATCH 0/4] ARM: OMAP2: Add support for Gumstix Overo (resubmission)
This patch series adds support for the Gumstix Overo board. Since it includes an ASoC driver I am copying both linux-omap and alsa-devel
This version incorporates feedback from both linux-omap and alsa-devel
From: Steve Sakoman steve@sakoman.com
This patch adds support for basic features: onenand, uarts, i2c, mmc, rtc, and usb --- arch/arm/mach-omap2/Kconfig | 4 + arch/arm/mach-omap2/Makefile | 4 + arch/arm/mach-omap2/board-overo.c | 234 +++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-omap2/board-overo.c
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 365b982..362edfa 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -123,6 +123,10 @@ config MACH_OMAP3_BEAGLE bool "OMAP3 BEAGLE board" depends on ARCH_OMAP3 && ARCH_OMAP34XX
+config MACH_OVERO + bool "Gumstix Overo board" + depends on ARCH_OMAP3 && ARCH_OMAP34XX + config OMAP_TICK_GPTIMER int "GPTIMER used for system tick timer" depends on ARCH_OMAP2 || ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d89b7cb..1f6c704 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -75,6 +75,10 @@ obj-$(CONFIG_MACH_NOKIA_N800) += board-n800.o board-n800-flash.o \ board-n800-dsp.o \ board-n800-camera.o obj-$(CONFIG_MACH_NOKIA_N810) += board-n810.o +obj-$(CONFIG_MACH_OVERO) += board-overo.o \ + hsmmc.o \ + usb-musb.o \ + usb-ehci.o
# TUSB 6010 chips obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c new file mode 100644 index 0000000..42c1661 --- /dev/null +++ b/arch/arm/mach-omap2/board-overo.c @@ -0,0 +1,234 @@ +/* + * board-overo.c (Gumstix Overo) + * + * Initial code: Steve Sakoman steve@sakoman.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/onenand_regs.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> +#include <asm/mach/map.h> + +#include <mach/board-overo.h> +#include <mach/board.h> +#include <mach/common.h> +#include <mach/gpio.h> +#include <mach/gpmc.h> +#include <mach/hardware.h> +#include <mach/hsmmc.h> +#include <mach/onenand.h> +#include <mach/usb-ehci.h> +#include <mach/usb-musb.h> + +#include "sdram-micron-mt46h32m32lf-6.h" + +#define NAND_BLOCK_SIZE SZ_128K + +#define OVERO_GPIO_W2W_NRESET 16 +#define OVERO_GPIO_BT_NRESET 164 +#define OVERO_GPIO_USBH_CPEN 168 +#define OVERO_GPIO_USBH_NRESET 183 + +static struct mtd_partition overo_onenand_partitions[] = { + { + .name = "xloader", + .offset = 0, + .size = 4 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE + }, + { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = 15 * NAND_BLOCK_SIZE, + }, + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = 1 * NAND_BLOCK_SIZE, + }, + { + .name = "linux", + .offset = MTDPART_OFS_APPEND, + .size = 40 * NAND_BLOCK_SIZE, + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct omap_onenand_platform_data overo_onenand_data = { + .parts = overo_onenand_partitions, + .nr_parts = ARRAY_SIZE(overo_onenand_partitions), + .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ +}; + +static struct platform_device overo_onenand_device = { + .name = "omap2-onenand", + .id = -1, + .dev = { + .platform_data = &overo_onenand_data, + }, +}; + +static void __init overo_flash_init(void) +{ + u8 cs = 0; + u8 onenandcs = GPMC_CS_NUM + 1; + + while (cs < GPMC_CS_NUM) { + u32 ret = 0; + ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + + if ((ret & 0x3F) == (ONENAND_MAP >> 24)) + onenandcs = cs; + cs++; + } + if (onenandcs > GPMC_CS_NUM) { + printk(KERN_ERR "OneNAND: Unable to find configuration " + " in GPMC\n"); + return; + } + + if (onenandcs < GPMC_CS_NUM) { + overo_onenand_data.cs = onenandcs; + if (platform_device_register(&overo_onenand_device) < 0) + printk(KERN_ERR "Unable to register OneNAND device\n"); + } +} +static struct omap_uart_config overo_uart_config __initdata = { + .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), +}; + +static int __init overo_i2c_init(void) +{ + omap_register_i2c_bus(1, 2600, NULL, 0); + /* i2c2 pins are used for gpio */ + omap_register_i2c_bus(3, 400, NULL, 0); + return 0; +} + +static void __init overo_init_irq(void) +{ + omap2_init_common_hw(mt46h32m32lf6_sdrc_params); + omap_init_irq(); + omap_gpio_init(); +} + +static struct omap_mmc_config overo_mmc_config __initdata = { + .mmc[0] = { + .enabled = 1, + .wire4 = 1, + }, + .mmc[1] = { + .enabled = 1, + .wire4 = 1, + }, +}; + +static struct platform_device overo_twl4030rtc_device = { + .name = "twl4030_rtc", + .id = -1, +}; + +static struct omap_board_config_kernel overo_config[] __initdata = { + { OMAP_TAG_UART, &overo_uart_config }, + { OMAP_TAG_MMC, &overo_mmc_config }, +}; + +static struct platform_device *overo_devices[] __initdata = { +#ifdef CONFIG_RTC_DRV_TWL4030 + &overo_twl4030rtc_device, +#endif +}; + +static void __init overo_init(void) +{ + overo_i2c_init(); + platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); + omap_board_config = overo_config; + omap_board_config_size = ARRAY_SIZE(overo_config); + omap_serial_init(); + hsmmc_init(); + usb_musb_init(); + usb_ehci_init(); + overo_flash_init(); + + if ((gpio_request(OVERO_GPIO_W2W_NRESET, + "OVERO_GPIO_W2W_NRESET") == 0) && + (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) { + gpio_export(OVERO_GPIO_W2W_NRESET, 0); + gpio_set_value(OVERO_GPIO_W2W_NRESET, 0); + udelay(10); + gpio_set_value(OVERO_GPIO_W2W_NRESET, 1); + } else { + printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_W2W_NRESET\n"); + } + + if ((gpio_request(OVERO_GPIO_BT_NRESET, "OVERO_GPIO_BT_NRESET") == 0) && + (gpio_direction_output(OVERO_GPIO_BT_NRESET, 1) == 0)) { + gpio_export(OVERO_GPIO_BT_NRESET, 0); + gpio_set_value(OVERO_GPIO_BT_NRESET, 0); + mdelay(6); + gpio_set_value(OVERO_GPIO_BT_NRESET, 1); + } else { + printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_BT_NRESET\n"); + } + + if ((gpio_request(OVERO_GPIO_USBH_CPEN, "OVERO_GPIO_USBH_CPEN") == 0) && + (gpio_direction_output(OVERO_GPIO_USBH_CPEN, 1) == 0)) + gpio_export(OVERO_GPIO_USBH_CPEN, 0); + else + printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_USBH_CPEN\n"); + + if ((gpio_request(OVERO_GPIO_USBH_NRESET, + "OVERO_GPIO_USBH_NRESET") == 0) && + (gpio_direction_output(OVERO_GPIO_USBH_NRESET, 1) == 0)) + gpio_export(OVERO_GPIO_USBH_NRESET, 0); + else + printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_USBH_NRESET\n"); +} + +static void __init overo_map_io(void) +{ + omap2_set_globals_343x(); + omap2_map_common_io(); +} + +MACHINE_START(OVERO, "Gumstix Overo") + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = overo_map_io, + .init_irq = overo_init_irq, + .init_machine = overo_init, + .timer = &omap_timer, +MACHINE_END
From: Steve Sakoman steve@sakoman.com
--- arch/arm/mach-omap2/board-overo.c | 11 +++ drivers/video/omap/Kconfig | 21 +++++ drivers/video/omap/Makefile | 1 + drivers/video/omap/lcd_overo.c | 179 +++++++++++++++++++++++++++++++++++++ 4 files changed, 212 insertions(+), 0 deletions(-) create mode 100644 drivers/video/omap/lcd_overo.c
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 42c1661..d4e86c7 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -159,12 +159,23 @@ static struct platform_device overo_twl4030rtc_device = { .id = -1, };
+static struct platform_device overo_lcd_device = { + .name = "overo_lcd", + .id = -1, +}; + +static struct omap_lcd_config overo_lcd_config __initdata = { + .ctrl_name = "internal", +}; + static struct omap_board_config_kernel overo_config[] __initdata = { { OMAP_TAG_UART, &overo_uart_config }, { OMAP_TAG_MMC, &overo_mmc_config }, + { OMAP_TAG_LCD, &overo_lcd_config }, };
static struct platform_device *overo_devices[] __initdata = { + &overo_lcd_device, #ifdef CONFIG_RTC_DRV_TWL4030 &overo_twl4030rtc_device, #endif diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig index bdeb8fb..5ebd591 100644 --- a/drivers/video/omap/Kconfig +++ b/drivers/video/omap/Kconfig @@ -7,6 +7,27 @@ config FB_OMAP help Frame buffer driver for OMAP based boards.
+choice + depends on FB_OMAP && MACH_OVERO + prompt "Screen resolution" + default FB_OMAP_079M3R + help + Selected desired screen resolution + +config FB_OMAP_031M3R + boolean "640 x 480 @ 60 Hz Reduced blanking" + +config FB_OMAP_048M3R + boolean "800 x 600 @ 60 Hz Reduced blanking" + +config FB_OMAP_079M3R + boolean "1024 x 768 @ 60 Hz Reduced blanking" + +config FB_OMAP_092M9R + boolean "1280 x 720 @ 60 Hz Reduced blanking" + +endchoice + config FB_OMAP_LCDC_EXTERNAL bool "External LCD controller support" depends on FB_OMAP diff --git a/drivers/video/omap/Makefile b/drivers/video/omap/Makefile index f9b5cd4..291c46e 100644 --- a/drivers/video/omap/Makefile +++ b/drivers/video/omap/Makefile @@ -35,6 +35,7 @@ objs-y$(CONFIG_MACH_OMAP2EVM) += lcd_omap2evm.o objs-y$(CONFIG_MACH_OMAP3EVM) += lcd_omap3evm.o objs-y$(CONFIG_MACH_OMAP3_BEAGLE) += lcd_omap3beagle.o objs-y$(CONFIG_FB_OMAP_LCD_MIPID) += lcd_mipid.o +objs-y$(CONFIG_MACH_OVERO) += lcd_overo.o
omapfb-objs := $(objs-yy)
diff --git a/drivers/video/omap/lcd_overo.c b/drivers/video/omap/lcd_overo.c new file mode 100644 index 0000000..2bc5c92 --- /dev/null +++ b/drivers/video/omap/lcd_overo.c @@ -0,0 +1,179 @@ +/* + * LCD panel support for the Gumstix Overo + * + * Author: Steve Sakoman steve@sakoman.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/i2c/twl4030.h> + +#include <mach/gpio.h> +#include <mach/mux.h> +#include <mach/omapfb.h> +#include <asm/mach-types.h> + +#define LCD_ENABLE 144 + +static int overo_panel_init(struct lcd_panel *panel, + struct omapfb_device *fbdev) +{ + if ((gpio_request(LCD_ENABLE, "LCD_ENABLE") == 0) && + (gpio_direction_output(LCD_ENABLE, 1) == 0)) + gpio_export(LCD_ENABLE, 0); + else + printk(KERN_ERR "could not obtain gpio for LCD_ENABLE\n"); + + return 0; +} + +static void overo_panel_cleanup(struct lcd_panel *panel) +{ + gpio_free(LCD_ENABLE); +} + +static int overo_panel_enable(struct lcd_panel *panel) +{ + gpio_set_value(LCD_ENABLE, 1); + return 0; +} + +static void overo_panel_disable(struct lcd_panel *panel) +{ + gpio_set_value(LCD_ENABLE, 0); +} + +static unsigned long overo_panel_get_caps(struct lcd_panel *panel) +{ + return 0; +} + +struct lcd_panel overo_panel = { + .name = "overo", + .config = OMAP_LCDC_PANEL_TFT, + .bpp = 16, + .data_lines = 24, + +#if defined CONFIG_FB_OMAP_031M3R + + /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ + .x_res = 640, + .y_res = 480, + .hfp = 48, + .hsw = 32, + .hbp = 80, + .vfp = 3, + .vsw = 4, + .vbp = 7, + .pixel_clock = 23500, + +#elif defined CONFIG_FB_OMAP_048M3R + + /* 800 x 600 @ 60 Hz Reduced blanking VESA CVT 0.48M3-R */ + .x_res = 800, + .y_res = 600, + .hfp = 48, + .hsw = 32, + .hbp = 80, + .vfp = 3, + .vsw = 4, + .vbp = 11, + .pixel_clock = 35500, + +#elif defined CONFIG_FB_OMAP_079M3R + + /* 1024 x 768 @ 60 Hz Reduced blanking VESA CVT 0.79M3-R */ + .x_res = 1024, + .y_res = 768, + .hfp = 48, + .hsw = 32, + .hbp = 80, + .vfp = 3, + .vsw = 4, + .vbp = 15, + .pixel_clock = 56000, + +#elif defined CONFIG_FB_OMAP_092M9R + + /* 1280 x 720 @ 60 Hz Reduced blanking VESA CVT 0.92M9-R */ + .x_res = 1280, + .y_res = 720, + .hfp = 48, + .hsw = 32, + .hbp = 80, + .vfp = 3, + .vsw = 5, + .vbp = 13, + .pixel_clock = 64000, + +#else + + /* use 640 x 480 if no config option */ + /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ + .x_res = 640, + .y_res = 480, + .hfp = 48, + .hsw = 32, + .hbp = 80, + .vfp = 3, + .vsw = 4, + .vbp = 7, + .pixel_clock = 23500, + +#endif + + .init = overo_panel_init, + .cleanup = overo_panel_cleanup, + .enable = overo_panel_enable, + .disable = overo_panel_disable, + .get_caps = overo_panel_get_caps, +}; + +static int overo_panel_probe(struct platform_device *pdev) +{ + omapfb_register_panel(&overo_panel); + return 0; +} + +static int overo_panel_remove(struct platform_device *pdev) +{ + /* omapfb does not have unregister_panel */ + return 0; +} + +static struct platform_driver overo_panel_driver = { + .probe = overo_panel_probe, + .remove = overo_panel_remove, + .driver = { + .name = "overo_lcd", + .owner = THIS_MODULE, + }, +}; + +static int __init overo_panel_drv_init(void) +{ + return platform_driver_register(&overo_panel_driver); +} + +static void __exit overo_panel_drv_exit(void) +{ + platform_driver_unregister(&overo_panel_driver); +} + +module_init(overo_panel_drv_init); +module_exit(overo_panel_drv_exit);
From: Steve Sakoman steve@sakoman.com
--- sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/twl4030.c | 628 ++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/twl4030.h | 197 ++++++++++++++ 4 files changed, 832 insertions(+), 0 deletions(-) create mode 100644 sound/soc/codecs/twl4030.c create mode 100644 sound/soc/codecs/twl4030.h
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 1db04a2..2f00e1e 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -50,3 +50,8 @@ config SND_SOC_CS4270_VD33_ERRATA config SND_SOC_TLV320AIC3X tristate depends on I2C + +config SND_SOC_TWL4030 + tristate + depends on SND_SOC && I2C + diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index d7b97ab..a519ced 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -10,6 +10,7 @@ snd-soc-wm9712-objs := wm9712.o snd-soc-wm9713-objs := wm9713.o snd-soc-cs4270-objs := cs4270.o snd-soc-tlv320aic3x-objs := tlv320aic3x.o +snd-soc-twl4030-objs := twl4030.o
obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o obj-$(CONFIG_SND_SOC_AK4535) += snd-soc-ak4535.o @@ -23,3 +24,4 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o +obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c new file mode 100644 index 0000000..683b8a1 --- /dev/null +++ b/sound/soc/codecs/twl4030.c @@ -0,0 +1,628 @@ +/* + * ALSA SoC TWL4030 codec driver + * + * Author: Steve Sakoman, steve@sakoman.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/i2c/twl4030.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> + +#include "twl4030.h" + +/* + * twl4030 register cache & default register settings + */ +static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { + 0x00, /* this register not used */ + 0x93, /* REG_CODEC_MODE (0x1) */ + 0xc3, /* REG_OPTION (0x2) */ + 0x00, /* REG_UNKNOWN (0x3) */ + 0x00, /* REG_MICBIAS_CTL (0x4) */ + 0x24, /* REG_ANAMICL (0x5) */ + 0x04, /* REG_ANAMICR (0x6) */ + 0x0a, /* REG_AVADC_CTL (0x7) */ + 0x00, /* REG_ADCMICSEL (0x8) */ + 0x00, /* REG_DIGMIXING (0x9) */ + 0x0c, /* REG_ATXL1PGA (0xA) */ + 0x0c, /* REG_ATXR1PGA (0xB) */ + 0x00, /* REG_AVTXL2PGA (0xC) */ + 0x00, /* REG_AVTXR2PGA (0xD) */ + 0x01, /* REG_AUDIO_IF (0xE) */ + 0x00, /* REG_VOICE_IF (0xF) */ + 0x00, /* REG_ARXR1PGA (0x10) */ + 0x00, /* REG_ARXL1PGA (0x11) */ + 0x6c, /* REG_ARXR2PGA (0x12) */ + 0x6c, /* REG_ARXL2PGA (0x13) */ + 0x00, /* REG_VRXPGA (0x14) */ + 0x00, /* REG_VSTPGA (0x15) */ + 0x00, /* REG_VRX2ARXPGA (0x16) */ + 0x0c, /* REG_AVDAC_CTL (0x17) */ + 0x00, /* REG_ARX2VTXPGA (0x18) */ + 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ + 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ + 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */ + 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */ + 0x00, /* REG_ATX2ARXPGA (0x1D) */ + 0x00, /* REG_BT_IF (0x1E) */ + 0x00, /* REG_BTPGA (0x1F) */ + 0x00, /* REG_BTSTPGA (0x20) */ + 0x00, /* REG_EAR_CTL (0x21) */ + 0x24, /* REG_HS_SEL (0x22) */ + 0x0a, /* REG_HS_GAIN_SET (0x23) */ + 0x00, /* REG_HS_POPN_SET (0x24) */ + 0x00, /* REG_PREDL_CTL (0x25) */ + 0x00, /* REG_PREDR_CTL (0x26) */ + 0x00, /* REG_PRECKL_CTL (0x27) */ + 0x00, /* REG_PRECKR_CTL (0x28) */ + 0x00, /* REG_HFL_CTL (0x29) */ + 0x00, /* REG_HFR_CTL (0x2A) */ + 0x00, /* REG_ALC_CTL (0x2B) */ + 0x00, /* REG_ALC_SET1 (0x2C) */ + 0x00, /* REG_ALC_SET2 (0x2D) */ + 0x00, /* REG_BOOST_CTL (0x2E) */ + 0x01, /* REG_SOFTVOL_CTL (0x2F) */ + 0x00, /* REG_DTMF_FREQSEL (0x30) */ + 0x00, /* REG_DTMF_TONEXT1H (0x31) */ + 0x00, /* REG_DTMF_TONEXT1L (0x32) */ + 0x00, /* REG_DTMF_TONEXT2H (0x33) */ + 0x00, /* REG_DTMF_TONEXT2L (0x34) */ + 0x00, /* REG_DTMF_TONOFF (0x35) */ + 0x00, /* REG_DTMF_WANONOFF (0x36) */ + 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ + 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ + 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ + 0x16, /* REG_APLL_CTL (0x3A) */ + 0x00, /* REG_DTMF_CTL (0x3B) */ + 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ + 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ + 0x00, /* REG_MISC_SET_1 (0x3E) */ + 0x00, /* REG_PCMBTMUX (0x3F) */ + 0x00, /* not used (0x40) */ + 0x00, /* not used (0x41) */ + 0x00, /* not used (0x42) */ + 0x00, /* REG_RX_PATH_SEL (0x43) */ + 0x00, /* REG_VDL_APGA_CTL (0x44) */ + 0x00, /* REG_VIBRA_CTL (0x45) */ + 0x00, /* REG_VIBRA_SET (0x46) */ + 0x00, /* REG_VIBRA_PWM_SET (0x47) */ + 0x00, /* REG_ANAMIC_GAIN (0x48) */ + 0x00, /* REG_MISC_SET_2 (0x49) */ +}; + +static void twl4030_dump_registers(void) +{ + int i = 0; + u8 data; + + printk(KERN_INFO "TWL 4030 Register dump for Audio Module\n"); + + for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { + twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &data, i); + printk(KERN_INFO "Register[0x%02x]=0x%02x\n", i, data); + } +} + +/* + * read twl4030 register cache + */ +static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 *cache = codec->reg_cache; + + return cache[reg]; +} + +/* + * write twl4030 register cache + */ +static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, + u8 reg, u8 value) +{ + u8 *cache = codec->reg_cache; + + if (reg >= TWL4030_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the twl4030 register space + */ +static int twl4030_write(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + twl4030_write_reg_cache(codec, reg, value); + return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); +} + +static void twl4030_init_chip(struct snd_soc_codec *codec) +{ + int i; + u8 byte; + + /* clear CODECPDZ prior to setting register defaults */ + twl4030_write(codec, REG_CODEC_MODE, + twl4030_reg[REG_CODEC_MODE] & ~CODECPDZ); + + udelay(10); + + /* set all audio section registers to reasonable defaults */ + for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) + twl4030_write(codec, i, twl4030_reg[i]); + +} + +static const struct snd_kcontrol_new twl4030_snd_controls[] = { + SOC_DOUBLE_R("Master Playback Volume", + REG_ARXL2PGA, REG_ARXR2PGA, + 0, 127, 0), + SOC_DOUBLE_R("Capture Volume", + REG_ATXL1PGA, REG_ATXR1PGA, + 0, 127, 0), +}; + +/* add non dapm controls */ +static int twl4030_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&twl4030_snd_controls[i], + codec, NULL)); + if (err < 0) + return err; + } + + return 0; +} + +static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("INL"), + SND_SOC_DAPM_INPUT("INR"), + + SND_SOC_DAPM_OUTPUT("OUTL"), + SND_SOC_DAPM_OUTPUT("OUTR"), + + SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0), +}; + +static const struct snd_soc_dapm_route intercon[] = { + /* outputs */ + {"OUTL", NULL, "DACL"}, + {"OUTR", NULL, "DACR"}, + + /* inputs */ + {"ADCL", NULL, "INL"}, + {"ADCR", NULL, "INR"}, +}; + +static int twl4030_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, + ARRAY_SIZE(twl4030_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +static void twl4030_power_up(struct snd_soc_codec *codec) +{ + u8 mode, byte, popn, hsgain; + + /* set CODECPDZ to turn on codec */ + mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); + twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ); + udelay(10); + + /* initiate offset cancellation */ + twl4030_write(codec, REG_ANAMICL, + twl4030_reg[REG_ANAMICL] | CNCL_OFFSET_START); + + /* wait for offset cancellation to complete */ + twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); + while ((byte & CNCL_OFFSET_START) == CNCL_OFFSET_START) + twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, + &byte, REG_ANAMICL); + + /* anti-pop when changing analog gain */ + twl4030_write(codec, REG_MISC_SET_1, + twl4030_reg[REG_MISC_SET_1] | SMOOTH_ANAVOL_EN); + + /* toggle CODECPDZ as per TRM */ + twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ); + udelay(10); + + twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ); + udelay(10); + + /* program anti-pop with bias ramp delay */ + popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); + popn &= RAMP_DELAY; + popn |= RAMP_DELAY_645MS; + twl4030_write(codec, REG_HS_POPN_SET, popn); + popn |= VMID_EN; + twl4030_write(codec, REG_HS_POPN_SET, popn); + + /* enable output stage and gain setting */ + hsgain = HSR_GAIN_0DB | HSL_GAIN_0DB; + twl4030_write(codec, REG_HS_GAIN_SET, hsgain); + + /* enable anti-pop ramp */ + popn |= RAMP_EN; + twl4030_write(codec, REG_HS_POPN_SET, popn); +} + +static void twl4030_power_down(struct snd_soc_codec *codec) +{ + u8 popn, hsgain, mode; + + /* disable anti-pop ramp */ + popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); + popn &= ~RAMP_EN; + twl4030_write(codec, REG_HS_POPN_SET, popn); + + /* disable output stage and gain setting */ + hsgain = HSR_GAIN_PWR_DOWN | HSL_GAIN_PWR_DOWN; + twl4030_write(codec, REG_HS_GAIN_SET, hsgain); + + /* disable bias out */ + popn &= ~VMID_EN; + twl4030_write(codec, REG_HS_POPN_SET, popn); + + /* power down */ + mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); + twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ); + + udelay(10); +} + +static int twl4030_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_ON: + twl4030_power_up(codec); + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + twl4030_power_down(codec); + break; + case SND_SOC_BIAS_OFF: + twl4030_power_down(codec); + break; + } + codec->bias_level = level; + + return 0; +} + +static int twl4030_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + u8 mode, old_mode, format, old_format; + + + /* bit rate */ + old_mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; + mode = old_mode; + mode &= ~APLL_RATE; + switch (params_rate(params)) { + case 44100: + mode |= APLL_RATE_44100; + break; + case 48000: + mode |= APLL_RATE_48000; + break; + default: + printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", + params_rate(params)); + return -EINVAL; + } + + if (mode != old_mode) { + /* change rate and turn codec back on */ + twl4030_write(codec, REG_CODEC_MODE, mode); + mode |= CODECPDZ; + twl4030_write(codec, REG_CODEC_MODE, mode); + } + + /* sample size */ + old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); + format = old_format; + format &= ~DATA_WIDTH; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + format |= DATA_WIDTH_16S_16W; + break; + case SNDRV_PCM_FORMAT_S24_LE: + format |= DATA_WIDTH_32S_24W; + break; + default: + printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", + params_format(params)); + return -EINVAL; + } + + if (format != old_format) { + + /* clear CODECPDZ before changing format (codec requirement) */ + mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); + mode &= ~CODECPDZ; + twl4030_write(codec, REG_CODEC_MODE, mode); + + /* change format */ + twl4030_write(codec, REG_AUDIO_IF, format); + + /* set CODECPDZ afterwards */ + mode |= CODECPDZ; + twl4030_write(codec, REG_CODEC_MODE, mode); + } + return 0; +} + +static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 infreq; + + switch (freq) { + case 19200000: + infreq = APLL_INFREQ_19200KHZ; + break; + case 26000000: + infreq = APLL_INFREQ_26000KHZ; + break; + case 38400000: + infreq = APLL_INFREQ_38400KHZ; + break; + default: + printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n", + freq); + return -EINVAL; + } + + infreq |= APLL_EN; + twl4030_write(codec, REG_APLL_CTL, infreq); + + return 0; +} + +static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 mode, old_format, format; + + /* get format */ + old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); + format = old_format; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + format &= ~(AIF_SLAVE_EN); + format |= CLK256FS_EN; + break; + case SND_SOC_DAIFMT_CBS_CFS: + format &= ~(CLK256FS_EN); + format |= AIF_SLAVE_EN; + break; + default: + return -EINVAL; + } + + /* interface format */ + format &= ~AIF_FORMAT; + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + format |= AIF_FORMAT_CODEC; + break; + default: + return -EINVAL; + } + + if (format != old_format) { + + /* clear CODECPDZ before changing format (codec requirement) */ + mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); + mode &= ~CODECPDZ; + twl4030_write(codec, REG_CODEC_MODE, mode); + + /* change format */ + twl4030_write(codec, REG_AUDIO_IF, format); + + /* set CODECPDZ afterwards */ + mode |= CODECPDZ; + twl4030_write(codec, REG_CODEC_MODE, mode); + } + + return 0; +} + +#define TWL4030_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) +#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) + +struct snd_soc_dai twl4030_dai = { + .name = "twl4030", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = TWL4030_RATES, + .formats = TWL4030_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 2, + .rates = TWL4030_RATES, + .formats = TWL4030_FORMATS,}, + .ops = { + .hw_params = twl4030_hw_params, + }, + .dai_ops = { + .set_sysclk = twl4030_set_dai_sysclk, + .set_fmt = twl4030_set_dai_fmt, + } +}; +EXPORT_SYMBOL_GPL(twl4030_dai); + +static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); + + return 0; +} + +static int twl4030_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + twl4030_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialize the driver + * register the mixer and dsp interfaces with the kernel + */ + +static int twl4030_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int ret = 0; + + printk(KERN_INFO "TWL4030 Audio Codec init \n"); + + codec->name = "twl4030"; + codec->owner = THIS_MODULE; + codec->read = twl4030_read_reg_cache; + codec->write = twl4030_write; + codec->set_bias_level = twl4030_set_bias_level; + codec->dai = &twl4030_dai; + codec->num_dai = 1; + codec->reg_cache_size = sizeof(twl4030_reg); + codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), + GFP_KERNEL); + if (codec->reg_cache == NULL) + return -ENOMEM; + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + printk(KERN_ERR "twl4030: failed to create pcms\n"); + goto pcm_err; + } + + twl4030_init_chip(codec); + + /* power on device */ + twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + twl4030_add_controls(codec); + twl4030_add_widgets(codec); + + ret = snd_soc_register_card(socdev); + if (ret < 0) { + printk(KERN_ERR "twl4030: failed to register card\n"); + goto card_err; + } + + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *twl4030_socdev; + +static int twl4030_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec; + + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + twl4030_socdev = socdev; + twl4030_init(socdev); + + return 0; +} + +static int twl4030_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + printk(KERN_INFO "TWL4030 Audio Codec remove\n"); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_twl4030 = { + .probe = twl4030_probe, + .remove = twl4030_remove, + .suspend = twl4030_suspend, + .resume = twl4030_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); + +MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); +MODULE_AUTHOR("Steve Sakoman"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h new file mode 100644 index 0000000..013dabc --- /dev/null +++ b/sound/soc/codecs/twl4030.h @@ -0,0 +1,197 @@ +/* + * ALSA SoC TWL4030 codec driver + * + * Author: Steve Sakoman steve@sakoman.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __TWL4030_AUDIO_H__ +#define __TWL4030_AUDIO_H__ + +#define REG_CODEC_MODE 0x1 +#define REG_OPTION 0x2 +#define REG_UNKNOWN 0x3 +#define REG_MICBIAS_CTL 0x4 +#define REG_ANAMICL 0x5 +#define REG_ANAMICR 0x6 +#define REG_AVADC_CTL 0x7 +#define REG_ADCMICSEL 0x8 +#define REG_DIGMIXING 0x9 +#define REG_ATXL1PGA 0xA +#define REG_ATXR1PGA 0xB +#define REG_AVTXL2PGA 0xC +#define REG_AVTXR2PGA 0xD +#define REG_AUDIO_IF 0xE +#define REG_VOICE_IF 0xF +#define REG_ARXR1PGA 0x10 +#define REG_ARXL1PGA 0x11 +#define REG_ARXR2PGA 0x12 +#define REG_ARXL2PGA 0x13 +#define REG_VRXPGA 0x14 +#define REG_VSTPGA 0x15 +#define REG_VRX2ARXPGA 0x16 +#define REG_AVDAC_CTL 0x17 +#define REG_ARX2VTXPGA 0x18 +#define REG_ARXL1_APGA_CTL 0x19 +#define REG_ARXR1_APGA_CTL 0x1A +#define REG_ARXL2_APGA_CTL 0x1B +#define REG_ARXR2_APGA_CTL 0x1C +#define REG_ATX2ARXPGA 0x1D +#define REG_BT_IF 0x1E +#define REG_BTPGA 0x1F +#define REG_BTSTPGA 0x20 +#define REG_EAR_CTL 0x21 +#define REG_HS_SEL 0x22 +#define REG_HS_GAIN_SET 0x23 +#define REG_HS_POPN_SET 0x24 +#define REG_PREDL_CTL 0x25 +#define REG_PREDR_CTL 0x26 +#define REG_PRECKL_CTL 0x27 +#define REG_PRECKR_CTL 0x28 +#define REG_HFL_CTL 0x29 +#define REG_HFR_CTL 0x2A +#define REG_ALC_CTL 0x2B +#define REG_ALC_SET1 0x2C +#define REG_ALC_SET2 0x2D +#define REG_BOOST_CTL 0x2E +#define REG_SOFTVOL_CTL 0x2F +#define REG_DTMF_FREQSEL 0x30 +#define REG_DTMF_TONEXT1H 0x31 +#define REG_DTMF_TONEXT1L 0x32 +#define REG_DTMF_TONEXT2H 0x33 +#define REG_DTMF_TONEXT2L 0x34 +#define REG_DTMF_TONOFF 0x35 +#define REG_DTMF_WANONOFF 0x36 +#define REG_I2S_RX_SCRAMBLE_H 0x37 +#define REG_I2S_RX_SCRAMBLE_M 0x38 +#define REG_I2S_RX_SCRAMBLE_L 0x39 +#define REG_APLL_CTL 0x3A +#define REG_DTMF_CTL 0x3B +#define REG_DTMF_PGA_CTL2 0x3C +#define REG_DTMF_PGA_CTL1 0x3D +#define REG_MISC_SET_1 0x3E +#define REG_PCMBTMUX 0x3F +#define REG_RX_PATH_SEL 0x43 +#define REG_VDL_APGA_CTL 0x44 +#define REG_VIBRA_CTL 0x45 +#define REG_VIBRA_SET 0x46 +#define REG_VIBRA_PWM_SET 0x47 +#define REG_ANAMIC_GAIN 0x48 +#define REG_MISC_SET_2 0x49 + +#define TWL4030_CACHEREGNUM (REG_MISC_SET_2 + 1) + +/* Bitfield Definitions */ + +/* CODEC_MODE (0x01) Fields */ + +#define APLL_RATE 0xF0 +#define APLL_RATE_8000 0x00 +#define APLL_RATE_11025 0x10 +#define APLL_RATE_12000 0x20 +#define APLL_RATE_16000 0x40 +#define APLL_RATE_22050 0x50 +#define APLL_RATE_24000 0x60 +#define APLL_RATE_32000 0x80 +#define APLL_RATE_44100 0x90 +#define APLL_RATE_48000 0xA0 +#define SEL_16K 0x04 +#define CODECPDZ 0x02 +#define OPT_MODE 0x01 + +/* ANAMICL (0x05) Fields */ +#define CNCL_OFFSET_START 0x80 +#define OFFSET_CNCL_SEL 0x60 +#define OFFSET_CNCL_SEL_ARX1 0x00 +#define OFFSET_CNCL_SEL_ARX2 0x20 +#define OFFSET_CNCL_SEL_VRX 0x40 +#define OFFSET_CNCL_SEL_ALL 0x60 +#define MICAMPL_EN 0x10 +#define CKMIC_EN 0x08 +#define AUXL_EN 0x04 +#define HSMIC_EN 0x02 +#define MAINMIC_EN 0x01 + +/* ANAMICR (0x06) Fields */ +#define MICAMPR_EN 0x10 +#define AUXR_EN 0x04 +#define SUBMIC_EN 0x01 + +/* AUDIO_IF (0x0E) Fields */ + +#define AIF_SLAVE_EN 0x80 +#define DATA_WIDTH 0x60 +#define DATA_WIDTH_16S_16W 0x00 +#define DATA_WIDTH_32S_16W 0x40 +#define DATA_WIDTH_32S_24W 0x60 +#define AIF_FORMAT 0x18 +#define AIF_FORMAT_CODEC 0x00 +#define AIF_FORMAT_LEFT 0x08 +#define AIF_FORMAT_RIGHT 0x10 +#define AIF_FORMAT_TDM 0x18 +#define AIF_TRI_EN 0x04 +#define CLK256FS_EN 0x02 +#define AIF_EN 0x01 + +/* HS_GAIN_SET (0x23) Fields */ + +#define HSR_GAIN 0x0C +#define HSR_GAIN_PWR_DOWN 0x00 +#define HSR_GAIN_PLUS_6DB 0x04 +#define HSR_GAIN_0DB 0x08 +#define HSR_GAIN_MINUS_6DB 0x0C +#define HSL_GAIN 0x03 +#define HSL_GAIN_PWR_DOWN 0x00 +#define HSL_GAIN_PLUS_6DB 0x01 +#define HSL_GAIN_0DB 0x02 +#define HSL_GAIN_MINUS_6DB 0x03 + +/* HS_POPN_SET (0x24) Fields */ + +#define VMID_EN 0x40 +#define EXTMUTE 0x20 +#define RAMP_DELAY 0x1C +#define RAMP_DELAY_20MS 0x00 +#define RAMP_DELAY_40MS 0x04 +#define RAMP_DELAY_81MS 0x08 +#define RAMP_DELAY_161MS 0x0C +#define RAMP_DELAY_323MS 0x10 +#define RAMP_DELAY_645MS 0x14 +#define RAMP_DELAY_1291MS 0x18 +#define RAMP_DELAY_2581MS 0x1C +#define RAMP_EN 0x02 + +/* APLL_CTL (0x3A) Fields */ + +#define APLL_EN 0x10 +#define APLL_INFREQ 0x0F +#define APLL_INFREQ_19200KHZ 0x05 +#define APLL_INFREQ_26000KHZ 0x06 +#define APLL_INFREQ_38400KHZ 0x0F + +/* REG_MISC_SET_1 (0x3E) Fields */ + +#define CLK64_EN 0x80 +#define SCRAMBLE_EN 0x40 +#define FMLOOP_EN 0x20 +#define SMOOTH_ANAVOL_EN 0x02 +#define DIGMIC_LR_SWAP_EN 0x01 + +extern struct snd_soc_dai twl4030_dai; +extern struct snd_soc_codec_device soc_codec_dev_twl4030; + +#endif /* End of __TWL4030_AUDIO_H__ */
From: Steve Sakoman steve@sakoman.com
--- sound/soc/omap/Kconfig | 9 +++ sound/soc/omap/Makefile | 3 + sound/soc/omap/overo.c | 149 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+), 0 deletions(-) create mode 100644 sound/soc/omap/overo.c
diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig index aea27e7..d7b8939 100644 --- a/sound/soc/omap/Kconfig +++ b/sound/soc/omap/Kconfig @@ -13,3 +13,12 @@ config SND_OMAP_SOC_N810 select SND_SOC_TLV320AIC3X help Say Y if you want to add support for SoC audio on Nokia N810. + +config SND_OMAP_SOC_OVERO + tristate "SoC Audio support for Gumstix Overo" + depends on SND_OMAP_SOC && MACH_OVERO + select SND_OMAP_SOC_MCBSP + select SND_SOC_TWL4030 + help + Say Y if you want to add support for SoC audio on the Gumstix Overo. + diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile index d8d8d58..b96b97b 100644 --- a/sound/soc/omap/Makefile +++ b/sound/soc/omap/Makefile @@ -7,5 +7,8 @@ obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o
# OMAP Machine Support snd-soc-n810-objs := n810.o +snd-soc-overo-objs := overo.o
obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o +obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o + diff --git a/sound/soc/omap/overo.c b/sound/soc/omap/overo.c new file mode 100644 index 0000000..542ff6b --- /dev/null +++ b/sound/soc/omap/overo.c @@ -0,0 +1,149 @@ +/* + * overo.c -- SoC audio for Gumstix Overo + * + * Author: Steve Sakoman steve@sakoman.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> + +#include <asm/mach-types.h> +#include <mach/hardware.h> +#include <mach/gpio.h> +#include <mach/mcbsp.h> + +#include "omap-mcbsp.h" +#include "omap-pcm.h" +#include "../codecs/twl4030.h" + +static int overo_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + int ret; + + /* Set codec DAI configuration */ + ret = snd_soc_dai_set_fmt(codec_dai, + SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) { + printk(KERN_ERR "can't set codec DAI configuration\n"); + return ret; + } + + /* Set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(cpu_dai, + SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) { + printk(KERN_ERR "can't set cpu DAI configuration\n"); + return ret; + } + + /* Set the codec system clock for DAC and ADC */ + ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000, + SND_SOC_CLOCK_IN); + if (ret < 0) { + printk(KERN_ERR "can't set codec system clock\n"); + return ret; + } + + return 0; +} + +static struct snd_soc_ops overo_ops = { + .hw_params = overo_hw_params, +}; + +/* Digital audio interface glue - connects codec <--> CPU */ +static struct snd_soc_dai_link overo_dai = { + .name = "TWL4030", + .stream_name = "TWL4030", + .cpu_dai = &omap_mcbsp_dai[0], + .codec_dai = &twl4030_dai, + .ops = &overo_ops, +}; + +/* Audio machine driver */ +static struct snd_soc_machine snd_soc_machine_overo = { + .name = "overo", + .dai_link = &overo_dai, + .num_links = 1, +}; + +/* Audio subsystem */ +static struct snd_soc_device overo_snd_devdata = { + .machine = &snd_soc_machine_overo, + .platform = &omap_soc_platform, + .codec_dev = &soc_codec_dev_twl4030, +}; + +static struct platform_device *overo_snd_device; + +static int __init overo_soc_init(void) +{ + int ret; + + printk(KERN_INFO "overo SoC init\n"); + if (!machine_is_overo()) { + printk(KERN_ERR "Not Overo!\n"); + return -ENODEV; + } + + overo_snd_device = platform_device_alloc("soc-audio", -1); + if (!overo_snd_device) { + printk(KERN_ERR "Platform device allocation failed\n"); + return -ENOMEM; + } + + platform_set_drvdata(overo_snd_device, &overo_snd_devdata); + overo_snd_devdata.dev = &overo_snd_device->dev; + *(unsigned int *)overo_dai.cpu_dai->private_data = 1; /* McBSP2 */ + + ret = platform_device_add(overo_snd_device); + if (ret) + goto err1; + + return 0; + +err1: + printk(KERN_ERR "Unable to add platform device\n"); + platform_device_put(overo_snd_device); + + return ret; +} + +static void __exit overo_soc_exit(void) +{ + platform_device_unregister(overo_snd_device); +} + +module_init(overo_soc_init); +module_exit(overo_soc_exit); + +MODULE_AUTHOR("Steve Sakoman steve@sakoman.com"); +MODULE_DESCRIPTION("ALSA SoC overo"); +MODULE_LICENSE("GPL");
From: Steve Sakoman steve@sakoman.com
--- arch/arm/configs/overo_defconfig | 1973 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 1973 insertions(+), 0 deletions(-) create mode 100644 arch/arm/configs/overo_defconfig
diff --git a/arch/arm/configs/overo_defconfig b/arch/arm/configs/overo_defconfig new file mode 100644 index 0000000..b21f7ec --- /dev/null +++ b/arch/arm/configs/overo_defconfig @@ -0,0 +1,1973 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.27-rc3-omap1 +# Sun Aug 31 21:51:11 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +CONFIG_HAVE_CLK=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_LSF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y +# CONFIG_ARCH_MSM7X00A is not set + +# +# TI OMAP Implementations +# +CONFIG_ARCH_OMAP_OTG=y +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_OMAP3=y + +# +# OMAP Feature Selections +# +# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set +# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set +CONFIG_OMAP_SMARTREFLEX=y +# CONFIG_OMAP_SMARTREFLEX_TESTING is not set +# CONFIG_OMAP_RESET_CLOCKS is not set +CONFIG_OMAP_BOOT_TAG=y +CONFIG_OMAP_BOOT_REASON=y +# CONFIG_OMAP_COMPONENT_VERSION is not set +# CONFIG_OMAP_GPIO_SWITCH is not set +# CONFIG_OMAP_MUX is not set +CONFIG_OMAP_MCBSP=y +# CONFIG_OMAP_MMU_FWK is not set +# CONFIG_OMAP_MBOX_FWK is not set +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_32K_TIMER_HZ=128 +CONFIG_OMAP_DM_TIMER=y +# CONFIG_OMAP_LL_DEBUG_UART1 is not set +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +CONFIG_OMAP_LL_DEBUG_UART3=y +# CONFIG_OMAP_PM_NONE is not set +CONFIG_OMAP_PM_NOOP=y +CONFIG_ARCH_OMAP34XX=y +CONFIG_ARCH_OMAP3430=y + +# +# OMAP Board Type +# +# CONFIG_MACH_OMAP_LDP is not set +# CONFIG_MACH_OMAP_3430SDP is not set +# CONFIG_MACH_OMAP3EVM is not set +# CONFIG_MACH_OMAP3_BEAGLE is not set +CONFIG_MACH_OVERO=y +CONFIG_OMAP_TICK_GPTIMER=1 + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=128 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_LEDS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE=" debug " +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +# CONFIG_NEON_CACHE_BUG is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUSB=m +CONFIG_BT_HCIUSB_SCO=y +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_HCIBPA10X=y +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIBRF6150 is not set +# CONFIG_BT_HCIH4P is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +CONFIG_CFG80211=y +CONFIG_NL80211=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_MAC80211=y + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_RC_DEFAULT_PID=y +CONFIG_MAC80211_RC_DEFAULT="pid" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_IEEE80211=y +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=y +CONFIG_IEEE80211_CRYPT_CCMP=y +CONFIG_IEEE80211_CRYPT_TKIP=y +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +# CONFIG_MTD_ONENAND_GENERIC is not set +CONFIG_MTD_ONENAND_OMAP2=y +# CONFIG_MTD_ONENAND_OTP is not set +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set +# CONFIG_MTD_ONENAND_SIM is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +CONFIG_EEPROM_93CX6=m +# CONFIG_OMAP_STI is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_RAID5_RESHAPE=y +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m +# CONFIG_DM_UEVENT is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_MII=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_USB=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_LIBERTAS_DEBUG=y +CONFIG_USB_ZD1201=m +# CONFIG_USB_NET_RNDIS_WLAN is not set +CONFIG_RTL8187=m +# CONFIG_MAC80211_HWSIM is not set +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +# CONFIG_IWLWIFI_LEDS is not set +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_ZD1211RW is not set +# CONFIG_RT2X00 is not set + +# +# USB Network Adapters +# +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_CDCETHER=y +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +CONFIG_SENSORS_EEPROM=y +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_ISP1301_OMAP is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_TLV320AIC23 is not set +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_GPIO=y +CONFIG_TWL4030_MADC=m +CONFIG_TWL4030_USB=y +CONFIG_TWL4030_USB_HS_ULPI=y +CONFIG_TWL4030_PWRBUTTON=y +CONFIG_TWL4030_POWEROFF=y +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_LP5521 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +CONFIG_SPI_OMAP24XX=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_TSC2101 is not set +# CONFIG_SPI_TSC2102 is not set +# CONFIG_SPI_TSC210X is not set +# CONFIG_SPI_TSC2301 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=m +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_BQ27x00 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_TSC210X is not set +CONFIG_SENSORS_OMAP34XX=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_OMAP_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_DVB_CORE=m +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_CX25840=m +CONFIG_VIDEO_CX2341X=m +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_TUNER_3036 is not set +# CONFIG_VIDEO_AU0828 is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +# CONFIG_USB_GSPCA is not set +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +# CONFIG_VIDEO_EM28XX is not set +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_USBVIDEO=m +CONFIG_USB_VICAM=m +CONFIG_USB_IBMCAM=m +CONFIG_USB_KONICAWC=m +CONFIG_USB_QUICKCAM_MESSENGER=m +# CONFIG_USB_ET61X251 is not set +CONFIG_VIDEO_OVCAMCHIP=m +CONFIG_USB_W9968CF=m +CONFIG_USB_OV511=m +CONFIG_USB_SE401=m +CONFIG_USB_SN9C102=m +CONFIG_USB_STV680=m +# CONFIG_USB_ZC0301 is not set +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_ZR364XX=m +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_TEA5761 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_SI470X is not set +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set + +# +# Supported USB Adapters +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +# CONFIG_DVB_USB_DW2102 is not set +# CONFIG_DVB_USB_ANYSEE is not set +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_DVB_CINERGYT2=m +# CONFIG_DVB_CINERGYT2_TUNING is not set +# CONFIG_DVB_SIANO_SMS1XXX is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +# CONFIG_DVB_DRX397XD is not set +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_TDA10048=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_S5H1411=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_LNBP21=m +# CONFIG_DVB_ISL6405 is not set +CONFIG_DVB_ISL6421=m +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_FB_OMAP=y +# CONFIG_FB_OMAP_031M3R is not set +# CONFIG_FB_OMAP_048M3R is not set +CONFIG_FB_OMAP_079M3R=y +# CONFIG_FB_OMAP_092M9R is not set +# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set +# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set +CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=8 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_LOGO is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +# CONFIG_SND_PCM_XRUN_DEBUG is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +# CONFIG_SND_OMAP_AIC23 is not set +# CONFIG_SND_OMAP_TSC2101 is not set +# CONFIG_SND_SX1 is not set +# CONFIG_SND_OMAP_TSC2102 is not set +# CONFIG_SND_OMAP24XX_EAC is not set +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_SOC=y +CONFIG_SND_OMAP_SOC=y +CONFIG_SND_OMAP_SOC_MCBSP=y +CONFIG_SND_OMAP_SOC_OVERO=y +CONFIG_SND_SOC_TWL4030=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_OMAP_EHCI_PHY_MODE=y +# CONFIG_OMAP_EHCI_TLL_MODE is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SOC=y + +# +# OMAP 343x high speed USB support +# +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_PERIPHERAL is not set +# CONFIG_USB_MUSB_OTG is not set +CONFIG_USB_MUSB_HDRC_HCD=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_MUSB_LOGLEVEL=0 + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=y + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_EZUSB is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP2101 is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +# CONFIG_USB_BERRY_CHARGE is not set +CONFIG_USB_LED=m +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_OMAP_HS=y +# CONFIG_MMC_SPI is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_OMAP_DEBUG is not set +# CONFIG_LEDS_OMAP is not set +# CONFIG_LEDS_OMAP_PWM is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_PCA955X is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +CONFIG_RTC_DRV_TWL4030=y +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_UIO is not set + +# +# CBUS support +# +# CONFIG_CBUS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_CRYPTD=m +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y
On Wed, 3 Sep 2008 22:01:59 -0700 "ext sakoman@gmail.com" sakoman@gmail.com wrote:
From: Steve Sakoman steve@sakoman.com
sound/soc/omap/Kconfig | 9 +++ sound/soc/omap/Makefile | 3 + sound/soc/omap/overo.c | 149 ++++++++++++++++++++++++++++++++++++++ +++++++++ 3 files changed, 161 insertions(+), 0 deletions(-) create mode 100644 sound/soc/omap/overo.c
diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig index aea27e7..d7b8939 100644 --- a/sound/soc/omap/Kconfig +++ b/sound/soc/omap/Kconfig @@ -13,3 +13,12 @@ config SND_OMAP_SOC_N810 select SND_SOC_TLV320AIC3X help Say Y if you want to add support for SoC audio on Nokia N810. + +config SND_OMAP_SOC_OVERO
- tristate "SoC Audio support for Gumstix Overo"
- depends on SND_OMAP_SOC && MACH_OVERO
- select SND_OMAP_SOC_MCBSP
- select SND_SOC_TWL4030
- help
Say Y if you want to add support for SoC audio on theGumstix Overo. +
Just advertisement that Overo (+ Beagle and SDP) needs two patches from me in order to work. One for McBSP low-level driver and one for McBSP DAI driver.
http://marc.info/?l=linux-omap&m=121931987919296&w=2
http://marc.info/?l=linux-omap&m=121931988119303&w=2 http://marc.info/?l=linux-omap&m=121931988019300&w=2
Assuming TWL4030 core and codec driver will find their way into upstream, it looks like sound/soc/omap/overo.c is still "make randconfig" safe even if my patches are missing.
I'll post my second patch to alsa-devel as soon it's possible after joint effort to clean low-level McBSP driver in linux-omap is done :-)
Jarkko
On Thu, Sep 4, 2008 at 3:40 AM, Jarkko Nikula jarkko.nikula@nokia.com wrote:
Just advertisement that Overo (+ Beagle and SDP) needs two patches from me in order to work. One for McBSP low-level driver and one for McBSP DAI driver.
This is correct! I unfortunately left that out of my cover letter.
Steve
On Wed, Sep 03, 2008 at 10:01:59PM -0700, sakoman@gmail.com wrote:
From: Steve Sakoman steve@sakoman.com
You should sign it off too. Anyway, it looks good:
Acked-by: Mark Brown broonie@opensource.wolfsonmicro.com
On Wed, 3 Sep 2008 22:01:58 -0700 "ext sakoman@gmail.com" sakoman@gmail.com wrote:
From: Steve Sakoman steve@sakoman.com
sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/twl4030.c | 628 +++++++++++++++++++++++++++++++++++
...
+static void twl4030_dump_registers(void) +{
This is not needed since there is already nice function for it: sound/soc/soc-core.c: codec_reg_show.
+static void twl4030_power_up(struct snd_soc_codec *codec) +{
- u8 mode, byte, popn, hsgain;
...
- /* wait for offset cancellation to complete */
- twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
REG_ANAMICL);
- while ((byte & CNCL_OFFSET_START) == CNCL_OFFSET_START)
twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE,&byte, REG_ANAMICL);
Probably some timeout escape here.
+static void twl4030_power_down(struct snd_soc_codec *codec) +{
...
- udelay(10);
+}
REVISIT comment for these kind of magic delays if doesn't work without.
+static int twl4030_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)+{
...
- switch (params_rate(params)) {
- case 44100:
mode |= APLL_RATE_44100;break;- case 48000:
mode |= APLL_RATE_48000;break;- default:
printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
params_rate(params));return -EINVAL;- }
I checked that chip supports also other standard rates from 8 kHz, 11.025 kHz, etc. However I didn't find from quick look how this relates to interface rate. I would say that small TODO comment to whom who has platform to try these combinations would be nice.
+static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)+{
...
- infreq |= APLL_EN;
- twl4030_write(codec, REG_APLL_CTL, infreq);
- return 0;
+}
If this actually place for set_pll callback if one wants to manage PLL (APLL_EN bit) dynamically?
Jarkko
On Thu, Sep 04, 2008 at 01:26:32PM +0300, Jarkko Nikula wrote:
+static void twl4030_dump_registers(void) +{
This is not needed since there is already nice function for it: sound/soc/soc-core.c: codec_reg_show.
It's doing something slighly different and dumping the chip registers rather than the register cache (the read() operation for this chip is _read_reg_cache()) but yes, should be sensible to drop it.
+static void twl4030_power_down(struct snd_soc_codec *codec) +{
...
- udelay(10);
+}
REVISIT comment for these kind of magic delays if doesn't work without.
Alternatively, if writes to CODECPDZ are always supposed to have delays after them according to the datasheet perhaps a function to wrap up the write plus delay would be a good idea?
+static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)+{
...
- infreq |= APLL_EN;
- twl4030_write(codec, REG_APLL_CTL, infreq);
- return 0;
+}
If this actually place for set_pll callback if one wants to manage PLL (APLL_EN bit) dynamically?
Might be nice, yes. That said, how much flexibility is there regarding the PLL on this part? If the configuration is determined very strongly by the audio configuration and it's likely that the configuration is entirely determined by the current audio status then it may not be worth exposing the decision making to the user, at least for a first pass. The impression I got from the code was that it was very fixed purpose.
If you do do this then make sure it interacts well with power_up() and power_down().
Hi,
I have made a sound driver similar to mpc5200_psc.c and tlv codec. I have 2 channels which are interleaved.
I want to register these two channels as different devices on same card, How can i do it.
Thanks, Dinesh Dua
On Thu, Sep 4, 2008 at 3:26 AM, Jarkko Nikula jarkko.nikula@nokia.com wrote:
On Wed, 3 Sep 2008 22:01:58 -0700 "ext sakoman@gmail.com" sakoman@gmail.com wrote:
+static void twl4030_dump_registers(void) +{
This is not needed since there is already nice function for it: sound/soc/soc-core.c: codec_reg_show.
I could probably get rid of this function. It was quite useful during debugging and I was not aware of codec_reg_show. IIRC, most of the other codec drivers also have the equivalent of this function, so we might want to clean them up too if there is a standard function to replace them.
/* wait for offset cancellation to complete */twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,REG_ANAMICL);
while ((byte & CNCL_OFFSET_START) == CNCL_OFFSET_START)twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE,&byte, REG_ANAMICL);Probably some timeout escape here.
Right you are! This is a pet peeve of mine and I am humiliated I let this sneak in :-)
+static void twl4030_power_down(struct snd_soc_codec *codec) +{
...
udelay(10);+}
REVISIT comment for these kind of magic delays if doesn't work without.
It *seems* to work without them, but every historic TI driver seemed to have them. I figured that they might know something not reflected in the documentation. I will add a REVIST comment.
+static int twl4030_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)+{
...
switch (params_rate(params)) {case 44100:mode |= APLL_RATE_44100;break;case 48000:mode |= APLL_RATE_48000;break;default:printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
params_rate(params));return -EINVAL;}I checked that chip supports also other standard rates from 8 kHz, 11.025 kHz, etc. However I didn't find from quick look how this relates to interface rate. I would say that small TODO comment to whom who has platform to try these combinations would be nice.
It would be trivial to add support for the other data rates. IIRC, I just matched the data rates that were supported by mcbsp.
+static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)+{
...
infreq |= APLL_EN;twl4030_write(codec, REG_APLL_CTL, infreq);return 0;+}
If this actually place for set_pll callback if one wants to manage PLL (APLL_EN bit) dynamically?
I can add a TODO comment for this. I'm under delivery pressure for the next few weeks and won't get time to work on this.
Steve
On Thu, Sep 04, 2008 at 07:32:28AM -0700, Steve Sakoman wrote:
On Thu, Sep 4, 2008 at 3:26 AM, Jarkko Nikula jarkko.nikula@nokia.com wrote:
+static void twl4030_dump_registers(void) +{
This is not needed since there is already nice function for it: sound/soc/soc-core.c: codec_reg_show.
I could probably get rid of this function. It was quite useful during debugging and I was not aware of codec_reg_show. IIRC, most of the other codec drivers also have the equivalent of this function, so we might want to clean them up too if there is a standard function to replace them.
Any references? None of the in-tree drivers have them...
+static void twl4030_power_down(struct snd_soc_codec *codec) +{
...
udelay(10);+}
REVISIT comment for these kind of magic delays if doesn't work without.
It *seems* to work without them, but every historic TI driver seemed to have them. I figured that they might know something not reflected in the documentation. I will add a REVIST comment.
This sort of stuff is very common in codec drivers - normally the delays are there to allow the analogue side of the system time to settle down (waiting for capacitors to charge/discharge or reference voltages to stabalise, for example). Ideally they have comments saying what's going on, of course. Missing these delays often won't actually stop things working completely but will instead do things like reduce performance or generate audio artefacts - and sometimes it's application dependant if these are important.
On Fri, Sep 5, 2008 at 3:30 AM, Mark Brown broonie@sirena.org.uk wrote:
On Thu, Sep 04, 2008 at 07:32:28AM -0700, Steve Sakoman wrote:
On Thu, Sep 4, 2008 at 3:26 AM, Jarkko Nikula jarkko.nikula@nokia.com wrote:
I could probably get rid of this function. It was quite useful during debugging and I was not aware of codec_reg_show. IIRC, most of the other codec drivers also have the equivalent of this function, so we might want to clean them up too if there is a standard function to replace them.
Any references? None of the in-tree drivers have them...
Heh, you are correct.
I could swear I did a cut'n'paste on the reg cache stuff including the dump. Perhaps just old timers disease . . .
It *seems* to work without them, but every historic TI driver seemed to have them. I figured that they might know something not reflected in the documentation. I will add a REVIST comment.
This sort of stuff is very common in codec drivers - normally the delays are there to allow the analogue side of the system time to settle down (waiting for capacitors to charge/discharge or reference voltages to stabalise, for example). Ideally they have comments saying what's going on, of course. Missing these delays often won't actually stop things working completely but will instead do things like reduce performance or generate audio artefacts - and sometimes it's application dependant if these are important.
That was my assumption too, so I left them under the "better safe than sorry" theory.
As suggested, I moved all sets and clears of CODEXPDZ to function calls which include the delay.
Thanks again for the comments.
Steve
On Wed, Sep 03, 2008 at 10:01:58PM -0700, sakoman@gmail.com wrote:
+static void twl4030_power_up(struct snd_soc_codec *codec) +{
- u8 mode, byte, popn, hsgain;
- /* set CODECPDZ to turn on codec */
- mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE);
- twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ);
- udelay(10);
- /* initiate offset cancellation */
- twl4030_write(codec, REG_ANAMICL,
twl4030_reg[REG_ANAMICL] | CNCL_OFFSET_START);
It looks a bit odd to see this reading the register defaults rather than the register cache.
- /* wait for offset cancellation to complete */
- twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL);
- while ((byte & CNCL_OFFSET_START) == CNCL_OFFSET_START)
twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE,&byte, REG_ANAMICL);
How long is this likely to take? If it might take a while then putting a delay in between reads might be nice. As Jarkko said, a timeout would be a good idea too in case something went wrong.
- /* anti-pop when changing analog gain */
- twl4030_write(codec, REG_MISC_SET_1,
twl4030_reg[REG_MISC_SET_1] | SMOOTH_ANAVOL_EN);
Another one reading the register defaults rather than register cache...
- /* disable bias out */
- popn &= ~VMID_EN;
- twl4030_write(codec, REG_HS_POPN_SET, popn);
...
- case SND_SOC_BIAS_ON:
twl4030_power_up(codec);break;- case SND_SOC_BIAS_PREPARE:
break;- case SND_SOC_BIAS_STANDBY:
twl4030_power_down(codec);break;
Normally SND_SOC_BIAS_STANDBY would leave Vmid enabled but your power down function turns it off. The normal thing here is to have standby bring the codec up and then apply relatively small tweaks in _ON and _PREPARE that do things like improve the quality of the reference voltages. Equally well, since the driver does not yet implement DAPM support doing this will give you power savings that you wouldn't otherwise get.
Does the codec have any bypass paths that can be set up? If not it shouldn't do much harm either way until you implement DAPM.
+/* AUDIO_IF (0x0E) Fields */
+#define AIF_SLAVE_EN 0x80 +#define DATA_WIDTH 0x60
These should really all get namespaced - some of them look relatively likely to collide with registers for CPU side stuff.
On Thu, Sep 4, 2008 at 5:04 AM, Mark Brown broonie@sirena.org.uk wrote:
On Wed, Sep 03, 2008 at 10:01:58PM -0700, sakoman@gmail.com wrote:
/* initiate offset cancellation */twl4030_write(codec, REG_ANAMICL,twl4030_reg[REG_ANAMICL] | CNCL_OFFSET_START);It looks a bit odd to see this reading the register defaults rather than the register cache.
True. I will fix this.
/* wait for offset cancellation to complete */twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL);while ((byte & CNCL_OFFSET_START) == CNCL_OFFSET_START)twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE,&byte, REG_ANAMICL);How long is this likely to take? If it might take a while then putting a delay in between reads might be nice. As Jarkko said, a timeout would be a good idea too in case something went wrong.
It happens quite quickly. I'll add an exit to the loop and measure how many passes it takes. If it is a large number I'll add a delay.
/* anti-pop when changing analog gain */twl4030_write(codec, REG_MISC_SET_1,twl4030_reg[REG_MISC_SET_1] | SMOOTH_ANAVOL_EN);Another one reading the register defaults rather than register cache...
I'll fix this.
/* disable bias out */popn &= ~VMID_EN;twl4030_write(codec, REG_HS_POPN_SET, popn);...
case SND_SOC_BIAS_ON:twl4030_power_up(codec);break;case SND_SOC_BIAS_PREPARE:break;case SND_SOC_BIAS_STANDBY:twl4030_power_down(codec);break;Normally SND_SOC_BIAS_STANDBY would leave Vmid enabled but your power down function turns it off. The normal thing here is to have standby bring the codec up and then apply relatively small tweaks in _ON and _PREPARE that do things like improve the quality of the reference voltages. Equally well, since the driver does not yet implement DAPM support doing this will give you power savings that you wouldn't otherwise get.
Does the codec have any bypass paths that can be set up? If not it shouldn't do much harm either way until you implement DAPM.
How about I add a "TODO" on this? I'm swamped for the next few weeks and won't be able to give it the attention it deserves test-wise.
+/* AUDIO_IF (0x0E) Fields */
+#define AIF_SLAVE_EN 0x80 +#define DATA_WIDTH 0x60
These should really all get namespaced - some of them look relatively likely to collide with registers for CPU side stuff.
Good point.
Steve
On Thu, Sep 04, 2008 at 07:48:02AM -0700, Steve Sakoman wrote:
On Thu, Sep 4, 2008 at 5:04 AM, Mark Brown broonie@sirena.org.uk wrote:
Normally SND_SOC_BIAS_STANDBY would leave Vmid enabled but your power down function turns it off. The normal thing here is to have standby bring the codec up and then apply relatively small tweaks in _ON and
...
Does the codec have any bypass paths that can be set up? If not it shouldn't do much harm either way until you implement DAPM.
How about I add a "TODO" on this? I'm swamped for the next few weeks and won't be able to give it the attention it deserves test-wise.
Like I say, if the codec/driver implement any bypass paths (paths that carry audio from the inputs to the outputs without using the DAC or ADC) then it'll break those - the device will be brought down to standby when there is no playback or record going, which will power the bypass paths down. If that is an issue then documenting it (ideally with printks for users) should cover it for now.
If there aren't any bypass paths then it should be fine to leave it as-is.
On Fri, Sep 5, 2008 at 3:06 AM, Mark Brown broonie@sirena.org.uk wrote:
How about I add a "TODO" on this? I'm swamped for the next few weeks and won't be able to give it the attention it deserves test-wise.
If there aren't any bypass paths then it should be fine to leave it as-is.
There are no bypass paths, so I will leave it as is for now.
I plan to get back to this in a few weeks and will then implement proper BIAS_PREPARE and BIAS_STANDBY support.
Steve
From: Steve Sakoman steve@sakoman.com
SOUND: SOC: CODECS: Add support for the TWL4030 audio codec
This version should take into account all feedback received to date
Signed-off-by: Steve Sakoman steve@sakoman.com --- diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 1db04a2..2f00e1e 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -50,3 +50,8 @@ config SND_SOC_CS4270_VD33_ERRATA config SND_SOC_TLV320AIC3X tristate depends on I2C + +config SND_SOC_TWL4030 + tristate + depends on SND_SOC && I2C + diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index d7b97ab..a519ced 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -10,6 +10,7 @@ snd-soc-wm9712-objs := wm9712.o snd-soc-wm9713-objs := wm9713.o snd-soc-cs4270-objs := cs4270.o snd-soc-tlv320aic3x-objs := tlv320aic3x.o +snd-soc-twl4030-objs := twl4030.o
obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o obj-$(CONFIG_SND_SOC_AK4535) += snd-soc-ak4535.o @@ -23,3 +24,4 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o +obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c new file mode 100644 index 0000000..ee2f0d3 --- /dev/null +++ b/sound/soc/codecs/twl4030.c @@ -0,0 +1,653 @@ +/* + * ALSA SoC TWL4030 codec driver + * + * Author: Steve Sakoman, steve@sakoman.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/i2c/twl4030.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> + +#include "twl4030.h" + +/* + * twl4030 register cache & default register settings + */ +static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { + 0x00, /* this register not used */ + 0x93, /* REG_CODEC_MODE (0x1) */ + 0xc3, /* REG_OPTION (0x2) */ + 0x00, /* REG_UNKNOWN (0x3) */ + 0x00, /* REG_MICBIAS_CTL (0x4) */ + 0x24, /* REG_ANAMICL (0x5) */ + 0x04, /* REG_ANAMICR (0x6) */ + 0x0a, /* REG_AVADC_CTL (0x7) */ + 0x00, /* REG_ADCMICSEL (0x8) */ + 0x00, /* REG_DIGMIXING (0x9) */ + 0x0c, /* REG_ATXL1PGA (0xA) */ + 0x0c, /* REG_ATXR1PGA (0xB) */ + 0x00, /* REG_AVTXL2PGA (0xC) */ + 0x00, /* REG_AVTXR2PGA (0xD) */ + 0x01, /* REG_AUDIO_IF (0xE) */ + 0x00, /* REG_VOICE_IF (0xF) */ + 0x00, /* REG_ARXR1PGA (0x10) */ + 0x00, /* REG_ARXL1PGA (0x11) */ + 0x6c, /* REG_ARXR2PGA (0x12) */ + 0x6c, /* REG_ARXL2PGA (0x13) */ + 0x00, /* REG_VRXPGA (0x14) */ + 0x00, /* REG_VSTPGA (0x15) */ + 0x00, /* REG_VRX2ARXPGA (0x16) */ + 0x0c, /* REG_AVDAC_CTL (0x17) */ + 0x00, /* REG_ARX2VTXPGA (0x18) */ + 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ + 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ + 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */ + 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */ + 0x00, /* REG_ATX2ARXPGA (0x1D) */ + 0x00, /* REG_BT_IF (0x1E) */ + 0x00, /* REG_BTPGA (0x1F) */ + 0x00, /* REG_BTSTPGA (0x20) */ + 0x00, /* REG_EAR_CTL (0x21) */ + 0x24, /* REG_HS_SEL (0x22) */ + 0x0a, /* REG_HS_GAIN_SET (0x23) */ + 0x00, /* REG_HS_POPN_SET (0x24) */ + 0x00, /* REG_PREDL_CTL (0x25) */ + 0x00, /* REG_PREDR_CTL (0x26) */ + 0x00, /* REG_PRECKL_CTL (0x27) */ + 0x00, /* REG_PRECKR_CTL (0x28) */ + 0x00, /* REG_HFL_CTL (0x29) */ + 0x00, /* REG_HFR_CTL (0x2A) */ + 0x00, /* REG_ALC_CTL (0x2B) */ + 0x00, /* REG_ALC_SET1 (0x2C) */ + 0x00, /* REG_ALC_SET2 (0x2D) */ + 0x00, /* REG_BOOST_CTL (0x2E) */ + 0x01, /* REG_SOFTVOL_CTL (0x2F) */ + 0x00, /* REG_DTMF_FREQSEL (0x30) */ + 0x00, /* REG_DTMF_TONEXT1H (0x31) */ + 0x00, /* REG_DTMF_TONEXT1L (0x32) */ + 0x00, /* REG_DTMF_TONEXT2H (0x33) */ + 0x00, /* REG_DTMF_TONEXT2L (0x34) */ + 0x00, /* REG_DTMF_TONOFF (0x35) */ + 0x00, /* REG_DTMF_WANONOFF (0x36) */ + 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ + 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ + 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ + 0x16, /* REG_APLL_CTL (0x3A) */ + 0x00, /* REG_DTMF_CTL (0x3B) */ + 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ + 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ + 0x00, /* REG_MISC_SET_1 (0x3E) */ + 0x00, /* REG_PCMBTMUX (0x3F) */ + 0x00, /* not used (0x40) */ + 0x00, /* not used (0x41) */ + 0x00, /* not used (0x42) */ + 0x00, /* REG_RX_PATH_SEL (0x43) */ + 0x00, /* REG_VDL_APGA_CTL (0x44) */ + 0x00, /* REG_VIBRA_CTL (0x45) */ + 0x00, /* REG_VIBRA_SET (0x46) */ + 0x00, /* REG_VIBRA_PWM_SET (0x47) */ + 0x00, /* REG_ANAMIC_GAIN (0x48) */ + 0x00, /* REG_MISC_SET_2 (0x49) */ +}; + +/* + * read twl4030 register cache + */ +static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 *cache = codec->reg_cache; + + return cache[reg]; +} + +/* + * write twl4030 register cache + */ +static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, + u8 reg, u8 value) +{ + u8 *cache = codec->reg_cache; + + if (reg >= TWL4030_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the twl4030 register space + */ +static int twl4030_write(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + twl4030_write_reg_cache(codec, reg, value); + return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); +} + +static void twl4030_clear_codecpdz(struct snd_soc_codec *codec) +{ + u8 mode; + + mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); + twl4030_write(codec, TWL4030_REG_CODEC_MODE, + mode & ~TWL4030_CODECPDZ); + + /* REVISIT: this delay is present in TI sample drivers */ + /* but there seems to be no TRM requirement for it */ + udelay(10); +} + +static void twl4030_set_codecpdz(struct snd_soc_codec *codec) +{ + u8 mode; + + mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); + twl4030_write(codec, TWL4030_REG_CODEC_MODE, + mode | TWL4030_CODECPDZ); + + /* REVISIT: this delay is present in TI sample drivers */ + /* but there seems to be no TRM requirement for it */ + udelay(10); +} + +static void twl4030_init_chip(struct snd_soc_codec *codec) +{ + int i; + + /* clear CODECPDZ prior to setting register defaults */ + twl4030_clear_codecpdz(codec); + + /* set all audio section registers to reasonable defaults */ + for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) + twl4030_write(codec, i, twl4030_reg[i]); + +} + +static const struct snd_kcontrol_new twl4030_snd_controls[] = { + SOC_DOUBLE_R("Master Playback Volume", + TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, + 0, 127, 0), + SOC_DOUBLE_R("Capture Volume", + TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, + 0, 127, 0), +}; + +/* add non dapm controls */ +static int twl4030_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&twl4030_snd_controls[i], + codec, NULL)); + if (err < 0) + return err; + } + + return 0; +} + +static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("INL"), + SND_SOC_DAPM_INPUT("INR"), + + SND_SOC_DAPM_OUTPUT("OUTL"), + SND_SOC_DAPM_OUTPUT("OUTR"), + + SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0), +}; + +static const struct snd_soc_dapm_route intercon[] = { + /* outputs */ + {"OUTL", NULL, "DACL"}, + {"OUTR", NULL, "DACR"}, + + /* inputs */ + {"ADCL", NULL, "INL"}, + {"ADCR", NULL, "INR"}, +}; + +static int twl4030_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, + ARRAY_SIZE(twl4030_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +static void twl4030_power_up(struct snd_soc_codec *codec) +{ + u8 anamicl, regmisc1, byte, popn, hsgain; + int i = 0; + + /* set CODECPDZ to turn on codec */ + twl4030_set_codecpdz(codec); + + /* initiate offset cancellation */ + anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL); + twl4030_write(codec, TWL4030_REG_ANAMICL, + anamicl | TWL4030_CNCL_OFFSET_START); + + /* wait for offset cancellation to complete */ + do { + /* this takes a little while, so don't slam i2c */ + udelay(2000); + twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, + TWL4030_REG_ANAMICL); + } while ((i++ < 100) && + ((byte & TWL4030_CNCL_OFFSET_START) == + TWL4030_CNCL_OFFSET_START)); + + /* anti-pop when changing analog gain */ + regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); + twl4030_write(codec, TWL4030_REG_MISC_SET_1, + regmisc1 | TWL4030_SMOOTH_ANAVOL_EN); + + /* toggle CODECPDZ as per TRM */ + twl4030_clear_codecpdz(codec); + twl4030_set_codecpdz(codec); + + /* program anti-pop with bias ramp delay */ + popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); + popn &= TWL4030_RAMP_DELAY; + popn |= TWL4030_RAMP_DELAY_645MS; + twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); + popn |= TWL4030_VMID_EN; + twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); + + /* enable output stage and gain setting */ + hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB; + twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain); + + /* enable anti-pop ramp */ + popn |= TWL4030_RAMP_EN; + twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); +} + +static void twl4030_power_down(struct snd_soc_codec *codec) +{ + u8 popn, hsgain; + + /* disable anti-pop ramp */ + popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); + popn &= ~TWL4030_RAMP_EN; + twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); + + /* disable output stage and gain setting */ + hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN; + twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain); + + /* disable bias out */ + popn &= ~TWL4030_VMID_EN; + twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn); + + /* power down */ + twl4030_clear_codecpdz(codec); +} + +static int twl4030_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_ON: + twl4030_power_up(codec); + break; + case SND_SOC_BIAS_PREPARE: + /* TODO: develop a twl4030_prepare function */ + break; + case SND_SOC_BIAS_STANDBY: + /* TODO: develop a twl4030_standby function */ + twl4030_power_down(codec); + break; + case SND_SOC_BIAS_OFF: + twl4030_power_down(codec); + break; + } + codec->bias_level = level; + + return 0; +} + +static int twl4030_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + u8 mode, old_mode, format, old_format; + + + /* bit rate */ + old_mode = twl4030_read_reg_cache(codec, + TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; + mode = old_mode & ~TWL4030_APLL_RATE; + + switch (params_rate(params)) { + case 8000: + mode |= TWL4030_APLL_RATE_8000; + break; + case 11025: + mode |= TWL4030_APLL_RATE_11025; + break; + case 12000: + mode |= TWL4030_APLL_RATE_12000; + break; + case 16000: + mode |= TWL4030_APLL_RATE_16000; + break; + case 22050: + mode |= TWL4030_APLL_RATE_22050; + break; + case 24000: + mode |= TWL4030_APLL_RATE_24000; + break; + case 32000: + mode |= TWL4030_APLL_RATE_32000; + break; + case 44100: + mode |= TWL4030_APLL_RATE_44100; + break; + case 48000: + mode |= TWL4030_APLL_RATE_48000; + break; + default: + printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", + params_rate(params)); + return -EINVAL; + } + + if (mode != old_mode) { + /* change rate and set CODECPDZ */ + twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); + twl4030_set_codecpdz(codec); + } + + /* sample size */ + old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); + format = old_format; + format &= ~TWL4030_DATA_WIDTH; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + format |= TWL4030_DATA_WIDTH_16S_16W; + break; + case SNDRV_PCM_FORMAT_S24_LE: + format |= TWL4030_DATA_WIDTH_32S_24W; + break; + default: + printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", + params_format(params)); + return -EINVAL; + } + + if (format != old_format) { + + /* clear CODECPDZ before changing format (codec requirement) */ + twl4030_clear_codecpdz(codec); + + /* change format */ + twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); + + /* set CODECPDZ afterwards */ + twl4030_set_codecpdz(codec); + } + return 0; +} + +static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 infreq; + + switch (freq) { + case 19200000: + infreq = TWL4030_APLL_INFREQ_19200KHZ; + break; + case 26000000: + infreq = TWL4030_APLL_INFREQ_26000KHZ; + break; + case 38400000: + infreq = TWL4030_APLL_INFREQ_38400KHZ; + break; + default: + printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n", + freq); + return -EINVAL; + } + + infreq |= TWL4030_APLL_EN; + twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq); + + return 0; +} + +static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 old_format, format; + + /* get format */ + old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); + format = old_format; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + format &= ~(TWL4030_AIF_SLAVE_EN); + format |= TWL4030_CLK256FS_EN; + break; + case SND_SOC_DAIFMT_CBS_CFS: + format &= ~(TWL4030_CLK256FS_EN); + format |= TWL4030_AIF_SLAVE_EN; + break; + default: + return -EINVAL; + } + + /* interface format */ + format &= ~TWL4030_AIF_FORMAT; + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + format |= TWL4030_AIF_FORMAT_CODEC; + break; + default: + return -EINVAL; + } + + if (format != old_format) { + + /* clear CODECPDZ before changing format (codec requirement) */ + twl4030_clear_codecpdz(codec); + + /* change format */ + twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); + + /* set CODECPDZ afterwards */ + twl4030_set_codecpdz(codec); + } + + return 0; +} + +#define TWL4030_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) +#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) + +struct snd_soc_dai twl4030_dai = { + .name = "twl4030", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = TWL4030_RATES, + .formats = TWL4030_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 2, + .rates = TWL4030_RATES, + .formats = TWL4030_FORMATS,}, + .ops = { + .hw_params = twl4030_hw_params, + }, + .dai_ops = { + .set_sysclk = twl4030_set_dai_sysclk, + .set_fmt = twl4030_set_dai_fmt, + } +}; +EXPORT_SYMBOL_GPL(twl4030_dai); + +static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); + + return 0; +} + +static int twl4030_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + twl4030_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialize the driver + * register the mixer and dsp interfaces with the kernel + */ + +static int twl4030_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int ret = 0; + + printk(KERN_INFO "TWL4030 Audio Codec init \n"); + + codec->name = "twl4030"; + codec->owner = THIS_MODULE; + codec->read = twl4030_read_reg_cache; + codec->write = twl4030_write; + codec->set_bias_level = twl4030_set_bias_level; + codec->dai = &twl4030_dai; + codec->num_dai = 1; + codec->reg_cache_size = sizeof(twl4030_reg); + codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), + GFP_KERNEL); + if (codec->reg_cache == NULL) + return -ENOMEM; + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + printk(KERN_ERR "twl4030: failed to create pcms\n"); + goto pcm_err; + } + + twl4030_init_chip(codec); + + /* power on device */ + twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + twl4030_add_controls(codec); + twl4030_add_widgets(codec); + + ret = snd_soc_register_card(socdev); + if (ret < 0) { + printk(KERN_ERR "twl4030: failed to register card\n"); + goto card_err; + } + + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *twl4030_socdev; + +static int twl4030_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec; + + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + twl4030_socdev = socdev; + twl4030_init(socdev); + + return 0; +} + +static int twl4030_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + printk(KERN_INFO "TWL4030 Audio Codec remove\n"); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_twl4030 = { + .probe = twl4030_probe, + .remove = twl4030_remove, + .suspend = twl4030_suspend, + .resume = twl4030_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); + +MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); +MODULE_AUTHOR("Steve Sakoman"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h new file mode 100644 index 0000000..09865d9 --- /dev/null +++ b/sound/soc/codecs/twl4030.h @@ -0,0 +1,197 @@ +/* + * ALSA SoC TWL4030 codec driver + * + * Author: Steve Sakoman steve@sakoman.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __TWL4030_AUDIO_H__ +#define __TWL4030_AUDIO_H__ + +#define TWL4030_REG_CODEC_MODE 0x1 +#define TWL4030_REG_OPTION 0x2 +#define TWL4030_REG_UNKNOWN 0x3 +#define TWL4030_REG_MICBIAS_CTL 0x4 +#define TWL4030_REG_ANAMICL 0x5 +#define TWL4030_REG_ANAMICR 0x6 +#define TWL4030_REG_AVADC_CTL 0x7 +#define TWL4030_REG_ADCMICSEL 0x8 +#define TWL4030_REG_DIGMIXING 0x9 +#define TWL4030_REG_ATXL1PGA 0xA +#define TWL4030_REG_ATXR1PGA 0xB +#define TWL4030_REG_AVTXL2PGA 0xC +#define TWL4030_REG_AVTXR2PGA 0xD +#define TWL4030_REG_AUDIO_IF 0xE +#define TWL4030_REG_VOICE_IF 0xF +#define TWL4030_REG_ARXR1PGA 0x10 +#define TWL4030_REG_ARXL1PGA 0x11 +#define TWL4030_REG_ARXR2PGA 0x12 +#define TWL4030_REG_ARXL2PGA 0x13 +#define TWL4030_REG_VRXPGA 0x14 +#define TWL4030_REG_VSTPGA 0x15 +#define TWL4030_REG_VRX2ARXPGA 0x16 +#define TWL4030_REG_AVDAC_CTL 0x17 +#define TWL4030_REG_ARX2VTXPGA 0x18 +#define TWL4030_REG_ARXL1_APGA_CTL 0x19 +#define TWL4030_REG_ARXR1_APGA_CTL 0x1A +#define TWL4030_REG_ARXL2_APGA_CTL 0x1B +#define TWL4030_REG_ARXR2_APGA_CTL 0x1C +#define TWL4030_REG_ATX2ARXPGA 0x1D +#define TWL4030_REG_BT_IF 0x1E +#define TWL4030_REG_BTPGA 0x1F +#define TWL4030_REG_BTSTPGA 0x20 +#define TWL4030_REG_EAR_CTL 0x21 +#define TWL4030_REG_HS_SEL 0x22 +#define TWL4030_REG_HS_GAIN_SET 0x23 +#define TWL4030_REG_HS_POPN_SET 0x24 +#define TWL4030_REG_PREDL_CTL 0x25 +#define TWL4030_REG_PREDR_CTL 0x26 +#define TWL4030_REG_PRECKL_CTL 0x27 +#define TWL4030_REG_PRECKR_CTL 0x28 +#define TWL4030_REG_HFL_CTL 0x29 +#define TWL4030_REG_HFR_CTL 0x2A +#define TWL4030_REG_ALC_CTL 0x2B +#define TWL4030_REG_ALC_SET1 0x2C +#define TWL4030_REG_ALC_SET2 0x2D +#define TWL4030_REG_BOOST_CTL 0x2E +#define TWL4030_REG_SOFTVOL_CTL 0x2F +#define TWL4030_REG_DTMF_FREQSEL 0x30 +#define TWL4030_REG_DTMF_TONEXT1H 0x31 +#define TWL4030_REG_DTMF_TONEXT1L 0x32 +#define TWL4030_REG_DTMF_TONEXT2H 0x33 +#define TWL4030_REG_DTMF_TONEXT2L 0x34 +#define TWL4030_REG_DTMF_TONOFF 0x35 +#define TWL4030_REG_DTMF_WANONOFF 0x36 +#define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37 +#define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38 +#define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39 +#define TWL4030_REG_APLL_CTL 0x3A +#define TWL4030_REG_DTMF_CTL 0x3B +#define TWL4030_REG_DTMF_PGA_CTL2 0x3C +#define TWL4030_REG_DTMF_PGA_CTL1 0x3D +#define TWL4030_REG_MISC_SET_1 0x3E +#define TWL4030_REG_PCMBTMUX 0x3F +#define TWL4030_REG_RX_PATH_SEL 0x43 +#define TWL4030_REG_VDL_APGA_CTL 0x44 +#define TWL4030_REG_VIBRA_CTL 0x45 +#define TWL4030_REG_VIBRA_SET 0x46 +#define TWL4030_REG_VIBRA_PWM_SET 0x47 +#define TWL4030_REG_ANAMIC_GAIN 0x48 +#define TWL4030_REG_MISC_SET_2 0x49 + +#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1) + +/* Bitfield Definitions */ + +/* TWL4030_CODEC_MODE (0x01) Fields */ + +#define TWL4030_APLL_RATE 0xF0 +#define TWL4030_APLL_RATE_8000 0x00 +#define TWL4030_APLL_RATE_11025 0x10 +#define TWL4030_APLL_RATE_12000 0x20 +#define TWL4030_APLL_RATE_16000 0x40 +#define TWL4030_APLL_RATE_22050 0x50 +#define TWL4030_APLL_RATE_24000 0x60 +#define TWL4030_APLL_RATE_32000 0x80 +#define TWL4030_APLL_RATE_44100 0x90 +#define TWL4030_APLL_RATE_48000 0xA0 +#define TWL4030_SEL_16K 0x04 +#define TWL4030_CODECPDZ 0x02 +#define TWL4030_OPT_MODE 0x01 + +/* ANAMICL (0x05) Fields */ +#define TWL4030_CNCL_OFFSET_START 0x80 +#define TWL4030_OFFSET_CNCL_SEL 0x60 +#define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00 +#define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20 +#define TWL4030_OFFSET_CNCL_SEL_VRX 0x40 +#define TWL4030_OFFSET_CNCL_SEL_ALL 0x60 +#define TWL4030_MICAMPL_EN 0x10 +#define TWL4030_CKMIC_EN 0x08 +#define TWL4030_AUXL_EN 0x04 +#define TWL4030_HSMIC_EN 0x02 +#define TWL4030_MAINMIC_EN 0x01 + +/* ANAMICR (0x06) Fields */ +#define TWL4030_MICAMPR_EN 0x10 +#define TWL4030_AUXR_EN 0x04 +#define TWL4030_SUBMIC_EN 0x01 + +/* AUDIO_IF (0x0E) Fields */ + +#define TWL4030_AIF_SLAVE_EN 0x80 +#define TWL4030_DATA_WIDTH 0x60 +#define TWL4030_DATA_WIDTH_16S_16W 0x00 +#define TWL4030_DATA_WIDTH_32S_16W 0x40 +#define TWL4030_DATA_WIDTH_32S_24W 0x60 +#define TWL4030_AIF_FORMAT 0x18 +#define TWL4030_AIF_FORMAT_CODEC 0x00 +#define TWL4030_AIF_FORMAT_LEFT 0x08 +#define TWL4030_AIF_FORMAT_RIGHT 0x10 +#define TWL4030_AIF_FORMAT_TDM 0x18 +#define TWL4030_AIF_TRI_EN 0x04 +#define TWL4030_CLK256FS_EN 0x02 +#define TWL4030_AIF_EN 0x01 + +/* HS_GAIN_SET (0x23) Fields */ + +#define TWL4030_HSR_GAIN 0x0C +#define TWL4030_HSR_GAIN_PWR_DOWN 0x00 +#define TWL4030_HSR_GAIN_PLUS_6DB 0x04 +#define TWL4030_HSR_GAIN_0DB 0x08 +#define TWL4030_HSR_GAIN_MINUS_6DB 0x0C +#define TWL4030_HSL_GAIN 0x03 +#define TWL4030_HSL_GAIN_PWR_DOWN 0x00 +#define TWL4030_HSL_GAIN_PLUS_6DB 0x01 +#define TWL4030_HSL_GAIN_0DB 0x02 +#define TWL4030_HSL_GAIN_MINUS_6DB 0x03 + +/* HS_POPN_SET (0x24) Fields */ + +#define TWL4030_VMID_EN 0x40 +#define TWL4030_EXTMUTE 0x20 +#define TWL4030_RAMP_DELAY 0x1C +#define TWL4030_RAMP_DELAY_20MS 0x00 +#define TWL4030_RAMP_DELAY_40MS 0x04 +#define TWL4030_RAMP_DELAY_81MS 0x08 +#define TWL4030_RAMP_DELAY_161MS 0x0C +#define TWL4030_RAMP_DELAY_323MS 0x10 +#define TWL4030_RAMP_DELAY_645MS 0x14 +#define TWL4030_RAMP_DELAY_1291MS 0x18 +#define TWL4030_RAMP_DELAY_2581MS 0x1C +#define TWL4030_RAMP_EN 0x02 + +/* APLL_CTL (0x3A) Fields */ + +#define TWL4030_APLL_EN 0x10 +#define TWL4030_APLL_INFREQ 0x0F +#define TWL4030_APLL_INFREQ_19200KHZ 0x05 +#define TWL4030_APLL_INFREQ_26000KHZ 0x06 +#define TWL4030_APLL_INFREQ_38400KHZ 0x0F + +/* REG_MISC_SET_1 (0x3E) Fields */ + +#define TWL4030_CLK64_EN 0x80 +#define TWL4030_SCRAMBLE_EN 0x40 +#define TWL4030_FMLOOP_EN 0x20 +#define TWL4030_SMOOTH_ANAVOL_EN 0x02 +#define TWL4030_DIGMIC_LR_SWAP_EN 0x01 + +extern struct snd_soc_dai twl4030_dai; +extern struct snd_soc_codec_device soc_codec_dev_twl4030; + +#endif /* End of __TWL4030_AUDIO_H__ */
On Fri, Sep 05, 2008 at 07:34:00AM -0700, Steve Sakoman wrote:
From: Steve Sakoman steve@sakoman.com
Looks good.
Acked-by: Mark Brown broonie@opensource.wolfsonmicro.com
SOUND: SOC: CODECS: Add support for the TWL4030 audio codec
Usually it'd be formatted as
ALSA: ASoC: Add support for TWL4030 audio codec
but that's not too important.
On Fri, Sep 5, 2008 at 7:48 AM, Mark Brown broonie@sirena.org.uk wrote:
Looks good.
Acked-by: Mark Brown broonie@opensource.wolfsonmicro.com
SOUND: SOC: CODECS: Add support for the TWL4030 audio codec
Usually it'd be formatted as
ALSA: ASoC: Add support for TWL4030 audio codec
Thanks Mark!
I'll change the title on my final resubmission of the series
Steve
participants (5)
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dinesh -
Jarkko Nikula -
Mark Brown -
sakoman＠gmail.com -
Steve Sakoman