[alsa-devel] [PATCH 0/6] add support for Sama5d2 audio PLL and enable ClassD
This patch series adds support for the audio PLL and enables ClassD that can be found in ATMEL Sama5d2 SoCs.
There are two audio PLLs (PMC and PAD) that shares the same parent (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of its parent. The two audio PLLs then divide the FRAC rate to best match the asked rate.
I basically took an old patch series posted by Nicolas on December, 6th 2016[1][2][3] and the comments Boris did on the first version[4] Nicolas sent on July, 15th 2015.
I also fixed the function used to compute the divisors, removed useless spinlocks and added a range to the audio frac PLL to stay within vendor's supported range. Clocks that are children of gclk (generated-clk) are now able to propagate rate to the audio PLL clocks when needed. However, since there is no rate locking, we enforce that classd_gclk be the only child of audio_pll_pmc so we avoid multiple children modifiying parent's rate, and classd driver modifying parent's rate which would impact the rate of each of parent's children.
Thanks, Quentin
[1] https://patchwork.kernel.org/patch/9462351/ [2] https://patchwork.kernel.org/patch/9462347/ [3] https://patchwork.kernel.org/patch/9462349/ [4] https://www.spinics.net/lists/arm-kernel/msg436120.html
Cyrille Pitchen (2): ARM: dts: at91: sama5d2: add classd nodes ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd
Nicolas Ferre (1): clk: at91: add audio pll clock driver
Quentin Schulz (3): clk: at91: clk-generated: remove useless divisor loop clk: at91: clk-generated: create function to find best_diff clk: at91: clk-generated: make gclk determine audio_pll rate
.../devicetree/bindings/clock/at91-clock.txt | 10 + arch/arm/boot/dts/at91-sama5d2_xplained.dts | 16 ++ arch/arm/boot/dts/sama5d2.dtsi | 39 +++- arch/arm/mach-at91/Kconfig | 4 + drivers/clk/at91/Makefile | 2 + drivers/clk/at91/clk-audio-pll-pad.c | 204 ++++++++++++++++++ drivers/clk/at91/clk-audio-pll-pmc.c | 175 +++++++++++++++ drivers/clk/at91/clk-audio-pll.c | 237 +++++++++++++++++++++ drivers/clk/at91/clk-generated.c | 79 +++++-- include/linux/clk/at91_pmc.h | 25 +++ sound/soc/atmel/atmel-classd.c | 20 +- 11 files changed, 772 insertions(+), 39 deletions(-) create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c create mode 100644 drivers/clk/at91/clk-audio-pll.c
The driver requests the current clk rate of each of its parent clocks to decide whether a clock rate is suitable or not. It does not request determine_rate from a parent clock which could request a rate change in parent clock (i.e. there is no parent rate propagation).
We know the rate we want (passed along req argument of the function) and the parent clock rate, thus we know the closest rounded divisor, we don't need to iterate over the available divisors to find the best one for a given clock.
Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com --- drivers/clk/at91/clk-generated.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 07c8f701e51c..dab7002937e6 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -124,19 +124,18 @@ static int clk_generated_determine_rate(struct clk_hw *hw, (gck->range.max && min_rate > gck->range.max)) continue;
- for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { - tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div); - tmp_diff = abs(req->rate - tmp_rate); - - if (best_diff < 0 || best_diff > tmp_diff) { - best_rate = tmp_rate; - best_diff = tmp_diff; - req->best_parent_rate = parent_rate; - req->best_parent_hw = parent; - } - - if (!best_diff || tmp_rate < req->rate) - break; + div = DIV_ROUND_CLOSEST(parent_rate, req->rate); + if (!div) + tmp_rate = parent_rate; + else + tmp_rate = parent_rate / div; + tmp_diff = abs(req->rate - tmp_rate); + + if (best_diff < 0 || best_diff > tmp_diff) { + best_rate = tmp_rate; + best_diff = tmp_diff; + req->best_parent_rate = parent_rate; + req->best_parent_hw = parent; }
if (!best_diff)
On Fri, 23 Jun 2017 11:00:54 +0200 Quentin Schulz quentin.schulz@free-electrons.com wrote:
The driver requests the current clk rate of each of its parent clocks to decide whether a clock rate is suitable or not. It does not request determine_rate from a parent clock which could request a rate change in parent clock (i.e. there is no parent rate propagation).
We know the rate we want (passed along req argument of the function) and the parent clock rate, thus we know the closest rounded divisor, we don't need to iterate over the available divisors to find the best one for a given clock.
Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com
Acked-by: Boris Brezillon boris.brezillon@free-electrons.com
drivers/clk/at91/clk-generated.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 07c8f701e51c..dab7002937e6 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -124,19 +124,18 @@ static int clk_generated_determine_rate(struct clk_hw *hw, (gck->range.max && min_rate > gck->range.max)) continue;
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);tmp_diff = abs(req->rate - tmp_rate);if (best_diff < 0 || best_diff > tmp_diff) {best_rate = tmp_rate;best_diff = tmp_diff;req->best_parent_rate = parent_rate;req->best_parent_hw = parent;}if (!best_diff || tmp_rate < req->rate)break;
div = DIV_ROUND_CLOSEST(parent_rate, req->rate);if (!div)tmp_rate = parent_rate;elsetmp_rate = parent_rate / div;tmp_diff = abs(req->rate - tmp_rate);if (best_diff < 0 || best_diff > tmp_diff) {best_rate = tmp_rate;best_diff = tmp_diff;req->best_parent_rate = parent_rate;req->best_parent_hw = parent;}
if (!best_diff)
From: Nicolas Ferre nicolas.ferre@atmel.com
This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications.
The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formula, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre nicolas.ferre@atmel.com Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com --- .../devicetree/bindings/clock/at91-clock.txt | 10 + arch/arm/mach-at91/Kconfig | 4 + drivers/clk/at91/Makefile | 2 + drivers/clk/at91/clk-audio-pll-pad.c | 204 ++++++++++++++++++ drivers/clk/at91/clk-audio-pll-pmc.c | 175 +++++++++++++++ drivers/clk/at91/clk-audio-pll.c | 237 +++++++++++++++++++++ include/linux/clk/at91_pmc.h | 25 +++ sound/soc/atmel/atmel-classd.c | 20 +- 8 files changed, 658 insertions(+), 19 deletions(-) create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c create mode 100644 drivers/clk/at91/clk-audio-pll.c
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt index 5f3ad65daf69..51c259a92d02 100644 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt @@ -81,6 +81,16 @@ Required properties: "atmel,sama5d2-clk-generated": at91 generated clock
+ "atmel,sama5d2-clk-audio-pll-frac": + at91 audio fractional pll + + "atmel,sama5d2-clk-audio-pll-pad": + at91 audio pll CLK_AUDIO output pin + + "atmel,sama5d2-clk-audio-pll-pmc" + at91 audio pll output on AUDIOPLLCLK that feeds the PMC + and can be used by peripheral clock or generic clock + Required properties for SCKC node: - reg : defines the IO memory reserved for the SCKC. - #size-cells : shall be 0 (reg is used to encode clk id). diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index d735e5fc4772..9ae14d59a9ce 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -26,6 +26,7 @@ config SOC_SAMA5D2 select HAVE_AT91_USB_CLK select HAVE_AT91_H32MX select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_AUDIO_PLL select PINCTRL_AT91PIO4 help Select this if ou are using one of Atmel's SAMA5D2 family SoC. @@ -125,6 +126,9 @@ config HAVE_AT91_H32MX config HAVE_AT91_GENERATED_CLK bool
+config HAVE_AT91_AUDIO_PLL + bool + config SOC_SAM_V4_V5 bool
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 13e67bd35cff..c9353d17763a 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -6,6 +6,8 @@ obj-y += pmc.o sckc.o obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o obj-y += clk-system.o clk-peripheral.o clk-programmable.o
+obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll.o +obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll-pmc.o clk-audio-pll-pad.o obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o diff --git a/drivers/clk/at91/clk-audio-pll-pad.c b/drivers/clk/at91/clk-audio-pll-pad.c new file mode 100644 index 000000000000..a60ce47b82c6 --- /dev/null +++ b/drivers/clk/at91/clk-audio-pll-pad.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2016 Atmel Corporation, + * Nicolas Ferre nicolas.ferre@atmel.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/clk/at91_pmc.h> +#include <linux/of.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> + +#include "pmc.h" + +/* + * DOC: PAD output for fractional PLL clock for audio + * + * Traits of this clock: + * enable - clk_enable writes divisors and enables PAD output + * rate - rate is adjustable. + * clk->rate = parent->rate / (qdaudio * div)) + * parent - fixed parent. No clk_set_parent support + */ + +#define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \ + AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \ + (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \ + AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK)) + +struct clk_audio_pad { + struct clk_hw hw; + struct regmap *regmap; + u8 qdaudio; + u8 div; +}; + +#define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw) + +static int clk_audio_pll_pad_enable(struct clk_hw *hw) +{ + struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); + + regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1, + AT91_PMC_AUDIO_PLL_QDPAD_MASK, + AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div)); + regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN); + + return 0; +} + +static void clk_audio_pll_pad_disable(struct clk_hw *hw) +{ + struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); + + regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PADEN, 0); +} + +static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); + unsigned long apad_rate = 0; + + if (apad_ck->qdaudio && apad_ck->div) + apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div); + + pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n", + __func__, apad_rate, apad_ck->div, apad_ck->qdaudio); + + return apad_rate; +} + +static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_hw *pclk = clk_hw_get_parent(hw); + long best_rate = -EINVAL; + unsigned long best_parent_rate; + unsigned long tmp_qd; + u32 div; + long tmp_rate; + int tmp_diff; + int best_diff = -1; + + pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__, + rate, *parent_rate); + + /* + * Rate divisor is actually made of two different divisors, multiplied + * between themselves before dividing the rate. + * tmp_qd goes from 1 to 31 and div is either 2 or 3. + * In order to avoid testing twice the rate divisor (e.g. divisor 12 can + * be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop + * for a rate divisor when div is 2 and tmp_qd is a multiple of 3. + * We cannot inverse it (condition div is 3 and tmp_qd is even) or we + * would miss some rate divisor that aren't reachable with div being 2 + * (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus + * tmp_qd is even so we skip it because we think div 2 could make this + * rate divisor which isn't possible since tmp_qd has to be <= 31). + */ + for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++) + for (div = 2; div <= 3; div++) { + if (div == 2 && tmp_qd % 3 == 0) + continue; + + best_parent_rate = clk_hw_round_rate(pclk, + rate * tmp_qd * div); + tmp_rate = best_parent_rate / (div * tmp_qd); + tmp_diff = abs(rate - tmp_rate); + + if (best_diff < 0 || best_diff > tmp_diff) { + *parent_rate = best_parent_rate; + best_rate = tmp_rate; + best_diff = tmp_diff; + } + } + + pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n", + __func__, best_rate, best_parent_rate); + + return best_rate; +} + +static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); + u8 tmp_div; + + pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__, + rate, parent_rate); + + if (!rate) + return -EINVAL; + + tmp_div = parent_rate / rate; + if (tmp_div % 3 == 0) { + apad_ck->qdaudio = tmp_div / 3; + apad_ck->div = 3; + } else { + apad_ck->qdaudio = tmp_div / 2; + apad_ck->div = 2; + } + + return 0; +} + +static const struct clk_ops audio_pll_pad_ops = { + .enable = clk_audio_pll_pad_enable, + .disable = clk_audio_pll_pad_disable, + .recalc_rate = clk_audio_pll_pad_recalc_rate, + .round_rate = clk_audio_pll_pad_round_rate, + .set_rate = clk_audio_pll_pad_set_rate, +}; + +static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np) +{ + struct clk_audio_pad *apad_ck; + struct clk_init_data init; + struct regmap *regmap; + const char *parent_name; + const char *name = np->name; + int ret; + + parent_name = of_clk_get_parent_name(np, 0); + + of_property_read_string(np, "clock-output-names", &name); + + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + + apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL); + if (!apad_ck) + return; + + init.name = name; + init.ops = &audio_pll_pad_ops; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = 1; + init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT; + + apad_ck->hw.init = &init; + apad_ck->regmap = regmap; + + ret = clk_hw_register(NULL, &apad_ck->hw); + if (ret) + kfree(apad_ck); + else + of_clk_add_hw_provider(np, of_clk_hw_simple_get, &apad_ck->hw); +} + +CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup, + "atmel,sama5d2-clk-audio-pll-pad", + of_sama5d2_clk_audio_pll_pad_setup); diff --git a/drivers/clk/at91/clk-audio-pll-pmc.c b/drivers/clk/at91/clk-audio-pll-pmc.c new file mode 100644 index 000000000000..208d0b59eb4e --- /dev/null +++ b/drivers/clk/at91/clk-audio-pll-pmc.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2016 Atmel Corporation, + * Nicolas Ferre nicolas.ferre@atmel.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/clk/at91_pmc.h> +#include <linux/of.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> + +#include "pmc.h" + +/* + * DOC: PMC output for fractional PLL clock for audio + * + * Traits of this clock: + * enable - clk_enable writes qdpmc, and enables PMC output + * rate - rate is adjustable. + * clk->rate = parent->rate / (qdpmc + 1) + * parent - fixed parent. No clk_set_parent support + */ + +#define AUDIO_PLL_FOUT_MIN 620000000 +#define AUDIO_PLL_FOUT_MAX 700000000 +#define AUDIO_PLL_REFERENCE_FOUT 660000000 +#define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \ + AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) +struct clk_audio_pmc { + struct clk_hw hw; + struct regmap *regmap; + u8 qdpmc; +}; + +#define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw) + +static int clk_audio_pll_pmc_enable(struct clk_hw *hw) +{ + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); + + regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PMCEN | + AT91_PMC_AUDIO_PLL_QDPMC_MASK, + AT91_PMC_AUDIO_PLL_PMCEN | + AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc)); + return 0; +} + +static void clk_audio_pll_pmc_disable(struct clk_hw *hw) +{ + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); + + regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PMCEN, 0); +} + +static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); + unsigned long apmc_rate = 0; + + apmc_rate = parent_rate / (apmc_ck->qdpmc + 1); + + pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__, + apmc_rate, apmc_ck->qdpmc); + + return apmc_rate; +} + +static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_hw *pclk = clk_hw_get_parent(hw); + long best_rate = -EINVAL; + unsigned long best_parent_rate = 0; + u32 tmp_qd = 0, div; + long tmp_rate; + int tmp_diff; + int best_diff = -1; + + pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__, + rate, *parent_rate); + + for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) { + best_parent_rate = clk_round_rate(pclk->clk, rate * div); + tmp_rate = best_parent_rate / div; + tmp_diff = abs(rate - tmp_rate); + + if (best_diff < 0 || best_diff > tmp_diff) { + *parent_rate = best_parent_rate; + best_rate = tmp_rate; + best_diff = tmp_diff; + tmp_qd = div; + } + } + + pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n", + __func__, best_rate, *parent_rate, tmp_qd - 1); + + return best_rate; +} + +static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); + + if (!rate) + return -EINVAL; + + pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__, + rate, parent_rate); + + apmc_ck->qdpmc = parent_rate / rate - 1; + + return 0; +} + +static const struct clk_ops audio_pll_pmc_ops = { + .enable = clk_audio_pll_pmc_enable, + .disable = clk_audio_pll_pmc_disable, + .recalc_rate = clk_audio_pll_pmc_recalc_rate, + .round_rate = clk_audio_pll_pmc_round_rate, + .set_rate = clk_audio_pll_pmc_set_rate, +}; + +static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np) +{ + struct clk_audio_pmc *apmc_ck; + struct clk_init_data init; + struct regmap *regmap; + const char *parent_name; + const char *name = np->name; + int ret; + + parent_name = of_clk_get_parent_name(np, 0); + + of_property_read_string(np, "clock-output-names", &name); + + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + + apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL); + if (!apmc_ck) + return; + + init.name = name; + init.ops = &audio_pll_pmc_ops; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = 1; + init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT; + + apmc_ck->hw.init = &init; + apmc_ck->regmap = regmap; + + ret = clk_hw_register(NULL, &apmc_ck->hw); + if (ret) + kfree(apmc_ck); + else + of_clk_add_hw_provider(np, of_clk_hw_simple_get, &apmc_ck->hw); +} + +CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup, + "atmel,sama5d2-clk-audio-pll-pmc", + of_sama5d2_clk_audio_pll_pmc_setup); diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c new file mode 100644 index 000000000000..ad8c8827681e --- /dev/null +++ b/drivers/clk/at91/clk-audio-pll.c @@ -0,0 +1,237 @@ +/* + * Copyright (C) 2016 Atmel Corporation, + * Songjun Wu songjun.wu@atmel.com, + * Nicolas Ferre nicolas.ferre@atmel.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/clk/at91_pmc.h> +#include <linux/of.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> + +#include "pmc.h" + +/* + * DOC: Fractional PLL clock for audio + * + * Traits of this clock: + * prepare - clk_prepare puts audio PLL in reset state + * enable - clk_enable writes nd, fracr parameters and enables PLL + * rate - rate is adjustable. + * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22)) + * parent - fixed parent. No clk_set_parent support + */ + +#define AUDIO_PLL_DIV_FRAC BIT(22) +#define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \ + AT91_PMC_AUDIO_PLL_ND_OFFSET) + +#define AUDIO_PLL_FOUT_MIN 620000000 +#define AUDIO_PLL_FOUT_MAX 700000000 + +struct clk_audio_frac { + struct clk_hw hw; + struct regmap *regmap; + u32 fracr; + u8 nd; +}; + +#define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw) + +static int clk_audio_pll_enable(struct clk_hw *hw) +{ + struct clk_audio_frac *fck = to_clk_audio_frac(hw); + + regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_RESETN, 0); + regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_RESETN, + AT91_PMC_AUDIO_PLL_RESETN); + regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL1, + AT91_PMC_AUDIO_PLL_FRACR_MASK, fck->fracr); + + /* + * reset and enable have to be done in 2 separated writes + * for AT91_PMC_AUDIO_PLL0 + */ + regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PLLEN | + AT91_PMC_AUDIO_PLL_ND_MASK, + AT91_PMC_AUDIO_PLL_PLLEN | + AT91_PMC_AUDIO_PLL_ND(fck->nd)); + + return 0; +} + +static void clk_audio_pll_disable(struct clk_hw *hw) +{ + struct clk_audio_frac *fck = to_clk_audio_frac(hw); + + regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_PLLEN, 0); + /* do it in 2 separated writes */ + regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0, + AT91_PMC_AUDIO_PLL_RESETN, 0); +} + +static unsigned long clk_audio_pll_fout(unsigned long parent_rate, + unsigned long nd, unsigned long fracr) +{ + unsigned long long fr = (unsigned long long)parent_rate * + (unsigned long long)fracr; + + pr_debug("A PLL: %s, fr = %llu\n", __func__, fr); + + fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC); + + pr_debug("A PLL: %s, fr = %llu\n", __func__, fr); + + return parent_rate * (nd + 1) + fr; +} + +static unsigned long clk_audio_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_audio_frac *fck = to_clk_audio_frac(hw); + unsigned long fout; + + fout = clk_audio_pll_fout(parent_rate, fck->nd, fck->fracr); + + pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__, + fout, fck->nd, (unsigned long)fck->fracr); + + return fout; +} + +static int clk_audio_pll_compute_frac(unsigned long rate, + unsigned long parent_rate, + unsigned long *nd, unsigned long *fracr) +{ + unsigned long long tmp, rem; + + if (!rate) + return -EINVAL; + + tmp = rate; + rem = do_div(tmp, parent_rate); + if (!tmp || tmp >= AUDIO_PLL_ND_MAX) + return -EINVAL; + + *nd = tmp - 1; + + tmp = rem * AUDIO_PLL_DIV_FRAC; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate); + if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK) + return -EINVAL; + + /* we can cast here as we verified the bounds just above */ + *fracr = (unsigned long)tmp; + + return 0; +} + +static long clk_audio_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + long best_rate = -EINVAL; + unsigned long fracr, nd; + int ret; + + pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, + *parent_rate); + + if (rate < AUDIO_PLL_FOUT_MIN) + rate = AUDIO_PLL_FOUT_MIN; + else if (rate > AUDIO_PLL_FOUT_MAX) + rate = AUDIO_PLL_FOUT_MAX; + + ret = clk_audio_pll_compute_frac(rate, *parent_rate, &nd, &fracr); + if (ret) + return ret; + + best_rate = clk_audio_pll_fout(*parent_rate, nd, fracr); + + pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n", + __func__, best_rate, nd, fracr); + + return best_rate; +} + +static int clk_audio_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_audio_frac *fck = to_clk_audio_frac(hw); + unsigned long fracr, nd; + int ret; + + pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, + parent_rate); + + if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX) + return -EINVAL; + + ret = clk_audio_pll_compute_frac(rate, parent_rate, &nd, &fracr); + if (ret) + return ret; + + fck->nd = nd; + fck->fracr = fracr; + + return 0; +} + +static const struct clk_ops audio_pll_ops = { + .enable = clk_audio_pll_enable, + .disable = clk_audio_pll_disable, + .recalc_rate = clk_audio_pll_recalc_rate, + .round_rate = clk_audio_pll_round_rate, + .set_rate = clk_audio_pll_set_rate, +}; + +static void __init of_sama5d2_clk_audio_pll_setup(struct device_node *np) +{ + struct clk_audio_frac *fck; + struct clk_init_data init; + struct regmap *regmap; + const char *parent_name; + const char *name = np->name; + int ret; + + parent_name = of_clk_get_parent_name(np, 0); + + of_property_read_string(np, "clock-output-names", &name); + + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + + fck = kzalloc(sizeof(*fck), GFP_KERNEL); + if (!fck) + return; + + init.name = name; + init.ops = &audio_pll_ops; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = 1; + init.flags = CLK_SET_RATE_GATE; + + fck->hw.init = &init; + fck->regmap = regmap; + + ret = clk_hw_register(NULL, &fck->hw); + if (ret) + kfree(fck); + else + of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fck->hw); +} + +CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_setup, + "atmel,sama5d2-clk-audio-pll-frac", + of_sama5d2_clk_audio_pll_setup); diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h index 17f413bbbedf..6aca5ce8a99a 100644 --- a/include/linux/clk/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h @@ -185,4 +185,29 @@ #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ #define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */
+#define AT91_PMC_AUDIO_PLL0 0x14c +#define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0) +#define AT91_PMC_AUDIO_PLL_PADEN (1 << 1) +#define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2) +#define AT91_PMC_AUDIO_PLL_RESETN (1 << 3) +#define AT91_PMC_AUDIO_PLL_ND_OFFSET 8 +#define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16 +#define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) + +#define AT91_PMC_AUDIO_PLL1 0x150 +#define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff +#define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24 +#define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26 +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) + #endif diff --git a/sound/soc/atmel/atmel-classd.c b/sound/soc/atmel/atmel-classd.c index b7ef8c59b49a..05bf5004fecc 100644 --- a/sound/soc/atmel/atmel-classd.c +++ b/sound/soc/atmel/atmel-classd.c @@ -32,7 +32,6 @@ struct atmel_classd { struct regmap *regmap; struct clk *pclk; struct clk *gclk; - struct clk *aclk; int irq; const struct atmel_classd_pdata *pdata; }; @@ -332,10 +331,6 @@ static int atmel_classd_codec_dai_startup(struct snd_pcm_substream *substream, struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card); int ret;
- ret = clk_prepare_enable(dd->aclk); - if (ret) - return ret; - return clk_prepare_enable(dd->gclk); }
@@ -414,9 +409,8 @@ atmel_classd_codec_dai_hw_params(struct snd_pcm_substream *substream, sample_rates[best].rate, sample_rates[best].aclk_rate);
clk_disable_unprepare(dd->gclk); - clk_disable_unprepare(dd->aclk);
- ret = clk_set_rate(dd->aclk, sample_rates[best].aclk_rate); + ret = clk_set_rate(dd->gclk, sample_rates[best].aclk_rate); if (ret) return ret;
@@ -426,10 +420,6 @@ atmel_classd_codec_dai_hw_params(struct snd_pcm_substream *substream,
snd_soc_update_bits(codec, CLASSD_INTPMR, mask, val);
- ret = clk_prepare_enable(dd->aclk); - if (ret) - return ret; - return clk_prepare_enable(dd->gclk); }
@@ -441,7 +431,6 @@ atmel_classd_codec_dai_shutdown(struct snd_pcm_substream *substream, struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
clk_disable_unprepare(dd->gclk); - clk_disable_unprepare(dd->aclk); }
static int atmel_classd_codec_dai_prepare(struct snd_pcm_substream *substream, @@ -596,13 +585,6 @@ static int atmel_classd_probe(struct platform_device *pdev) return ret; }
- dd->aclk = devm_clk_get(dev, "aclk"); - if (IS_ERR(dd->aclk)) { - ret = PTR_ERR(dd->aclk); - dev_err(dev, "failed to get audio clock: %d\n", ret); - return ret; - } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); io_base = devm_ioremap_resource(dev, res); if (IS_ERR(io_base)) {
Hi,
On 23/06/2017 at 11:00:55 +0200, Quentin Schulz wrote:
From: Nicolas Ferre nicolas.ferre@atmel.com
This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications.
The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formula, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre nicolas.ferre@atmel.com Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com
.../devicetree/bindings/clock/at91-clock.txt | 10 + arch/arm/mach-at91/Kconfig | 4 + drivers/clk/at91/Makefile | 2 + drivers/clk/at91/clk-audio-pll-pad.c | 204 ++++++++++++++++++ drivers/clk/at91/clk-audio-pll-pmc.c | 175 +++++++++++++++ drivers/clk/at91/clk-audio-pll.c | 237 +++++++++++++++++++++ include/linux/clk/at91_pmc.h | 25 +++ sound/soc/atmel/atmel-classd.c | 20 +-
This should definitively go in a separate patch.
8 files changed, 658 insertions(+), 19 deletions(-) create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c create mode 100644 drivers/clk/at91/clk-audio-pll.c
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt index 5f3ad65daf69..51c259a92d02 100644 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt @@ -81,6 +81,16 @@ Required properties: "atmel,sama5d2-clk-generated": at91 generated clock
- "atmel,sama5d2-clk-audio-pll-frac":
at91 audio fractional pll- "atmel,sama5d2-clk-audio-pll-pad":
at91 audio pll CLK_AUDIO output pin- "atmel,sama5d2-clk-audio-pll-pmc"
at91 audio pll output on AUDIOPLLCLK that feeds the PMCand can be used by peripheral clock or generic clockRequired properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index d735e5fc4772..9ae14d59a9ce 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -26,6 +26,7 @@ config SOC_SAMA5D2 select HAVE_AT91_USB_CLK select HAVE_AT91_H32MX select HAVE_AT91_GENERATED_CLK
- select HAVE_AT91_AUDIO_PLL select PINCTRL_AT91PIO4 help Select this if ou are using one of Atmel's SAMA5D2 family SoC.
@@ -125,6 +126,9 @@ config HAVE_AT91_H32MX config HAVE_AT91_GENERATED_CLK bool
+config HAVE_AT91_AUDIO_PLL
- bool
config SOC_SAM_V4_V5 bool
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 13e67bd35cff..c9353d17763a 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -6,6 +6,8 @@ obj-y += pmc.o sckc.o obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o obj-y += clk-system.o clk-peripheral.o clk-programmable.o
+obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll.o +obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll-pmc.o clk-audio-pll-pad.o obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o diff --git a/drivers/clk/at91/clk-audio-pll-pad.c b/drivers/clk/at91/clk-audio-pll-pad.c new file mode 100644 index 000000000000..a60ce47b82c6 --- /dev/null +++ b/drivers/clk/at91/clk-audio-pll-pad.c @@ -0,0 +1,204 @@ +/*
- Copyright (C) 2016 Atmel Corporation,
Nicolas Ferre <nicolas.ferre@atmel.com>
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- */
+#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/clk/at91_pmc.h> +#include <linux/of.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h>
+#include "pmc.h"
+/*
- DOC: PAD output for fractional PLL clock for audio
- Traits of this clock:
- enable - clk_enable writes divisors and enables PAD output
- rate - rate is adjustable.
clk->rate = parent->rate / (qdaudio * div))
- parent - fixed parent. No clk_set_parent support
- */
+#define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \
AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \(AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK))+struct clk_audio_pad {
- struct clk_hw hw;
- struct regmap *regmap;
- u8 qdaudio;
- u8 div;
+};
+#define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw)
+static int clk_audio_pll_pad_enable(struct clk_hw *hw) +{
- struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
- regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1,
AT91_PMC_AUDIO_PLL_QDPAD_MASK,AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div));- regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN);- return 0;
+}
+static void clk_audio_pll_pad_disable(struct clk_hw *hw) +{
- struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
- regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
AT91_PMC_AUDIO_PLL_PADEN, 0);+}
+static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)+{
- struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
- unsigned long apad_rate = 0;
- if (apad_ck->qdaudio && apad_ck->div)
apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div);- pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n",
__func__, apad_rate, apad_ck->div, apad_ck->qdaudio);- return apad_rate;
+}
+static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)+{
- struct clk_hw *pclk = clk_hw_get_parent(hw);
- long best_rate = -EINVAL;
- unsigned long best_parent_rate;
- unsigned long tmp_qd;
- u32 div;
- long tmp_rate;
- int tmp_diff;
- int best_diff = -1;
- pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
rate, *parent_rate);- /*
* Rate divisor is actually made of two different divisors, multiplied* between themselves before dividing the rate.* tmp_qd goes from 1 to 31 and div is either 2 or 3.* In order to avoid testing twice the rate divisor (e.g. divisor 12 can* be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop* for a rate divisor when div is 2 and tmp_qd is a multiple of 3.* We cannot inverse it (condition div is 3 and tmp_qd is even) or we* would miss some rate divisor that aren't reachable with div being 2* (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus* tmp_qd is even so we skip it because we think div 2 could make this* rate divisor which isn't possible since tmp_qd has to be <= 31).*/- for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++)
for (div = 2; div <= 3; div++) {if (div == 2 && tmp_qd % 3 == 0)continue;best_parent_rate = clk_hw_round_rate(pclk,rate * tmp_qd * div);tmp_rate = best_parent_rate / (div * tmp_qd);tmp_diff = abs(rate - tmp_rate);if (best_diff < 0 || best_diff > tmp_diff) {*parent_rate = best_parent_rate;best_rate = tmp_rate;best_diff = tmp_diff;}}- pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n",
__func__, best_rate, best_parent_rate);- return best_rate;
+}
+static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)+{
- struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw);
- u8 tmp_div;
- pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
rate, parent_rate);- if (!rate)
return -EINVAL;- tmp_div = parent_rate / rate;
- if (tmp_div % 3 == 0) {
apad_ck->qdaudio = tmp_div / 3;apad_ck->div = 3;- } else {
apad_ck->qdaudio = tmp_div / 2;apad_ck->div = 2;- }
- return 0;
+}
+static const struct clk_ops audio_pll_pad_ops = {
- .enable = clk_audio_pll_pad_enable,
- .disable = clk_audio_pll_pad_disable,
- .recalc_rate = clk_audio_pll_pad_recalc_rate,
- .round_rate = clk_audio_pll_pad_round_rate,
- .set_rate = clk_audio_pll_pad_set_rate,
+};
+static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np) +{
- struct clk_audio_pad *apad_ck;
- struct clk_init_data init;
- struct regmap *regmap;
- const char *parent_name;
- const char *name = np->name;
- int ret;
- parent_name = of_clk_get_parent_name(np, 0);
- of_property_read_string(np, "clock-output-names", &name);
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
return;- apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL);
- if (!apad_ck)
return;- init.name = name;
- init.ops = &audio_pll_pad_ops;
- init.parent_names = (parent_name ? &parent_name : NULL);
- init.num_parents = 1;
- init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
CLK_SET_RATE_PARENT;- apad_ck->hw.init = &init;
- apad_ck->regmap = regmap;
- ret = clk_hw_register(NULL, &apad_ck->hw);
- if (ret)
kfree(apad_ck);- else
of_clk_add_hw_provider(np, of_clk_hw_simple_get, &apad_ck->hw);+}
+CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
"atmel,sama5d2-clk-audio-pll-pad",of_sama5d2_clk_audio_pll_pad_setup);diff --git a/drivers/clk/at91/clk-audio-pll-pmc.c b/drivers/clk/at91/clk-audio-pll-pmc.c new file mode 100644 index 000000000000..208d0b59eb4e --- /dev/null +++ b/drivers/clk/at91/clk-audio-pll-pmc.c @@ -0,0 +1,175 @@ +/*
- Copyright (C) 2016 Atmel Corporation,
Nicolas Ferre <nicolas.ferre@atmel.com>
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- */
+#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/clk/at91_pmc.h> +#include <linux/of.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h>
+#include "pmc.h"
+/*
- DOC: PMC output for fractional PLL clock for audio
- Traits of this clock:
- enable - clk_enable writes qdpmc, and enables PMC output
- rate - rate is adjustable.
clk->rate = parent->rate / (qdpmc + 1)
- parent - fixed parent. No clk_set_parent support
- */
+#define AUDIO_PLL_FOUT_MIN 620000000 +#define AUDIO_PLL_FOUT_MAX 700000000 +#define AUDIO_PLL_REFERENCE_FOUT 660000000 +#define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \
AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)+struct clk_audio_pmc {
- struct clk_hw hw;
- struct regmap *regmap;
- u8 qdpmc;
+};
+#define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw)
+static int clk_audio_pll_pmc_enable(struct clk_hw *hw) +{
- struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
- regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
AT91_PMC_AUDIO_PLL_PMCEN |AT91_PMC_AUDIO_PLL_QDPMC_MASK,AT91_PMC_AUDIO_PLL_PMCEN |AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc));- return 0;
+}
+static void clk_audio_pll_pmc_disable(struct clk_hw *hw) +{
- struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
- regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
AT91_PMC_AUDIO_PLL_PMCEN, 0);+}
+static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)+{
- struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
- unsigned long apmc_rate = 0;
- apmc_rate = parent_rate / (apmc_ck->qdpmc + 1);
- pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__,
apmc_rate, apmc_ck->qdpmc);- return apmc_rate;
+}
+static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)+{
- struct clk_hw *pclk = clk_hw_get_parent(hw);
- long best_rate = -EINVAL;
- unsigned long best_parent_rate = 0;
- u32 tmp_qd = 0, div;
- long tmp_rate;
- int tmp_diff;
- int best_diff = -1;
- pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
rate, *parent_rate);- for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) {
best_parent_rate = clk_round_rate(pclk->clk, rate * div);tmp_rate = best_parent_rate / div;tmp_diff = abs(rate - tmp_rate);if (best_diff < 0 || best_diff > tmp_diff) {*parent_rate = best_parent_rate;best_rate = tmp_rate;best_diff = tmp_diff;tmp_qd = div;}- }
- pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n",
__func__, best_rate, *parent_rate, tmp_qd - 1);- return best_rate;
+}
+static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)+{
- struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw);
- if (!rate)
return -EINVAL;- pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
rate, parent_rate);- apmc_ck->qdpmc = parent_rate / rate - 1;
- return 0;
+}
+static const struct clk_ops audio_pll_pmc_ops = {
- .enable = clk_audio_pll_pmc_enable,
- .disable = clk_audio_pll_pmc_disable,
- .recalc_rate = clk_audio_pll_pmc_recalc_rate,
- .round_rate = clk_audio_pll_pmc_round_rate,
- .set_rate = clk_audio_pll_pmc_set_rate,
+};
+static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np) +{
- struct clk_audio_pmc *apmc_ck;
- struct clk_init_data init;
- struct regmap *regmap;
- const char *parent_name;
- const char *name = np->name;
- int ret;
- parent_name = of_clk_get_parent_name(np, 0);
- of_property_read_string(np, "clock-output-names", &name);
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
return;- apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
- if (!apmc_ck)
return;- init.name = name;
- init.ops = &audio_pll_pmc_ops;
- init.parent_names = (parent_name ? &parent_name : NULL);
- init.num_parents = 1;
- init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
CLK_SET_RATE_PARENT;- apmc_ck->hw.init = &init;
- apmc_ck->regmap = regmap;
- ret = clk_hw_register(NULL, &apmc_ck->hw);
- if (ret)
kfree(apmc_ck);- else
of_clk_add_hw_provider(np, of_clk_hw_simple_get, &apmc_ck->hw);+}
+CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
"atmel,sama5d2-clk-audio-pll-pmc",of_sama5d2_clk_audio_pll_pmc_setup);diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c new file mode 100644 index 000000000000..ad8c8827681e --- /dev/null +++ b/drivers/clk/at91/clk-audio-pll.c @@ -0,0 +1,237 @@ +/*
- Copyright (C) 2016 Atmel Corporation,
Songjun Wu <songjun.wu@atmel.com>,
Nicolas Ferre <nicolas.ferre@atmel.com>
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- */
+#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/clk/at91_pmc.h> +#include <linux/of.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h>
+#include "pmc.h"
+/*
- DOC: Fractional PLL clock for audio
- Traits of this clock:
- prepare - clk_prepare puts audio PLL in reset state
- enable - clk_enable writes nd, fracr parameters and enables PLL
- rate - rate is adjustable.
clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
- parent - fixed parent. No clk_set_parent support
- */
+#define AUDIO_PLL_DIV_FRAC BIT(22) +#define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \
AT91_PMC_AUDIO_PLL_ND_OFFSET)+#define AUDIO_PLL_FOUT_MIN 620000000 +#define AUDIO_PLL_FOUT_MAX 700000000
+struct clk_audio_frac {
- struct clk_hw hw;
- struct regmap *regmap;
- u32 fracr;
- u8 nd;
+};
+#define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw)
+static int clk_audio_pll_enable(struct clk_hw *hw) +{
- struct clk_audio_frac *fck = to_clk_audio_frac(hw);
- regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0,
AT91_PMC_AUDIO_PLL_RESETN, 0);- regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0,
AT91_PMC_AUDIO_PLL_RESETN,AT91_PMC_AUDIO_PLL_RESETN);- regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL1,
AT91_PMC_AUDIO_PLL_FRACR_MASK, fck->fracr);- /*
* reset and enable have to be done in 2 separated writes* for AT91_PMC_AUDIO_PLL0*/- regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0,
AT91_PMC_AUDIO_PLL_PLLEN |AT91_PMC_AUDIO_PLL_ND_MASK,AT91_PMC_AUDIO_PLL_PLLEN |AT91_PMC_AUDIO_PLL_ND(fck->nd));- return 0;
+}
+static void clk_audio_pll_disable(struct clk_hw *hw) +{
- struct clk_audio_frac *fck = to_clk_audio_frac(hw);
- regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0,
AT91_PMC_AUDIO_PLL_PLLEN, 0);- /* do it in 2 separated writes */
- regmap_update_bits(fck->regmap, AT91_PMC_AUDIO_PLL0,
AT91_PMC_AUDIO_PLL_RESETN, 0);+}
+static unsigned long clk_audio_pll_fout(unsigned long parent_rate,
unsigned long nd, unsigned long fracr)+{
- unsigned long long fr = (unsigned long long)parent_rate *
(unsigned long long)fracr;- pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
- fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC);
- pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
- return parent_rate * (nd + 1) + fr;
+}
+static unsigned long clk_audio_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)+{
- struct clk_audio_frac *fck = to_clk_audio_frac(hw);
- unsigned long fout;
- fout = clk_audio_pll_fout(parent_rate, fck->nd, fck->fracr);
- pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__,
fout, fck->nd, (unsigned long)fck->fracr);- return fout;
+}
+static int clk_audio_pll_compute_frac(unsigned long rate,
unsigned long parent_rate,unsigned long *nd, unsigned long *fracr)+{
- unsigned long long tmp, rem;
- if (!rate)
return -EINVAL;- tmp = rate;
- rem = do_div(tmp, parent_rate);
- if (!tmp || tmp >= AUDIO_PLL_ND_MAX)
return -EINVAL;- *nd = tmp - 1;
- tmp = rem * AUDIO_PLL_DIV_FRAC;
- tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate);
- if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK)
return -EINVAL;- /* we can cast here as we verified the bounds just above */
- *fracr = (unsigned long)tmp;
- return 0;
+}
+static long clk_audio_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)+{
- long best_rate = -EINVAL;
- unsigned long fracr, nd;
- int ret;
- pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate,
*parent_rate);- if (rate < AUDIO_PLL_FOUT_MIN)
rate = AUDIO_PLL_FOUT_MIN;- else if (rate > AUDIO_PLL_FOUT_MAX)
rate = AUDIO_PLL_FOUT_MAX;- ret = clk_audio_pll_compute_frac(rate, *parent_rate, &nd, &fracr);
- if (ret)
return ret;- best_rate = clk_audio_pll_fout(*parent_rate, nd, fracr);
- pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n",
__func__, best_rate, nd, fracr);- return best_rate;
+}
+static int clk_audio_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)+{
- struct clk_audio_frac *fck = to_clk_audio_frac(hw);
- unsigned long fracr, nd;
- int ret;
- pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate,
parent_rate);- if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX)
return -EINVAL;- ret = clk_audio_pll_compute_frac(rate, parent_rate, &nd, &fracr);
- if (ret)
return ret;- fck->nd = nd;
- fck->fracr = fracr;
- return 0;
+}
+static const struct clk_ops audio_pll_ops = {
- .enable = clk_audio_pll_enable,
- .disable = clk_audio_pll_disable,
- .recalc_rate = clk_audio_pll_recalc_rate,
- .round_rate = clk_audio_pll_round_rate,
- .set_rate = clk_audio_pll_set_rate,
+};
+static void __init of_sama5d2_clk_audio_pll_setup(struct device_node *np) +{
- struct clk_audio_frac *fck;
- struct clk_init_data init;
- struct regmap *regmap;
- const char *parent_name;
- const char *name = np->name;
- int ret;
- parent_name = of_clk_get_parent_name(np, 0);
- of_property_read_string(np, "clock-output-names", &name);
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
return;- fck = kzalloc(sizeof(*fck), GFP_KERNEL);
- if (!fck)
return;- init.name = name;
- init.ops = &audio_pll_ops;
- init.parent_names = (parent_name ? &parent_name : NULL);
- init.num_parents = 1;
- init.flags = CLK_SET_RATE_GATE;
- fck->hw.init = &init;
- fck->regmap = regmap;
- ret = clk_hw_register(NULL, &fck->hw);
- if (ret)
kfree(fck);- else
of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fck->hw);+}
+CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_setup,
"atmel,sama5d2-clk-audio-pll-frac",of_sama5d2_clk_audio_pll_setup);diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h index 17f413bbbedf..6aca5ce8a99a 100644 --- a/include/linux/clk/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h @@ -185,4 +185,29 @@ #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ #define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */
+#define AT91_PMC_AUDIO_PLL0 0x14c +#define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0) +#define AT91_PMC_AUDIO_PLL_PADEN (1 << 1) +#define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2) +#define AT91_PMC_AUDIO_PLL_RESETN (1 << 3) +#define AT91_PMC_AUDIO_PLL_ND_OFFSET 8 +#define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16 +#define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
+#define AT91_PMC_AUDIO_PLL1 0x150 +#define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff +#define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24 +#define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26 +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
#endif diff --git a/sound/soc/atmel/atmel-classd.c b/sound/soc/atmel/atmel-classd.c index b7ef8c59b49a..05bf5004fecc 100644 --- a/sound/soc/atmel/atmel-classd.c +++ b/sound/soc/atmel/atmel-classd.c @@ -32,7 +32,6 @@ struct atmel_classd { struct regmap *regmap; struct clk *pclk; struct clk *gclk;
- struct clk *aclk; int irq; const struct atmel_classd_pdata *pdata;
}; @@ -332,10 +331,6 @@ static int atmel_classd_codec_dai_startup(struct snd_pcm_substream *substream, struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card); int ret;
- ret = clk_prepare_enable(dd->aclk);
- if (ret)
return ret;- return clk_prepare_enable(dd->gclk);
}
@@ -414,9 +409,8 @@ atmel_classd_codec_dai_hw_params(struct snd_pcm_substream *substream, sample_rates[best].rate, sample_rates[best].aclk_rate);
clk_disable_unprepare(dd->gclk);
clk_disable_unprepare(dd->aclk);
ret = clk_set_rate(dd->aclk, sample_rates[best].aclk_rate);
- ret = clk_set_rate(dd->gclk, sample_rates[best].aclk_rate); if (ret) return ret;
@@ -426,10 +420,6 @@ atmel_classd_codec_dai_hw_params(struct snd_pcm_substream *substream,
snd_soc_update_bits(codec, CLASSD_INTPMR, mask, val);
- ret = clk_prepare_enable(dd->aclk);
- if (ret)
return ret;- return clk_prepare_enable(dd->gclk);
}
@@ -441,7 +431,6 @@ atmel_classd_codec_dai_shutdown(struct snd_pcm_substream *substream, struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
clk_disable_unprepare(dd->gclk);
- clk_disable_unprepare(dd->aclk);
}
static int atmel_classd_codec_dai_prepare(struct snd_pcm_substream *substream, @@ -596,13 +585,6 @@ static int atmel_classd_probe(struct platform_device *pdev) return ret; }
- dd->aclk = devm_clk_get(dev, "aclk");
- if (IS_ERR(dd->aclk)) {
ret = PTR_ERR(dd->aclk);dev_err(dev, "failed to get audio clock: %d\n", ret);return ret;- }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); io_base = devm_ioremap_resource(dev, res); if (IS_ERR(io_base)) {
-- 2.11.0
On Fri, Jun 23, 2017 at 11:00:55AM +0200, Quentin Schulz wrote:
From: Nicolas Ferre nicolas.ferre@atmel.com
This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications.
The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formula, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre nicolas.ferre@atmel.com Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com
.../devicetree/bindings/clock/at91-clock.txt | 10 +
It would be nice to see at91 to transition away from a node per clock to just clock controller nodes. In any case:
Acked-by: Rob Herring robh@kernel.org
arch/arm/mach-at91/Kconfig | 4 + drivers/clk/at91/Makefile | 2 + drivers/clk/at91/clk-audio-pll-pad.c | 204 ++++++++++++++++++ drivers/clk/at91/clk-audio-pll-pmc.c | 175 +++++++++++++++ drivers/clk/at91/clk-audio-pll.c | 237 +++++++++++++++++++++ include/linux/clk/at91_pmc.h | 25 +++ sound/soc/atmel/atmel-classd.c | 20 +- 8 files changed, 658 insertions(+), 19 deletions(-) create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c create mode 100644 drivers/clk/at91/clk-audio-pll.c
Hi,
On 29/06/2017 at 16:47:58 -0500, Rob Herring wrote:
On Fri, Jun 23, 2017 at 11:00:55AM +0200, Quentin Schulz wrote:
From: Nicolas Ferre nicolas.ferre@atmel.com
This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications.
The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formula, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre nicolas.ferre@atmel.com Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com
.../devicetree/bindings/clock/at91-clock.txt | 10 +
It would be nice to see at91 to transition away from a node per clock to just clock controller nodes. In any case:
Yes, that is exactly our plan.
Acked-by: Rob Herring robh@kernel.org
arch/arm/mach-at91/Kconfig | 4 + drivers/clk/at91/Makefile | 2 + drivers/clk/at91/clk-audio-pll-pad.c | 204 ++++++++++++++++++ drivers/clk/at91/clk-audio-pll-pmc.c | 175 +++++++++++++++ drivers/clk/at91/clk-audio-pll.c | 237 +++++++++++++++++++++ include/linux/clk/at91_pmc.h | 25 +++ sound/soc/atmel/atmel-classd.c | 20 +- 8 files changed, 658 insertions(+), 19 deletions(-) create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c create mode 100644 drivers/clk/at91/clk-audio-pll.c
On Fri, 23 Jun 2017 11:00:55 +0200 Quentin Schulz quentin.schulz@free-electrons.com wrote:
From: Nicolas Ferre nicolas.ferre@atmel.com
This new clock driver set allows to have a fractional divided clock that would generate a precise clock particularly suitable for audio applications.
The main audio pll clock has two children clocks: one that is connected to the PMC, the other that can directly drive a pad. As these two routes have different enable bits and different dividers and divider formula, they are handled by two different drivers. Each of them could modify the rate of the main audio pll parent. The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre nicolas.ferre@atmel.com Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com
.../devicetree/bindings/clock/at91-clock.txt | 10 +
As already mentioned by Alex, DT bindings should go in a separate patch
arch/arm/mach-at91/Kconfig | 4 + drivers/clk/at91/Makefile | 2 + drivers/clk/at91/clk-audio-pll-pad.c | 204 ++++++++++++++++++ drivers/clk/at91/clk-audio-pll-pmc.c | 175 +++++++++++++++ drivers/clk/at91/clk-audio-pll.c | 237 +++++++++++++++++++++ include/linux/clk/at91_pmc.h | 25 +++ sound/soc/atmel/atmel-classd.c | 20 +-
Same goes for the atmel-classd changes.
8 files changed, 658 insertions(+), 19 deletions(-) create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c create mode 100644 drivers/clk/at91/clk-audio-pll.c
[...]
diff --git a/drivers/clk/at91/clk-audio-pll-pmc.c b/drivers/clk/at91/clk-audio-pll-pmc.c new file mode 100644 index 000000000000..208d0b59eb4e --- /dev/null +++ b/drivers/clk/at91/clk-audio-pll-pmc.c @@ -0,0 +1,175 @@ +/*
- Copyright (C) 2016 Atmel Corporation,
Nicolas Ferre <nicolas.ferre@atmel.com>
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- */
+#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/clk/at91_pmc.h> +#include <linux/of.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h>
+#include "pmc.h"
+/*
- DOC: PMC output for fractional PLL clock for audio
- Traits of this clock:
- enable - clk_enable writes qdpmc, and enables PMC output
- rate - rate is adjustable.
clk->rate = parent->rate / (qdpmc + 1)
- parent - fixed parent. No clk_set_parent support
- */
+#define AUDIO_PLL_FOUT_MIN 620000000 +#define AUDIO_PLL_FOUT_MAX 700000000 +#define AUDIO_PLL_REFERENCE_FOUT 660000000
These 3 macros are not unused, you can drop them.
From: Cyrille Pitchen cyrille.pitchen@atmel.com
This patch adds nodes for the classd device and its generated clock.
Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com Signed-off-by: Nicolas Ferre nicolas.ferre@atmel.com Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com --- arch/arm/boot/dts/sama5d2.dtsi | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index cc06da394366..a564cd1ba327 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -494,6 +494,24 @@ clocks = <&plla>; };
+ audio_pll_frac: audiopll_fracck { + compatible = "atmel,sama5d2-clk-audio-pll-frac"; + #clock-cells = <0>; + clocks = <&main>; + }; + + audio_pll_pad: audiopll_padck { + compatible = "atmel,sama5d2-clk-audio-pll-pad"; + #clock-cells = <0>; + clocks = <&audio_pll_frac>; + }; + + audio_pll_pmc: audiopll_pmcck { + compatible = "atmel,sama5d2-clk-audio-pll-pmc"; + #clock-cells = <0>; + clocks = <&audio_pll_frac>; + }; + utmi: utmick { compatible = "atmel,at91sam9x5-clk-utmi"; #clock-cells = <0>; @@ -895,7 +913,7 @@ #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
sdmmc0_gclk: sdmmc0_gclk { #clock-cells = <0>; @@ -951,6 +969,12 @@ reg = <57>; atmel,clk-output-range = <0 80000000>; }; + + classd_gclk: classd_gclk { + #clock-cells = <0>; + reg = <59>; + atmel,clk-output-range = <0 100000000>; + }; }; };
@@ -1406,6 +1430,19 @@ status = "okay"; };
+ classd: classd@fc048000 { + compatible = "atmel,sama5d2-classd"; + reg = <0xfc048000 0x100>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(47))>; + dma-names = "tx"; + clocks = <&classd_clk>, <&classd_gclk>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + can1: can@fc050000 { compatible = "bosch,m_can"; reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
The way to find the best_diff and do the appropriate process afterwards can be re-used.
This patch prepares the driver for an upcoming patch that will allow clk_generated to determine the rate of the audio_pll.
Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com --- drivers/clk/at91/clk-generated.c | 41 ++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index dab7002937e6..6530a2e7e84d 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -99,15 +99,36 @@ clk_generated_recalc_rate(struct clk_hw *hw, return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1); }
+static void clk_generated_best_diff(struct clk_rate_request *req, + struct clk_hw *parent, + unsigned long parent_rate, u32 div, + int *best_diff, long *best_rate) +{ + unsigned long tmp_rate; + int tmp_diff; + + if (!div) + tmp_rate = parent_rate; + else + tmp_rate = parent_rate / div; + tmp_diff = abs(req->rate - tmp_rate); + + if (*best_diff < 0 || *best_diff > tmp_diff) { + *best_rate = tmp_rate; + *best_diff = tmp_diff; + req->best_parent_rate = parent_rate; + req->best_parent_hw = parent; + } +} + static int clk_generated_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_generated *gck = to_clk_generated(hw); struct clk_hw *parent = NULL; long best_rate = -EINVAL; - unsigned long tmp_rate, min_rate; + unsigned long min_rate; int best_diff = -1; - int tmp_diff; int i;
for (i = 0; i < clk_hw_get_num_parents(hw); i++) { @@ -125,18 +146,10 @@ static int clk_generated_determine_rate(struct clk_hw *hw, continue;
div = DIV_ROUND_CLOSEST(parent_rate, req->rate); - if (!div) - tmp_rate = parent_rate; - else - tmp_rate = parent_rate / div; - tmp_diff = abs(req->rate - tmp_rate); - - if (best_diff < 0 || best_diff > tmp_diff) { - best_rate = tmp_rate; - best_diff = tmp_diff; - req->best_parent_rate = parent_rate; - req->best_parent_hw = parent; - } + + clk_generated_best_diff(req, parent, parent_rate, div, + &best_diff, &best_rate); +
if (!best_diff) break;
On Fri, 23 Jun 2017 11:00:57 +0200 Quentin Schulz quentin.schulz@free-electrons.com wrote:
The way to find the best_diff and do the appropriate process afterwards can be re-used.
This patch prepares the driver for an upcoming patch that will allow clk_generated to determine the rate of the audio_pll.
Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com
Acked-by: Boris Brezillon boris.brezillon@free-electrons.com
drivers/clk/at91/clk-generated.c | 41 ++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index dab7002937e6..6530a2e7e84d 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -99,15 +99,36 @@ clk_generated_recalc_rate(struct clk_hw *hw, return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1); }
+static void clk_generated_best_diff(struct clk_rate_request *req,
struct clk_hw *parent,unsigned long parent_rate, u32 div,int *best_diff, long *best_rate)+{
- unsigned long tmp_rate;
- int tmp_diff;
- if (!div)
tmp_rate = parent_rate;- else
tmp_rate = parent_rate / div;- tmp_diff = abs(req->rate - tmp_rate);
- if (*best_diff < 0 || *best_diff > tmp_diff) {
*best_rate = tmp_rate;*best_diff = tmp_diff;req->best_parent_rate = parent_rate;req->best_parent_hw = parent;- }
+}
static int clk_generated_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_generated *gck = to_clk_generated(hw); struct clk_hw *parent = NULL; long best_rate = -EINVAL;
- unsigned long tmp_rate, min_rate;
- unsigned long min_rate; int best_diff = -1;
int tmp_diff; int i;
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
@@ -125,18 +146,10 @@ static int clk_generated_determine_rate(struct clk_hw *hw, continue;
div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
if (!div)tmp_rate = parent_rate;elsetmp_rate = parent_rate / div;tmp_diff = abs(req->rate - tmp_rate);if (best_diff < 0 || best_diff > tmp_diff) {best_rate = tmp_rate;best_diff = tmp_diff;req->best_parent_rate = parent_rate;req->best_parent_hw = parent;}
clk_generated_best_diff(req, parent, parent_rate, div,&best_diff, &best_rate);if (!best_diff) break;
This allows gclk to determine audio_pll rate and set the parent rate accordingly.
However, there are multiple children clocks that could technically change the rate of audio_pll. Since the clock rate is usually critical for IPs, it isn't a good idea to have multiple clocks changing audio_pll clock rate. There isn't any rate locking system for the moment, thus we enforce that classd_gclk be the only one allowed to change audio_pll rate. To remain consistent, we deny other clocks to be children of audio_pll so classd_gclk altering audio_pll rate does not impact any other device.
This needs to be re-worked once we have a rate locking system so two clocks could be children of the same clock and be sure the clock rate isn't changed by one or the other.
Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com --- drivers/clk/at91/clk-generated.c | 41 ++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 6530a2e7e84d..e66ee735a569 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -26,6 +26,9 @@ #define GENERATED_SOURCE_MAX 6 #define GENERATED_MAX_DIV 255
+#define GCK_ID_CLASSD 59 +#define GCK_INDEX_DT_AUDIO_PLL 5 + struct clk_generated { struct clk_hw hw; struct regmap *regmap; @@ -126,15 +129,14 @@ static int clk_generated_determine_rate(struct clk_hw *hw, { struct clk_generated *gck = to_clk_generated(hw); struct clk_hw *parent = NULL; + struct clk_rate_request req_parent = *req; long best_rate = -EINVAL; - unsigned long min_rate; + unsigned long min_rate, parent_rate; int best_diff = -1; int i; + u32 div;
- for (i = 0; i < clk_hw_get_num_parents(hw); i++) { - u32 div; - unsigned long parent_rate; - + for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) { parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; @@ -150,11 +152,37 @@ static int clk_generated_determine_rate(struct clk_hw *hw, clk_generated_best_diff(req, parent, parent_rate, div, &best_diff, &best_rate);
+ if (!best_diff) + break; + } + + /* + * The audio_pll rate can be modified unlike the five others clocks that + * should never be altered. + * The audio_pll can technically be used by multiple consumers. However, + * they all are likely to want to modify its rate while the rate is + * critical for each one. Since we do not have a rate locking for the + * moment, let classd_gclk be the only consumer of the audio_pll clock. + */ + + if (gck->id != GCK_ID_CLASSD) + goto end; + + parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL); + if (!parent) + goto end; + + for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { + req_parent.rate = req->rate * div; + __clk_determine_rate(parent, &req_parent); + clk_generated_best_diff(req, parent, req_parent.rate, div, + &best_diff, &best_rate);
if (!best_diff) break; }
+end: pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", __func__, best_rate, __clk_get_name((req->best_parent_hw)->clk), @@ -264,7 +292,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, init.ops = &generated_ops; init.parent_names = parent_names; init.num_parents = num_parents; - init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; + init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT;
gck->id = id; gck->hw.init = &init;
On Fri, 23 Jun 2017 11:00:58 +0200 Quentin Schulz quentin.schulz@free-electrons.com wrote:
This allows gclk to determine audio_pll rate and set the parent rate accordingly.
However, there are multiple children clocks that could technically change the rate of audio_pll. Since the clock rate is usually critical for IPs, it isn't a good idea to have multiple clocks changing audio_pll clock rate. There isn't any rate locking system for the moment, thus we enforce that classd_gclk be the only one allowed to change audio_pll rate. To remain consistent, we deny other clocks to be children of audio_pll so classd_gclk altering audio_pll rate does not impact any other device.
This needs to be re-worked once we have a rate locking system so two clocks could be children of the same clock and be sure the clock rate isn't changed by one or the other.
Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com
drivers/clk/at91/clk-generated.c | 41 ++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 6530a2e7e84d..e66ee735a569 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -26,6 +26,9 @@ #define GENERATED_SOURCE_MAX 6 #define GENERATED_MAX_DIV 255
+#define GCK_ID_CLASSD 59 +#define GCK_INDEX_DT_AUDIO_PLL 5
struct clk_generated { struct clk_hw hw; struct regmap *regmap; @@ -126,15 +129,14 @@ static int clk_generated_determine_rate(struct clk_hw *hw, { struct clk_generated *gck = to_clk_generated(hw); struct clk_hw *parent = NULL;
- struct clk_rate_request req_parent = *req; long best_rate = -EINVAL;
- unsigned long min_rate;
- unsigned long min_rate, parent_rate; int best_diff = -1; int i;
- u32 div;
- for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
u32 div;unsigned long parent_rate;
- for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) { parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue;
@@ -150,11 +152,37 @@ static int clk_generated_determine_rate(struct clk_hw *hw, clk_generated_best_diff(req, parent, parent_rate, div, &best_diff, &best_rate);
if (!best_diff)break;- }
- /*
* The audio_pll rate can be modified unlike the five others clocks that* should never be altered.* The audio_pll can technically be used by multiple consumers. However,* they all are likely to want to modify its rate while the rate is* critical for each one. Since we do not have a rate locking for the* moment, let classd_gclk be the only consumer of the audio_pll clock.*/- if (gck->id != GCK_ID_CLASSD)
goto end;
As discussed on IRC with Nicolas and Cyrille, it seems we have other potential users of the audio-pll: SSC and I2S. Can you extend the test to let these GCK clks take the audio-pll?
parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
if (!parent)
goto end;for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
req_parent.rate = req->rate * div;__clk_determine_rate(parent, &req_parent);clk_generated_best_diff(req, parent, req_parent.rate, div,&best_diff, &best_rate);if (!best_diff) break; }
+end: pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", __func__, best_rate, __clk_get_name((req->best_parent_hw)->clk), @@ -264,7 +292,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, init.ops = &generated_ops; init.parent_names = parent_names; init.num_parents = num_parents;
- init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
CLK_SET_RATE_PARENT;gck->id = id; gck->hw.init = &init;
From: Cyrille Pitchen cyrille.pitchen@atmel.com
This patch adds the pin muxing for classd and enables it.
Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com Signed-off-by: Nicolas Ferre nicolas.ferre@atmel.com Signed-off-by: Quentin Schulz quentin.schulz@free-electrons.com --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 2e2c3d1a1fa2..e92b030ca45a 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -355,6 +355,14 @@ bias-pull-up; };
+ pinctrl_classd_default: classd_default { + pinmux = <PIN_PB1__CLASSD_R0>, + <PIN_PB2__CLASSD_R1>, + <PIN_PB3__CLASSD_R2>, + <PIN_PB4__CLASSD_R3>; + bias-pull-up; + }; + pinctrl_flx0_default: flx0_default { pinmux = <PIN_PB28__FLEXCOM0_IO0>, <PIN_PB29__FLEXCOM0_IO1>; @@ -488,6 +496,14 @@
};
+ classd: classd@fc048000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_classd_default>; + atmel,pwm-type = "diff"; + atmel,non-overlap-time = <10>; + status = "okay"; + }; + can1: can@fc050000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>;
participants (4)
-
Alexandre Belloni -
Boris Brezillon -
Quentin Schulz -
Rob Herring