Re: [alsa-devel] Random inverted audio channels
On Fri, Feb 15, 2008 at 05:39:49PM +0100, Alexandre BOUIN wrote:
This embedded project includes a AT91SAM9260 CPU and a WM8900 codec.
JOOI, is this the WM8900 driver in our dev branch or another one? It shouldn't make any difference either way what driver is used for the codec, though, so long as it is generating the relevant clock signals.
We have an issue : when we play a right channel stereo track, sound is played on right channel, but sometimes on left. This issue could happen right after starting kernel, or later after 10-20 sounds played. With Frank Mandarino, we've checked any issue from SSC(audio bus) or PDC (dma) controlers, but no much success.
Any idea to help us debugging this issue would be welcome !
The most likely issue here is a DMA underrun but from what you say you may already have ruled that out? It would be helpful if you could run through the debugging you've already done here.
One thing to try if your design allows it would be to try making the CPU the master. That should reduce the number of variables, at least.
This embedded project includes a AT91SAM9260 CPU and a WM8900 codec.
JOOI, is this the WM8900 driver in our dev branch or another one? It shouldn't make any difference either way what driver is used for the codec, though, so long as it is generating the relevant clock signals.
We are porting a WM8900 driver from a 8731 one. It fit quite well our requirements and should not be the same as your dev branch. Sincerely, It didn't know you're working on it.
We have an issue : when we play a right channel stereo track, sound
is
played on right channel, but sometimes on left. This issue could happen right after starting kernel, or later after
10-20
sounds played. With Frank Mandarino, we've checked any issue from SSC(audio bus) or
PDC
(dma) controlers, but no much success.
Any idea to help us debugging this issue would be welcome !
The most likely issue here is a DMA underrun but from what you say you may already have ruled that out? It would be helpful if you could run through the debugging you've already done here.
I had traced the addresses sent into PDC (soc/at91-pcm.c), and are always the same. What other traces are you looking for ?
One thing to try if your design allows it would be to try making the CPU the master. That should reduce the number of variables, at least.
You're right I should try this way, so it would confirm if I have or not an issue with my LRC clock.
participants (2)
-
Alexandre BOUIN -
Mark Brown