[PATCH v4 0/3] Update SoundWire RX and TX cgcr register control
This patch series is to add v1.6.0 compatable name for qcom soundwire driver and to update soundwire RX and TX cgcr register control.
Changes Since V3: -- Add v1.6.0 compatable name and soundwire data structure. -- Change macro define name properly. -- Update bindings for new property. -- Change commit message description. -- Change signedoff by sequence. Changes since v2: -- Update error check after ioremap. Changes since v1: -- Add const name to mask value. Srinivasa Rao Mandadapu (3): ASoC: qcom: soundwire: Disable soundwire rxtx cgcr hardware control dt-bindings: soundwire: qcom: Add bindings for RX and TX cgcr register control soundwire: qcom: Add compatible name for v1.6.0
.../devicetree/bindings/soundwire/qcom,sdw.txt | 9 +++++++++ drivers/soundwire/qcom.c | 20 ++++++++++++++++++++ 2 files changed, 29 insertions(+)
Update soundwire master rxtx cgcr register field to make clock gating control as software controllable. It is required for soundwire v1.6.0 and above for RX and TX path to work.
Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org --- drivers/soundwire/qcom.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 0ef79d6..2492190 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -109,6 +109,7 @@ #define SWR_MAX_CMD_ID 14 #define MAX_FIFO_RD_RETRY 3 #define SWR_OVERFLOW_RETRY_COUNT 30 +#define SWR_RXTX_CGCR_HW_CTL_MASK ~BIT(1)
struct qcom_swrm_port_config { u8 si; @@ -127,6 +128,7 @@ struct qcom_swrm_ctrl { struct device *dev; struct regmap *regmap; void __iomem *mmio; + char __iomem *audio_csr_mmio; struct completion broadcast; struct completion enumeration; struct work_struct slave_work; @@ -610,6 +612,12 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
+ if (ctrl->audio_csr_mmio) { + val = ioread32(ctrl->audio_csr_mmio); + val &= SWR_RXTX_CGCR_HW_CTL_MASK; + iowrite32(val, ctrl->audio_csr_mmio); + } + ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
/* Enable Auto enumeration */ @@ -1201,6 +1209,7 @@ static int qcom_swrm_probe(struct platform_device *pdev) const struct qcom_swrm_data *data; int ret; u32 val; + int swrm_hctl_reg;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); if (!ctrl) @@ -1251,6 +1260,11 @@ static int qcom_swrm_probe(struct platform_device *pdev) ctrl->bus.port_ops = &qcom_swrm_port_ops; ctrl->bus.compute_params = &qcom_swrm_compute_params;
+ if (!of_property_read_u32(dev->of_node, "qcom,swrm-hctl-reg", &swrm_hctl_reg)) { + ctrl->audio_csr_mmio = devm_ioremap(&pdev->dev, swrm_hctl_reg, 0x4); + if (!ctrl->audio_csr_mmio) + return -ENODEV; + } ret = qcom_swrm_get_port_config(ctrl); if (ret) goto err_clk;
Quoting Srinivasa Rao Mandadapu (2021-10-26 05:19:22)
Update soundwire master rxtx cgcr register field to make clock gating control as software controllable. It is required for soundwire v1.6.0 and above for RX and TX path to work.
Why not do that when the clk driver probes?
Update description for RX and TX cgcr register control property required for soundwire version 1.6.0 and above.
Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org --- Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt index b93a2b3..91b9086 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt +++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt @@ -150,6 +150,15 @@ board specific bus parameters. or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications.
+- qcom,swrm-hctl-reg: + Usage: optional + Value type: <prop-encoded-array> + Definition: The base address of SoundWire RX and TX cgcr register + address space. + This is to update soundwire master rxtx cgcr register field to + make clock gating control as software controllable for RX path and + TX path which is required for SoundWire version 1.6.0 and above. + Note: More Information on detail of encoding of these fields can be found in MIPI Alliance SoundWire 1.0 Specifications.
On Tue, 26 Oct 2021 17:49:23 +0530, Srinivasa Rao Mandadapu wrote:
Update description for RX and TX cgcr register control property required for soundwire version 1.6.0 and above.
Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 9 +++++++++ 1 file changed, 9 insertions(+)
Acked-by: Rob Herring robh@kernel.org
Quoting Srinivasa Rao Mandadapu (2021-10-26 05:19:23)
Update description for RX and TX cgcr register control property required for soundwire version 1.6.0 and above.
Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt index b93a2b3..91b9086 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt +++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt @@ -150,6 +150,15 @@ board specific bus parameters. or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications.
+- qcom,swrm-hctl-reg:
Usage: optionalValue type: <prop-encoded-array>Definition: The base address of SoundWire RX and TX cgcr registeraddress space.
cgcr is "clock gate control register"?
This is to update soundwire master rxtx cgcr register field tomake clock gating control as software controllable for RX path andTX path which is required for SoundWire version 1.6.0 and above.
Nak. Use clk APIs to control clks, not direct MMIO writes into a different device.
Update compatible string and master data information in soundwire driver to support v1.6.0 in lpass sc7280 based platform.
Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org --- drivers/soundwire/qcom.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 2492190..2b39f4c 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -173,6 +173,11 @@ static struct qcom_swrm_data swrm_v1_5_data = { .default_cols = 16, };
+static struct qcom_swrm_data swrm_v1_6_data = { + .default_rows = 50, + .default_cols = 16, +}; + #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, @@ -1339,6 +1344,7 @@ static int qcom_swrm_remove(struct platform_device *pdev) static const struct of_device_id qcom_swrm_of_match[] = { { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, + { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, {/* sentinel */}, };
Quoting Srinivasa Rao Mandadapu (2021-10-26 05:19:24)
Update compatible string and master data information in soundwire driver to support v1.6.0 in lpass sc7280 based platform.
Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org
drivers/soundwire/qcom.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 2492190..2b39f4c 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -173,6 +173,11 @@ static struct qcom_swrm_data swrm_v1_5_data = { .default_cols = 16, };
+static struct qcom_swrm_data swrm_v1_6_data = {
const?
.default_rows = 50,.default_cols = 16,+};
#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
participants (3)
-
Rob Herring -
Srinivasa Rao Mandadapu -
Stephen Boyd