[alsa-devel] [PATCH 0/3] Add mclk0 clock source for SAI
This patch series brings together patches [1] and [2] which introduce mclk0 clock source via DT.
mclk0..3 are the four clock sources options of SAI's clock MUX.
mclk0 option selects: - Bus Clock on i.MX8 - MCLK1 on i.MX6/7
Finally we also update the DT binding information for SAI clocks.
In [1] and [2] Nicolin had a very good point on the fact that mclk0 might not be needed in the DT. Anyhow, there are two reasons for which I think mlck0 should be added to DT:
1) SAI clock source select MUX is really part of the hardware 2) flexibility! We let DT tell us which is the option for MUX option 0.
[1] lkml.org/lkml/2019/4/20/141 [2] lkml.org/lkml/2019/4/20/56
Daniel Baluta (2): dt-bindings: sound: Clarify the usage of clocks in SAI ASoC: fsl_sai: Read SAI clock source 0 from DT
Shengjiu Wang (1): ARM: dts: imx: Add mclk0 clock for SAI
Documentation/devicetree/bindings/sound/fsl-sai.txt | 5 +++-- arch/arm/boot/dts/imx6sx.dtsi | 6 ++++-- arch/arm/boot/dts/imx6ul.dtsi | 9 ++++++--- arch/arm/boot/dts/imx7s.dtsi | 9 ++++++--- sound/soc/fsl/fsl_sai.c | 3 +-- 5 files changed, 20 insertions(+), 12 deletions(-)
From: Shengjiu Wang shengjiu.wang@nxp.com
Audio MCLK source option is selected with a 4:1 MUX controller using MCLK Select bits in SAI xCR2 register.
On imx6/7 mclk0 and mclk1 always point to the same clock source. Anyhow, this is no longer true for imx8.
For this reason, we need to add mclk0 and handle it in a generic way in SAI driver.
Signed-off-by: Shengjiu Wang shengjiu.wang@nxp.com Signed-off-by: Daniel Baluta daniel.baluta@nxp.com --- arch/arm/boot/dts/imx6sx.dtsi | 6 ++++-- arch/arm/boot/dts/imx6ul.dtsi | 9 ++++++--- arch/arm/boot/dts/imx7s.dtsi | 9 ++++++--- 3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index b16a123990a2..682207b5d868 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1071,9 +1071,10 @@ reg = <0x021d4000 0x4000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_SAI1_IPG>, + <&clks IMX6SX_CLK_SAI1>, <&clks IMX6SX_CLK_SAI1>, <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; status = "disabled"; @@ -1090,9 +1091,10 @@ reg = <0x021dc000 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_SAI2_IPG>, + <&clks IMX6SX_CLK_SAI2>, <&clks IMX6SX_CLK_SAI2>, <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index bbf010c73336..e9691306f557 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -304,9 +304,10 @@ reg = <0x02028000 0x4000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_SAI1_IPG>, + <&clks IMX6UL_CLK_SAI1>, <&clks IMX6UL_CLK_SAI1>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma 35 24 0>, <&sdma 36 24 0>; dma-names = "rx", "tx"; @@ -319,9 +320,10 @@ reg = <0x0202c000 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_SAI2_IPG>, + <&clks IMX6UL_CLK_SAI2>, <&clks IMX6UL_CLK_SAI2>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma 37 24 0>, <&sdma 38 24 0>; dma-names = "rx", "tx"; @@ -334,9 +336,10 @@ reg = <0x02030000 0x4000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_SAI3_IPG>, + <&clks IMX6UL_CLK_SAI3>, <&clks IMX6UL_CLK_SAI3>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma 39 24 0>, <&sdma 40 24 0>; dma-names = "rx", "tx"; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 106711d2c01b..c345a2e6d824 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -886,10 +886,11 @@ reg = <0x308a0000 0x10000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_SAI1_ROOT_CLK>, <&clks IMX7D_SAI1_ROOT_CLK>, <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; status = "disabled"; @@ -901,10 +902,11 @@ reg = <0x308b0000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_SAI2_ROOT_CLK>, <&clks IMX7D_SAI2_ROOT_CLK>, <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; status = "disabled"; @@ -916,10 +918,11 @@ reg = <0x308c0000 0x10000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_SAI3_ROOT_CLK>, <&clks IMX7D_SAI3_ROOT_CLK>, <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; status = "disabled";
On Tue, May 28, 2019 at 01:21:00PM +0000, Daniel Baluta wrote:
From: Shengjiu Wang shengjiu.wang@nxp.com
Audio MCLK source option is selected with a 4:1 MUX controller using MCLK Select bits in SAI xCR2 register.
On imx6/7 mclk0 and mclk1 always point to the same clock source. Anyhow, this is no longer true for imx8.
For this reason, we need to add mclk0 and handle it in a generic way in SAI driver.
Signed-off-by: Shengjiu Wang shengjiu.wang@nxp.com Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
arch/arm/boot/dts/imx6sx.dtsi | 6 ++++-- arch/arm/boot/dts/imx6ul.dtsi | 9 ++++++--- arch/arm/boot/dts/imx7s.dtsi | 9 ++++++---
These are dtsi/dts files that have SAI missing mclk0: arch/arm/boot/dts/imx6ul.dtsi arch/arm/boot/dts/imx6sx.dtsi arch/arm/boot/dts/ls1021a.dtsi arch/arm/boot/dts/imx7s.dtsi arch/arm/boot/dts/vfxxx.dtsi arch/arm64/boot/dts/freescale/imx8mq.dtsi arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
Would it be possible for you to update the others also?
Thanks Nicolin
SAI might have up to 4 clock sources selected by an internal CLK mux.
On imx6/7 mclk0/mclk1 are the same, while on imx8 mclk0 and mclk1 are coming from different sources.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 2e726b983845..db0497d1920a 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -15,8 +15,9 @@ Required properties: - clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the "bus" for register access and - "mclk1", "mclk2", "mclk3" for bit clock and frame - clock providing. + "mclk0", "mclk1", "mclk2", "mclk3" the four clock + sources of the SAI clock MUX selecting a clock + for bit clock and frame clock providing. - dmas : Generic dma devicetree binding as described in Documentation/devicetree/bindings/dma/dma.txt.
On Tue, 28 May 2019 13:21:01 +0000, Daniel Baluta wrote:
SAI might have up to 4 clock sources selected by an internal CLK mux.
On imx6/7 mclk0/mclk1 are the same, while on imx8 mclk0 and mclk1 are coming from different sources.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
Documentation/devicetree/bindings/sound/fsl-sai.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Rob Herring robh@kernel.org
SAI provide multiple master clock source options selectable via bit MSEL of TCR2/RCR2.
All possible master clock sources are stored in sai->mclk_clk array. Current implementation assumes that MCLK0 source is always busclk, but this is wrong!
For example, on i.MX8QM we have:
00b - Bus Clock selected. 01b - Master Clock (MCLK) 1 option selected. 10b - Master Clock (MCLK) 2 option selected. 11b - Master Clock (MCLK) 3 option selected.
while on i.MX6SX we have:
00b - Master Clock (MCLK) 1 option selected. 01b - Master Clock (MCLK) 1 option selected. 10b - Master Clock (MCLK) 2 option selected. 11b - Master Clock (MCLK) 3 option selected.
So, this patch will read mclk0 source clock from device tree.
Signed-off-by: Shengjiu Wang shengjiu.wang@nxp.com Signed-off-by: Daniel Baluta daniel.baluta@nxp.com --- sound/soc/fsl/fsl_sai.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index db9e0872f73d..b563004fb89f 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -826,8 +826,7 @@ static int fsl_sai_probe(struct platform_device *pdev) sai->bus_clk = NULL; }
- sai->mclk_clk[0] = sai->bus_clk; - for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { + for (i = 0; i < FSL_SAI_MCLK_MAX; i++) { sprintf(tmp, "mclk%d", i); sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); if (IS_ERR(sai->mclk_clk[i])) {
On Tue, May 28, 2019 at 01:20:46PM +0000, Daniel Baluta wrote:
- SAI clock source select MUX is really part of the hardware
- flexibility! We let DT tell us which is the option for MUX
option 0.
I think the "MUX" is plausible comparing to your previous version. As long as DT maintainers ack the DT binding doc, I would be okay to ack too. Just one comments at the dts/dtsi changes, I know the driver would just warn old DTs, but it does change the behavior at the mclk_clk[0] from previously bus_clk to NULL after this series.
On Wed, 2019-05-29 at 16:03 -0700, Nicolin Chen wrote:
On Tue, May 28, 2019 at 01:20:46PM +0000, Daniel Baluta wrote:
- SAI clock source select MUX is really part of the hardware
- flexibility! We let DT tell us which is the option for MUX
option 0.
I think the "MUX" is plausible comparing to your previous version. As long as DT maintainers ack the DT binding doc, I would be okay to ack too. Just one comments at the dts/dtsi changes, I know the driver would just warn old DTs, but it does change the behavior at the mclk_clk[0] from previously bus_clk to NULL after this series.
Thanks for review, will fix in v2.
participants (3)
-
Daniel Baluta -
Nicolin Chen -
Rob Herring