This patch copies some parts from imx-ssi to support AC97 on imx27-pca100 and imx35-pcm043. This is a implementation of the ac97-slave mode.

For ac97, the registers have to be setup earlier than for other ssi modes because there is some communication with the external device before actual streaming. So this patch introduces a fsl_ssi_setup function to setup the registers at different times.

To seperate board specific ac97 reset functions, ac97 read/write functions are exported. The reset functions are set by other drivers.

This patch was tested with imx27-pca100.

Signed-off-by: Markus Pargmann mpa@pengutronix.de Tested-by: Shawn Guo shawn.guo@linaro.org ---

Notes: Changes in v9: - Minor style fixes.

Changes in v7: - ac97 ops are now assigned to soc_ac97_ops to allow enabled imx-ssi and fsl-ssi at the same time.

Changes in v6: - ac97 reset functions are not provided by fsl-ssi code anymore. They were moved to board specific code like phycore-ac97. Therefore ac97 read/write functions are exported and a helper function to set the soc_ac97_ops reset functions was created.

Changes in v3: - Cleanup ac97 code by adding a fsl_ssi_setup function for initial register setup. For ac97 the registers have to be setup earlier than in normal mode.

sound/soc/fsl/fsl_ssi.c | 364 ++++++++++++++++++++++++++++++++++++++---------- sound/soc/fsl/fsl_ssi.h | 7 + 2 files changed, 299 insertions(+), 72 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index ed1fbbb..34cc1c8 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -141,6 +141,7 @@ struct fsl_ssi_private {

bool new_binding; bool ssi_on_imx; + bool imx_ac97; bool use_dma; struct clk *clk; struct snd_dmaengine_dai_dma_data dma_params_tx; @@ -320,6 +321,124 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) return ret; }

+static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private) +{ + struct ccsr_ssi __iomem *ssi = ssi_private->ssi; + u8 i2s_mode; + u8 wm; + int synchronous = ssi_private->cpu_dai_drv.symmetric_rates; + + if (ssi_private->imx_ac97) + i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET; + else + i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE; + + /* + * Section 16.5 of the MPC8610 reference manual says that the SSI needs + * to be disabled before updating the registers we set here. + */ + write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); + + /* + * Program the SSI into I2S Slave Non-Network Synchronous mode. Also + * enable the transmit and receive FIFO. + * + * FIXME: Little-endian samples require a different shift dir + */ + write_ssi_mask(&ssi->scr, + CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, + CCSR_SSI_SCR_TFR_CLK_DIS | + i2s_mode | + (synchronous ? CCSR_SSI_SCR_SYN : 0)); + + write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | + CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | + CCSR_SSI_STCR_TSCKP, &ssi->stcr); + + write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | + CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | + CCSR_SSI_SRCR_RSCKP, &ssi->srcr); + /* + * The DC and PM bits are only used if the SSI is the clock master. + */ + + /* + * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't + * use FIFO 1. We program the transmit water to signal a DMA transfer + * if there are only two (or fewer) elements left in the FIFO. Two + * elements equals one frame (left channel, right channel). This value, + * however, depends on the depth of the transmit buffer. + * + * We set the watermark on the same level as the DMA burstsize. For + * fiq it is probably better to use the biggest possible watermark + * size. + */ + if (ssi_private->use_dma) + wm = ssi_private->fifo_depth - 2; + else + wm = ssi_private->fifo_depth; + + write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | + CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), + &ssi->sfcsr); + + /* + * For non-ac97 setups, we keep the SSI disabled because if we enable + * it, then the DMA controller will start. It's not supposed to start + * until the SCR.TE (or SCR.RE) bit is set, but it does anyway. The DMA + * controller will transfer one "BWC" of data (i.e. the amount of data + * that the MR.BWC bits are set to). The reason this is bad is because + * at this point, the PCM driver has not finished initializing the DMA + * controller. + */ + + + /* + * For ac97 interrupts are enabled with the startup of the substream + * because it is also running without an active substream. Normally SSI + * is only enabled when there is a substream. + */ + if (!ssi_private->imx_ac97) { + /* Enable the interrupts and DMA requests */ + if (ssi_private->use_dma) + write_ssi(SIER_FLAGS, &ssi->sier); + else + write_ssi(CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN | + CCSR_SSI_SIER_RIE | + CCSR_SSI_SIER_RFF0_EN, &ssi->sier); + } else { + /* + * Setup the clock control register + */ + write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), + &ssi->stccr); + write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), + &ssi->srccr); + + /* + * Enable AC97 mode and startup the SSI + */ + write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, + &ssi->sacnt); + write_ssi(0xff, &ssi->saccdis); + write_ssi(0x300, &ssi->saccen); + + /* + * Enable SSI + */ + write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); + write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); + + /* + * Enable Transmit and Receive + */ + write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); + } + + return 0; +} + + /** * fsl_ssi_startup: create a new substream * @@ -341,75 +460,14 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream, * and initialize the SSI registers. */ if (!ssi_private->first_stream) { - struct ccsr_ssi __iomem *ssi = ssi_private->ssi; - ssi_private->first_stream = substream;

/* - * Section 16.5 of the MPC8610 reference manual says that the - * SSI needs to be disabled before updating the registers we set - * here. - */ - write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); - - /* - * Program the SSI into I2S Slave Non-Network Synchronous mode. - * Also enable the transmit and receive FIFO. - * - * FIXME: Little-endian samples require a different shift dir - */ - write_ssi_mask(&ssi->scr, - CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, - CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE - | (synchronous ? CCSR_SSI_SCR_SYN : 0)); - - write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | - CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | - CCSR_SSI_STCR_TSCKP, &ssi->stcr); - - write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | - CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | - CCSR_SSI_SRCR_RSCKP, &ssi->srcr); - - /* - * The DC and PM bits are only used if the SSI is the clock - * master. - */ - - /* Enable the interrupts and DMA requests */ - if (ssi_private->use_dma) - write_ssi(SIER_FLAGS, &ssi->sier); - else - write_ssi(CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN | - CCSR_SSI_SIER_RIE | - CCSR_SSI_SIER_RFF0_EN, &ssi->sier); - - /* - * Set the watermark for transmit FIFI 0 and receive FIFO 0. We - * don't use FIFO 1. We program the transmit water to signal a - * DMA transfer if there are only two (or fewer) elements left - * in the FIFO. Two elements equals one frame (left channel, - * right channel). This value, however, depends on the depth of - * the transmit buffer. - * - * We program the receive FIFO to notify us if at least two - * elements (one frame) have been written to the FIFO. We could - * make this value larger (and maybe we should), but this way - * data will be written to memory as soon as it's available. - */ - write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) | - CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2), - &ssi->sfcsr); - - /* - * We keep the SSI disabled because if we enable it, then the - * DMA controller will start. It's not supposed to start until - * the SCR.TE (or SCR.RE) bit is set, but it does anyway. The - * DMA controller will transfer one "BWC" of data (i.e. the - * amount of data that the MR.BWC bits are set to). The reason - * this is bad is because at this point, the PCM driver has not - * finished initializing the DMA controller. + * fsl_ssi_setup was already called by ac97_init earlier if + * the driver is in ac97 mode. */ + if (!ssi_private->imx_ac97) + fsl_ssi_setup(ssi_private); } else { if (synchronous) { struct snd_pcm_runtime *first_runtime = @@ -564,8 +622,9 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,

/* * If this is the last active substream, disable the SSI. + * If AC97 is active, we don't want to disable SSI. */ - if (!ssi_private->first_stream) { + if (!ssi_private->first_stream && !ssi_private->imx_ac97) { struct ccsr_ssi __iomem *ssi = ssi_private->ssi;

write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); @@ -614,6 +673,130 @@ static const struct snd_soc_component_driver fsl_ssi_component = { .name = "fsl-ssi", };

+/** + * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit. + * + * This function is called by ALSA to start, stop, pause, and resume the + * transfer of data. + */ +static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata( + rtd->cpu_dai); + struct ccsr_ssi __iomem *ssi = ssi_private->ssi; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE | + CCSR_SSI_SIER_TFE0_EN); + else + write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE | + CCSR_SSI_SIER_RFF0_EN); + break; + + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE | + CCSR_SSI_SIER_TFE0_EN, 0); + else + write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE | + CCSR_SSI_SIER_RFF0_EN, 0); + break; + + default: + return -EINVAL; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); + else + write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); + + return 0; +} + +static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = { + .startup = fsl_ssi_startup, + .shutdown = fsl_ssi_shutdown, + .trigger = fsl_ssi_ac97_trigger, +}; + +static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { + .ac97_control = 1, + .playback = { + .stream_name = "AC97 Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .capture = { + .stream_name = "AC97 Capture", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &fsl_ssi_ac97_dai_ops, +}; + + +static struct fsl_ssi_private *fsl_ac97_data; + +static void fsl_ssi_ac97_init(void) +{ + fsl_ssi_setup(fsl_ac97_data); +} + +void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, + unsigned short val) +{ + struct ccsr_ssi *ssi = fsl_ac97_data->ssi; + unsigned int lreg; + unsigned int lval; + + if (reg > 0x7f) + return; + + + lreg = reg << 12; + write_ssi(lreg, &ssi->sacadd); + + lval = val << 4; + write_ssi(lval , &ssi->sacdat); + + write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, + CCSR_SSI_SACNT_WR); + udelay(100); +} +EXPORT_SYMBOL(fsl_ssi_ac97_write); + +unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, + unsigned short reg) +{ + struct ccsr_ssi *ssi = fsl_ac97_data->ssi; + + unsigned short val = -1; + unsigned int lreg; + + lreg = (reg & 0x7f) << 12; + write_ssi(lreg, &ssi->sacadd); + write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, + CCSR_SSI_SACNT_RD); + + udelay(100); + + val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; + + return val; +} +EXPORT_SYMBOL(fsl_ssi_ac97_read); + /* * FIXME: As soon as all boards using imx-ssi AC97 mode are able to use * fsl-ssi, soc_ac97_ops can be used exclusively in this driver without copying @@ -622,6 +805,23 @@ static const struct snd_soc_component_driver fsl_ssi_component = { struct snd_ac97_bus_ops soc_ac97_ops; EXPORT_SYMBOL_GPL(soc_ac97_ops);

+static struct snd_ac97_bus_ops fsl_ssi_soc_ac97_ops = { + .read = fsl_ssi_ac97_read, + .write = fsl_ssi_ac97_write, +}; + +/* + * ac97 reset and warm_reset functions are setup by board specific drivers. + * ssi does not have any knowledge about the used board. + */ +void fsl_ssi_ac97_set_reset(void (*ac97_reset)(struct snd_ac97 *ac97), + void (*ac97_warm_reset)(struct snd_ac97 *ac97)) +{ + soc_ac97_ops.reset = ac97_reset; + soc_ac97_ops.warm_reset = ac97_warm_reset; +} +EXPORT_SYMBOL(fsl_ssi_ac97_set_reset); + /* Show the statistics of a flag only if its interrupt is enabled. The * compiler will optimze this code to a no-op if the interrupt is not * enabled. @@ -698,6 +898,7 @@ static int fsl_ssi_probe(struct platform_device *pdev) struct resource res; char name[64]; bool shared; + bool ac97 = false;

/* SSIs that are not connected on the board should have a * status = "disabled" @@ -708,7 +909,13 @@ static int fsl_ssi_probe(struct platform_device *pdev)

/* We only support the SSI in "I2S Slave" mode */ sprop = of_get_property(np, "fsl,mode", NULL); - if (!sprop || strcmp(sprop, "i2s-slave")) { + if (!sprop) { + dev_err(&pdev->dev, "fsl,mode property is necessary\n"); + return -EINVAL; + } + if (!strcmp(sprop, "ac97-slave")) { + ac97 = true; + } else if (strcmp(sprop, "i2s-slave")) { dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop); return -ENODEV; } @@ -724,13 +931,23 @@ static int fsl_ssi_probe(struct platform_device *pdev)

strcpy(ssi_private->name, p);

- /* Initialize this copy of the CPU DAI driver structure */ - memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, - sizeof(fsl_ssi_dai_template)); - ssi_private->cpu_dai_drv.name = ssi_private->name; - ssi_private->use_dma = !of_property_read_bool(np, "fsl,imx-fiq");

+ if (ac97) { + memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, + sizeof(fsl_ssi_ac97_dai)); + memcpy(&soc_ac97_ops, &fsl_ssi_soc_ac97_ops, + sizeof(soc_ac97_ops)); + + fsl_ac97_data = ssi_private; + ssi_private->imx_ac97 = true; + } else { + /* Initialize this copy of the CPU DAI driver structure */ + memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, + sizeof(fsl_ssi_dai_template)); + } + ssi_private->cpu_dai_drv.name = ssi_private->name; + /* Get the addresses and IRQ */ ret = of_address_to_resource(np, 0, &res); if (ret) { @@ -910,6 +1127,9 @@ static int fsl_ssi_probe(struct platform_device *pdev) }

done: + if (ssi_private->imx_ac97) + fsl_ssi_ac97_init(); + return 0;

error_dai: diff --git a/sound/soc/fsl/fsl_ssi.h b/sound/soc/fsl/fsl_ssi.h index e6b9a69..87004ae 100644 --- a/sound/soc/fsl/fsl_ssi.h +++ b/sound/soc/fsl/fsl_ssi.h @@ -206,3 +206,10 @@ struct ccsr_ssi {

#endif

+ +void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, + unsigned short val); +unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, + unsigned short reg); +void fsl_ssi_ac97_set_reset(void (*ac97_reset)(struct snd_ac97 *ac97), + void (*ac97_warm_reset)(struct snd_ac97 *ac97));

Add devicetree support for phycore-ac97 driver in a seperated driver for DT loading. The seperation reduces the confusion with the old style initialization of this driver via late_initcall. Also this driver is using fsl-ssi instead of imx-ssi.

platform_of_node and cpu_of_node are set according to the fsl,audmux phandle.

This patch adds handling of ac97 reset functions according to fsl ac97 support. They are setup from here to avoid board specific code in the generic fsl-ssi driver.

Signed-off-by: Markus Pargmann mpa@pengutronix.de Tested-by: Shawn Guo shawn.guo@linaro.org ---

Notes: Changes in v9: - Fix blank line at end of file.

Changes in v8: - Seperate DT capable driver from old phycore-ac97. This eliminates a lot of build issues and makes the driver easier to read. - fsl_ssi may not be built as module if used with ac97 because it defines the soc_ac97_ops symbol which is used by the soc ac97 core and codec drivers. So phycore-ac97-dt actually does not support building as module anymore. The same issue was existing with imx-ssi and phycore-ac97, which is also fixed now in this patch.

Changes in v7: - Declare empty ac97 reset functions static. - Replace complicated machine compatible comparison with of_machine_is_compatible - Missing snd_soc_unregister_card in imx_phycore_ac97_remove - Rename driver

Changes in v6: - phycore-ac97 now manages the ac97 reset functions of the boards using this combination of ssi-codec. - Removed preprocessor ifs for DT, non-DT distinction. pcm043 is now non-DT only and pca100 DT only.

Changes in v4: - New property phytec,audmux to check which audmux setup should be executed. Checking for fsl,imx21-audmux and fsl,imx31-audmux.

Changes in v3: - Add some more information in the commit message.

Changes in v2: - Simplify the driver, by combining audmux port configurations. The audmux driver actually knows on which platform he is running and will return the appropriate error code if we use functions for another platform. So we don't need to have the knowledge about it in phycore-ac97 and can try both functions. This removes the need of different compatibilities and renames it to phycore-ac97. - Use a phandle for the cpu_dai link. - Add devicetree binding documentation. - Rename binding to phytec,phycore-ac97 and fsl,ssi to phytec,ssi

.../bindings/sound/phytec,phycore-ac97.txt | 14 ++ sound/soc/fsl/Kconfig | 16 +- sound/soc/fsl/Makefile | 2 + sound/soc/fsl/phycore-ac97-dt.c | 242 +++++++++++++++++++++ sound/soc/fsl/phycore-ac97.c | 13 +- 5 files changed, 273 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt create mode 100644 sound/soc/fsl/phycore-ac97-dt.c

diff --git a/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt new file mode 100644 index 0000000..41201ff --- /dev/null +++ b/Documentation/devicetree/bindings/sound/phytec,phycore-ac97.txt @@ -0,0 +1,14 @@ +Phytec phycore AC97 + +Required properties: +- compatible: "phytec,phycore-ac97" +- phytec,ssi: A phandle to the ssi device that is connected to ac97. +- phytec,audmux: A phandle to the audmux device. + +Example: + +sound { + compatible = "phytec,phycore-ac97"; + phytec,ssi = <&ssi1>; + phytec,audmux = <&audmux>; +}; diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index 74ef96e..dafffd1 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -143,8 +143,8 @@ config SND_SOC_MX27VIS_AIC32X4 board with TLV320AIC32X4 codec.

config SND_SOC_PHYCORE_AC97 - tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards" - depends on MACH_PCM043 || MACH_PCA100 + bool "SoC Audio support for Phytec phyCORE boards" + depends on MACH_PCM043 select SND_SOC_AC97_BUS select SND_SOC_WM9712 select SND_SOC_IMX_PCM_FIQ @@ -154,6 +154,18 @@ config SND_SOC_PHYCORE_AC97 Say Y if you want to add support for SoC audio on Phytec phyCORE and phyCARD boards in AC97 mode

+config SND_SOC_PHYCORE_AC97_DT + bool "SoC Audio support for Phytec phyCORE (and phyCARD) boards (devicetree only)" + depends on MACH_PCA100 || MACH_PCM043 + select SND_SOC_AC97_BUS + select SND_SOC_WM9712 + select SND_SOC_IMX_PCM_FIQ + select SND_SOC_IMX_AUDMUX + select SND_SOC_FSL_SSI + help + Say Y if you want to add support for SoC audio on Phytec phyCORE + and phyCARD boards in AC97 mode when using devicetree. + config SND_SOC_EUKREA_TLV320 tristate "Eukrea TLV320" depends on MACH_EUKREA_MBIMX27_BASEBOARD \ diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile index 91883f8..be9b198 100644 --- a/sound/soc/fsl/Makefile +++ b/sound/soc/fsl/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_SND_SOC_IMX_PCM_DMA) += imx-pcm-dma.o # i.MX Machine Support snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o snd-soc-phycore-ac97-objs := phycore-ac97.o +snd-soc-phycore-ac97-dt-objs := phycore-ac97-dt.o snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o snd-soc-wm1133-ev1-objs := wm1133-ev1.o snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o @@ -46,6 +47,7 @@ snd-soc-imx-mc13783-objs := imx-mc13783.o

obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o +obj-$(CONFIG_SND_SOC_PHYCORE_AC97_DT) += snd-soc-phycore-ac97-dt.o obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o diff --git a/sound/soc/fsl/phycore-ac97-dt.c b/sound/soc/fsl/phycore-ac97-dt.c new file mode 100644 index 0000000..f494b30 --- /dev/null +++ b/sound/soc/fsl/phycore-ac97-dt.c @@ -0,0 +1,242 @@ +/* + * phycore-ac97-dt.c -- SoC audio for imx_phycore in AC97 mode + * + * Copyright 2009 Sascha Hauer, Pengutronix s.hauer@pengutronix.de + * Copyright 2013 Markus Pargmann, Pengutronix mpa@pengutronix.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <linux/device.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/of.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/soc.h> + +#include "imx-audmux.h" +#include "fsl_ssi.h" + +#define DRV_NAME "phycore-ac97-dt-driver" + +static struct snd_soc_card imx_phycore; +static struct device_node *phycore_dai_cpu_node; +static void (*phycore_ac97_reset) (struct snd_ac97 *ac97); +static void (*phycore_ac97_warm_reset)(struct snd_ac97 *ac97); + +static struct snd_soc_ops imx_phycore_hifi_ops = { +}; + +static struct snd_soc_dai_link imx_phycore_dai_ac97[] = { + { + .name = "HiFi", + .stream_name = "HiFi", + .codec_dai_name = "wm9712-hifi", + .codec_name = "wm9712-codec", + .ops = &imx_phycore_hifi_ops, + }, +}; + +static struct snd_soc_card imx_phycore = { + .name = "PhyCORE-ac97-audio", + .owner = THIS_MODULE, + .dai_link = imx_phycore_dai_ac97, + .num_links = ARRAY_SIZE(imx_phycore_dai_ac97), +}; + +static struct platform_device *imx_phycore_snd_device; + +static void phycore_ac97_imx21_audmux(void) +{ + imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0, + IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */ + IMX_AUDMUX_V1_PCR_TFCSEL(3) | + IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */ + IMX_AUDMUX_V1_PCR_RXDSEL(3)); + imx_audmux_v1_configure_port(3, + IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */ + IMX_AUDMUX_V1_PCR_TFCSEL(0) | + IMX_AUDMUX_V1_PCR_TFSDIR | + IMX_AUDMUX_V1_PCR_RXDSEL(0)); +} + +static void phycore_ac97_imx31_audmux(void) +{ + imx_audmux_v2_configure_port(3, + IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ + IMX_AUDMUX_V2_PTCR_TFSEL(0) | + IMX_AUDMUX_V2_PTCR_TFSDIR, + IMX_AUDMUX_V2_PDCR_RXDSEL(0)); + imx_audmux_v2_configure_port(0, + IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ + IMX_AUDMUX_V2_PTCR_TCSEL(3) | + IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */ + IMX_AUDMUX_V2_PDCR_RXDSEL(3)); +} + +static const struct of_device_id imx_phycore_ac97_of_dev_id[] = { + { + .compatible = "phytec,phycore-ac97", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, imx_phycore_ac97_of_dev_id); + + +/* + * Pointer to AC97 reset functions for specific boards + */ +#if IS_ENABLED(CONFIG_MACH_PCA100) +extern void pca100_ac97_cold_reset(struct snd_ac97 *ac97); +extern void pca100_ac97_warm_reset(struct snd_ac97 *ac97); +#else +static void pca100_ac97_cold_reset(struct snd_ac97 *ac97) { } +static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) { } +#endif + +#if IS_ENABLED(CONFIG_MACH_PCM043) +extern void pcm043_ac97_cold_reset(struct snd_ac97 *ac97); +extern void pcm043_ac97_warm_reset(struct snd_ac97 *ac97); +#else +static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) { } +static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { } +#endif + +static void phycore_soc_ac97_reset(struct snd_ac97 *ac97) +{ + if (phycore_ac97_reset) + phycore_ac97_reset(ac97); + /* First read sometimes fails, do a dummy read */ + fsl_ssi_ac97_read(ac97, 0); +} + +static void phycore_soc_ac97_warm_reset(struct snd_ac97 *ac97) +{ + if (phycore_ac97_warm_reset) + phycore_ac97_warm_reset(ac97); + + /* First read sometimes fails, do a dummy read */ + fsl_ssi_ac97_read(ac97, 0); +} + +static int phycore_ac97_setup_devices(struct platform_device *pdev) +{ + int ret; + + imx_phycore_snd_device = platform_device_alloc("wm9712-codec", -1); + if (!imx_phycore_snd_device) + return -ENOMEM; + + ret = platform_device_add(imx_phycore_snd_device); + if (ret) { + dev_err(&pdev->dev, "ASoC: Platform device allocation failed\n"); + goto fail1; + } + + ret = snd_soc_register_card(&imx_phycore); + if (ret) { + dev_err(&pdev->dev, "ASoC: soc card registration failed\n"); + goto fail2; + } + return 0; + +fail2: + platform_device_del(imx_phycore_snd_device); +fail1: + platform_device_put(imx_phycore_snd_device); + return ret; +} + +static int imx_phycore_ac97_probe(struct platform_device *pdev) +{ + int ret; + struct device_node *ssi_np; + struct device_node *audmux_np; + + imx_phycore.dev = &pdev->dev; + + audmux_np = of_parse_phandle(pdev->dev.of_node, "phytec,audmux", 0); + if (!audmux_np) { + dev_err(&pdev->dev, "Failed to parse phytec,audmux phandle\n"); + return -EINVAL; + } + + if (of_device_is_compatible(audmux_np, "fsl,imx21-audmux")) { + phycore_ac97_imx21_audmux(); + } else if (of_device_is_compatible(audmux_np, "fsl,imx31-audmux")) { + phycore_ac97_imx31_audmux(); + } else { + dev_err(&pdev->dev, "Unknown audmux, failed to setup audmux\n"); + of_node_put(audmux_np); + return -EINVAL; + } + of_node_put(audmux_np); + + ssi_np = of_parse_phandle(pdev->dev.of_node, "phytec,ssi", 0); + if (!ssi_np) { + dev_err(&pdev->dev, "No valid ssi phandle found\n"); + return -EINVAL; + } + + imx_phycore_dai_ac97[0].cpu_of_node = ssi_np; + imx_phycore_dai_ac97[0].platform_of_node = ssi_np; + phycore_dai_cpu_node = ssi_np; + + if (of_machine_is_compatible("phytec,imx27-pca100")) { + phycore_ac97_reset = pca100_ac97_cold_reset; + phycore_ac97_warm_reset = pca100_ac97_warm_reset; + } else if (of_machine_is_compatible("phytec,imx35-pcm043")) { + phycore_ac97_reset = pcm043_ac97_cold_reset; + phycore_ac97_warm_reset = pcm043_ac97_warm_reset; + } else { + dev_err(&pdev->dev, "Failed to set AC97 reset functions, unknown board.\n"); + return -EINVAL; + } + + fsl_ssi_ac97_set_reset(phycore_soc_ac97_reset, + phycore_soc_ac97_warm_reset); + + ret = phycore_ac97_setup_devices(pdev); + if (ret) + of_node_put(phycore_dai_cpu_node); + + return ret; +} + +static int imx_phycore_ac97_remove(struct platform_device *pdev) +{ + of_node_put(phycore_dai_cpu_node); + phycore_dai_cpu_node = NULL; + + snd_soc_unregister_card(&imx_phycore); + + platform_device_unregister(imx_phycore_snd_device); + + phycore_ac97_reset = NULL; + phycore_ac97_warm_reset = NULL; + + return 0; +} + +static struct platform_driver imx_phycore_ac97_driver = { + .probe = imx_phycore_ac97_probe, + .remove = imx_phycore_ac97_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = imx_phycore_ac97_of_dev_id, + }, +}; + +module_platform_driver(imx_phycore_ac97_driver); + +MODULE_AUTHOR("Sascha Hauer s.hauer@pengutronix.de"); +MODULE_AUTHOR("Markus Pargmann mpa@pengutronix.de"); +MODULE_DESCRIPTION(DRV_NAME ": PhyCORE ALSA SoC DT driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/fsl/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c index ae403c2..4126edc 100644 --- a/sound/soc/fsl/phycore-ac97.c +++ b/sound/soc/fsl/phycore-ac97.c @@ -52,18 +52,7 @@ static int __init imx_phycore_init(void) { int ret;

- if (machine_is_pca100()) { - imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0, - IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */ - IMX_AUDMUX_V1_PCR_TFCSEL(3) | - IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */ - IMX_AUDMUX_V1_PCR_RXDSEL(3)); - imx_audmux_v1_configure_port(3, - IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */ - IMX_AUDMUX_V1_PCR_TFCSEL(0) | - IMX_AUDMUX_V1_PCR_TFSDIR | - IMX_AUDMUX_V1_PCR_RXDSEL(0)); - } else if (machine_is_pcm043()) { + if (machine_is_pcm043()) { imx_audmux_v2_configure_port(3, IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ IMX_AUDMUX_V2_PTCR_TFSEL(0) |

Update the fsl-ssi bindings. DMA is no required property anymore and uses the generic DMA bindings. imx-fiq is a new alternative to DMA

Signed-off-by: Markus Pargmann mpa@pengutronix.de Tested-by: Shawn Guo shawn.guo@linaro.org ---

Notes: Changes in v9: - Remove space before tab

Changes in v4: - Add a comment about hardware bugs for imx-pcm-fiq

Changes in v3: - In previous versions, I removed fsl,playback-dma and capture-dma. But they are still in use by fsl_dma.c, so I added them again.

Documentation/devicetree/bindings/sound/fsl,ssi.txt | 10 ++++++++++ 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt index 5ff76c9..cae80d2 100644 --- a/Documentation/devicetree/bindings/sound/fsl,ssi.txt +++ b/Documentation/devicetree/bindings/sound/fsl,ssi.txt @@ -43,10 +43,20 @@ Required properties: together. This would still allow different sample sizes, but not different sample rates.

+Note that either dmas, dma-names or fsl,imx-fiq are required. + Optional properties: - codec-handle: Phandle to a 'codec' node that defines an audio codec connected to this SSI. This node is typically a child of an I2C or other control node. +- dmas: Generic dma devicetree binding as described in + Documentation/devicetree/bindings/dma/dma.txt. +- dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq + is not defined. +- fsl,imx-fiq: Bool property. Use imx-pcm-fiq instead of imx-pcm-dma. + Only necessary for some boards with incompatible + codec. imx-pcm-fiq will manually filter some data from + the codec. It is a workaround for a hardware bug.

Child 'codec' node required properties: - compatible: Compatible list, contains the name of the codec