Re: [alsa-devel] ASoC: pxa2xx-i2s
On Wed, Jan 21, 2009 at 10:46:17AM -0600, Brian G Rhodes wrote:
Mark Brown wrote:
What is the clock master in your system?
The master is the i2s controller sysclk. The dac2x is in slave mode. Though the i2s controller isn't directly supplying the bit clock to the codec in this case. We're using the PLL on the dac2x.
Just to confirm, the codec is the clock master on the I2S bus itself?
Mark Brown wrote:
On Wed, Jan 21, 2009 at 10:46:17AM -0600, Brian G Rhodes wrote:
Mark Brown wrote:
What is the clock master in your system?
The master is the i2s controller sysclk. The dac2x is in slave mode. Though the i2s controller isn't directly supplying the bit clock to the codec in this case. We're using the PLL on the dac2x.
Just to confirm, the codec is the clock master on the I2S bus itself?
No, the 270 is the clock master on the I2S bus. The codec is sourcing the clock input using the PLL. I apologize for being unclear.
On Wed, Jan 21, 2009 at 02:13:12PM -0600, Brian Rhodes wrote:
No, the 270 is the clock master on the I2S bus. The codec is sourcing the clock input using the PLL. I apologize for being unclear.
I think it's me that's not being clear, sorry - I'm trying to find out is if the LRCLK and BCLK signals on the I2S bus itself are being driven by the codec or by the I2S controller. If the codec driver is the clock master then your earlier speculation that your problems with the I2S controller may be due to some interaction with the codec driver are more likely to be true.
Mark Brown wrote:
On Wed, Jan 21, 2009 at 02:13:12PM -0600, Brian Rhodes wrote:
No, the 270 is the clock master on the I2S bus. The codec is sourcing the clock input using the PLL. I apologize for being unclear.
I think it's me that's not being clear, sorry - I'm trying to find out is if the LRCLK and BCLK signals on the I2S bus itself are being driven by the codec or by the I2S controller. If the codec driver is the clock master then your earlier speculation that your problems with the I2S controller may be due to some interaction with the codec driver are more likely to be true.
LCRK and BCLK are configured as inputs. The Codec is not the bus master.
Mark Brown wrote:
On Wed, Jan 21, 2009 at 02:13:12PM -0600, Brian Rhodes wrote:
No, the 270 is the clock master on the I2S bus. The codec is sourcing the clock input using the PLL. I apologize for being unclear.
I think it's me that's not being clear, sorry - I'm trying to find out is if the LRCLK and BCLK signals on the I2S bus itself are being driven by the codec or by the I2S controller. If the codec driver is the clock master then your earlier speculation that your problems with the I2S controller may be due to some interaction with the codec driver are more likely to be true.
I'm curious if you think this problem may be arising from the toggling of the direction of BCLK on the PXA while the I2S clock is enabled. I'm sure there are people who have a reason for switching the bit clock master, but I'm thinking that this should not be explicitly done if it is not changing.
On Fri, Jan 23, 2009 at 10:50:39AM -0600, Brian Rhodes wrote:
I'm curious if you think this problem may be arising from the toggling of the direction of BCLK on the PXA while the I2S clock is enabled. I'm sure there are people who have a reason for switching the bit clock master, but I'm thinking that this should not be explicitly done if it is not changing.
Looking at the way the clock is enabled it looks like the hardware requires the clock to be enabled to write to the registers, though again I've not actually looked at the reference manual to check so this is idle speculation.
Avoiding changing the register settings if they are already correct does seem like a reasonable thing to try, though. The ordering used when configuring may be worth looking at too.
Maybe you still have some device at hand for testing.
http://mailman.alsa-project.org/pipermail/alsa-devel/2009-May/017038.html
participants (3)
-
Brian Rhodes -
Karl Beldan -
Mark Brown