From: Weidong Wang wangweidong.a@awinic.com

The Awinic AW883XX is an I2S/TDM input, high efficiency digital Smart K audio amplifier with an integrated 10.25V smart boost convert

Signed-off-by: Nick Li liweilei@awinic.com Signed-off-by: Bruce zhao zhaolei@awinic.com Signed-off-by: Weidong Wang wangweidong.a@awinic.com --- sound/soc/codecs/aw883xx/aw883xx.c | 909 +++++++++++++++++++++++++++++ sound/soc/codecs/aw883xx/aw883xx.h | 81 +++ 2 files changed, 990 insertions(+) create mode 100644 sound/soc/codecs/aw883xx/aw883xx.c create mode 100644 sound/soc/codecs/aw883xx/aw883xx.h

diff --git a/sound/soc/codecs/aw883xx/aw883xx.c b/sound/soc/codecs/aw883xx/aw883xx.c new file mode 100644 index 000000000000..f82e6d8c71a7 --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx.c @@ -0,0 +1,909 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/debugfs.h> +#include <linux/firmware.h> +#include <linux/hrtimer.h> +#include <linux/i2c.h> +#include <linux/input.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/regmap.h> +#include <linux/syscalls.h> +#include <linux/timer.h> +#include <linux/uaccess.h> +#include <linux/version.h> +#include <linux/vmalloc.h> +#include <linux/workqueue.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/tlv.h> +#include "aw883xx_pid_2049_reg.h" +#include "aw883xx.h" +#include "aw883xx_bin_parse.h" +#include "aw883xx_device.h" + +static const struct regmap_config aw883xx_remap_config = { + .val_bits = 16, + .reg_bits = 8, + .max_register = AW_PID_2049_REG_MAX - 1, +}; + +/* + * aw883xx dsp write/read + */ +static int aw883xx_dsp_write_16bit(struct aw883xx *aw883xx, + unsigned short dsp_addr, unsigned int dsp_data) +{ + int ret; + struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc; + + ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, (u16)dsp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + return 0; +} + +static int aw883xx_dsp_write_32bit(struct aw883xx *aw883xx, + unsigned short dsp_addr, unsigned int dsp_data) +{ + int ret; + u16 temp_data = 0; + struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc; + + ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + temp_data = dsp_data & AW_DSP_16_DATA_MASK; + ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + temp_data = dsp_data >> 16; + ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret); + return ret; + } + + return 0; +} + +/* + * aw883xx clear dsp chip select state + */ +static void aw883xx_clear_dsp_sel_st(struct aw883xx *aw883xx) +{ + unsigned int reg_value; + u8 reg = aw883xx->aw_pa->soft_rst.reg; + + regmap_read(aw883xx->regmap, reg, &reg_value); +} + +int aw883xx_dsp_write(struct aw883xx *aw883xx, + unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type) +{ + int ret = -1; + + mutex_lock(&aw883xx->dsp_lock); + switch (data_type) { + case AW_DSP_16_DATA: + ret = aw883xx_dsp_write_16bit(aw883xx, dsp_addr, dsp_data); + if (ret < 0) + dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 16 bit dsp_data[%04x] failed", + (u32)dsp_addr, dsp_data); + break; + case AW_DSP_32_DATA: + ret = aw883xx_dsp_write_32bit(aw883xx, dsp_addr, dsp_data); + if (ret < 0) + dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 32 bit dsp_data[%08x] failed", + (u32)dsp_addr, dsp_data); + break; + default: + dev_err(aw883xx->dev, "data type[%d] unsupported", data_type); + ret = -EINVAL; + break; + } + + aw883xx_clear_dsp_sel_st(aw883xx); + mutex_unlock(&aw883xx->dsp_lock); + return ret; +} + +static int aw883xx_dsp_read_16bit(struct aw883xx *aw883xx, + unsigned short dsp_addr, unsigned int *dsp_data) +{ + int ret; + unsigned int temp_data = 0; + struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc; + + ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c write error, ret=%d", ret); + return ret; + } + + ret = regmap_read(aw883xx->regmap, desc->dsp_mdat_reg, &temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c write error, ret=%d", ret); + return ret; + } + + *dsp_data = temp_data; + + return 0; +} + +static int aw883xx_dsp_read_32bit(struct aw883xx *aw883xx, + unsigned short dsp_addr, unsigned int *dsp_data) +{ + int ret; + unsigned int temp_data = 0; + struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc; + + /*write dsp addr*/ + ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c write error, ret=%d", ret); + return ret; + } + + /*get Low 16 bit data*/ + ret = regmap_read(aw883xx->regmap, desc->dsp_mdat_reg, &temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c read error, ret=%d", ret); + return ret; + } + + *dsp_data = temp_data; + + /*get high 16 bit data*/ + ret = regmap_read(aw883xx->regmap, desc->dsp_mdat_reg, &temp_data); + if (ret < 0) { + dev_err(aw883xx->dev, "i2c read error, ret=%d", ret); + return ret; + } + *dsp_data |= (temp_data << 16); + + return 0; +} + +int aw883xx_dsp_read(struct aw883xx *aw883xx, + unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type) +{ + int ret = -1; + + mutex_lock(&aw883xx->dsp_lock); + switch (data_type) { + case AW_DSP_16_DATA: + ret = aw883xx_dsp_read_16bit(aw883xx, dsp_addr, dsp_data); + if (ret < 0) + dev_err(aw883xx->dev, "read dsp_addr[0x%04x] 16 bit dsp_data[%04x] failed", + (u32)dsp_addr, *dsp_data); + break; + case AW_DSP_32_DATA: + ret = aw883xx_dsp_read_32bit(aw883xx, dsp_addr, dsp_data); + if (ret < 0) + dev_err(aw883xx->dev, "read dsp_addr[0x%04x] 32 bit dsp_data[%08x] failed", + (u32)dsp_addr, *dsp_data); + break; + default: + dev_err(aw883xx->dev, "data type[%d] unsupported", data_type); + ret = -EINVAL; + break; + } + + aw883xx_clear_dsp_sel_st(aw883xx); + mutex_unlock(&aw883xx->dsp_lock); + return ret; +} + +static void aw883xx_start_pa(struct aw883xx *aw883xx) +{ + int ret, i; + + if (!aw883xx->allow_pw) { + dev_info(aw883xx->dev, "%s:dev can not allow power", __func__); + return; + } + + if (aw883xx->pstream == AW883XX_STREAM_CLOSE) { + dev_info(aw883xx->dev, "%s:pstream is close", __func__); + return; + } + + for (i = 0; i < AW_START_RETRIES; i++) { + ret = aw883xx_device_start(aw883xx->aw_pa); + if (ret) { + dev_err(aw883xx->dev, "aw883xx device start failed. retry = %d", i); + ret = aw883xx_dev_fw_update(aw883xx->aw_pa, AW_DSP_FW_UPDATE_ON, true); + if (ret < 0) { + dev_err(aw883xx->dev, "fw update failed"); + continue; + } + } else { + dev_info(aw883xx->dev, "start success\n"); + break; + } + } +} + +static void aw883xx_startup_work(struct work_struct *work) +{ + struct aw883xx *aw883xx = + container_of(work, struct aw883xx, start_work.work); + + mutex_lock(&aw883xx->lock); + aw883xx_start_pa(aw883xx); + mutex_unlock(&aw883xx->lock); +} + +static void aw883xx_start(struct aw883xx *aw883xx, bool sync_start) +{ + int ret; + int i; + + if (aw883xx->aw_pa->fw_status != AW_DEV_FW_OK) + return; + + if (!aw883xx->allow_pw) { + dev_info(aw883xx->dev, "%s:dev can not allow power", __func__); + return; + } + + if (aw883xx->aw_pa->status == AW_DEV_PW_ON) + return; + + for (i = 0; i < AW_START_RETRIES; i++) { + ret = aw883xx_dev_fw_update(aw883xx->aw_pa, AW_DSP_FW_UPDATE_OFF, + aw883xx->phase_sync); + if (ret < 0) { + dev_err(aw883xx->dev, "fw update failed. retry = %d", i); + continue; + } else { + /*firmware update success*/ + if (sync_start == AW_SYNC_START) + aw883xx_start_pa(aw883xx); + else + queue_delayed_work(aw883xx->work_queue, + &aw883xx->start_work, + AW_START_WORK_DELAY_MS); + return; + } + } +} + +/* + * Digital Audio Interface + */ +static int aw883xx_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *codec = dai->component; + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + + aw883xx->pstream = AW883XX_STREAM_OPEN; + + mutex_lock(&aw883xx->lock); + aw883xx_start(aw883xx, AW_ASYNC_START); + mutex_unlock(&aw883xx->lock); + + return 0; +} + +static void aw883xx_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *codec = dai->component; + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + + aw883xx->pstream = AW883XX_STREAM_CLOSE; + cancel_delayed_work_sync(&aw883xx->start_work); + mutex_lock(&aw883xx->lock); + aw883xx_device_stop(aw883xx->aw_pa); + mutex_unlock(&aw883xx->lock); + +} + +static const struct snd_soc_dai_ops aw883xx_dai_ops = { + .startup = aw883xx_startup, + .shutdown = aw883xx_shutdown, +}; + +static struct snd_soc_dai_driver aw883xx_dai[] = { + { + .name = "aw883xx-aif", + .id = 1, + .playback = { + .stream_name = "Speaker_Playback", + .channels_min = 1, + .channels_max = 2, + .rates = AW_RATES, + .formats = AW_FORMATS, + }, + .capture = { + .stream_name = "Speaker_Capture", + .channels_min = 1, + .channels_max = 2, + .rates = AW_RATES, + .formats = AW_FORMATS, + }, + .ops = &aw883xx_dai_ops, + }, +}; + +/* + * codec driver + */ +static int aw883xx_get_fade_in_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component); + struct aw_device *aw_dev = aw883xx->aw_pa; + + ucontrol->value.integer.value[0] = aw_dev->fade_in_time; + + return 0; + +} + +static int aw883xx_set_fade_in_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int time = 0; + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component); + struct aw_device *aw_dev = aw883xx->aw_pa; + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + time = ucontrol->value.integer.value[0]; + + if (time < mc->min || time > mc->max) + return 0; + + if (time != aw_dev->fade_in_time) { + aw_dev->fade_in_time = time; + return 1; + } + + return 0; +} + +static int aw883xx_get_fade_out_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component); + struct aw_device *aw_dev = aw883xx->aw_pa; + + ucontrol->value.integer.value[0] = aw_dev->fade_out_time; + + return 0; +} + +static int aw883xx_set_fade_out_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct aw_device *aw_dev = aw883xx->aw_pa; + unsigned int time = 0; + + time = ucontrol->value.integer.value[0]; + if (time < mc->min || time > mc->max) + return 0; + + if (time != aw_dev->fade_out_time) { + aw_dev->fade_out_time = time; + return 1; + } + + return 0; +} + +static int aw883xx_profile_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + int count; + char *name = NULL; + const char *prof_name = NULL; + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; + uinfo->count = 1; + + count = aw883xx_dev_get_profile_count(aw883xx->aw_pa); + if (count <= 0) { + uinfo->value.enumerated.items = 0; + return 0; + } + + uinfo->value.enumerated.items = count; + + if (uinfo->value.enumerated.item >= count) + uinfo->value.enumerated.item = count - 1; + + name = uinfo->value.enumerated.name; + count = uinfo->value.enumerated.item; + + prof_name = aw_dev_get_prof_name(aw883xx->aw_pa, count); + if (!prof_name) { + strscpy(uinfo->value.enumerated.name, "null", + strlen("null") + 1); + return 0; + } + + strscpy(name, prof_name, sizeof(uinfo->value.enumerated.name)); + + return 0; +} + +static int aw883xx_profile_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + + ucontrol->value.integer.value[0] = aw883xx_dev_get_profile_index(aw883xx->aw_pa); + + return 0; +} + +static int aw883xx_profile_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + int ret; + int cur_index; + + /* check value valid */ + ret = aw883xx_dev_check_profile_index(aw883xx->aw_pa, ucontrol->value.integer.value[0]); + if (ret) + return 0; + + /*check cur_index == set value*/ + cur_index = aw883xx_dev_get_profile_index(aw883xx->aw_pa); + if (cur_index == ucontrol->value.integer.value[0]) { + dev_dbg(codec->dev, "index no change"); + return 0; + } + + /*pa stop or stopping just set profile*/ + mutex_lock(&aw883xx->lock); + aw883xx_dev_set_profile_index(aw883xx->aw_pa, ucontrol->value.integer.value[0]); + + if (aw883xx->pstream) { + aw883xx_device_stop(aw883xx->aw_pa); + aw883xx_start(aw883xx, AW_SYNC_START); + } + + mutex_unlock(&aw883xx->lock); + + return 1; +} + +static int aw883xx_switch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + + ucontrol->value.integer.value[0] = aw883xx->allow_pw; + + return 0; +} + +static int aw883xx_switch_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int value = 0; + + value = ucontrol->value.integer.value[0]; + if (value < mc->min || value > mc->max) + return 0; + + if (value == aw883xx->allow_pw) { + dev_dbg(aw883xx->dev, "PA switch not change"); + return 0; + } + aw883xx->allow_pw = value; + + if (aw883xx->pstream) { + if (!aw883xx->allow_pw) { + cancel_delayed_work_sync(&aw883xx->start_work); + mutex_lock(&aw883xx->lock); + aw883xx_device_stop(aw883xx->aw_pa); + mutex_unlock(&aw883xx->lock); + } else { + cancel_delayed_work_sync(&aw883xx->start_work); + mutex_lock(&aw883xx->lock); + aw883xx_start(aw883xx, AW_SYNC_START); + mutex_unlock(&aw883xx->lock); + } + } + + return 1; +} + +static int aw883xx_volume_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc; + + ucontrol->value.integer.value[0] = vol_desc->ctl_volume; + + return 0; +} + +static int aw883xx_volume_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int value = 0; + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc; + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + value = ucontrol->value.integer.value[0]; + if (value < mc->min || value > mc->max) + return 0; + + if (vol_desc->ctl_volume != value) { + vol_desc->ctl_volume = value; + aw883xx_dev_set_volume(aw883xx->aw_pa, vol_desc->ctl_volume); + + return 1; + } + + return 0; +} + +static int aw883xx_get_fade_step(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + + ucontrol->value.integer.value[0] = aw883xx->aw_pa->fade_step; + + return 0; +} +static int aw883xx_set_fade_step(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int value = 0; + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + value = ucontrol->value.integer.value[0]; + if (value < mc->min || value > mc->max) + return 0; + + if (aw883xx->aw_pa->fade_step != value) { + aw883xx->aw_pa->fade_step = value; + return 1; + } + + return 0; +} +static int aw883xx_re_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + struct aw_device *aw_dev = aw883xx->aw_pa; + + ucontrol->value.integer.value[0] = aw_dev->cali_desc.cali_re; + + return 0; +} + +static int aw883xx_re_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int value = 0; + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec); + struct aw_device *aw_dev = aw883xx->aw_pa; + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + value = ucontrol->value.integer.value[0]; + if (value < mc->min || value > mc->max) + return 0; + + if (aw_dev->cali_desc.cali_re != value) { + aw_dev->cali_desc.cali_re = value; + return 1; + } + + return 0; +} +static const struct snd_kcontrol_new aw883xx_controls[] = { + SOC_SINGLE_EXT("PCM Playback Switch", SND_SOC_NOPM, 0, 1, 0, + aw883xx_switch_get, aw883xx_switch_set), + SOC_SINGLE_EXT("PCM Playback Volume", AW_PID_2049_SYSCTRL2_REG, + 6, AW_PID_2049_MUTE_VOL, 0, aw883xx_volume_get, + aw883xx_volume_set), + SOC_SINGLE_EXT("Fade Step", 0, 0, AW_PID_2049_MUTE_VOL, 0, + aw883xx_get_fade_step, aw883xx_set_fade_step), + SOC_SINGLE_EXT("Volume Ramp Up Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN, + aw883xx_get_fade_in_time, aw883xx_set_fade_in_time), + SOC_SINGLE_EXT("Volume Ramp Down Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN, + aw883xx_get_fade_out_time, aw883xx_set_fade_out_time), + SOC_SINGLE_EXT("Calib", 0, 0, 100, 0, + aw883xx_re_get, aw883xx_re_set), + AW_PROFILE_EXT("Profile Set", aw883xx_profile_info, + aw883xx_profile_get, aw883xx_profile_set), +}; + +static const struct snd_soc_dapm_widget aw883xx_dapm_widgets[] = { + /* playback */ + SND_SOC_DAPM_AIF_IN("AIF_RX", "Speaker_Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_OUTPUT("DAC Output"), + /* capture */ + SND_SOC_DAPM_AIF_OUT("AIF_TX", "Speaker_Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_INPUT("ADC Input"), +}; + +static const struct snd_soc_dapm_route aw883xx_audio_map[] = { + {"DAC Output", NULL, "AIF_RX"}, + {"AIF_TX", NULL, "ADC Input"}, +}; + +static int aw883xx_codec_probe(struct snd_soc_component *component) +{ + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + int ret = 0; + + /*destroy_workqueue(struct workqueue_struct *wq)*/ + aw883xx->work_queue = create_singlethread_workqueue("aw883xx"); + if (!aw883xx->work_queue) { + dev_err(aw883xx->dev, "create workqueue failed !"); + return -EINVAL; + } + + INIT_DELAYED_WORK(&aw883xx->start_work, aw883xx_startup_work); + + /*add widgets*/ + ret = snd_soc_dapm_new_controls(dapm, aw883xx_dapm_widgets, + ARRAY_SIZE(aw883xx_dapm_widgets)); + if (ret < 0) + return ret; + + /*add route*/ + ret = snd_soc_dapm_add_routes(dapm, aw883xx_audio_map, + ARRAY_SIZE(aw883xx_audio_map)); + if (ret < 0) + return ret; + + ret = snd_soc_add_component_controls(component, aw883xx_controls, + ARRAY_SIZE(aw883xx_controls)); + if (ret < 0) + return ret; + + return ret; +} + +static void aw883xx_codec_remove(struct snd_soc_component *aw_codec) +{ + struct aw883xx *aw883xx = snd_soc_component_get_drvdata(aw_codec); + + cancel_delayed_work_sync(&aw883xx->start_work); + + if (aw883xx->work_queue) + destroy_workqueue(aw883xx->work_queue); + +} + +static const struct snd_soc_component_driver soc_codec_dev_aw883xx = { + .probe = aw883xx_codec_probe, + .remove = aw883xx_codec_remove, +}; + +static struct aw883xx *aw883xx_malloc_init(struct i2c_client *i2c) +{ + struct aw883xx *aw883xx = devm_kzalloc(&i2c->dev, + sizeof(struct aw883xx), GFP_KERNEL); + if (!aw883xx) + return NULL; + + aw883xx->dev = &i2c->dev; + aw883xx->i2c = i2c; + aw883xx->aw_pa = NULL; + aw883xx->codec = NULL; + aw883xx->allow_pw = true; + aw883xx->work_queue = NULL; + mutex_init(&aw883xx->lock); + mutex_init(&aw883xx->dsp_lock); + + return aw883xx; +} + +static void aw883xx_parse_sync_flag_dt(struct aw883xx *aw883xx) +{ + int ret; + int32_t sync_enable = 0; + struct device_node *np = aw883xx->dev->of_node; + + ret = of_property_read_u32(np, "sync-flag", &sync_enable); + if (ret < 0) { + dev_dbg(aw883xx->dev, + "read sync flag failed,default phase sync off"); + sync_enable = false; + } else { + dev_dbg(aw883xx->dev, + "sync flag is %d", sync_enable); + } + + aw883xx->phase_sync = sync_enable; +} + +static void aw883xx_hw_reset(struct aw883xx *aw883xx) +{ + if (aw883xx->reset_gpio) { + gpiod_set_value_cansleep(aw883xx->reset_gpio, 0); + usleep_range(AW_1000_US, AW_1000_US + 10); + gpiod_set_value_cansleep(aw883xx->reset_gpio, 1); + usleep_range(AW_1000_US, AW_1000_US + 10); + } else { + dev_err(aw883xx->dev, "%s failed", __func__); + } +} + +static int aw883xx_read_chipid(struct aw883xx *aw883xx) +{ + int ret = -1; + int reg_val = 0; + + ret = regmap_read(aw883xx->regmap, AW_CHIP_ID_REG, &reg_val); + if (ret) + return -EIO; + + dev_info(aw883xx->dev, "chip id = %x\n", reg_val); + aw883xx->chip_id = reg_val; + + return 0; +} + +static void aw883xx_parse_dt(struct aw883xx *aw883xx) +{ + aw883xx_parse_sync_flag_dt(aw883xx); + + aw883xx->reset_gpio = devm_gpiod_get_optional(aw883xx->dev, + "reset", GPIOD_OUT_LOW); + if (IS_ERR(aw883xx->reset_gpio)) + dev_info(aw883xx->dev, "reset gpio not defined\n"); +} +/* + * i2c driver + */ +static int aw883xx_i2c_probe(struct i2c_client *i2c) +{ + struct aw883xx *aw883xx = NULL; + int ret = -1; + + if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) { + dev_err(&i2c->dev, "check_functionality failed"); + return -EIO; + } + + aw883xx = aw883xx_malloc_init(i2c); + if (!aw883xx) { + dev_err(&i2c->dev, "malloc aw883xx failed"); + return -ENOMEM; + } + i2c_set_clientdata(i2c, aw883xx); + + aw883xx_parse_dt(aw883xx); + + /* hardware reset */ + aw883xx_hw_reset(aw883xx); + + aw883xx->regmap = devm_regmap_init_i2c(i2c, &aw883xx_remap_config); + if (IS_ERR(aw883xx->regmap)) { + ret = PTR_ERR(aw883xx->regmap); + dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret); + return ret; + } + + /* aw883xx chip id */ + ret = aw883xx_read_chipid(aw883xx); + if (ret < 0) { + dev_err(&i2c->dev, "aw883xx_read_chipid failed ret=%d", ret); + return ret; + } + + /*aw pa init*/ + ret = aw883xx_init(aw883xx); + if (ret < 0) + return ret; + + ret = aw883xx_request_firmware_file(aw883xx); + if (ret < 0) { + dev_err(aw883xx->dev, "%s failed\n", __func__); + return ret; + } + + ret = snd_soc_register_component(aw883xx->dev, + &soc_codec_dev_aw883xx, + aw883xx_dai, ARRAY_SIZE(aw883xx_dai)); + if (ret < 0) { + dev_err(aw883xx->dev, "failed to register aw883xx: %d", ret); + return ret; + } + + return 0; +} + +static void aw883xx_i2c_remove(struct i2c_client *i2c) +{ + struct aw883xx *aw883xx = i2c_get_clientdata(i2c); + + aw883xx_dev_deinit(aw883xx->aw_pa); + snd_soc_unregister_component(&i2c->dev); + + if (aw883xx->aw_cfg) { + vfree(aw883xx->aw_cfg); + aw883xx->aw_cfg = NULL; + } +} + +static const struct i2c_device_id aw883xx_i2c_id[] = { + { AW_I2C_NAME, 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, aw883xx_i2c_id); + +static struct i2c_driver aw883xx_i2c_driver = { + .driver = { + .name = AW_I2C_NAME, + .owner = THIS_MODULE, + }, + .probe_new = aw883xx_i2c_probe, + .remove = aw883xx_i2c_remove, + .id_table = aw883xx_i2c_id, +}; +module_i2c_driver(aw883xx_i2c_driver); + +MODULE_DESCRIPTION("ASoC AW883XX Smart PA Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/aw883xx/aw883xx.h b/sound/soc/codecs/aw883xx/aw883xx.h new file mode 100644 index 000000000000..209851cae7ef --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_H__ +#define __AW883XX_H__ + +#include <linux/version.h> +#include <sound/control.h> +#include <sound/soc.h> +#include "aw883xx_data_type.h" + +#define AW_CHIP_ID_REG (0x00) +#define AW_START_RETRIES (5) +#define AW_START_WORK_DELAY_MS (0) + +#define AW_DSP_16_DATA_MASK (0x0000ffff) + +#define AW_I2C_NAME "aw883xx_smartpa" + +#define AW_RATES (SNDRV_PCM_RATE_8000_48000 | \ + SNDRV_PCM_RATE_96000) +#define AW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) +#define AW_REQUEST_FW_RETRIES 5 /* 5 times */ +#define AW_SYNC_LOAD + +#define FADE_TIME_MAX 100000 +#define FADE_TIME_MIN 0 + +#define AW_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \ +{ \ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .name = xname, \ + .info = profile_info, \ + .get = profile_get, \ + .put = profile_set, \ +} + +enum { + AW_SYNC_START = 0, + AW_ASYNC_START, +}; + +enum { + AW883XX_STREAM_CLOSE = 0, + AW883XX_STREAM_OPEN, +}; + +struct aw883xx { + struct i2c_client *i2c; + struct device *dev; + struct mutex lock; + struct mutex dsp_lock; + struct snd_soc_component *codec; + struct aw_device *aw_pa; + struct gpio_desc *reset_gpio; + unsigned char phase_sync; /*phase sync*/ + bool allow_pw; + u8 pstream; + struct workqueue_struct *work_queue; + struct delayed_work start_work; + u16 chip_id; + struct regmap *regmap; + struct aw_container *aw_cfg; +}; + +int aw883xx_init(struct aw883xx *aw883xx); + +int aw883xx_dsp_write(struct aw883xx *aw883xx, + unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type); +int aw883xx_dsp_read(struct aw883xx *aw883xx, + unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type); + +#endif

From: Weidong Wang wangweidong.a@awinic.com

The Awinic AW883XX is an I2S/TDM input, high efficiency digital Smart K audio amplifier with an integrated 10.25V smart boost convert

Signed-off-by: Nick Li liweilei@awinic.com Signed-off-by: Bruce zhao zhaolei@awinic.com Signed-off-by: Weidong Wang wangweidong.a@awinic.com --- sound/soc/codecs/aw883xx/aw883xx_device.c | 1613 +++++++++++++++++++++ sound/soc/codecs/aw883xx/aw883xx_device.h | 537 +++++++ 2 files changed, 2150 insertions(+) create mode 100644 sound/soc/codecs/aw883xx/aw883xx_device.c create mode 100644 sound/soc/codecs/aw883xx/aw883xx_device.h

diff --git a/sound/soc/codecs/aw883xx/aw883xx_device.c b/sound/soc/codecs/aw883xx/aw883xx_device.c new file mode 100644 index 000000000000..f4419e1a2fed --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_device.c @@ -0,0 +1,1613 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/debugfs.h> +#include <linux/firmware.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/syscalls.h> +#include <linux/version.h> +#include <linux/uaccess.h> +#include <linux/workqueue.h> +#include <sound/core.h> +#include <sound/control.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include "aw883xx_data_type.h" +#include "aw883xx_device.h" +#include "aw883xx_bin_parse.h" + +int aw883xx_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol) +{ + u16 hw_vol = 0; + int ret = -1; + struct aw_volume_desc *vol_desc = &aw_dev->volume_desc; + + hw_vol = set_vol + vol_desc->init_volume; + + ret = aw_dev->ops.aw_set_hw_volume(aw_dev, hw_vol); + if (ret < 0) { + dev_err(aw_dev->dev, "set volume failed"); + return ret; + } + + return 0; +} + +int aw883xx_dev_get_volume(struct aw_device *aw_dev, unsigned short *get_vol) +{ + int ret = -1; + u16 hw_vol = 0; + struct aw_volume_desc *vol_desc = &aw_dev->volume_desc; + + ret = aw_dev->ops.aw_get_hw_volume(aw_dev, &hw_vol); + if (ret < 0) { + dev_err(aw_dev->dev, "read volume failed"); + return ret; + } + + if (hw_vol > vol_desc->init_volume) + *get_vol = hw_vol - vol_desc->init_volume; + + return 0; +} + +static void aw_dev_fade_in(struct aw_device *aw_dev) +{ + int i = 0; + struct aw_volume_desc *desc = &aw_dev->volume_desc; + int fade_step = aw_dev->fade_step; + u16 fade_in_vol = desc->ctl_volume; + + if (!aw_dev->fade_en) + return; + + if (fade_step == 0 || aw_dev->fade_in_time == 0) { + aw883xx_dev_set_volume(aw_dev, fade_in_vol); + return; + } + /*volume up*/ + for (i = desc->mute_volume; i >= fade_in_vol; i -= fade_step) { + aw883xx_dev_set_volume(aw_dev, i); + usleep_range(aw_dev->fade_in_time, aw_dev->fade_in_time + 10); + } + if (i != fade_in_vol) + aw883xx_dev_set_volume(aw_dev, fade_in_vol); + +} + +static void aw_dev_fade_out(struct aw_device *aw_dev) +{ + int i = 0; + struct aw_volume_desc *desc = &aw_dev->volume_desc; + int fade_step = aw_dev->fade_step; + + if (!aw_dev->fade_en) + return; + + if (fade_step == 0 || aw_dev->fade_out_time == 0) { + aw883xx_dev_set_volume(aw_dev, desc->mute_volume); + return; + } + + for (i = desc->ctl_volume; i <= desc->mute_volume; i += fade_step) { + aw883xx_dev_set_volume(aw_dev, i); + usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10); + } + if (i != desc->mute_volume) { + aw883xx_dev_set_volume(aw_dev, desc->mute_volume); + usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10); + } +} + +static uint64_t aw_dev_dsp_crc32_reflect(uint64_t ref, unsigned char ch) +{ + int i; + uint64_t value = 0; + + for (i = 1; i < (ch + 1); i++) { + if (ref & 1) + value |= 1 << (ch - i); + + ref >>= 1; + } + + return value; +} + +static unsigned int aw_dev_calc_dsp_cfg_crc32(unsigned char *buf, unsigned int len) +{ + u8 i; + u32 crc = 0xffffffff; + + while (len--) { + for (i = 1; i != 0; i <<= 1) { + if ((crc & 0x80000000) != 0) { + crc <<= 1; + crc ^= 0x1EDC6F41; + } else { + crc <<= 1; + } + + if ((*buf & i) != 0) + crc ^= 0x1EDC6F41; + } + buf++; + } + + return (aw_dev_dsp_crc32_reflect(crc, 32)^0xffffffff); +} + +static int aw_dev_set_dsp_crc32(struct aw_device *aw_dev) +{ + u32 crc_value = 0; + u32 crc_data_len = 0; + int ret = -1; + struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg; + struct aw_dsp_crc_desc *desc = &aw_dev->dsp_crc_desc; + + /*get crc data len*/ + crc_data_len = (desc->dsp_reg - aw_dev->dsp_mem_desc.dsp_cfg_base_addr) * 2; + if (crc_data_len > crc_dsp_cfg->len) { + dev_err(aw_dev->dev, "crc data len :%d > cfg_data len:%d", + crc_data_len, crc_dsp_cfg->len); + return -EINVAL; + } + + if (crc_data_len % 4 != 0) { + dev_err(aw_dev->dev, "The crc data len :%d unsupport", crc_data_len); + return -EINVAL; + } + + crc_value = aw_dev_calc_dsp_cfg_crc32(crc_dsp_cfg->data, crc_data_len); + + dev_dbg(aw_dev->dev, "crc_value:0x%x", crc_value); + ret = aw_dev->ops.aw_dsp_write(aw_dev, desc->dsp_reg, crc_value, + desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "set dsp crc value failed"); + return ret; + } + + return 0; +} + +static void aw_dev_dsp_crc_check_enable(struct aw_device *aw_dev, bool flag) +{ + struct aw_dsp_crc_desc *dsp_crc_desc = &aw_dev->dsp_crc_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + int ret; + + if (flag) { + ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, dsp_crc_desc->ctl_reg, + ~dsp_crc_desc->ctl_mask, dsp_crc_desc->ctl_enable); + if (ret < 0) { + dev_err(aw_dev->dev, "enable dsp crc failed"); + return; + } + } else { + ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, dsp_crc_desc->ctl_reg, + ~dsp_crc_desc->ctl_mask, dsp_crc_desc->ctl_disable); + if (ret < 0) { + dev_err(aw_dev->dev, "close dsp crc failed"); + return; + } + } +} + +static int aw_dev_dsp_st_check(struct aw_device *aw_dev) +{ + struct aw_sysst_desc *desc = &aw_dev->sysst_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + int ret = -1; + unsigned int reg_val = 0; + int i; + + for (i = 0; i < AW_DSP_ST_CHECK_MAX; i++) { + ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val); + if (ret < 0) { + dev_err(aw_dev->dev, "read reg0x%x failed", desc->reg); + continue; + } + + if ((reg_val & (~desc->dsp_mask)) != desc->dsp_check) { + dev_err(aw_dev->dev, "check dsp st fail,reg_val:0x%04x", reg_val); + ret = -EINVAL; + continue; + } else { + dev_dbg(aw_dev->dev, "dsp st check ok, reg_val:0x%04x", reg_val); + return 0; + } + } + + return ret; +} + +static int aw_dev_dsp_crc32_check(struct aw_device *aw_dev) +{ + int ret; + + if (aw_dev->dsp_cfg == AW_DEV_DSP_BYPASS) { + dev_info(aw_dev->dev, "dsp bypass"); + return 0; + } + + ret = aw_dev_set_dsp_crc32(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "set dsp crc32 failed"); + return ret; + } + + aw_dev_dsp_crc_check_enable(aw_dev, true); + + /*dsp enable*/ + aw883xx_dev_dsp_enable(aw_dev, true); + usleep_range(AW_5000_US, AW_5000_US + 100); + + ret = aw_dev_dsp_st_check(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "check crc32 fail"); + return ret; + } + + aw_dev_dsp_crc_check_enable(aw_dev, false); + aw_dev->dsp_crc_st = AW_DSP_CRC_OK; + return 0; +} + +static void aw_dev_pwd(struct aw_device *aw_dev, bool pwd) +{ + struct aw_pwd_desc *pwd_desc = &aw_dev->pwd_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + if (pwd) { + aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, pwd_desc->reg, + ~pwd_desc->mask, + pwd_desc->enable); + } else { + aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, pwd_desc->reg, + ~pwd_desc->mask, + pwd_desc->disable); + } +} + +static void aw_dev_amppd(struct aw_device *aw_dev, bool amppd) +{ + struct aw_amppd_desc *amppd_desc = &aw_dev->amppd_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + if (amppd) { + aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, amppd_desc->reg, + ~amppd_desc->mask, + amppd_desc->enable); + } else { + aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, amppd_desc->reg, + ~amppd_desc->mask, + amppd_desc->disable); + } +} + +void aw883xx_dev_mute(struct aw_device *aw_dev, bool mute) +{ + struct aw_mute_desc *mute_desc = &aw_dev->mute_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + if (mute) { + aw_dev_fade_out(aw_dev); + aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, mute_desc->reg, + ~mute_desc->mask, mute_desc->enable); + } else { + aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, mute_desc->reg, + ~mute_desc->mask, mute_desc->disable); + aw_dev_fade_in(aw_dev); + } +} + +int aw883xx_dev_get_hmute(struct aw_device *aw_dev) +{ + unsigned int reg_val = 0; + int ret; + struct aw_mute_desc *desc = &aw_dev->mute_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val); + if (ret < 0) + return ret; + + if (reg_val & (~desc->mask)) + ret = 1; + else + ret = 0; + + return ret; +} + +static int aw_dev_get_icalk(struct aw_device *aw_dev, int16_t *icalk) +{ + int ret = -1; + unsigned int reg_val = 0; + u16 reg_icalk = 0; + struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->icalk_reg, &reg_val); + if (ret < 0) { + dev_err(aw_dev->dev, "reg read failed"); + return ret; + } + + reg_icalk = reg_val & (~desc->icalk_reg_mask); + + if (reg_icalk & (~desc->icalk_sign_mask)) + reg_icalk = reg_icalk | desc->icalk_neg_mask; + + *icalk = (int16_t)reg_icalk; + + return 0; +} + +static int aw_dev_get_vcalk(struct aw_device *aw_dev, int16_t *vcalk) +{ + int ret = -1; + unsigned int reg_val = 0; + u16 reg_vcalk = 0; + struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->vcalk_reg, &reg_val); + if (ret < 0) { + dev_err(aw_dev->dev, "reg read failed"); + return ret; + } + + reg_val = reg_val >> desc->vcalk_shift; + + reg_vcalk = (u16)reg_val & (~desc->vcalk_reg_mask); + + if (reg_vcalk & (~desc->vcalk_sign_mask)) + reg_vcalk = reg_vcalk | desc->vcalk_neg_mask; + + *vcalk = (int16_t)reg_vcalk; + + return 0; +} + +static int aw_dev_get_vcalk_dac(struct aw_device *aw_dev, int16_t *vcalk) +{ + int ret = -1; + unsigned int reg_val = 0; + u16 reg_vcalk = 0; + struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->icalk_reg, &reg_val); + if (ret < 0) { + dev_err(aw_dev->dev, "reg read failed"); + return ret; + } + + reg_vcalk = reg_val >> desc->vcalk_dac_shift; + + if (reg_vcalk & desc->vcalk_dac_mask) + reg_vcalk = reg_vcalk | desc->vcalk_dac_neg_mask; + + *vcalk = (int16_t)reg_vcalk; + + return 0; +} + +int aw883xx_dev_modify_dsp_cfg(struct aw_device *aw_dev, + unsigned int addr, unsigned int dsp_data, unsigned char data_type) +{ + u32 addr_offset = 0; + int len = 0; + u8 temp_data[4] = { 0 }; + struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg; + + dev_dbg(aw_dev->dev, "addr:0x%x, dsp_data:0x%x", addr, dsp_data); + + switch (data_type) { + case AW_DSP_16_DATA: + temp_data[0] = (u8)(dsp_data & 0x00ff); + temp_data[1] = (u8)((dsp_data & 0xff00) >> 8); + len = 2; + break; + case AW_DSP_32_DATA: + temp_data[0] = (u8)(dsp_data & 0x000000ff); + temp_data[1] = (u8)((dsp_data & 0x0000ff00) >> 8); + temp_data[2] = (u8)((dsp_data & 0x00ff0000) >> 16); + temp_data[3] = (u8)((dsp_data & 0xff000000) >> 24); + len = 4; + break; + default: + dev_err(aw_dev->dev, "data type[%d] unsupported", data_type); + return -EINVAL; + } + + addr_offset = (addr - aw_dev->dsp_mem_desc.dsp_cfg_base_addr) * 2; + if (addr_offset > crc_dsp_cfg->len) { + dev_err(aw_dev->dev, "addr_offset[%d] > crc_dsp_cfg->len[%d]", + addr_offset, crc_dsp_cfg->len); + return -EINVAL; + } + + memcpy(crc_dsp_cfg->data + addr_offset, temp_data, len); + return 0; +} + +static int aw_dev_vsense_select(struct aw_device *aw_dev, int *vsense_select) +{ + int ret = -1; + struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc; + unsigned int vsense_reg_val; + struct aw883xx *aw883xx = aw_dev->private_data; + + ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->vcalb_vsense_reg, &vsense_reg_val); + if (ret < 0) { + dev_err(aw_dev->dev, "read vsense_reg_val failed"); + return ret; + } + dev_dbg(aw_dev->dev, "vsense_reg = 0x%x", vsense_reg_val); + + if (vsense_reg_val & (~desc->vcalk_vdsel_mask)) { + *vsense_select = AW_DEV_VDSEL_VSENSE; + dev_dbg(aw_dev->dev, "vsense outside"); + return 0; + } + + *vsense_select = AW_DEV_VDSEL_DAC; + dev_dbg(aw_dev->dev, "vsense inside"); + return 0; +} + +static int aw_dev_set_vcalb(struct aw_device *aw_dev) +{ + int ret = -1; + u32 reg_val = 0; + int vcalb; + int icalk; + int vcalk; + int16_t icalk_val = 0; + int16_t vcalk_val = 0; + struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc; + u32 vcalb_adj; + int vsense_select = -1; + + ret = aw_dev->ops.aw_dsp_read(aw_dev, desc->vcalb_dsp_reg, &vcalb_adj, desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "read vcalb_adj failed"); + return ret; + } + + ret = aw_dev_vsense_select(aw_dev, &vsense_select); + if (ret < 0) + return ret; + dev_dbg(aw_dev->dev, "vsense_select = %d", vsense_select); + + ret = aw_dev_get_icalk(aw_dev, &icalk_val); + if (ret < 0) + return ret; + icalk = desc->cabl_base_value + desc->icalk_value_factor * icalk_val; + + switch (vsense_select) { + case AW_DEV_VDSEL_VSENSE: + ret = aw_dev_get_vcalk(aw_dev, &vcalk_val); + if (ret < 0) + return ret; + vcalk = desc->cabl_base_value + desc->vcalk_value_factor * vcalk_val; + vcalb = desc->vcal_factor * desc->vscal_factor / + desc->iscal_factor * icalk / vcalk * vcalb_adj; + + dev_dbg(aw_dev->dev, "vcalk_factor=%d, vscal_factor=%d, icalk=%d, vcalk=%d", + desc->vcalk_value_factor, desc->vscal_factor, icalk, vcalk); + break; + case AW_DEV_VDSEL_DAC: + ret = aw_dev_get_vcalk_dac(aw_dev, &vcalk_val); + if (ret < 0) + return ret; + vcalk = desc->cabl_base_value + desc->vcalk_value_factor_vsense_in * vcalk_val; + vcalb = desc->vcal_factor * desc->vscal_factor_vsense_in / + desc->iscal_factor * icalk / vcalk * vcalb_adj; + + dev_dbg(aw_dev->dev, "vcalk_dac_factor=%d, vscal_dac_factor=%d, icalk=%d, vcalk=%d", + desc->vcalk_value_factor_vsense_in, + desc->vscal_factor_vsense_in, icalk, vcalk); + break; + default: + dev_err(aw_dev->dev, "unsupport vsense status"); + return -EINVAL; + } + + if ((vcalk == 0) || (desc->iscal_factor == 0)) { + dev_err(aw_dev->dev, "vcalk:%d or desc->iscal_factor:%d unsupported", + vcalk, desc->iscal_factor); + return -EINVAL; + } + + vcalb = vcalb >> aw_dev->vcalb_desc.vcalb_adj_shift; + reg_val = (u32)vcalb; + + dev_dbg(aw_dev->dev, "vcalb=%d, reg_val=0x%x, vcalb_adj =0x%x", + vcalb, reg_val, vcalb_adj); + + ret = aw_dev->ops.aw_dsp_write(aw_dev, desc->vcalb_dsp_reg, reg_val, desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "write vcalb failed"); + return ret; + } + + ret = aw883xx_dev_modify_dsp_cfg(aw_dev, desc->vcalb_dsp_reg, + (u32)reg_val, desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "modify dsp cfg failed"); + return ret; + } + + return 0; +} + +static int aw_dev_get_cali_f0_delay(struct aw_device *aw_dev) +{ + struct aw_cali_delay_desc *desc = &aw_dev->cali_delay_desc; + u32 cali_delay = 0; + int ret = -1; + + ret = aw_dev->ops.aw_dsp_read(aw_dev, + desc->dsp_reg, &cali_delay, desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "read cali delay failed, ret=%d", ret); + return ret; + } + + desc->delay = AW_CALI_DELAY_CACL(cali_delay); + dev_dbg(aw_dev->dev, "read cali delay: %d ms", desc->delay); + + return 0; +} + +static void aw883xx_dev_get_int_status(struct aw_device *aw_dev, unsigned short *int_status) +{ + int ret = -1; + unsigned int reg_val = 0; + struct aw883xx *aw883xx = aw_dev->private_data; + + ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, aw_dev->int_desc.st_reg, &reg_val); + if (ret < 0) + dev_err(aw_dev->dev, "read interrupt reg fail, ret=%d", ret); + else + *int_status = reg_val; + + dev_dbg(aw_dev->dev, "read interrupt reg = 0x%04x", *int_status); +} + +static void aw883xx_dev_clear_int_status(struct aw_device *aw_dev) +{ + u16 int_status = 0; + + /*read int status and clear*/ + aw883xx_dev_get_int_status(aw_dev, &int_status); + /*make sure int status is clear*/ + aw883xx_dev_get_int_status(aw_dev, &int_status); +} + +int aw883xx_dev_get_iis_status(struct aw_device *aw_dev) +{ + int ret = -1; + unsigned int reg_val = 0; + struct aw_sysst_desc *desc = &aw_dev->sysst_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val); + if ((reg_val & desc->pll_check) == desc->pll_check) + ret = 0; + else + dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val); + + return ret; +} + +static int aw_dev_mode1_pll_check(struct aw_device *aw_dev) +{ + int ret = -1; + u16 i = 0; + + for (i = 0; i < AW_DEV_SYSST_CHECK_MAX; i++) { + ret = aw883xx_dev_get_iis_status(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "mode1 iis signal check error"); + usleep_range(AW_2000_US, AW_2000_US + 10); + } else { + return 0; + } + } + + return ret; +} + +static int aw_dev_mode2_pll_check(struct aw_device *aw_dev) +{ + int ret = -1; + u16 i = 0; + unsigned int reg_val = 0; + struct aw_cco_mux_desc *cco_mux_desc = &aw_dev->cco_mux_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + aw_dev->ops.aw_reg_read(aw883xx->regmap, cco_mux_desc->reg, &reg_val); + reg_val &= (~cco_mux_desc->mask); + if (reg_val == cco_mux_desc->divider) { + dev_dbg(aw_dev->dev, "CCO_MUX is already divider"); + return ret; + } + + /* change mode2 */ + aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, cco_mux_desc->reg, + ~cco_mux_desc->mask, cco_mux_desc->divider); + + for (i = 0; i < AW_DEV_SYSST_CHECK_MAX; i++) { + ret = aw883xx_dev_get_iis_status(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "mode2 iis signal check error"); + usleep_range(AW_2000_US, AW_2000_US + 10); + } else { + break; + } + } + + /* change mode1*/ + aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, cco_mux_desc->reg, + ~cco_mux_desc->mask, cco_mux_desc->bypass); + + if (ret == 0) { + usleep_range(AW_2000_US, AW_2000_US + 10); + for (i = 0; i < AW_DEV_SYSST_CHECK_MAX; i++) { + ret = aw_dev_mode1_pll_check(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "mode2 switch to mode1, iis signal check error"); + usleep_range(AW_2000_US, AW_2000_US + 10); + } else { + break; + } + } + } + + return ret; +} + +int aw883xx_dev_syspll_check(struct aw_device *aw_dev) +{ + int ret = -1; + + ret = aw_dev_mode1_pll_check(aw_dev); + if (ret < 0) { + dev_dbg(aw_dev->dev, "mode1 check iis failed try switch to mode2 check"); + ret = aw_dev_mode2_pll_check(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "mode2 check iis failed"); + return ret; + } + } + + return ret; +} + +int aw883xx_dev_sysst_check(struct aw_device *aw_dev) +{ + int ret = -1; + unsigned char i; + unsigned int reg_val = 0; + struct aw_sysst_desc *desc = &aw_dev->sysst_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + for (i = 0; i < AW_DEV_SYSST_CHECK_MAX; i++) { + aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val); + if (((reg_val & (~desc->st_mask)) & desc->st_check) != desc->st_check) { + dev_dbg(aw_dev->dev, "check fail, cnt=%d, reg_val=0x%04x", + i, reg_val); + usleep_range(AW_2000_US, AW_2000_US + 10); + } else { + ret = 0; + break; + } + } + if (ret < 0) + dev_err(aw_dev->dev, "check fail"); + + return ret; +} + +static int aw_dev_sysint_check(struct aw_device *aw_dev) +{ + int ret = 0; + u16 reg_val = 0; + struct aw_int_desc *desc = &aw_dev->int_desc; + + aw883xx_dev_get_int_status(aw_dev, &reg_val); + + if (reg_val & (desc->intst_mask)) { + dev_err(aw_dev->dev, "pa stop check fail:0x%04x", reg_val); + ret = -EINVAL; + } + + return ret; +} + +static void aw_dev_get_cur_mode_st(struct aw_device *aw_dev) +{ + unsigned int reg_val; + struct aw_profctrl_desc *profctrl_desc = &aw_dev->profctrl_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + aw_dev->ops.aw_reg_read(aw883xx->regmap, aw_dev->pwd_desc.reg, &reg_val); + if ((reg_val & (~profctrl_desc->mask)) == profctrl_desc->rcv_mode_val) + profctrl_desc->cur_mode = AW_RCV_MODE; + else + profctrl_desc->cur_mode = AW_NOT_RCV_MODE; +} + +void aw883xx_dev_dsp_enable(struct aw_device *aw_dev, bool dsp) +{ + int ret = -1; + struct aw_dsp_en_desc *desc = &aw_dev->dsp_en_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + if (dsp) { + ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg, + ~desc->mask, desc->enable); + if (ret < 0) + dev_err(aw_dev->dev, "enable dsp failed"); + } else { + ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg, + ~desc->mask, desc->disable); + if (ret < 0) + dev_err(aw_dev->dev, "disable dsp failed"); + } +} + +static void aw_dev_get_dsp_config(struct aw_device *aw_dev, unsigned char *dsp_cfg) +{ + int ret = -1; + unsigned int reg_val = 0; + struct aw_dsp_en_desc *desc = &aw_dev->dsp_en_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val); + if (ret < 0) { + dev_err(aw_dev->dev, "reg read failed"); + return; + } + + if (reg_val & (~desc->mask)) + *dsp_cfg = AW_DEV_DSP_BYPASS; + else + *dsp_cfg = AW_DEV_DSP_WORK; +} + +void aw883xx_dev_memclk_select(struct aw_device *aw_dev, unsigned char flag) +{ + struct aw_memclk_desc *desc = &aw_dev->memclk_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + int ret = -1; + + switch (flag) { + case AW_DEV_MEMCLK_PLL: + ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg, + ~desc->mask, desc->mcu_hclk); + if (ret < 0) + dev_err(aw_dev->dev, "memclk select pll failed"); + break; + case AW_DEV_MEMCLK_OSC: + ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg, + ~desc->mask, desc->osc_clk); + if (ret < 0) + dev_err(aw_dev->dev, "memclk select OSC failed"); + break; + default: + dev_err(aw_dev->dev, "unknown memclk config, flag=0x%x", flag); + break; + } +} + +int aw883xx_dev_get_dsp_status(struct aw_device *aw_dev) +{ + int ret = -1; + unsigned int reg_val = 0; + struct aw_watch_dog_desc *desc = &aw_dev->watch_dog_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val); + if (reg_val & (~desc->mask)) + ret = 0; + + return ret; +} + +static int aw_dev_get_vmax(struct aw_device *aw_dev, unsigned int *vmax) +{ + int ret = -1; + struct aw_vmax_desc *desc = &aw_dev->vmax_desc; + + ret = aw_dev->ops.aw_dsp_read(aw_dev, desc->dsp_reg, vmax, desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "get vmax failed"); + return ret; + } + + return 0; +} + +/* + * aw_dev update cfg + */ +static int aw_dev_reg_container_update(struct aw_device *aw_dev, + unsigned char *data, unsigned int len) +{ + int i, ret; + u8 reg_addr = 0; + u16 reg_val = 0; + unsigned int read_val = 0; + u16 read_vol = 0; + struct aw_volume_desc *vol_desc = &aw_dev->volume_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + int16_t *reg_data = NULL; + int data_len; + + reg_data = (int16_t *)data; + data_len = len >> 1; + + if (data_len % 2 != 0) { + dev_err(aw_dev->dev, "data len:%d unsupported", + data_len); + return -EINVAL; + } + + for (i = 0; i < data_len; i += 2) { + reg_addr = reg_data[i]; + reg_val = reg_data[i + 1]; + dev_dbg(aw_dev->dev, "reg = 0x%02x, val = 0x%04x", + reg_addr, reg_val); + if (reg_addr == aw_dev->mute_desc.reg) { + aw_dev->ops.aw_reg_read(aw883xx->regmap, reg_addr, &read_val); + read_val &= (~aw_dev->mute_desc.mask); + reg_val &= aw_dev->mute_desc.mask; + reg_val |= read_val; + } + if (reg_addr == aw_dev->dsp_crc_desc.ctl_reg) + reg_val &= aw_dev->dsp_crc_desc.ctl_mask; + + if (reg_addr == aw_dev->chansel_desc.txchan_reg) { + /*close tx*/ + reg_val &= aw_dev->tx_en_desc.tx_en_mask; + reg_val |= aw_dev->tx_en_desc.tx_disable; + } + + if (reg_addr == aw_dev->volume_desc.reg) { + read_vol = (reg_val & (~aw_dev->volume_desc.mask)) >> + aw_dev->volume_desc.shift; + aw_dev->volume_desc.init_volume = + aw_dev->ops.aw_reg_val_to_db(read_vol); + } + ret = aw_dev->ops.aw_reg_write(aw883xx->regmap, reg_addr, reg_val); + if (ret < 0) + break; + + } + + aw_dev_get_cur_mode_st(aw_dev); + + if (aw_dev->cur_prof != aw_dev->set_prof) { + /*clear control volume when PA change profile*/ + vol_desc->ctl_volume = 0; + } else { + /*keep control volume when PA start with sync mode*/ + aw883xx_dev_set_volume(aw_dev, vol_desc->ctl_volume); + } + + /*keep min volume*/ + if (aw_dev->fade_en) + aw883xx_dev_set_volume(aw_dev, vol_desc->mute_volume); + + aw_dev_get_dsp_config(aw_dev, &aw_dev->dsp_cfg); + + dev_dbg(aw_dev->dev, "exit"); + + return ret; +} + +static int aw_dev_reg_update(struct aw_device *aw_dev, + unsigned char *data, unsigned int len) +{ + int ret = 0; + + dev_dbg(aw_dev->dev, "reg len:%d", len); + + if (len && (data != NULL)) { + ret = aw_dev_reg_container_update(aw_dev, data, len); + if (ret < 0) { + dev_err(aw_dev->dev, "reg update failed"); + return ret; + } + } else { + dev_err(aw_dev->dev, "reg data is null or len is 0"); + return -EPERM; + } + + return 0; +} + +static int aw_dev_get_ra(struct aw_cali_desc *cali_desc) +{ + int ret; + u32 dsp_ra; + struct aw_device *aw_dev = + container_of(cali_desc, struct aw_device, cali_desc); + struct aw_ra_desc *desc = &aw_dev->ra_desc; + + ret = aw_dev->ops.aw_dsp_read(aw_dev, desc->dsp_reg, + &dsp_ra, desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "read ra error"); + return ret; + } + + cali_desc->ra = AW_DSP_RE_TO_SHOW_RE(dsp_ra, + aw_dev->adpz_re_desc.shift); + dev_dbg(aw_dev->dev, "get ra:%d", cali_desc->ra); + return 0; +} + +static int aw_dev_dsp_container_update(struct aw_device *aw_dev, + unsigned char *data, unsigned int len, unsigned short base) +{ + int i; + struct aw_dsp_mem_desc *dsp_mem_desc = &aw_dev->dsp_mem_desc; + struct aw883xx *aw883xx = aw_dev->private_data; +#ifdef AW_DSP_I2C_WRITES + u32 tmp_len = 0; +#else + u16 reg_val = 0; +#endif + + mutex_lock(aw_dev->dsp_lock); +#ifdef AW_DSP_I2C_WRITES + /* i2c writes */ + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, base); + + for (i = 0; i < len; i += AW_MAX_RAM_WRITE_BYTE_SIZE) { + if ((len - i) < AW_MAX_RAM_WRITE_BYTE_SIZE) + tmp_len = len - i; + else + tmp_len = AW_MAX_RAM_WRITE_BYTE_SIZE; + aw_dev->ops.aw_i2c_writes(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg, + &data[i], tmp_len); + } + +#else + /* i2c write */ + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, base); + for (i = 0; i < len; i += 2) { + reg_val = (data[i] << 8) + data[i + 1]; + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg, + reg_val); + } +#endif + mutex_unlock(aw_dev->dsp_lock); + dev_dbg(aw_dev->dev, "exit"); + + return 0; +} + +static int aw_dev_dsp_fw_update(struct aw_device *aw_dev, + unsigned char *data, unsigned int len) +{ + struct aw_dsp_mem_desc *dsp_mem_desc = &aw_dev->dsp_mem_desc; + + dev_dbg(aw_dev->dev, "dsp firmware len:%d", len); + + if (len && (data != NULL)) { + aw_dev_dsp_container_update(aw_dev, + data, len, dsp_mem_desc->dsp_fw_base_addr); + aw_dev->dsp_fw_len = len; + } else { + dev_err(aw_dev->dev, "dsp firmware data is null or len is 0"); + return -EPERM; + } + + return 0; +} + +static int aw_dev_copy_to_crc_dsp_cfg(struct aw_device *aw_dev, + unsigned char *data, unsigned int size) +{ + struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg; + int ret; + + if (!crc_dsp_cfg->data) { + crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL); + if (!crc_dsp_cfg->data) + return -ENOMEM; + crc_dsp_cfg->len = size; + } else if (crc_dsp_cfg->len < size) { + devm_kfree(aw_dev->dev, crc_dsp_cfg->data); + crc_dsp_cfg->data = NULL; + crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL); + if (!crc_dsp_cfg->data) { + dev_err(aw_dev->dev, "error allocating memory"); + return -ENOMEM; + } + crc_dsp_cfg->len = size; + } + memcpy(crc_dsp_cfg->data, data, size); + ret = aw883xx_dev_dsp_data_order(aw_dev, crc_dsp_cfg->data, size); + if (ret < 0) + return ret; + + return 0; +} + +int aw883xx_dev_dsp_cfg_update(struct aw_device *aw_dev, + unsigned char *data, unsigned int len) +{ + struct aw_dsp_mem_desc *dsp_mem_desc = &aw_dev->dsp_mem_desc; + int ret; + + dev_dbg(aw_dev->dev, "dsp config len:%d", len); + + if (len && (data != NULL)) { + aw_dev_dsp_container_update(aw_dev, + data, len, dsp_mem_desc->dsp_cfg_base_addr); + aw_dev->dsp_cfg_len = len; + + ret = aw_dev_copy_to_crc_dsp_cfg(aw_dev, data, len); + if (ret < 0) + return ret; + + ret = aw_dev_set_vcalb(aw_dev); + if (ret < 0) + return ret; + ret = aw_dev_get_ra(&aw_dev->cali_desc); + if (ret < 0) + return ret; + ret = aw_dev_get_cali_f0_delay(aw_dev); + if (ret < 0) + return ret; + + ret = aw_dev_get_vmax(aw_dev, &aw_dev->vmax_desc.init_vmax); + if (ret < 0) { + dev_err(aw_dev->dev, "get vmax failed"); + return ret; + } + dev_dbg(aw_dev->dev, "get init vmax:0x%x", + aw_dev->vmax_desc.init_vmax); + aw_dev->dsp_crc_st = AW_DSP_CRC_NA; + } else { + dev_err(aw_dev->dev, "dsp config data is null or len is 0"); + return -EPERM; + } + + return 0; +} + +static int aw_dev_sram_check(struct aw_device *aw_dev) +{ + int ret = -1; + unsigned int reg_val = 0; + struct aw_dsp_mem_desc *dsp_mem_desc = &aw_dev->dsp_mem_desc; + struct aw883xx *aw883xx = aw_dev->private_data; + + mutex_lock(aw_dev->dsp_lock); + /*check the odd bits of reg 0x40*/ + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, + AW_DSP_ODD_NUM_BIT_TEST); + aw_dev->ops.aw_i2c_read(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, &reg_val); + if (reg_val != AW_DSP_ODD_NUM_BIT_TEST) { + dev_err(aw_dev->dev, "check reg 0x40 odd bit failed, read[0x%x] does not match write[0x%x]", + reg_val, AW_DSP_ODD_NUM_BIT_TEST); + goto error; + } + + /*check the even bits of reg 0x40*/ + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, + AW_DSP_EVEN_NUM_BIT_TEST); + aw_dev->ops.aw_i2c_read(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, &reg_val); + if (reg_val != AW_DSP_EVEN_NUM_BIT_TEST) { + dev_err(aw_dev->dev, "check reg 0x40 even bit failed, read[0x%x] does not match write[0x%x]", + reg_val, AW_DSP_EVEN_NUM_BIT_TEST); + goto error; + } + + /*check dsp_fw_base_addr*/ + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, + dsp_mem_desc->dsp_fw_base_addr); + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg, + AW_DSP_EVEN_NUM_BIT_TEST); + + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, + dsp_mem_desc->dsp_fw_base_addr); + aw_dev->ops.aw_i2c_read(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg, &reg_val); + if (reg_val != AW_DSP_EVEN_NUM_BIT_TEST) { + dev_err(aw_dev->dev, "check dsp fw addr failed, read[0x%x] does not match write[0x%x]", + reg_val, AW_DSP_EVEN_NUM_BIT_TEST); + goto error; + } + + /*check dsp_cfg_base_addr*/ + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, + dsp_mem_desc->dsp_cfg_base_addr); + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg, + AW_DSP_ODD_NUM_BIT_TEST); + + aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, + dsp_mem_desc->dsp_cfg_base_addr); + aw_dev->ops.aw_i2c_read(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg, &reg_val); + if (reg_val != AW_DSP_ODD_NUM_BIT_TEST) { + dev_err(aw_dev->dev, "check dsp cfg failed, read[0x%x] does not match write[0x%x]", + reg_val, AW_DSP_ODD_NUM_BIT_TEST); + goto error; + } + + mutex_unlock(aw_dev->dsp_lock); + return 0; + +error: + mutex_unlock(aw_dev->dsp_lock); + return ret; +} + +int aw883xx_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en) +{ + int ret = -1; + struct aw_prof_desc *set_prof_desc = NULL; + struct aw_sec_data_desc *sec_desc = NULL; + char *prof_name = NULL; + + if ((aw_dev->cur_prof == aw_dev->set_prof) && + (force_up_en == AW_FORCE_UPDATE_OFF)) { + dev_dbg(aw_dev->dev, "scene no change, not update"); + return 0; + } + + if (aw_dev->fw_status == AW_DEV_FW_FAILED) { + dev_err(aw_dev->dev, "fw status[%d] error", aw_dev->fw_status); + return -EPERM; + } + + prof_name = aw_dev_get_prof_name(aw_dev, aw_dev->set_prof); + if (!prof_name) + return -ENOMEM; + + dev_dbg(aw_dev->dev, "start update %s", prof_name); + + ret = aw883xx_dev_get_prof_data(aw_dev, aw_dev->set_prof, &set_prof_desc); + if (ret < 0) + return ret; + + /*update reg*/ + sec_desc = set_prof_desc->sec_desc; + ret = aw_dev_reg_update(aw_dev, sec_desc[AW_DATA_TYPE_REG].data, + sec_desc[AW_DATA_TYPE_REG].len); + if (ret < 0) { + dev_err(aw_dev->dev, "update reg failed"); + return ret; + } + + aw883xx_dev_mute(aw_dev, true); + + if (aw_dev->dsp_cfg == AW_DEV_DSP_WORK) + aw883xx_dev_dsp_enable(aw_dev, false); + + aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_OSC); + + if (up_dsp_fw_en) { + ret = aw_dev_sram_check(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "check sram failed"); + goto error; + } + + /*update dsp firmware*/ + dev_dbg(aw_dev->dev, "fw_ver: [%x]", set_prof_desc->fw_ver); + ret = aw_dev_dsp_fw_update(aw_dev, sec_desc[AW_DATA_TYPE_DSP_FW].data, + sec_desc[AW_DATA_TYPE_DSP_FW].len); + if (ret < 0) { + dev_err(aw_dev->dev, "update dsp fw failed"); + goto error; + } + } + + /*update dsp config*/ + ret = aw883xx_dev_dsp_cfg_update(aw_dev, sec_desc[AW_DATA_TYPE_DSP_CFG].data, + sec_desc[AW_DATA_TYPE_DSP_CFG].len); + if (ret < 0) { + dev_err(aw_dev->dev, "update dsp cfg failed"); + goto error; + } + + aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_PLL); + + aw_dev->cur_prof = aw_dev->set_prof; + + return 0; + +error: + aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_PLL); + + return ret; +} + +int aw883xx_dev_dsp_check(struct aw_device *aw_dev) +{ + int ret = -1; + u16 i = 0; + + switch (aw_dev->dsp_cfg) { + case AW_DEV_DSP_BYPASS: + dev_dbg(aw_dev->dev, "dsp bypass"); + ret = 0; + break; + case AW_DEV_DSP_WORK: + aw883xx_dev_dsp_enable(aw_dev, false); + aw883xx_dev_dsp_enable(aw_dev, true); + usleep_range(AW_1000_US, AW_1000_US + 10); + for (i = 0; i < AW_DEV_DSP_CHECK_MAX; i++) { + ret = aw883xx_dev_get_dsp_status(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "dsp wdt status error=%d", ret); + usleep_range(AW_2000_US, AW_2000_US + 10); + } + } + break; + default: + dev_err(aw_dev->dev, "unknown dsp cfg=%d", aw_dev->dsp_cfg); + ret = -EINVAL; + break; + } + + return ret; +} + +static void aw_dev_set_cfg_f0_fs(struct aw_device *aw_dev) +{ + u32 f0_fs = 0; + struct aw_cfgf0_fs_desc *cfgf0_fs_desc = &aw_dev->cfgf0_fs_desc; + int ret; + + if (aw_dev->ops.aw_set_cfg_f0_fs) { + aw_dev->ops.aw_set_cfg_f0_fs(aw_dev, &f0_fs); + ret = aw883xx_dev_modify_dsp_cfg(aw_dev, cfgf0_fs_desc->dsp_reg, + f0_fs, cfgf0_fs_desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "modify dsp cfg failed"); + return; + } + } +} + +static void aw_dev_cali_re_update(struct aw_cali_desc *cali_desc) +{ + int ret = 0; + struct aw_device *aw_dev = + container_of(cali_desc, struct aw_device, cali_desc); + + if (aw_dev->cali_desc.cali_re < AW_CALI_RE_MAX && + aw_dev->cali_desc.cali_re > AW_CALI_RE_MIN) { + if (aw_dev->ops.aw_set_cali_re) { + ret = aw_dev->ops.aw_set_cali_re(aw_dev); + if (ret < 0) + dev_err(aw_dev->dev, "set cali re failed"); + } else { + dev_err(aw_dev->dev, "cali_re:%d out of range, no set", + aw_dev->cali_desc.cali_re); + } + } +} + +int aw883xx_device_start(struct aw_device *aw_dev) +{ + int ret = -1; + + if (aw_dev->status == AW_DEV_PW_ON) { + dev_info(aw_dev->dev, "already power on"); + return 0; + } + + /*power on*/ + aw_dev_pwd(aw_dev, false); + usleep_range(AW_2000_US, AW_2000_US + 10); + + ret = aw883xx_dev_syspll_check(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "pll check failed cannot start"); + goto pll_check_fail; + } + + /*amppd on*/ + aw_dev_amppd(aw_dev, false); + usleep_range(AW_1000_US, AW_1000_US + 50); + + /*check i2s status*/ + ret = aw883xx_dev_sysst_check(aw_dev); + if (ret < 0) + goto sysst_check_fail; + + if (aw_dev->dsp_cfg == AW_DEV_DSP_WORK) { + /*dsp bypass*/ + aw883xx_dev_dsp_enable(aw_dev, false); + if (aw_dev->ops.aw_dsp_fw_check) { + ret = aw_dev->ops.aw_dsp_fw_check(aw_dev); + if (ret < 0) + goto dsp_fw_check_fail; + } + aw_dev_set_cfg_f0_fs(aw_dev); + + aw_dev_cali_re_update(&aw_dev->cali_desc); + + if (aw_dev->dsp_crc_st != AW_DSP_CRC_OK) { + ret = aw_dev_dsp_crc32_check(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "dsp crc check failed"); + goto crc_check_fail; + } + } + + ret = aw883xx_dev_dsp_check(aw_dev); + if (ret < 0) { + dev_err(aw_dev->dev, "check dsp status failed"); + goto dsp_check_fail; + } + } else { + dev_dbg(aw_dev->dev, "start pa with dsp bypass"); + } + + /*enable tx feedback*/ + if (aw_dev->ops.aw_i2s_tx_enable) + aw_dev->ops.aw_i2s_tx_enable(aw_dev, true); + + /*close mute*/ + aw883xx_dev_mute(aw_dev, false); + /*clear inturrupt*/ + aw883xx_dev_clear_int_status(aw_dev); + aw_dev->status = AW_DEV_PW_ON; + + return 0; + +dsp_check_fail: +crc_check_fail: + aw883xx_dev_dsp_enable(aw_dev, false); +dsp_fw_check_fail: +sysst_check_fail: + aw883xx_dev_clear_int_status(aw_dev); + aw_dev_amppd(aw_dev, true); +pll_check_fail: + aw_dev_pwd(aw_dev, true); + aw_dev->status = AW_DEV_PW_OFF; + return ret; +} + +int aw883xx_device_stop(struct aw_device *aw_dev) +{ + struct aw_sec_data_desc *dsp_cfg = + &aw_dev->prof_info.prof_desc[aw_dev->cur_prof].sec_desc[AW_DATA_TYPE_DSP_CFG]; + struct aw_sec_data_desc *dsp_fw = + &aw_dev->prof_info.prof_desc[aw_dev->cur_prof].sec_desc[AW_DATA_TYPE_DSP_FW]; + int int_st = 0; + int ret = 0; + + if (aw_dev->status == AW_DEV_PW_OFF) { + dev_info(aw_dev->dev, "already power off"); + return 0; + } + + aw_dev->status = AW_DEV_PW_OFF; + + /*set mute*/ + aw883xx_dev_mute(aw_dev, true); + usleep_range(AW_4000_US, AW_4000_US + 100); + + /*close tx feedback*/ + if (aw_dev->ops.aw_i2s_tx_enable) + aw_dev->ops.aw_i2s_tx_enable(aw_dev, false); + usleep_range(AW_1000_US, AW_1000_US + 100); + + /*check sysint state*/ + int_st = aw_dev_sysint_check(aw_dev); + + /*close dsp*/ + aw883xx_dev_dsp_enable(aw_dev, false); + + /*enable amppd*/ + aw_dev_amppd(aw_dev, true); + + if (int_st < 0) { + /*system status anomaly*/ + aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_OSC); + ret = aw_dev_dsp_fw_update(aw_dev, dsp_fw->data, dsp_fw->len); + if (ret < 0) + dev_err(aw_dev->dev, "update dsp fw failed"); + ret = aw883xx_dev_dsp_cfg_update(aw_dev, dsp_cfg->data, dsp_cfg->len); + if (ret < 0) + dev_err(aw_dev->dev, "update dsp cfg failed"); + aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_PLL); + } + + /*set power down*/ + aw_dev_pwd(aw_dev, true); + + return 0; +} + +/*deinit aw_device*/ +void aw883xx_dev_deinit(struct aw_device *aw_dev) +{ + if (!aw_dev) + return; + + if (aw_dev->prof_info.prof_desc) { + devm_kfree(aw_dev->dev, aw_dev->prof_info.prof_desc); + aw_dev->prof_info.prof_desc = NULL; + } + aw_dev->prof_info.count = 0; + + if (aw_dev->crc_dsp_cfg.data) { + aw_dev->crc_dsp_cfg.len = 0; + devm_kfree(aw_dev->dev, aw_dev->crc_dsp_cfg.data); + aw_dev->crc_dsp_cfg.data = NULL; + } + +} + +/*init aw_device*/ +int aw883xx_device_init(struct aw_device *aw_dev, struct aw_container *aw_cfg) +{ + int ret; + + if ((!aw_dev) || (!aw_cfg)) { + pr_err("aw_dev is NULL or aw_cfg is NULL"); + return -ENOMEM; + } + ret = aw883xx_dev_cfg_load(aw_dev, aw_cfg); + if (ret < 0) { + aw883xx_dev_deinit(aw_dev); + dev_err(aw_dev->dev, "aw_dev acf parse failed"); + return -EINVAL; + } + aw_dev->fade_in_time = AW_1000_US / 10; + aw_dev->fade_out_time = AW_1000_US >> 1; + + aw_dev->cur_prof = aw_dev->prof_info.prof_desc[0].id; + aw_dev->set_prof = aw_dev->prof_info.prof_desc[0].id; + ret = aw883xx_dev_fw_update(aw_dev, AW_FORCE_UPDATE_ON, + AW_DSP_FW_UPDATE_ON); + if (ret < 0) { + dev_err(aw_dev->dev, "fw update failed"); + return ret; + } + + /*set mute*/ + aw883xx_dev_mute(aw_dev, true); + usleep_range(AW_4000_US, AW_4000_US + 100); + + /*close tx feedback*/ + if (aw_dev->ops.aw_i2s_tx_enable) + aw_dev->ops.aw_i2s_tx_enable(aw_dev, false); + usleep_range(AW_1000_US, AW_1000_US + 100); + + /*close dsp*/ + aw883xx_dev_dsp_enable(aw_dev, false); + /*enable amppd*/ + aw_dev_amppd(aw_dev, true); + /*set power down*/ + aw_dev_pwd(aw_dev, true); + + return 0; +} + +static void aw883xx_parse_channel_dt(struct aw_device *aw_dev) +{ + int ret; + u32 channel_value; + struct device_node *np = aw_dev->dev->of_node; + + ret = of_property_read_u32(np, "sound-channel", &channel_value); + if (ret < 0) { + dev_dbg(aw_dev->dev, + "read sound-channel failed,use default 0"); + aw_dev->channel = AW_DEV_DEFAULT_CH; + return; + } + + dev_dbg(aw_dev->dev, "read sound-channel value is: %d", + channel_value); + aw_dev->channel = channel_value; +} + +static void aw883xx_parse_fade_enable_dt(struct aw_device *aw_dev) +{ + int ret = -1; + struct device_node *np = aw_dev->dev->of_node; + u32 fade_en; + + ret = of_property_read_u32(np, "fade-enable", &fade_en); + if (ret < 0) { + dev_dbg(aw_dev->dev, + "read fade-enable failed, close fade_in_out"); + fade_en = AW_FADE_IN_OUT_DEFAULT; + } else { + dev_dbg(aw_dev->dev, "read fade-enable value is: %d", fade_en); + } + + aw_dev->fade_en = fade_en; +} + +static void aw_device_parse_dt(struct aw_device *aw_dev) +{ + aw883xx_parse_channel_dt(aw_dev); + aw883xx_parse_fade_enable_dt(aw_dev); +} + +int aw883xx_device_probe(struct aw_device *aw_dev) +{ + aw_device_parse_dt(aw_dev); + + return 0; +} + +int aw883xx_request_firmware_file(struct aw883xx *aw883xx) +{ + const struct firmware *cont = NULL; + int ret = -1; + + aw883xx->aw_pa->fw_status = AW_DEV_FW_FAILED; + + ret = request_firmware(&cont, AW_ACF_FILE, aw883xx->dev); + if ((ret < 0) || (!cont)) { + dev_err(aw883xx->dev, "load [%s] failed!", AW_ACF_FILE); + return ret; + } + + dev_info(aw883xx->dev, "loaded %s - size: %zu", + AW_ACF_FILE, cont ? cont->size : 0); + + aw883xx->aw_cfg = vzalloc(cont->size + sizeof(int)); + if (!aw883xx->aw_cfg) { + release_firmware(cont); + return -ENOMEM; + } + aw883xx->aw_cfg->len = (int)cont->size; + memcpy(aw883xx->aw_cfg->data, cont->data, cont->size); + release_firmware(cont); + + ret = aw883xx_dev_load_acf_check(aw883xx->aw_cfg); + if (ret < 0) { + dev_err(aw883xx->dev, "Load [%s] failed ....!", AW_ACF_FILE); + vfree(aw883xx->aw_cfg); + aw883xx->aw_cfg = NULL; + return ret; + } + + dev_dbg(aw883xx->dev, "%s : bin load success\n", __func__); + + mutex_lock(&aw883xx->lock); + /*aw device init*/ + ret = aw883xx_device_init(aw883xx->aw_pa, aw883xx->aw_cfg); + if (ret < 0) { + dev_err(aw883xx->dev, "dev init failed"); + vfree(aw883xx->aw_cfg); + mutex_unlock(&aw883xx->lock); + return ret; + } + + mutex_unlock(&aw883xx->lock); + + return 0; +} + diff --git a/sound/soc/codecs/aw883xx/aw883xx_device.h b/sound/soc/codecs/aw883xx/aw883xx_device.h new file mode 100644 index 000000000000..505cef1fd3e6 --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_device.h @@ -0,0 +1,537 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_DEVICE_FILE_H__ +#define __AW883XX_DEVICE_FILE_H__ + +#include "aw883xx_data_type.h" +#include "aw883xx.h" + + +#define AW_DEV_DEFAULT_CH (0) +#define AW_DEV_DSP_CHECK_MAX (5) + +/* + * DSP I2C WRITES + */ +#define AW_DSP_I2C_WRITES +#define AW_MAX_RAM_WRITE_BYTE_SIZE (128) +#define AW_DSP_ODD_NUM_BIT_TEST (0x5555) +#define AW_DSP_EVEN_NUM_BIT_TEST (0xAAAA) +#define AW_DSP_ST_CHECK_MAX (2) +#define AW_FADE_IN_OUT_DEFAULT (0) +#define AW_CALI_DELAY_CACL(value) ((value * 32) / 48) +#define AW_CALI_RE_MAX (15000) +#define AW_CALI_RE_MIN (4000) + +#define AW_GET_MIN_VALUE(value1, value2) \ + ((value1) > (value2) ? (value2) : (value1)) + +#define AW_GET_MAX_VALUE(value1, value2) \ + ((value1) > (value2) ? (value1) : (value2)) + +#define AW_DSP_RE_TO_SHOW_RE(re, shift) (((re) * (1000)) >> (shift)) +#define AW_SHOW_RE_TO_DSP_RE(re, shift) (((re) << shift) / (1000)) + +#define AW_ACF_FILE "aw883xx_acf.bin" +#define AW_DEV_SYSST_CHECK_MAX (10) + +enum { + AW_EXT_DSP_WRITE_NONE = 0, + AW_EXT_DSP_WRITE, +}; + +struct aw_device; + +enum { + AW_DEV_VDSEL_DAC = 0, + AW_DEV_VDSEL_VSENSE = 1, +}; + +enum { + AW_DSP_CRC_NA = 0, + AW_DSP_CRC_OK = 1, +}; + +enum { + AW_DSP_FW_UPDATE_OFF = 0, + AW_DSP_FW_UPDATE_ON = 1, +}; + +enum { + AW_FORCE_UPDATE_OFF = 0, + AW_FORCE_UPDATE_ON = 1, +}; + +enum { + AW_1000_US = 1000, + AW_2000_US = 2000, + AW_3000_US = 3000, + AW_4000_US = 4000, + AW_5000_US = 5000, + AW_10000_US = 10000, + AW_100000_US = 100000, +}; + +enum { + AW_DEV_TYPE_OK = 0, + AW_DEV_TYPE_NONE = 1, +}; + + +enum AW_DEV_STATUS { + AW_DEV_PW_OFF = 0, + AW_DEV_PW_ON, +}; + +enum AW_DEV_FW_STATUS { + AW_DEV_FW_FAILED = 0, + AW_DEV_FW_OK, +}; + +enum AW_DEV_MEMCLK { + AW_DEV_MEMCLK_OSC = 0, + AW_DEV_MEMCLK_PLL = 1, +}; + +enum AW_DEV_DSP_CFG { + AW_DEV_DSP_WORK = 0, + AW_DEV_DSP_BYPASS = 1, +}; + +enum { + AW_DSP_16_DATA = 0, + AW_DSP_32_DATA = 1, +}; + +enum { + AW_NOT_RCV_MODE = 0, + AW_RCV_MODE = 1, +}; + +struct aw_device_ops { + int (*aw_i2c_writes)(struct regmap *map, unsigned int reg_addr, + const void *val, size_t val_len); + int (*aw_i2c_write)(struct regmap *map, unsigned int reg, unsigned int val); + int (*aw_i2c_read)(struct regmap *map, unsigned int reg, unsigned int *val); + + int (*aw_reg_write)(struct regmap *map, unsigned int reg, unsigned int val); + int (*aw_reg_read)(struct regmap *map, unsigned int reg, unsigned int *val); + int (*aw_reg_write_bits)(struct regmap *map, unsigned int reg, + unsigned int mask, unsigned int val); + + int (*aw_dsp_write)(struct aw_device *aw_dev, + unsigned short dsp_addr, + unsigned int reg_data, + unsigned char data_type); + int (*aw_dsp_read)(struct aw_device *aw_dev, + unsigned short dsp_addr, + unsigned int *dsp_data, + unsigned char data_type); + int (*aw_dsp_write_bits)(struct aw_device *aw_dev, unsigned short dsp_addr, + unsigned short mask, unsigned short dsp_data); + + int (*aw_set_hw_volume)(struct aw_device *aw_dev, unsigned short value); + int (*aw_get_hw_volume)(struct aw_device *aw_dev, unsigned short *value); + unsigned int (*aw_reg_val_to_db)(unsigned int value); + + void (*aw_i2s_tx_enable)(struct aw_device *aw_dev, bool flag); + + bool (*aw_check_wr_access)(int reg); + int (*aw_get_reg_num)(void); + int (*aw_get_version)(char *buf, int size); + int (*aw_read_dsp_pid)(struct aw_device *aw_dev); + void (*aw_set_cfg_f0_fs)(struct aw_device *aw_dev, unsigned int *f0_fs); + int (*aw_dsp_fw_check)(struct aw_device *aw_dev); + int (*aw_set_cali_re)(struct aw_device *aw_dev); +}; + +struct aw_int_desc { + unsigned int mask_reg; /*interrupt mask reg*/ + unsigned int st_reg; /*interrupt status reg*/ + unsigned int mask_default; /*default mask close all*/ + unsigned int int_mask; /*set mask*/ + unsigned int intst_mask; /*interrupt check mask*/ + u16 sysint_st; /*interrupt reg status*/ +}; + +struct aw_pwd_desc { + unsigned int reg; + unsigned int mask; + unsigned int enable; + unsigned int disable; +}; + +struct aw_vcalb_desc { + unsigned int icalk_reg; + unsigned int icalk_reg_mask; + unsigned int icalk_sign_mask; + unsigned int icalk_neg_mask; + int icalk_value_factor; + + unsigned int vcalk_reg; + unsigned int vcalk_reg_mask; + unsigned int vcalk_sign_mask; + unsigned int vcalk_neg_mask; + unsigned int vcalk_shift; + int vcalk_value_factor; + + unsigned int vcalb_dsp_reg; + unsigned char data_type; + int cabl_base_value; + int vcal_factor; + int vscal_factor; + int iscal_factor; + + unsigned int vcalb_adj_shift; + + unsigned int vcalb_vsense_reg; + int vscal_factor_vsense_in; + int vcalk_value_factor_vsense_in; + unsigned int vcalk_dac_shift; + unsigned int vcalk_dac_mask; + unsigned int vcalk_dac_neg_mask; + unsigned int vcalk_vdsel_mask; +}; + +struct aw_mute_desc { + unsigned int reg; + unsigned int mask; + unsigned int enable; + unsigned int disable; +}; + +struct aw_sysst_desc { + unsigned int reg; + unsigned int st_check; + unsigned int st_mask; + unsigned int pll_check; + unsigned int dsp_check; + unsigned int dsp_mask; +}; + +struct aw_profctrl_desc { + unsigned int reg; + unsigned int mask; + unsigned int rcv_mode_val; + unsigned int cur_mode; +}; + +struct aw_volume_desc { + unsigned int reg; + unsigned int mask; + unsigned int shift; + unsigned int init_volume; + unsigned int mute_volume; + unsigned int ctl_volume; + unsigned int max_volume; +}; + +struct aw_dsp_en_desc { + unsigned int reg; + unsigned int mask; + unsigned int enable; + unsigned int disable; +}; + +struct aw_memclk_desc { + unsigned int reg; + unsigned int mask; + unsigned int mcu_hclk; + unsigned int osc_clk; +}; + +struct aw_watch_dog_desc { + unsigned int reg; + unsigned int mask; +}; + +struct aw_dsp_mem_desc { + unsigned int dsp_madd_reg; + unsigned int dsp_mdat_reg; + unsigned int dsp_fw_base_addr; + unsigned int dsp_cfg_base_addr; +}; + +struct aw_voltage_desc { + unsigned int reg; + unsigned int vbat_range; + unsigned int int_bit; +}; + +struct aw_temperature_desc { + unsigned int reg; + unsigned int sign_mask; + unsigned int neg_mask; +}; + +struct aw_ipeak_desc { + unsigned int reg; + unsigned int mask; +}; + +struct aw_vmax_desc { + unsigned int dsp_reg; + unsigned char data_type; + unsigned int init_vmax; +}; + +struct aw_soft_rst { + u8 reg; + u16 reg_value; +}; + +struct aw_cali_cfg_desc { + unsigned int actampth_reg; + unsigned char actampth_data_type; + + unsigned int noiseampth_reg; + unsigned char noiseampth_data_type; + + unsigned int ustepn_reg; + unsigned char ustepn_data_type; + + unsigned int alphan_reg; + unsigned int alphan_data_type; +}; + +struct aw_dsp_vol_desc { + unsigned int reg; + unsigned int mute_st; + unsigned int noise_st; + unsigned int mask; +}; + +struct aw_amppd_desc { + unsigned int reg; + unsigned int mask; + unsigned int enable; + unsigned int disable; +}; + +struct aw_f0_desc { + unsigned int dsp_reg; + unsigned char data_type; + unsigned int shift; +}; + +struct aw_cfgf0_fs_desc { + unsigned int dsp_reg; + unsigned char data_type; +}; + +struct aw_q_desc { + unsigned int dsp_reg; + unsigned char data_type; + unsigned int shift; +}; + +struct aw_ra_desc { + unsigned int dsp_reg; + unsigned char data_type; +}; + +struct aw_noise_desc { + unsigned int dsp_reg; + unsigned char data_type; + unsigned int mask; +}; + +struct aw_ste_re_desc { + unsigned int dsp_reg; + unsigned char data_type; + unsigned int shift; +}; + +struct aw_adpz_re_desc { + unsigned int dsp_reg; + unsigned char data_type; + unsigned int shift; +}; + +struct aw_adpz_t0_desc { + unsigned int dsp_reg; + unsigned char data_type; + u16 coilalpha_reg; + unsigned char coil_type; +}; + +struct aw_spkr_temp_desc { + unsigned int reg; +}; + +struct aw_dsp_crc_desc { + unsigned int ctl_reg; + unsigned int ctl_mask; + unsigned int ctl_enable; + unsigned int ctl_disable; + + unsigned int dsp_reg; + unsigned char data_type; +}; + +struct aw_cco_mux_desc { + unsigned int reg; + unsigned int mask; + unsigned int divider; + unsigned int bypass; +}; + +struct aw_hw_temp_desc { + unsigned int dsp_reg; + unsigned char data_type; +}; + +struct aw_cali_delay_desc { + unsigned int dsp_reg; + unsigned char data_type; + unsigned int delay; +}; + +struct aw_chansel_desc { + unsigned int rxchan_reg; + unsigned int rxchan_mask; + unsigned int txchan_reg; + unsigned int txchan_mask; + + unsigned int rx_left; + unsigned int rx_right; + unsigned int tx_left; + unsigned int tx_right; +}; + +struct aw_tx_en_desc { + unsigned int tx_en_mask; + unsigned int tx_disable; +}; + +struct aw_dsp_st { + unsigned int dsp_reg_s1; + unsigned int dsp_reg_e1; + + unsigned int dsp_reg_s2; + unsigned int dsp_reg_e2; +}; + +struct aw_cali_desc { + u32 cali_re; /*cali value*/ + u32 ra; +}; + +struct aw_container { + int len; + u8 data[]; +}; + +struct aw_device { + int status; + struct mutex *dsp_lock; + + unsigned char cur_prof; /*current profile index*/ + unsigned char set_prof; /*set profile index*/ + unsigned char dsp_crc_st; + u16 chip_id; + + unsigned int channel; /*pa channel select*/ + unsigned int fade_step; + + struct i2c_client *i2c; + struct device *dev; + char *acf; + void *private_data; + + u32 fade_en; + unsigned char dsp_cfg; + + u32 dsp_fw_len; + u32 dsp_cfg_len; + u8 platform; + u8 fw_status; /*load cfg status*/ + + unsigned int fade_in_time; + unsigned int fade_out_time; + + struct aw_prof_info prof_info; + struct aw_sec_data_desc crc_dsp_cfg; + struct aw_int_desc int_desc; + struct aw_pwd_desc pwd_desc; + struct aw_mute_desc mute_desc; + struct aw_vcalb_desc vcalb_desc; + struct aw_sysst_desc sysst_desc; + struct aw_profctrl_desc profctrl_desc; + struct aw_volume_desc volume_desc; + struct aw_dsp_en_desc dsp_en_desc; + struct aw_memclk_desc memclk_desc; + struct aw_watch_dog_desc watch_dog_desc; + struct aw_dsp_mem_desc dsp_mem_desc; + struct aw_voltage_desc voltage_desc; + struct aw_temperature_desc temp_desc; + struct aw_vmax_desc vmax_desc; + struct aw_ipeak_desc ipeak_desc; + struct aw_soft_rst soft_rst; + struct aw_cali_cfg_desc cali_cfg_desc; + struct aw_ra_desc ra_desc; + struct aw_dsp_vol_desc dsp_vol_desc; + struct aw_noise_desc noise_desc; + struct aw_f0_desc f0_desc; + struct aw_cfgf0_fs_desc cfgf0_fs_desc; + struct aw_q_desc q_desc; + struct aw_ste_re_desc ste_re_desc; + struct aw_adpz_re_desc adpz_re_desc; + struct aw_adpz_t0_desc t0_desc; + struct aw_amppd_desc amppd_desc; + struct aw_spkr_temp_desc spkr_temp_desc; + struct aw_dsp_crc_desc dsp_crc_desc; + struct aw_cco_mux_desc cco_mux_desc; + struct aw_hw_temp_desc hw_temp_desc; + + struct aw_chansel_desc chansel_desc; + struct aw_tx_en_desc tx_en_desc; + struct aw_cali_delay_desc cali_delay_desc; + struct aw_dsp_st dsp_st_desc; + struct aw_cali_desc cali_desc; + + struct aw_device_ops ops; +}; + +void aw883xx_dev_deinit(struct aw_device *aw_dev); +int aw883xx_device_init(struct aw_device *aw_dev, struct aw_container *aw_prof); +int aw883xx_device_start(struct aw_device *aw_dev); +int aw883xx_device_stop(struct aw_device *aw_dev); + +int aw883xx_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en); + +int aw883xx_device_probe(struct aw_device *aw_dev); +int aw883xx_device_remove(struct aw_device *aw_dev); +int aw883xx_dev_syspll_check(struct aw_device *aw_dev); +int aw883xx_dev_get_dsp_status(struct aw_device *aw_dev); + +int aw883xx_dev_get_hmute(struct aw_device *aw_dev); +int aw883xx_dev_sysst_check(struct aw_device *aw_dev); + +int aw883xx_dev_dsp_check(struct aw_device *aw_dev); +void aw883xx_dev_memclk_select(struct aw_device *aw_dev, unsigned char flag); + +void aw883xx_dev_dsp_enable(struct aw_device *aw_dev, bool dsp); + +void aw883xx_dev_mute(struct aw_device *aw_dev, bool mute); +int aw883xx_dev_dsp_fw_update(struct aw_device *aw_dev, + unsigned char *data, unsigned int len); +int aw883xx_dev_dsp_cfg_update(struct aw_device *aw_dev, + unsigned char *data, unsigned int len); +int aw883xx_dev_modify_dsp_cfg(struct aw_device *aw_dev, + unsigned int addr, unsigned int dsp_data, unsigned char data_type); +int aw883xx_dev_get_iis_status(struct aw_device *aw_dev); + +int aw883xx_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol); +int aw883xx_dev_get_volume(struct aw_device *aw_dev, unsigned short *get_vol); +int aw883xx_request_firmware_file(struct aw883xx *aw883xx); + +#endif +

From: Weidong Wang wangweidong.a@awinic.com

The Awinic AW883XX is an I2S/TDM input, high efficiency digital Smart K audio amplifier with an integrated 10.25V smart boost convert

Signed-off-by: Nick Li liweilei@awinic.com Signed-off-by: Bruce zhao zhaolei@awinic.com Signed-off-by: Weidong Wang wangweidong.a@awinic.com --- sound/soc/codecs/Kconfig | 10 + sound/soc/codecs/Makefile | 7 + sound/soc/codecs/aw883xx/aw883xx_data_type.h | 146 ++ sound/soc/codecs/aw883xx/aw883xx_init.c | 615 +++++ .../soc/codecs/aw883xx/aw883xx_pid_2049_reg.h | 2300 +++++++++++++++++ 5 files changed, 3078 insertions(+) create mode 100644 sound/soc/codecs/aw883xx/aw883xx_data_type.h create mode 100644 sound/soc/codecs/aw883xx/aw883xx_init.c create mode 100644 sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 7022e6286e6c..f14e0a78acd4 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -54,6 +54,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_ALC5623 imply SND_SOC_ALC5632 imply SND_SOC_AW8738 + imply SND_SOC_AW883XX imply SND_SOC_BT_SCO imply SND_SOC_BD28623 imply SND_SOC_CQ0093VC @@ -2161,4 +2162,13 @@ config SND_SOC_LPASS_TX_MACRO select SND_SOC_LPASS_MACRO_COMMON tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)"

+config SND_SOC_AW883XX + tristate "Soc Audio for awinic aw883xx series" + depends on I2C + help + this option enables support for aw883xx series Smart PA. + The Awinic AW883XX is an I2S/TDM input, high efficiency + digital Smart K audio amplifier with an integrated 10V + smart boost convert. + endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9170ee1447dd..858ca24ad398 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -357,6 +357,11 @@ snd-soc-tas2780-objs := tas2780.o # Mux snd-soc-simple-mux-objs := simple-mux.o

+snd_soc_aw883xx-objs := aw883xx/aw883xx.o \ + aw883xx/aw883xx_init.o \ + aw883xx/aw883xx_device.o \ + aw883xx/aw883xx_bin_parse.o \ + obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o @@ -719,3 +724,5 @@ obj-$(CONFIG_SND_SOC_LPASS_TX_MACRO) += snd-soc-lpass-tx-macro.o

# Mux obj-$(CONFIG_SND_SOC_SIMPLE_MUX) += snd-soc-simple-mux.o + +obj-$(CONFIG_SND_SOC_AW883XX) +=snd_soc_aw883xx.o diff --git a/sound/soc/codecs/aw883xx/aw883xx_data_type.h b/sound/soc/codecs/aw883xx/aw883xx_data_type.h new file mode 100644 index 000000000000..3aacf5eedde6 --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_data_type.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_DATA_TYPE_H__ +#define __AW883XX_DATA_TYPE_H__ + +/* + * aw profile + */ +#define PROJECT_NAME_MAX (24) +#define CUSTOMER_NAME_MAX (16) +#define CFG_VERSION_MAX (4) +#define DEV_NAME_MAX (16) +#define PROFILE_STR_MAX (32) + +#define ACF_FILE_ID (0xa15f908) + +enum aw_cfg_hdr_version { + AW_CFG_HDR_VER_0_0_0_1 = 0x00000001, + AW_CFG_HDR_VER_1_0_0_0 = 0x01000000, +}; + +enum aw_cfg_dde_type { + AW_DEV_NONE_TYPE_ID = 0xFFFFFFFF, + AW_DEV_TYPE_ID = 0x00000000, + AW_SKT_TYPE_ID = 0x00000001, + AW_DEV_DEFAULT_TYPE_ID = 0x00000002, +}; + +enum aw_sec_type { + ACF_SEC_TYPE_REG = 0, + ACF_SEC_TYPE_DSP, + ACF_SEC_TYPE_DSP_CFG, + ACF_SEC_TYPE_DSP_FW, + ACF_SEC_TYPE_HDR_REG, + ACF_SEC_TYPE_HDR_DSP_CFG, + ACF_SEC_TYPE_HDR_DSP_FW, + ACF_SEC_TYPE_MUTLBIN, + ACF_SEC_TYPE_SKT_PROJECT, + ACF_SEC_TYPE_DSP_PROJECT, + ACF_SEC_TYPE_MONITOR, + ACF_SEC_TYPE_MAX, +}; + +enum profile_data_type { + AW_DATA_TYPE_REG = 0, + AW_DATA_TYPE_DSP_CFG, + AW_DATA_TYPE_DSP_FW, + AW_DATA_TYPE_MAX, +}; + +enum aw_prof_type { + AW_PROFILE_MUSIC = 0, + AW_PROFILE_VOICE, + AW_PROFILE_VOIP, + AW_PROFILE_RINGTONE, + AW_PROFILE_RINGTONE_HS, + AW_PROFILE_LOWPOWER, + AW_PROFILE_BYPASS, + AW_PROFILE_MMI, + AW_PROFILE_FM, + AW_PROFILE_NOTIFICATION, + AW_PROFILE_RECEIVER, + AW_PROFILE_MAX, +}; + +enum aw_profile_status { + AW_PROFILE_WAIT = 0, + AW_PROFILE_OK, +}; + +struct aw_cfg_hdr { + u32 a_id; /*acf file ID 0xa15f908*/ + char a_project[PROJECT_NAME_MAX]; /*project name*/ + char a_custom[CUSTOMER_NAME_MAX]; /*custom name :huawei xiaomi vivo oppo*/ + char a_version[CFG_VERSION_MAX]; /*author update version*/ + u32 a_author_id; /*author id*/ + u32 a_ddt_size; /*sub section table entry size*/ + u32 a_ddt_num; /*sub section table entry num*/ + u32 a_hdr_offset; /*sub section table offset in file*/ + u32 a_hdr_version; /*sub section table version*/ + u32 reserve[3]; +}; + +struct aw_cfg_dde { + u32 type; /*DDE type id*/ + char dev_name[DEV_NAME_MAX]; + u16 dev_index; /*dev id*/ + u16 dev_bus; /*dev bus id*/ + u16 dev_addr; /*dev addr id*/ + u16 dev_profile; /*dev profile id*/ + u32 data_type; /*data type id*/ + u32 data_size; + u32 data_offset; + u32 data_crc; + u32 reserve[5]; +}; + +struct aw_cfg_dde_v_1_0_0_0 { + u32 type; /*DDE type id*/ + char dev_name[DEV_NAME_MAX]; + u16 dev_index; /*dev id*/ + u16 dev_bus; /*dev bus id*/ + u16 dev_addr; /*dev addr id*/ + u16 dev_profile; /*dev profile id*/ + u32 data_type; /*data type id*/ + u32 data_size; + u32 data_offset; + u32 data_crc; + char dev_profile_str[PROFILE_STR_MAX]; + u32 chip_id; + u32 reserve[4]; +}; + +struct aw_sec_data_desc { + u32 len; + unsigned char *data; +}; + +struct aw_prof_desc { + u32 id; + u32 prof_st; + char *prf_str; + u32 fw_ver; + struct aw_sec_data_desc sec_desc[AW_DATA_TYPE_MAX]; +}; + +struct aw_all_prof_info { + struct aw_prof_desc prof_desc[AW_PROFILE_MAX]; +}; + +struct aw_prof_info { + int count; + int prof_type; + char **prof_name_list; + struct aw_prof_desc *prof_desc; +}; + +#endif + diff --git a/sound/soc/codecs/aw883xx/aw883xx_init.c b/sound/soc/codecs/aw883xx/aw883xx_init.c new file mode 100644 index 000000000000..2ef62fdebb57 --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_init.c @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/firmware.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/regmap.h> +#include <linux/syscalls.h> +#include <linux/uaccess.h> +#include <linux/version.h> +#include <linux/workqueue.h> +#include <sound/control.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include "aw883xx.h" +#include "aw883xx_bin_parse.h" +#include "aw883xx_pid_2049_reg.h" + +static const unsigned char aw_pid_2049_reg_access[AW_PID_2049_REG_MAX] = { + [AW_PID_2049_ID_REG] = (REG_RD_ACCESS), + [AW_PID_2049_SYSST_REG] = (REG_RD_ACCESS), + [AW_PID_2049_SYSINT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_SYSINTM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SYSCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCCFG7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_MPDCFG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PWMCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_I2SCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DBGCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_HAGCST_REG] = (REG_RD_ACCESS), + [AW_PID_2049_VBAT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TEMP_REG] = (REG_RD_ACCESS), + [AW_PID_2049_PVDD_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ISNDAT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_VSNDAT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_I2SINT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_I2SCAPCNT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA1_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA2_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA3_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ANASTA4_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TESTDET_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TESTIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_TESTOUT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_DSPMADD_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSPMDAT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_WDT_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ACR1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ACR2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ASR1_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ASR2_REG] = (REG_RD_ACCESS), + [AW_PID_2049_DSPCFG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ASR3_REG] = (REG_RD_ACCESS), + [AW_PID_2049_ASR4_REG] = (REG_RD_ACCESS), + [AW_PID_2049_VSNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_ISNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PLLCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PLLCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_PLLCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_CDACTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_CDACTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SADCCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_SADCCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_CPCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_BSTCTRL7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_DSMCFG8_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_TESTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_TESTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWM2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWM1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFWL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), + [AW_PID_2049_EFRH_REG] = (REG_RD_ACCESS), + [AW_PID_2049_EFRM2_REG] = (REG_RD_ACCESS), + [AW_PID_2049_EFRM1_REG] = (REG_RD_ACCESS), + [AW_PID_2049_EFRL_REG] = (REG_RD_ACCESS), + [AW_PID_2049_TM_REG] = (REG_NONE_ACCESS), +}; + +static int aw883xx_dev_dsp_write(struct aw_device *aw_dev, + unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_dsp_write(aw883xx, dsp_addr, dsp_data, data_type); +} + +static int aw883xx_dev_dsp_read(struct aw_device *aw_dev, + unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_dsp_read(aw883xx, dsp_addr, dsp_data, data_type); +} + +/* + * aw883xx i2c write/read + */ +/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB real_value = value * 8 : 0.125db --> 1*/ +static unsigned int aw_pid_2049_reg_val_to_db(unsigned int value) +{ + return (((value >> AW_PID_2049_VOL_6DB_START) * AW_PID_2049_VOLUME_STEP_DB) + + ((value & 0x3f) % AW_PID_2049_VOLUME_STEP_DB)); +} + +/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB reg_value = value / step << 6 + value % step ; step = 6 * 8*/ +static unsigned short aw_pid_2049_db_val_to_reg(unsigned short value) +{ + return (((value / AW_PID_2049_VOLUME_STEP_DB) << AW_PID_2049_VOL_6DB_START) + + (value % AW_PID_2049_VOLUME_STEP_DB)); +} + +static int aw883xx_set_volume(struct aw883xx *aw883xx, unsigned short value) +{ + unsigned int reg_value = 0; + u16 real_value = 0; + u16 volume = 0; + struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc; + + volume = AW_GET_MIN_VALUE(value, vol_desc->mute_volume); + real_value = aw_pid_2049_db_val_to_reg(volume); + + /* cal real value */ + regmap_read(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, &reg_value); + + dev_dbg(aw883xx->dev, "value 0x%x , reg:0x%x", value, real_value); + + /*[15 : 6] volume*/ + real_value = (real_value << AW_PID_2049_VOL_START_BIT) | (reg_value & AW_PID_2049_VOL_MASK); + + /* write value */ + regmap_write(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, real_value); + + return 0; +} + +static int aw883xx_get_volume(struct aw883xx *aw883xx, unsigned short *value) +{ + unsigned int reg_value = 0; + u16 real_value = 0; + + /* read value */ + regmap_read(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, &reg_value); + + /*[15 : 6] volume*/ + real_value = reg_value >> AW_PID_2049_VOL_START_BIT; + + real_value = aw_pid_2049_reg_val_to_db(real_value); + + *value = real_value; + + return 0; +} + +static int aw_pid_2049_set_volume(struct aw_device *aw_dev, unsigned short value) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_set_volume(aw883xx, value); +} + +static int aw_pid_2049_get_volume(struct aw_device *aw_dev, unsigned short *value) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + return aw883xx_get_volume(aw883xx, value); +} + +static void aw_pid_2049_i2s_tx_enable(struct aw_device *aw_dev, bool flag) +{ + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + if (flag) { + regmap_update_bits(aw883xx->regmap, AW_PID_2049_I2SCFG1_REG, + ~AW_PID_2049_I2STXEN_MASK, + AW_PID_2049_I2STXEN_ENABLE_VALUE); + } else { + regmap_update_bits(aw883xx->regmap, AW_PID_2049_I2SCFG1_REG, + ~AW_PID_2049_I2STXEN_MASK, + AW_PID_2049_I2STXEN_DISABLE_VALUE); + } +} + +static void aw_pid_2049_set_cfg_f0_fs(struct aw_device *aw_dev, unsigned int *f0_fs) +{ + unsigned int rate_data = 0; + u32 fs = 0; + struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data; + + regmap_read(aw883xx->regmap, AW_PID_2049_I2SCTRL_REG, &rate_data); + + switch (rate_data & (~AW_PID_2049_I2SSR_MASK)) { + case AW_PID_2049_I2SSR_8_KHZ_VALUE: + fs = 8000; + break; + case AW_PID_2049_I2SSR_16_KHZ_VALUE: + fs = 16000; + break; + case AW_PID_2049_I2SSR_32_KHZ_VALUE: + fs = 32000; + break; + case AW_PID_2049_I2SSR_44_KHZ_VALUE: + fs = 44000; + break; + case AW_PID_2049_I2SSR_48_KHZ_VALUE: + fs = 48000; + break; + case AW_PID_2049_I2SSR_96_KHZ_VALUE: + fs = 96000; + break; + case AW_PID_2049_I2SSR_192KHZ_VALUE: + fs = 192000; + break; + default: + fs = 48000; + dev_err(aw883xx->dev, + "rate can not support, use default 48k"); + break; + } + + dev_dbg(aw883xx->dev, "get i2s fs:%d", fs); + *f0_fs = fs / 8; + + aw883xx_dsp_write(aw883xx, + AW_PID_2049_DSP_REG_CFGF0_FS, *f0_fs, AW_DSP_32_DATA); +} + +static bool aw_pid_2049_check_wr_access(int reg) +{ + if (reg >= AW_PID_2049_REG_MAX) + return false; + + if (aw_pid_2049_reg_access[reg] & REG_WR_ACCESS) + return true; + else + return false; +} + +static int aw_pid_2049_get_reg_num(void) +{ + return AW_PID_2049_REG_MAX; +} + +static int aw_pid_2049_dsp_fw_check(struct aw_device *aw_dev) +{ + struct aw_prof_desc *set_prof_desc = NULL; + struct aw_sec_data_desc *dsp_fw_desc = NULL; + u16 base_addr = AW_PID_2049_DSP_FW_ADDR; + u16 addr = base_addr; + int ret, i; + u32 dsp_val; + u16 bin_val; + + ret = aw883xx_dev_get_prof_data(aw_dev, aw_dev->cur_prof, &set_prof_desc); + if (ret < 0) + return ret; + + /*update reg*/ + dsp_fw_desc = &set_prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW]; + + for (i = 0; i < AW_FW_CHECK_PART; i++) { + ret = aw883xx_dev_dsp_read(aw_dev, addr, &dsp_val, AW_DSP_16_DATA); + if (ret < 0) { + dev_err(aw_dev->dev, "dsp read failed"); + return ret; + } + + bin_val = be16_to_cpup((void *)&dsp_fw_desc->data[2 * (addr - base_addr)]); + + if (dsp_val != bin_val) { + dev_err(aw_dev->dev, "check failed, addr[0x%x], read[0x%x] != bindata[0x%x]", + addr, dsp_val, bin_val); + return -EINVAL; + } + + addr += (dsp_fw_desc->len / 2) / AW_FW_CHECK_PART; + if ((addr - base_addr) > dsp_fw_desc->len) { + dev_err(aw_dev->dev, "check failed, addr[0x%x] too large", addr); + return -EINVAL; + } + } + + return 0; +} + +static int aw_pid_2049_set_cali_re_to_dsp(struct aw_device *aw_dev) +{ + struct aw_adpz_re_desc *adpz_re_desc = &aw_dev->adpz_re_desc; + u32 cali_re = 0; + int ret = 0; + + cali_re = AW_SHOW_RE_TO_DSP_RE((aw_dev->cali_desc.cali_re + + aw_dev->cali_desc.ra), adpz_re_desc->shift); + + /* set cali re to aw883xx */ + ret = aw_dev->ops.aw_dsp_write(aw_dev, + adpz_re_desc->dsp_reg, cali_re, adpz_re_desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "set cali re error"); + return ret; + } + + ret = aw883xx_dev_modify_dsp_cfg(aw_dev, adpz_re_desc->dsp_reg, + cali_re, adpz_re_desc->data_type); + if (ret < 0) { + dev_err(aw_dev->dev, "modify dsp cfg failed"); + return ret; + } + + return ret; + +} + +static int aw883xx_pid_2049_dev_init(struct aw883xx *aw883xx) +{ + struct aw_device *aw_pa = NULL; + + aw_pa = devm_kzalloc(aw883xx->dev, sizeof(struct aw_device), GFP_KERNEL); + if (!aw_pa) + return -ENOMEM; + + /*call aw device init func*/ + aw_pa->acf = NULL; + aw_pa->prof_info.prof_desc = NULL; + aw_pa->prof_info.count = 0; + aw_pa->prof_info.prof_type = AW_DEV_NONE_TYPE_ID; + aw_pa->channel = 0; + aw_pa->dsp_lock = &aw883xx->dsp_lock; + aw_pa->i2c = aw883xx->i2c; + aw_pa->fw_status = AW_DEV_FW_FAILED; + aw_pa->fade_step = AW_PID_2049_VOLUME_STEP_DB; + + aw_pa->chip_id = aw883xx->chip_id; + aw_pa->private_data = (void *)aw883xx; + aw_pa->dev = aw883xx->dev; + aw_pa->ops.aw_i2c_writes = regmap_raw_write; + aw_pa->ops.aw_i2c_write = regmap_write; + aw_pa->ops.aw_reg_write = regmap_write; + aw_pa->ops.aw_reg_write_bits = regmap_update_bits; + aw_pa->ops.aw_i2c_read = regmap_read; + aw_pa->ops.aw_reg_read = regmap_read; + aw_pa->ops.aw_dsp_read = aw883xx_dev_dsp_read; + aw_pa->ops.aw_dsp_write = aw883xx_dev_dsp_write; + + aw_pa->ops.aw_get_hw_volume = aw_pid_2049_get_volume; + aw_pa->ops.aw_set_hw_volume = aw_pid_2049_set_volume; + aw_pa->ops.aw_reg_val_to_db = aw_pid_2049_reg_val_to_db; + + aw_pa->ops.aw_check_wr_access = aw_pid_2049_check_wr_access; + aw_pa->ops.aw_get_reg_num = aw_pid_2049_get_reg_num; + + aw_pa->ops.aw_i2s_tx_enable = aw_pid_2049_i2s_tx_enable; + + aw_pa->ops.aw_set_cfg_f0_fs = aw_pid_2049_set_cfg_f0_fs; + aw_pa->ops.aw_dsp_fw_check = aw_pid_2049_dsp_fw_check; + + aw_pa->ops.aw_set_cali_re = aw_pid_2049_set_cali_re_to_dsp; + + aw_pa->int_desc.mask_reg = AW_PID_2049_SYSINTM_REG; + aw_pa->int_desc.mask_default = AW_PID_2049_SYSINTM_DEFAULT; + aw_pa->int_desc.int_mask = AW_PID_2049_SYSINTM_DEFAULT; + aw_pa->int_desc.st_reg = AW_PID_2049_SYSINT_REG; + aw_pa->int_desc.intst_mask = AW_PID_2049_BIT_SYSINT_CHECK; + + aw_pa->pwd_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->pwd_desc.mask = AW_PID_2049_PWDN_MASK; + aw_pa->pwd_desc.enable = AW_PID_2049_PWDN_POWER_DOWN_VALUE; + aw_pa->pwd_desc.disable = AW_PID_2049_PWDN_WORKING_VALUE; + + aw_pa->mute_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->mute_desc.mask = AW_PID_2049_HMUTE_MASK; + aw_pa->mute_desc.enable = AW_PID_2049_HMUTE_ENABLE_VALUE; + aw_pa->mute_desc.disable = AW_PID_2049_HMUTE_DISABLE_VALUE; + + aw_pa->vcalb_desc.vcalb_dsp_reg = AW_PID_2049_DSP_REG_VCALB; + aw_pa->vcalb_desc.data_type = AW_DSP_16_DATA; + aw_pa->vcalb_desc.vcal_factor = AW_PID_2049_VCAL_FACTOR; + aw_pa->vcalb_desc.cabl_base_value = AW_PID_2049_CABL_BASE_VALUE; + aw_pa->vcalb_desc.vscal_factor = AW_PID_2049_VSCAL_FACTOR; + aw_pa->vcalb_desc.iscal_factor = AW_PID_2049_ISCAL_FACTOR; + + aw_pa->vcalb_desc.vcalb_adj_shift = AW_PID_2049_VCALB_ADJ_FACTOR; + + aw_pa->vcalb_desc.icalk_value_factor = AW_PID_2049_ICABLK_FACTOR; + aw_pa->vcalb_desc.icalk_reg = AW_PID_2049_EFRM2_REG; + aw_pa->vcalb_desc.icalk_reg_mask = AW_PID_2049_EF_ISN_GESLP_MASK; + aw_pa->vcalb_desc.icalk_sign_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_MASK; + aw_pa->vcalb_desc.icalk_neg_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_NEG; + + aw_pa->vcalb_desc.vcalk_reg = AW_PID_2049_EFRH_REG; + aw_pa->vcalb_desc.vcalk_reg_mask = AW_PID_2049_EF_VSN_GESLP_MASK; + aw_pa->vcalb_desc.vcalk_sign_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_MASK; + aw_pa->vcalb_desc.vcalk_neg_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_NEG; + aw_pa->vcalb_desc.vcalk_value_factor = AW_PID_2049_VCABLK_FACTOR; + aw_pa->vcalb_desc.vcalk_shift = AW_PID_2049_EF_VSENSE_GAIN_SHIFT; + + aw_pa->vcalb_desc.vcalb_vsense_reg = AW_PID_2049_I2SCFG3_REG; + aw_pa->vcalb_desc.vcalk_vdsel_mask = AW_PID_2049_VDSEL_MASK; + aw_pa->vcalb_desc.vcalk_value_factor_vsense_in = AW_PID_2049_VCABLK_FACTOR_DAC; + aw_pa->vcalb_desc.vscal_factor_vsense_in = AW_PID_2049_VSCAL_FACTOR_DAC; + aw_pa->vcalb_desc.vcalk_dac_shift = AW_PID_2049_EF_DAC_GESLP_SHIFT; + aw_pa->vcalb_desc.vcalk_dac_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_MASK; + aw_pa->vcalb_desc.vcalk_dac_neg_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_NEG; + + aw_pa->sysst_desc.reg = AW_PID_2049_SYSST_REG; + aw_pa->sysst_desc.st_check = AW_PID_2049_BIT_SYSST_CHECK; + aw_pa->sysst_desc.st_mask = AW_PID_2049_BIT_SYSST_CHECK_MASK; + aw_pa->sysst_desc.pll_check = AW_PID_2049_BIT_PLL_CHECK; + aw_pa->sysst_desc.dsp_check = AW_PID_2049_DSPS_NORMAL_VALUE; + aw_pa->sysst_desc.dsp_mask = AW_PID_2049_DSPS_MASK; + + aw_pa->profctrl_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->profctrl_desc.mask = AW_PID_2049_RCV_MODE_MASK; + aw_pa->profctrl_desc.rcv_mode_val = AW_PID_2049_RCV_MODE_RECEIVER_VALUE; + + aw_pa->volume_desc.reg = AW_PID_2049_SYSCTRL2_REG; + aw_pa->volume_desc.mask = AW_PID_2049_VOL_MASK; + aw_pa->volume_desc.shift = AW_PID_2049_VOL_START_BIT; + aw_pa->volume_desc.mute_volume = AW_PID_2049_MUTE_VOL; + aw_pa->volume_desc.max_volume = AW_PID_2049_VOL_DEFAULT_VALUE; + aw_pa->volume_desc.ctl_volume = AW_PID_2049_VOL_DEFAULT_VALUE; + + aw_pa->dsp_en_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->dsp_en_desc.mask = AW_PID_2049_DSPBY_MASK; + aw_pa->dsp_en_desc.enable = AW_PID_2049_DSPBY_WORKING_VALUE; + aw_pa->dsp_en_desc.disable = AW_PID_2049_DSPBY_BYPASS_VALUE; + + aw_pa->memclk_desc.reg = AW_PID_2049_DBGCTRL_REG; + aw_pa->memclk_desc.mask = AW_PID_2049_MEM_CLKSEL_MASK; + aw_pa->memclk_desc.mcu_hclk = AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE; + aw_pa->memclk_desc.osc_clk = AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE; + + aw_pa->watch_dog_desc.reg = AW_PID_2049_WDT_REG; + aw_pa->watch_dog_desc.mask = AW_PID_2049_WDT_CNT_MASK; + + aw_pa->dsp_mem_desc.dsp_madd_reg = AW_PID_2049_DSPMADD_REG; + aw_pa->dsp_mem_desc.dsp_mdat_reg = AW_PID_2049_DSPMDAT_REG; + aw_pa->dsp_mem_desc.dsp_cfg_base_addr = AW_PID_2049_DSP_CFG_ADDR; + aw_pa->dsp_mem_desc.dsp_fw_base_addr = AW_PID_2049_DSP_FW_ADDR; + + aw_pa->voltage_desc.reg = AW_PID_2049_VBAT_REG; + aw_pa->voltage_desc.vbat_range = AW_PID_2049_VBAT_RANGE; + aw_pa->voltage_desc.int_bit = AW_PID_2049_INT_10BIT; + + aw_pa->temp_desc.reg = AW_PID_2049_TEMP_REG; + aw_pa->temp_desc.sign_mask = AW_PID_2049_TEMP_SIGN_MASK; + aw_pa->temp_desc.neg_mask = AW_PID_2049_TEMP_NEG_MASK; + + aw_pa->vmax_desc.dsp_reg = AW_PID_2049_DSP_REG_VMAX; + aw_pa->vmax_desc.data_type = AW_DSP_16_DATA; + + aw_pa->ipeak_desc.reg = AW_PID_2049_SYSCTRL2_REG; + aw_pa->ipeak_desc.mask = AW_PID_2049_BST_IPEAK_MASK; + + aw_pa->soft_rst.reg = AW_PID_2049_ID_REG; + aw_pa->soft_rst.reg_value = AW_PID_2049_SOFT_RESET_VALUE; + + aw_pa->dsp_vol_desc.reg = AW_PID_2049_DSPCFG_REG; + aw_pa->dsp_vol_desc.mask = AW_PID_2049_DSP_VOL_MASK; + aw_pa->dsp_vol_desc.mute_st = AW_PID_2049_DSP_VOL_MUTE; + aw_pa->dsp_vol_desc.noise_st = AW_PID_2049_DSP_VOL_NOISE_ST; + + aw_pa->amppd_desc.reg = AW_PID_2049_SYSCTRL_REG; + aw_pa->amppd_desc.mask = AW_PID_2049_AMPPD_MASK; + aw_pa->amppd_desc.enable = AW_PID_2049_AMPPD_POWER_DOWN_VALUE; + aw_pa->amppd_desc.disable = AW_PID_2049_AMPPD_WORKING_VALUE; + + aw_pa->spkr_temp_desc.reg = AW_PID_2049_ASR2_REG; + + /*32-bit data types need bypass dsp*/ + aw_pa->ra_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RA; + aw_pa->ra_desc.data_type = AW_DSP_32_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->cali_cfg_desc.actampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH; + aw_pa->cali_cfg_desc.actampth_data_type = AW_DSP_32_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->cali_cfg_desc.noiseampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH; + aw_pa->cali_cfg_desc.noiseampth_data_type = AW_DSP_32_DATA; + + aw_pa->cali_cfg_desc.ustepn_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN; + aw_pa->cali_cfg_desc.ustepn_data_type = AW_DSP_16_DATA; + + aw_pa->cali_cfg_desc.alphan_reg = AW_PID_2049_DSP_REG_CFG_RE_ALPHA; + aw_pa->cali_cfg_desc.alphan_data_type = AW_DSP_16_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->adpz_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RE; + aw_pa->adpz_re_desc.data_type = AW_DSP_32_DATA; + aw_pa->adpz_re_desc.shift = AW_PID_2049_DSP_RE_SHIFT; + + aw_pa->t0_desc.dsp_reg = AW_PID_2049_DSP_CFG_ADPZ_T0; + aw_pa->t0_desc.data_type = AW_DSP_16_DATA; + aw_pa->t0_desc.coilalpha_reg = AW_PID_2049_DSP_CFG_ADPZ_COILALPHA; + aw_pa->t0_desc.coil_type = AW_DSP_16_DATA; + + aw_pa->ste_re_desc.shift = AW_PID_2049_DSP_REG_CALRE_SHIFT; + aw_pa->ste_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CALRE; + aw_pa->ste_re_desc.data_type = AW_DSP_16_DATA; + + aw_pa->noise_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG; + aw_pa->noise_desc.data_type = AW_DSP_16_DATA; + aw_pa->noise_desc.mask = AW_PID_2049_DSP_REG_NOISE_MASK; + + aw_pa->f0_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_F0; + aw_pa->f0_desc.shift = AW_PID_2049_DSP_F0_SHIFT; + aw_pa->f0_desc.data_type = AW_DSP_16_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->cfgf0_fs_desc.dsp_reg = AW_PID_2049_DSP_REG_CFGF0_FS; + aw_pa->cfgf0_fs_desc.data_type = AW_DSP_32_DATA; + + aw_pa->q_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_Q; + aw_pa->q_desc.shift = AW_PID_2049_DSP_Q_SHIFT; + aw_pa->q_desc.data_type = AW_DSP_16_DATA; + + /*32-bit data types need bypass dsp*/ + aw_pa->dsp_crc_desc.dsp_reg = AW_PID_2049_DSP_REG_CRC_ADDR; + aw_pa->dsp_crc_desc.data_type = AW_DSP_32_DATA; + + aw_pa->dsp_crc_desc.ctl_reg = AW_PID_2049_HAGCCFG7_REG; + aw_pa->dsp_crc_desc.ctl_mask = AW_PID_2049_AGC_DSP_CTL_MASK; + aw_pa->dsp_crc_desc.ctl_enable = AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE; + aw_pa->dsp_crc_desc.ctl_disable = AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE; + + aw_pa->cco_mux_desc.reg = AW_PID_2049_PLLCTRL1_REG; + aw_pa->cco_mux_desc.mask = AW_PID_2049_CCO_MUX_MASK; + aw_pa->cco_mux_desc.divider = AW_PID_2049_CCO_MUX_DIVIDED_VALUE; + aw_pa->cco_mux_desc.bypass = AW_PID_2049_CCO_MUX_BYPASS_VALUE; + + /*hw monitor temp reg*/ + aw_pa->hw_temp_desc.dsp_reg = AW_PID_2049_DSP_REG_TEMP_ADDR; + aw_pa->hw_temp_desc.data_type = AW_DSP_16_DATA; + + aw_pa->chansel_desc.rxchan_reg = AW_PID_2049_I2SCTRL_REG; + aw_pa->chansel_desc.rxchan_mask = AW_PID_2049_CHSEL_MASK; + aw_pa->chansel_desc.txchan_reg = AW_PID_2049_I2SCFG1_REG; + aw_pa->chansel_desc.txchan_mask = AW_PID_2049_I2SCHS_MASK; + + aw_pa->chansel_desc.rx_left = AW_PID_2049_CHSEL_LEFT_VALUE; + aw_pa->chansel_desc.rx_right = AW_PID_2049_CHSEL_RIGHT_VALUE; + aw_pa->chansel_desc.tx_left = AW_PID_2049_I2SCHS_LEFT_VALUE; + aw_pa->chansel_desc.tx_right = AW_PID_2049_I2SCHS_RIGHT_VALUE; + + aw_pa->tx_en_desc.tx_en_mask = AW_PID_2049_I2STXEN_MASK; + aw_pa->tx_en_desc.tx_disable = AW_PID_2049_I2STXEN_DISABLE_VALUE; + + aw_pa->cali_delay_desc.dsp_reg = AW_PID_2049_DSP_CALI_F0_DELAY; + aw_pa->cali_delay_desc.data_type = AW_DSP_16_DATA; + + aw_pa->dsp_st_desc.dsp_reg_s1 = AW_PID_2049_DSP_ST_S1; + aw_pa->dsp_st_desc.dsp_reg_e1 = AW_PID_2049_DSP_ST_E1; + aw_pa->dsp_st_desc.dsp_reg_s2 = AW_PID_2049_DSP_ST_S2; + aw_pa->dsp_st_desc.dsp_reg_e2 = AW_PID_2049_DSP_ST_E2; + + aw883xx_device_probe(aw_pa); + + aw883xx->aw_pa = aw_pa; + + return 0; +} + +int aw883xx_init(struct aw883xx *aw883xx) +{ + int ret = 0; + + switch (aw883xx->chip_id) { + case AW883XX_PID_2049: + ret = aw883xx_pid_2049_dev_init(aw883xx); + break; + default: + ret = -EINVAL; + dev_err(aw883xx->dev, "unsupported device"); + break; + } + return ret; +} + diff --git a/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h new file mode 100644 index 000000000000..e7c4703d1627 --- /dev/null +++ b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h @@ -0,0 +1,2300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * aw883xx.c -- ALSA Soc AW883XX codec support + * + * Copyright (c) 2022 AWINIC Technology CO., LTD + * + * Author: Bruce zhao zhaolei@awinic.com + */ + +#ifndef __AW883XX_PID_2049_REG_H__ +#define __AW883XX_PID_2049_REG_H__ + +#define AW_PID_2049_ID_REG (0x00) +#define AW_PID_2049_SYSST_REG (0x01) +#define AW_PID_2049_SYSINT_REG (0x02) +#define AW_PID_2049_SYSINTM_REG (0x03) +#define AW_PID_2049_SYSCTRL_REG (0x04) +#define AW_PID_2049_SYSCTRL2_REG (0x05) +#define AW_PID_2049_I2SCTRL_REG (0x06) +#define AW_PID_2049_I2SCFG1_REG (0x07) +#define AW_PID_2049_I2SCFG2_REG (0x08) +#define AW_PID_2049_HAGCCFG1_REG (0x09) +#define AW_PID_2049_HAGCCFG2_REG (0x0A) +#define AW_PID_2049_HAGCCFG3_REG (0x0B) +#define AW_PID_2049_HAGCCFG4_REG (0x0C) +#define AW_PID_2049_HAGCCFG5_REG (0x0D) +#define AW_PID_2049_HAGCCFG6_REG (0x0E) +#define AW_PID_2049_HAGCCFG7_REG (0x0F) +#define AW_PID_2049_MPDCFG_REG (0x10) +#define AW_PID_2049_PWMCTRL_REG (0x11) +#define AW_PID_2049_I2SCFG3_REG (0x12) +#define AW_PID_2049_DBGCTRL_REG (0x13) +#define AW_PID_2049_HAGCST_REG (0x20) +#define AW_PID_2049_VBAT_REG (0x21) +#define AW_PID_2049_TEMP_REG (0x22) +#define AW_PID_2049_PVDD_REG (0x23) +#define AW_PID_2049_ISNDAT_REG (0x24) +#define AW_PID_2049_VSNDAT_REG (0x25) +#define AW_PID_2049_I2SINT_REG (0x26) +#define AW_PID_2049_I2SCAPCNT_REG (0x27) +#define AW_PID_2049_ANASTA1_REG (0x28) +#define AW_PID_2049_ANASTA2_REG (0x29) +#define AW_PID_2049_ANASTA3_REG (0x2A) +#define AW_PID_2049_ANASTA4_REG (0x2B) +#define AW_PID_2049_TESTDET_REG (0x2C) +#define AW_PID_2049_TESTIN_REG (0x38) +#define AW_PID_2049_TESTOUT_REG (0x39) +#define AW_PID_2049_DSPMADD_REG (0x40) +#define AW_PID_2049_DSPMDAT_REG (0x41) +#define AW_PID_2049_WDT_REG (0x42) +#define AW_PID_2049_ACR1_REG (0x43) +#define AW_PID_2049_ACR2_REG (0x44) +#define AW_PID_2049_ASR1_REG (0x45) +#define AW_PID_2049_ASR2_REG (0x46) +#define AW_PID_2049_DSPCFG_REG (0x47) +#define AW_PID_2049_ASR3_REG (0x48) +#define AW_PID_2049_ASR4_REG (0x49) +#define AW_PID_2049_VSNCTRL1_REG (0x50) +#define AW_PID_2049_ISNCTRL1_REG (0x51) +#define AW_PID_2049_PLLCTRL1_REG (0x52) +#define AW_PID_2049_PLLCTRL2_REG (0x53) +#define AW_PID_2049_PLLCTRL3_REG (0x54) +#define AW_PID_2049_CDACTRL1_REG (0x55) +#define AW_PID_2049_CDACTRL2_REG (0x56) +#define AW_PID_2049_SADCCTRL1_REG (0x57) +#define AW_PID_2049_SADCCTRL2_REG (0x58) +#define AW_PID_2049_CPCTRL1_REG (0x59) +#define AW_PID_2049_BSTCTRL1_REG (0x60) +#define AW_PID_2049_BSTCTRL2_REG (0x61) +#define AW_PID_2049_BSTCTRL3_REG (0x62) +#define AW_PID_2049_BSTCTRL4_REG (0x63) +#define AW_PID_2049_BSTCTRL5_REG (0x64) +#define AW_PID_2049_BSTCTRL6_REG (0x65) +#define AW_PID_2049_BSTCTRL7_REG (0x66) +#define AW_PID_2049_DSMCFG1_REG (0x67) +#define AW_PID_2049_DSMCFG2_REG (0x68) +#define AW_PID_2049_DSMCFG3_REG (0x69) +#define AW_PID_2049_DSMCFG4_REG (0x6A) +#define AW_PID_2049_DSMCFG5_REG (0x6B) +#define AW_PID_2049_DSMCFG6_REG (0x6C) +#define AW_PID_2049_DSMCFG7_REG (0x6D) +#define AW_PID_2049_DSMCFG8_REG (0x6E) +#define AW_PID_2049_TESTCTRL1_REG (0x70) +#define AW_PID_2049_TESTCTRL2_REG (0x71) +#define AW_PID_2049_EFCTRL1_REG (0x72) +#define AW_PID_2049_EFCTRL2_REG (0x73) +#define AW_PID_2049_EFWH_REG (0x74) +#define AW_PID_2049_EFWM2_REG (0x75) +#define AW_PID_2049_EFWM1_REG (0x76) +#define AW_PID_2049_EFWL_REG (0x77) +#define AW_PID_2049_EFRH_REG (0x78) +#define AW_PID_2049_EFRM2_REG (0x79) +#define AW_PID_2049_EFRM1_REG (0x7A) +#define AW_PID_2049_EFRL_REG (0x7B) +#define AW_PID_2049_TM_REG (0x7C) + +/* + * Register Access + */ +enum aw883xx_id { + AW883XX_PID_2049 = 0x2049, +}; + +#define AW_PID_2049_REG_MAX (0x7D) + +#define REG_NONE_ACCESS (0) +#define REG_RD_ACCESS (1 << 0) +#define REG_WR_ACCESS (1 << 1) + +#define AW_PID_2049_VOLUME_STEP_DB (6 * 8) + +/* detail information of registers begin */ +/* ID (0x00) detail */ +/* IDCODE bit 15:0 (ID 0x00) */ +#define AW_PID_2049_IDCODE_START_BIT (0) +#define AW_PID_2049_IDCODE_BITS_LEN (16) +#define AW_PID_2049_IDCODE_MASK \ + (~(((1<<AW_PID_2049_IDCODE_BITS_LEN)-1) << AW_PID_2049_IDCODE_START_BIT)) + +#define AW_PID_2049_IDCODE_DEFAULT_VALUE (0x2049) +#define AW_PID_2049_IDCODE_DEFAULT \ + (AW_PID_2049_IDCODE_DEFAULT_VALUE << AW_PID_2049_IDCODE_START_BIT) + +#define AW_PID_2049_SOFT_RESET_VALUE (0x55aa) + +/* default value of ID (0x00) */ +/* #define AW_PID_2049_ID_DEFAULT (0x2049) */ + +/* SYSST (0x01) detail */ +/* OVP2S bit 15 (SYSST 0x01) */ +#define AW_PID_2049_OVP2S_START_BIT (15) +#define AW_PID_2049_OVP2S_BITS_LEN (1) +#define AW_PID_2049_OVP2S_MASK \ + (~(((1<<AW_PID_2049_OVP2S_BITS_LEN)-1) << AW_PID_2049_OVP2S_START_BIT)) + +#define AW_PID_2049_OVP2S_NORMAL (0) +#define AW_PID_2049_OVP2S_NORMAL_VALUE \ + (AW_PID_2049_OVP2S_NORMAL << AW_PID_2049_OVP2S_START_BIT) + +#define AW_PID_2049_OVP2S_OVP (1) +#define AW_PID_2049_OVP2S_OVP_VALUE \ + (AW_PID_2049_OVP2S_OVP << AW_PID_2049_OVP2S_START_BIT) + +#define AW_PID_2049_OVP2S_DEFAULT_VALUE (0) +#define AW_PID_2049_OVP2S_DEFAULT \ + (AW_PID_2049_OVP2S_DEFAULT_VALUE << AW_PID_2049_OVP2S_START_BIT) + +/* UVLS bit 14 (SYSST 0x01) */ +#define AW_PID_2049_UVLS_START_BIT (14) +#define AW_PID_2049_UVLS_BITS_LEN (1) +#define AW_PID_2049_UVLS_MASK \ + (~(((1<<AW_PID_2049_UVLS_BITS_LEN)-1) << AW_PID_2049_UVLS_START_BIT)) + +#define AW_PID_2049_UVLS_NORMAL (0) +#define AW_PID_2049_UVLS_NORMAL_VALUE \ + (AW_PID_2049_UVLS_NORMAL << AW_PID_2049_UVLS_START_BIT) + +#define AW_PID_2049_UVLS_UVLO (1) +#define AW_PID_2049_UVLS_UVLO_VALUE \ + (AW_PID_2049_UVLS_UVLO << AW_PID_2049_UVLS_START_BIT) + +#define AW_PID_2049_UVLS_DEFAULT_VALUE (0) +#define AW_PID_2049_UVLS_DEFAULT \ + (AW_PID_2049_UVLS_DEFAULT_VALUE << AW_PID_2049_UVLS_START_BIT) + +/* ADPS bit 13 (SYSST 0x01) */ +#define AW_PID_2049_ADPS_START_BIT (13) +#define AW_PID_2049_ADPS_BITS_LEN (1) +#define AW_PID_2049_ADPS_MASK \ + (~(((1<<AW_PID_2049_ADPS_BITS_LEN)-1) << AW_PID_2049_ADPS_START_BIT)) + +#define AW_PID_2049_ADPS_TRANSPARENT (0) +#define AW_PID_2049_ADPS_TRANSPARENT_VALUE \ + (AW_PID_2049_ADPS_TRANSPARENT << AW_PID_2049_ADPS_START_BIT) + +#define AW_PID_2049_ADPS_BOOST (1) +#define AW_PID_2049_ADPS_BOOST_VALUE \ + (AW_PID_2049_ADPS_BOOST << AW_PID_2049_ADPS_START_BIT) + +#define AW_PID_2049_ADPS_DEFAULT_VALUE (0) +#define AW_PID_2049_ADPS_DEFAULT \ + (AW_PID_2049_ADPS_DEFAULT_VALUE << AW_PID_2049_ADPS_START_BIT) + +/* DSPS bit 12 (SYSST 0x01) */ +#define AW_PID_2049_DSPS_START_BIT (12) +#define AW_PID_2049_DSPS_BITS_LEN (1) +#define AW_PID_2049_DSPS_MASK \ + (~(((1<<AW_PID_2049_DSPS_BITS_LEN)-1) << AW_PID_2049_DSPS_START_BIT)) + +#define AW_PID_2049_DSPS_NORMAL (0) +#define AW_PID_2049_DSPS_NORMAL_VALUE \ + (AW_PID_2049_DSPS_NORMAL << AW_PID_2049_DSPS_START_BIT) + +#define AW_PID_2049_DSPS_DSP_STABLE (1) +#define AW_PID_2049_DSPS_DSP_STABLE_VALUE \ + (AW_PID_2049_DSPS_DSP_STABLE << AW_PID_2049_DSPS_START_BIT) + +#define AW_PID_2049_DSPS_DEFAULT_VALUE (0) +#define AW_PID_2049_DSPS_DEFAULT \ + (AW_PID_2049_DSPS_DEFAULT_VALUE << AW_PID_2049_DSPS_START_BIT) + +/* BSTOCS bit 11 (SYSST 0x01) */ +#define AW_PID_2049_BSTOCS_START_BIT (11) +#define AW_PID_2049_BSTOCS_BITS_LEN (1) +#define AW_PID_2049_BSTOCS_MASK \ + (~(((1<<AW_PID_2049_BSTOCS_BITS_LEN)-1) << AW_PID_2049_BSTOCS_START_BIT)) + +#define AW_PID_2049_BSTOCS_NORMAL (0) +#define AW_PID_2049_BSTOCS_NORMAL_VALUE \ + (AW_PID_2049_BSTOCS_NORMAL << AW_PID_2049_BSTOCS_START_BIT) + +#define AW_PID_2049_BSTOCS_OVER_CURRENT (1) +#define AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE \ + (AW_PID_2049_BSTOCS_OVER_CURRENT << AW_PID_2049_BSTOCS_START_BIT) + +#define AW_PID_2049_BSTOCS_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTOCS_DEFAULT \ + (AW_PID_2049_BSTOCS_DEFAULT_VALUE << AW_PID_2049_BSTOCS_START_BIT) + +/* OVPS bit 10 (SYSST 0x01) */ +#define AW_PID_2049_OVPS_START_BIT (10) +#define AW_PID_2049_OVPS_BITS_LEN (1) +#define AW_PID_2049_OVPS_MASK \ + (~(((1<<AW_PID_2049_OVPS_BITS_LEN)-1) << AW_PID_2049_OVPS_START_BIT)) + +#define AW_PID_2049_OVPS_NORMAL (0) +#define AW_PID_2049_OVPS_NORMAL_VALUE \ + (AW_PID_2049_OVPS_NORMAL << AW_PID_2049_OVPS_START_BIT) + +#define AW_PID_2049_OVPS_OVP (1) +#define AW_PID_2049_OVPS_OVP_VALUE \ + (AW_PID_2049_OVPS_OVP << AW_PID_2049_OVPS_START_BIT) + +#define AW_PID_2049_OVPS_DEFAULT_VALUE (0) +#define AW_PID_2049_OVPS_DEFAULT \ + (AW_PID_2049_OVPS_DEFAULT_VALUE << AW_PID_2049_OVPS_START_BIT) + +/* BSTS bit 9 (SYSST 0x01) */ +#define AW_PID_2049_BSTS_START_BIT (9) +#define AW_PID_2049_BSTS_BITS_LEN (1) +#define AW_PID_2049_BSTS_MASK \ + (~(((1<<AW_PID_2049_BSTS_BITS_LEN)-1) << AW_PID_2049_BSTS_START_BIT)) + +#define AW_PID_2049_BSTS_NOT_FINISHED (0) +#define AW_PID_2049_BSTS_NOT_FINISHED_VALUE \ + (AW_PID_2049_BSTS_NOT_FINISHED << AW_PID_2049_BSTS_START_BIT) + +#define AW_PID_2049_BSTS_FINISHED (1) +#define AW_PID_2049_BSTS_FINISHED_VALUE \ + (AW_PID_2049_BSTS_FINISHED << AW_PID_2049_BSTS_START_BIT) + +#define AW_PID_2049_BSTS_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTS_DEFAULT \ + (AW_PID_2049_BSTS_DEFAULT_VALUE << AW_PID_2049_BSTS_START_BIT) + +/* SWS bit 8 (SYSST 0x01) */ +#define AW_PID_2049_SWS_START_BIT (8) +#define AW_PID_2049_SWS_BITS_LEN (1) +#define AW_PID_2049_SWS_MASK \ + (~(((1<<AW_PID_2049_SWS_BITS_LEN)-1) << AW_PID_2049_SWS_START_BIT)) + +#define AW_PID_2049_SWS_NOT_SWITCHING (0) +#define AW_PID_2049_SWS_NOT_SWITCHING_VALUE \ + (AW_PID_2049_SWS_NOT_SWITCHING << AW_PID_2049_SWS_START_BIT) + +#define AW_PID_2049_SWS_SWITCHING (1) +#define AW_PID_2049_SWS_SWITCHING_VALUE \ + (AW_PID_2049_SWS_SWITCHING << AW_PID_2049_SWS_START_BIT) + +#define AW_PID_2049_SWS_DEFAULT_VALUE (0) +#define AW_PID_2049_SWS_DEFAULT \ + (AW_PID_2049_SWS_DEFAULT_VALUE << AW_PID_2049_SWS_START_BIT) + +/* CLIPS bit 7 (SYSST 0x01) */ +#define AW_PID_2049_CLIPS_START_BIT (7) +#define AW_PID_2049_CLIPS_BITS_LEN (1) +#define AW_PID_2049_CLIPS_MASK \ + (~(((1<<AW_PID_2049_CLIPS_BITS_LEN)-1) << AW_PID_2049_CLIPS_START_BIT)) + +#define AW_PID_2049_CLIPS_NOT_CLIPPING (0) +#define AW_PID_2049_CLIPS_NOT_CLIPPING_VALUE \ + (AW_PID_2049_CLIPS_NOT_CLIPPING << AW_PID_2049_CLIPS_START_BIT) + +#define AW_PID_2049_CLIPS_CLIPPING (1) +#define AW_PID_2049_CLIPS_CLIPPING_VALUE \ + (AW_PID_2049_CLIPS_CLIPPING << AW_PID_2049_CLIPS_START_BIT) + +#define AW_PID_2049_CLIPS_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIPS_DEFAULT \ + (AW_PID_2049_CLIPS_DEFAULT_VALUE << AW_PID_2049_CLIPS_START_BIT) + +/* WDS bit 6 (SYSST 0x01) */ +#define AW_PID_2049_WDS_START_BIT (6) +#define AW_PID_2049_WDS_BITS_LEN (1) +#define AW_PID_2049_WDS_MASK \ + (~(((1<<AW_PID_2049_WDS_BITS_LEN)-1) << AW_PID_2049_WDS_START_BIT)) + +#define AW_PID_2049_WDS_NORMAL (0) +#define AW_PID_2049_WDS_NORMAL_VALUE \ + (AW_PID_2049_WDS_NORMAL << AW_PID_2049_WDS_START_BIT) + +#define AW_PID_2049_WDS_ABNORMAL (1) +#define AW_PID_2049_WDS_ABNORMAL_VALUE \ + (AW_PID_2049_WDS_ABNORMAL << AW_PID_2049_WDS_START_BIT) + +#define AW_PID_2049_WDS_DEFAULT_VALUE (0) +#define AW_PID_2049_WDS_DEFAULT \ + (AW_PID_2049_WDS_DEFAULT_VALUE << AW_PID_2049_WDS_START_BIT) + +/* NOCLKS bit 5 (SYSST 0x01) */ +#define AW_PID_2049_NOCLKS_START_BIT (5) +#define AW_PID_2049_NOCLKS_BITS_LEN (1) +#define AW_PID_2049_NOCLKS_MASK \ + (~(((1<<AW_PID_2049_NOCLKS_BITS_LEN)-1) << AW_PID_2049_NOCLKS_START_BIT)) + +#define AW_PID_2049_NOCLKS_CLOCK_OK (0) +#define AW_PID_2049_NOCLKS_CLOCK_OK_VALUE \ + (AW_PID_2049_NOCLKS_CLOCK_OK << AW_PID_2049_NOCLKS_START_BIT) + +#define AW_PID_2049_NOCLKS_NO_CLOCK (1) +#define AW_PID_2049_NOCLKS_NO_CLOCK_VALUE \ + (AW_PID_2049_NOCLKS_NO_CLOCK << AW_PID_2049_NOCLKS_START_BIT) + +#define AW_PID_2049_NOCLKS_DEFAULT_VALUE (0) +#define AW_PID_2049_NOCLKS_DEFAULT \ + (AW_PID_2049_NOCLKS_DEFAULT_VALUE << AW_PID_2049_NOCLKS_START_BIT) + +/* CLKS bit 4 (SYSST 0x01) */ +#define AW_PID_2049_CLKS_START_BIT (4) +#define AW_PID_2049_CLKS_BITS_LEN (1) +#define AW_PID_2049_CLKS_MASK \ + (~(((1<<AW_PID_2049_CLKS_BITS_LEN)-1) << AW_PID_2049_CLKS_START_BIT)) + +#define AW_PID_2049_CLKS_NOT_STABLE (0) +#define AW_PID_2049_CLKS_NOT_STABLE_VALUE \ + (AW_PID_2049_CLKS_NOT_STABLE << AW_PID_2049_CLKS_START_BIT) + +#define AW_PID_2049_CLKS_STABLE (1) +#define AW_PID_2049_CLKS_STABLE_VALUE \ + (AW_PID_2049_CLKS_STABLE << AW_PID_2049_CLKS_START_BIT) + +#define AW_PID_2049_CLKS_DEFAULT_VALUE (0) +#define AW_PID_2049_CLKS_DEFAULT \ + (AW_PID_2049_CLKS_DEFAULT_VALUE << AW_PID_2049_CLKS_START_BIT) + +/* OCDS bit 3 (SYSST 0x01) */ +#define AW_PID_2049_OCDS_START_BIT (3) +#define AW_PID_2049_OCDS_BITS_LEN (1) +#define AW_PID_2049_OCDS_MASK \ + (~(((1<<AW_PID_2049_OCDS_BITS_LEN)-1) << AW_PID_2049_OCDS_START_BIT)) + +#define AW_PID_2049_OCDS_NORAML (0) +#define AW_PID_2049_OCDS_NORAML_VALUE \ + (AW_PID_2049_OCDS_NORAML << AW_PID_2049_OCDS_START_BIT) + +#define AW_PID_2049_OCDS_OC (1) +#define AW_PID_2049_OCDS_OC_VALUE \ + (AW_PID_2049_OCDS_OC << AW_PID_2049_OCDS_START_BIT) + +#define AW_PID_2049_OCDS_DEFAULT_VALUE (0) +#define AW_PID_2049_OCDS_DEFAULT \ + (AW_PID_2049_OCDS_DEFAULT_VALUE << AW_PID_2049_OCDS_START_BIT) + +/* CLIP_PRES bit 2 (SYSST 0x01) */ +#define AW_PID_2049_CLIP_PRES_START_BIT (2) +#define AW_PID_2049_CLIP_PRES_BITS_LEN (1) +#define AW_PID_2049_CLIP_PRES_MASK \ + (~(((1<<AW_PID_2049_CLIP_PRES_BITS_LEN)-1) << AW_PID_2049_CLIP_PRES_START_BIT)) + +#define AW_PID_2049_CLIP_PRES_NOT_CLIPPING (0) +#define AW_PID_2049_CLIP_PRES_NOT_CLIPPING_VALUE \ + (AW_PID_2049_CLIP_PRES_NOT_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT) + +#define AW_PID_2049_CLIP_PRES_CLIPPING (1) +#define AW_PID_2049_CLIP_PRES_CLIPPING_VALUE \ + (AW_PID_2049_CLIP_PRES_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT) + +#define AW_PID_2049_CLIP_PRES_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIP_PRES_DEFAULT \ + (AW_PID_2049_CLIP_PRES_DEFAULT_VALUE << AW_PID_2049_CLIP_PRES_START_BIT) + +/* OTHS bit 1 (SYSST 0x01) */ +#define AW_PID_2049_OTHS_START_BIT (1) +#define AW_PID_2049_OTHS_BITS_LEN (1) +#define AW_PID_2049_OTHS_MASK \ + (~(((1<<AW_PID_2049_OTHS_BITS_LEN)-1) << AW_PID_2049_OTHS_START_BIT)) + +#define AW_PID_2049_OTHS_NORMAL (0) +#define AW_PID_2049_OTHS_NORMAL_VALUE \ + (AW_PID_2049_OTHS_NORMAL << AW_PID_2049_OTHS_START_BIT) + +#define AW_PID_2049_OTHS_OT (1) +#define AW_PID_2049_OTHS_OT_VALUE \ + (AW_PID_2049_OTHS_OT << AW_PID_2049_OTHS_START_BIT) + +#define AW_PID_2049_OTHS_DEFAULT_VALUE (0) +#define AW_PID_2049_OTHS_DEFAULT \ + (AW_PID_2049_OTHS_DEFAULT_VALUE << AW_PID_2049_OTHS_START_BIT) + +/* PLLS bit 0 (SYSST 0x01) */ +#define AW_PID_2049_PLLS_START_BIT (0) +#define AW_PID_2049_PLLS_BITS_LEN (1) +#define AW_PID_2049_PLLS_MASK \ + (~(((1<<AW_PID_2049_PLLS_BITS_LEN)-1) << AW_PID_2049_PLLS_START_BIT)) + +#define AW_PID_2049_PLLS_UNLOCKED (0) +#define AW_PID_2049_PLLS_UNLOCKED_VALUE \ + (AW_PID_2049_PLLS_UNLOCKED << AW_PID_2049_PLLS_START_BIT) + +#define AW_PID_2049_PLLS_LOCKED (1) +#define AW_PID_2049_PLLS_LOCKED_VALUE \ + (AW_PID_2049_PLLS_LOCKED << AW_PID_2049_PLLS_START_BIT) + +#define AW_PID_2049_PLLS_DEFAULT_VALUE (0) +#define AW_PID_2049_PLLS_DEFAULT \ + (AW_PID_2049_PLLS_DEFAULT_VALUE << AW_PID_2049_PLLS_START_BIT) + + + +#define AW_PID_2049_BIT_PLL_CHECK \ + (AW_PID_2049_CLKS_STABLE_VALUE | \ + AW_PID_2049_PLLS_LOCKED_VALUE) + + +#define AW_PID_2049_BIT_SYSST_CHECK_MASK \ + (~(AW_PID_2049_UVLS_NORMAL_VALUE | \ + AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE | \ + AW_PID_2049_BSTS_FINISHED_VALUE | \ + AW_PID_2049_SWS_SWITCHING_VALUE | \ + AW_PID_2049_NOCLKS_NO_CLOCK_VALUE | \ + AW_PID_2049_CLKS_STABLE_VALUE | \ + AW_PID_2049_OCDS_OC_VALUE | \ + AW_PID_2049_OTHS_OT_VALUE | \ + AW_PID_2049_PLLS_LOCKED_VALUE)) + +#define AW_PID_2049_BIT_SYSST_CHECK \ + (AW_PID_2049_BSTS_FINISHED_VALUE | \ + AW_PID_2049_SWS_SWITCHING_VALUE | \ + AW_PID_2049_CLKS_STABLE_VALUE | \ + AW_PID_2049_PLLS_LOCKED_VALUE) + +/* default value of SYSST (0x01) */ +/* #define AW_PID_2049_SYSST_DEFAULT (0x0000) */ + +/* SYSINT (0x02) detail */ +/* OVP2I bit 15 (SYSINT 0x02) */ +#define AW_PID_2049_OVP2I_START_BIT (15) +#define AW_PID_2049_OVP2I_BITS_LEN (1) +#define AW_PID_2049_OVP2I_MASK \ + (~(((1<<AW_PID_2049_OVP2I_BITS_LEN)-1) << AW_PID_2049_OVP2I_START_BIT)) + +#define AW_PID_2049_OVP2I_DEFAULT_VALUE (0) +#define AW_PID_2049_OVP2I_DEFAULT \ + (AW_PID_2049_OVP2I_DEFAULT_VALUE << AW_PID_2049_OVP2I_START_BIT) + +/* UVLI bit 14 (SYSINT 0x02) */ +#define AW_PID_2049_UVLI_START_BIT (14) +#define AW_PID_2049_UVLI_BITS_LEN (1) +#define AW_PID_2049_UVLI_MASK \ + (~(((1<<AW_PID_2049_UVLI_BITS_LEN)-1) << AW_PID_2049_UVLI_START_BIT)) + +#define AW_PID_2049_UVLI_DEFAULT_VALUE (0) +#define AW_PID_2049_UVLI_DEFAULT \ + (AW_PID_2049_UVLI_DEFAULT_VALUE << AW_PID_2049_UVLI_START_BIT) + +/* ADPI bit 13 (SYSINT 0x02) */ +#define AW_PID_2049_ADPI_START_BIT (13) +#define AW_PID_2049_ADPI_BITS_LEN (1) +#define AW_PID_2049_ADPI_MASK \ + (~(((1<<AW_PID_2049_ADPI_BITS_LEN)-1) << AW_PID_2049_ADPI_START_BIT)) + +#define AW_PID_2049_ADPI_DEFAULT_VALUE (0) +#define AW_PID_2049_ADPI_DEFAULT \ + (AW_PID_2049_ADPI_DEFAULT_VALUE << AW_PID_2049_ADPI_START_BIT) + +/* DSPI bit 12 (SYSINT 0x02) */ +#define AW_PID_2049_DSPI_START_BIT (12) +#define AW_PID_2049_DSPI_BITS_LEN (1) +#define AW_PID_2049_DSPI_MASK \ + (~(((1<<AW_PID_2049_DSPI_BITS_LEN)-1) << AW_PID_2049_DSPI_START_BIT)) + +#define AW_PID_2049_DSPI_DEFAULT_VALUE (0) +#define AW_PID_2049_DSPI_DEFAULT \ + (AW_PID_2049_DSPI_DEFAULT_VALUE << AW_PID_2049_DSPI_START_BIT) + +/* BSTOCI bit 11 (SYSINT 0x02) */ +#define AW_PID_2049_BSTOCI_START_BIT (11) +#define AW_PID_2049_BSTOCI_BITS_LEN (1) +#define AW_PID_2049_BSTOCI_MASK \ + (~(((1<<AW_PID_2049_BSTOCI_BITS_LEN)-1) << AW_PID_2049_BSTOCI_START_BIT)) + +#define AW_PID_2049_BSTOCI_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTOCI_DEFAULT \ + (AW_PID_2049_BSTOCI_DEFAULT_VALUE << AW_PID_2049_BSTOCI_START_BIT) + +/* OVPI bit 10 (SYSINT 0x02) */ +#define AW_PID_2049_OVPI_START_BIT (10) +#define AW_PID_2049_OVPI_BITS_LEN (1) +#define AW_PID_2049_OVPI_MASK \ + (~(((1<<AW_PID_2049_OVPI_BITS_LEN)-1) << AW_PID_2049_OVPI_START_BIT)) + +#define AW_PID_2049_OVPI_DEFAULT_VALUE (0) +#define AW_PID_2049_OVPI_DEFAULT \ + (AW_PID_2049_OVPI_DEFAULT_VALUE << AW_PID_2049_OVPI_START_BIT) + +/* BSTI bit 9 (SYSINT 0x02) */ +#define AW_PID_2049_BSTI_START_BIT (9) +#define AW_PID_2049_BSTI_BITS_LEN (1) +#define AW_PID_2049_BSTI_MASK \ + (~(((1<<AW_PID_2049_BSTI_BITS_LEN)-1) << AW_PID_2049_BSTI_START_BIT)) + +#define AW_PID_2049_BSTI_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTI_DEFAULT \ + (AW_PID_2049_BSTI_DEFAULT_VALUE << AW_PID_2049_BSTI_START_BIT) + +/* SWI bit 8 (SYSINT 0x02) */ +#define AW_PID_2049_SWI_START_BIT (8) +#define AW_PID_2049_SWI_BITS_LEN (1) +#define AW_PID_2049_SWI_MASK \ + (~(((1<<AW_PID_2049_SWI_BITS_LEN)-1) << AW_PID_2049_SWI_START_BIT)) + +#define AW_PID_2049_SWI_DEFAULT_VALUE (0) +#define AW_PID_2049_SWI_DEFAULT \ + (AW_PID_2049_SWI_DEFAULT_VALUE << AW_PID_2049_SWI_START_BIT) + +/* CLIPI bit 7 (SYSINT 0x02) */ +#define AW_PID_2049_CLIPI_START_BIT (7) +#define AW_PID_2049_CLIPI_BITS_LEN (1) +#define AW_PID_2049_CLIPI_MASK \ + (~(((1<<AW_PID_2049_CLIPI_BITS_LEN)-1) << AW_PID_2049_CLIPI_START_BIT)) + +#define AW_PID_2049_CLIPI_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIPI_DEFAULT \ + (AW_PID_2049_CLIPI_DEFAULT_VALUE << AW_PID_2049_CLIPI_START_BIT) + +/* WDI bit 6 (SYSINT 0x02) */ +#define AW_PID_2049_WDI_START_BIT (6) +#define AW_PID_2049_WDI_BITS_LEN (1) +#define AW_PID_2049_WDI_MASK \ + (~(((1<<AW_PID_2049_WDI_BITS_LEN)-1) << AW_PID_2049_WDI_START_BIT)) + +#define AW_PID_2049_WDI_DEFAULT_VALUE (0) +#define AW_PID_2049_WDI_INT_VALUE (1) +#define AW_PID_2049_WDI_DEFAULT \ + (AW_PID_2049_WDI_DEFAULT_VALUE << AW_PID_2049_WDI_START_BIT) +#define AW_PID_2049_WDI_INTERRUPT \ + (AW_PID_2049_WDI_INT_VALUE << AW_PID_2049_WDI_START_BIT) + +/* NOCLKI bit 5 (SYSINT 0x02) */ +#define AW_PID_2049_NOCLKI_START_BIT (5) +#define AW_PID_2049_NOCLKI_BITS_LEN (1) +#define AW_PID_2049_NOCLKI_MASK \ + (~(((1<<AW_PID_2049_NOCLKI_BITS_LEN)-1) << AW_PID_2049_NOCLKI_START_BIT)) + +#define AW_PID_2049_NOCLKI_DEFAULT_VALUE (0) +#define AW_PID_2049_NOCLKI_INT_VALUE (1) +#define AW_PID_2049_NOCLKI_DEFAULT \ + (AW_PID_2049_NOCLKI_DEFAULT_VALUE << AW_PID_2049_NOCLKI_START_BIT) +#define AW_PID_2049_NOCLKI_INTERRUPT \ + (AW_PID_2049_NOCLKI_INT_VALUE << AW_PID_2049_NOCLKI_START_BIT) + +/* CLKI bit 4 (SYSINT 0x02) */ +#define AW_PID_2049_CLKI_START_BIT (4) +#define AW_PID_2049_CLKI_BITS_LEN (1) +#define AW_PID_2049_CLKI_MASK \ + (~(((1<<AW_PID_2049_CLKI_BITS_LEN)-1) << AW_PID_2049_CLKI_START_BIT)) + +#define AW_PID_2049_CLKI_DEFAULT_VALUE (0) +#define AW_PID_2049_CLKI_INT_VALUE (1) +#define AW_PID_2049_CLKI_DEFAULT \ + (AW_PID_2049_CLKI_DEFAULT_VALUE << AW_PID_2049_CLKI_START_BIT) +#define AW_PID_2049_CLKI_INTERRUPT \ + (AW_PID_2049_CLKI_INT_VALUE << AW_PID_2049_CLKI_START_BIT) + +/* OCDI bit 3 (SYSINT 0x02) */ +#define AW_PID_2049_OCDI_START_BIT (3) +#define AW_PID_2049_OCDI_BITS_LEN (1) +#define AW_PID_2049_OCDI_MASK \ + (~(((1<<AW_PID_2049_OCDI_BITS_LEN)-1) << AW_PID_2049_OCDI_START_BIT)) + +#define AW_PID_2049_OCDI_DEFAULT_VALUE (0) +#define AW_PID_2049_OCDI_DEFAULT \ + (AW_PID_2049_OCDI_DEFAULT_VALUE << AW_PID_2049_OCDI_START_BIT) + +/* CLIP_PREI bit 2 (SYSINT 0x02) */ +#define AW_PID_2049_CLIP_PREI_START_BIT (2) +#define AW_PID_2049_CLIP_PREI_BITS_LEN (1) +#define AW_PID_2049_CLIP_PREI_MASK \ + (~(((1<<AW_PID_2049_CLIP_PREI_BITS_LEN)-1) << AW_PID_2049_CLIP_PREI_START_BIT)) + +#define AW_PID_2049_CLIP_PREI_DEFAULT_VALUE (0) +#define AW_PID_2049_CLIP_PREI_DEFAULT \ + (AW_PID_2049_CLIP_PREI_DEFAULT_VALUE << AW_PID_2049_CLIP_PREI_START_BIT) + +/* OTHI bit 1 (SYSINT 0x02) */ +#define AW_PID_2049_OTHI_START_BIT (1) +#define AW_PID_2049_OTHI_BITS_LEN (1) +#define AW_PID_2049_OTHI_MASK \ + (~(((1<<AW_PID_2049_OTHI_BITS_LEN)-1) << AW_PID_2049_OTHI_START_BIT)) + +#define AW_PID_2049_OTHI_DEFAULT_VALUE (0) +#define AW_PID_2049_OTHI_DEFAULT \ + (AW_PID_2049_OTHI_DEFAULT_VALUE << AW_PID_2049_OTHI_START_BIT) + +/* PLLI bit 0 (SYSINT 0x02) */ +#define AW_PID_2049_PLLI_START_BIT (0) +#define AW_PID_2049_PLLI_BITS_LEN (1) +#define AW_PID_2049_PLLI_MASK \ + (~(((1<<AW_PID_2049_PLLI_BITS_LEN)-1) << AW_PID_2049_PLLI_START_BIT)) + +#define AW_PID_2049_PLLI_DEFAULT_VALUE (0) +#define AW_PID_2049_PLLI_INT_VALUE (1) +#define AW_PID_2049_PLLI_DEFAULT \ + (AW_PID_2049_PLLI_DEFAULT_VALUE << AW_PID_2049_PLLI_START_BIT) +#define AW_PID_2049_PLLI_INTERRUPT \ + (AW_PID_2049_PLLI_INT_VALUE << AW_PID_2049_PLLI_START_BIT) + +/* default value of SYSINT (0x02) */ +/* #define AW_PID_2049_SYSINT_DEFAULT (0x0000) */ + +#define AW_PID_2049_BIT_SYSINT_CHECK \ + (AW_PID_2049_WDI_INTERRUPT | \ + AW_PID_2049_CLKI_INTERRUPT | \ + AW_PID_2049_NOCLKI_INTERRUPT | \ + AW_PID_2049_PLLI_INTERRUPT) + +/* SYSINTM (0x03) detail */ +/* OVP2M bit 15 (SYSINTM 0x03) */ +#define AW_PID_2049_OVP2M_START_BIT (15) +#define AW_PID_2049_OVP2M_BITS_LEN (1) +#define AW_PID_2049_OVP2M_MASK \ + (~(((1<<AW_PID_2049_OVP2M_BITS_LEN)-1) << AW_PID_2049_OVP2M_START_BIT)) + +#define AW_PID_2049_OVP2M_DEFAULT_VALUE (1) +#define AW_PID_2049_OVP2M_DEFAULT \ + (AW_PID_2049_OVP2M_DEFAULT_VALUE << AW_PID_2049_OVP2M_START_BIT) + +/* UVLM bit 14 (SYSINTM 0x03) */ +#define AW_PID_2049_UVLM_START_BIT (14) +#define AW_PID_2049_UVLM_BITS_LEN (1) +#define AW_PID_2049_UVLM_MASK \ + (~(((1<<AW_PID_2049_UVLM_BITS_LEN)-1) << AW_PID_2049_UVLM_START_BIT)) + +#define AW_PID_2049_UVLM_DEFAULT_VALUE (1) +#define AW_PID_2049_UVLM_DEFAULT \ + (AW_PID_2049_UVLM_DEFAULT_VALUE << AW_PID_2049_UVLM_START_BIT) + +/* ADPM bit 13 (SYSINTM 0x03) */ +#define AW_PID_2049_ADPM_START_BIT (13) +#define AW_PID_2049_ADPM_BITS_LEN (1) +#define AW_PID_2049_ADPM_MASK \ + (~(((1<<AW_PID_2049_ADPM_BITS_LEN)-1) << AW_PID_2049_ADPM_START_BIT)) + +#define AW_PID_2049_ADPM_DEFAULT_VALUE (1) +#define AW_PID_2049_ADPM_DEFAULT \ + (AW_PID_2049_ADPM_DEFAULT_VALUE << AW_PID_2049_ADPM_START_BIT) + +/* DSPM bit 12 (SYSINTM 0x03) */ +#define AW_PID_2049_DSPM_START_BIT (12) +#define AW_PID_2049_DSPM_BITS_LEN (1) +#define AW_PID_2049_DSPM_MASK \ + (~(((1<<AW_PID_2049_DSPM_BITS_LEN)-1) << AW_PID_2049_DSPM_START_BIT)) + +#define AW_PID_2049_DSPM_DEFAULT_VALUE (1) +#define AW_PID_2049_DSPM_DEFAULT \ + (AW_PID_2049_DSPM_DEFAULT_VALUE << AW_PID_2049_DSPM_START_BIT) + +/* BSTOCM bit 11 (SYSINTM 0x03) */ +#define AW_PID_2049_BSTOCM_START_BIT (11) +#define AW_PID_2049_BSTOCM_BITS_LEN (1) +#define AW_PID_2049_BSTOCM_MASK \ + (~(((1<<AW_PID_2049_BSTOCM_BITS_LEN)-1) << AW_PID_2049_BSTOCM_START_BIT)) + +#define AW_PID_2049_BSTOCM_DEFAULT_VALUE (1) +#define AW_PID_2049_BSTOCM_DEFAULT \ + (AW_PID_2049_BSTOCM_DEFAULT_VALUE << AW_PID_2049_BSTOCM_START_BIT) + +/* OVPM bit 10 (SYSINTM 0x03) */ +#define AW_PID_2049_OVPM_START_BIT (10) +#define AW_PID_2049_OVPM_BITS_LEN (1) +#define AW_PID_2049_OVPM_MASK \ + (~(((1<<AW_PID_2049_OVPM_BITS_LEN)-1) << AW_PID_2049_OVPM_START_BIT)) + +#define AW_PID_2049_OVPM_DEFAULT_VALUE (1) +#define AW_PID_2049_OVPM_DEFAULT \ + (AW_PID_2049_OVPM_DEFAULT_VALUE << AW_PID_2049_OVPM_START_BIT) + +/* BSTM bit 9 (SYSINTM 0x03) */ +#define AW_PID_2049_BSTM_START_BIT (9) +#define AW_PID_2049_BSTM_BITS_LEN (1) +#define AW_PID_2049_BSTM_MASK \ + (~(((1<<AW_PID_2049_BSTM_BITS_LEN)-1) << AW_PID_2049_BSTM_START_BIT)) + +#define AW_PID_2049_BSTM_DEFAULT_VALUE (1) +#define AW_PID_2049_BSTM_DEFAULT \ + (AW_PID_2049_BSTM_DEFAULT_VALUE << AW_PID_2049_BSTM_START_BIT) + +/* SWM bit 8 (SYSINTM 0x03) */ +#define AW_PID_2049_SWM_START_BIT (8) +#define AW_PID_2049_SWM_BITS_LEN (1) +#define AW_PID_2049_SWM_MASK \ + (~(((1<<AW_PID_2049_SWM_BITS_LEN)-1) << AW_PID_2049_SWM_START_BIT)) + +#define AW_PID_2049_SWM_DEFAULT_VALUE (1) +#define AW_PID_2049_SWM_DEFAULT \ + (AW_PID_2049_SWM_DEFAULT_VALUE << AW_PID_2049_SWM_START_BIT) + +/* CLIPM bit 7 (SYSINTM 0x03) */ +#define AW_PID_2049_CLIPM_START_BIT (7) +#define AW_PID_2049_CLIPM_BITS_LEN (1) +#define AW_PID_2049_CLIPM_MASK \ + (~(((1<<AW_PID_2049_CLIPM_BITS_LEN)-1) << AW_PID_2049_CLIPM_START_BIT)) + +#define AW_PID_2049_CLIPM_DEFAULT_VALUE (1) +#define AW_PID_2049_CLIPM_DEFAULT \ + (AW_PID_2049_CLIPM_DEFAULT_VALUE << AW_PID_2049_CLIPM_START_BIT) + +/* WDM bit 6 (SYSINTM 0x03) */ +#define AW_PID_2049_WDM_START_BIT (6) +#define AW_PID_2049_WDM_BITS_LEN (1) +#define AW_PID_2049_WDM_MASK \ + (~(((1<<AW_PID_2049_WDM_BITS_LEN)-1) << AW_PID_2049_WDM_START_BIT)) + +#define AW_PID_2049_WDM_DEFAULT_VALUE (1) +#define AW_PID_2049_WDM_DEFAULT \ + (AW_PID_2049_WDM_DEFAULT_VALUE << AW_PID_2049_WDM_START_BIT) + +/* NOCLKM bit 5 (SYSINTM 0x03) */ +#define AW_PID_2049_NOCLKM_START_BIT (5) +#define AW_PID_2049_NOCLKM_BITS_LEN (1) +#define AW_PID_2049_NOCLKM_MASK \ + (~(((1<<AW_PID_2049_NOCLKM_BITS_LEN)-1) << AW_PID_2049_NOCLKM_START_BIT)) + +#define AW_PID_2049_NOCLKM_DEFAULT_VALUE (1) +#define AW_PID_2049_NOCLKM_DEFAULT \ + (AW_PID_2049_NOCLKM_DEFAULT_VALUE << AW_PID_2049_NOCLKM_START_BIT) + +/* CLKM bit 4 (SYSINTM 0x03) */ +#define AW_PID_2049_CLKM_START_BIT (4) +#define AW_PID_2049_CLKM_BITS_LEN (1) +#define AW_PID_2049_CLKM_MASK \ + (~(((1<<AW_PID_2049_CLKM_BITS_LEN)-1) << AW_PID_2049_CLKM_START_BIT)) + +#define AW_PID_2049_CLKM_DEFAULT_VALUE (1) +#define AW_PID_2049_CLKM_DEFAULT \ + (AW_PID_2049_CLKM_DEFAULT_VALUE << AW_PID_2049_CLKM_START_BIT) + +/* OCDM bit 3 (SYSINTM 0x03) */ +#define AW_PID_2049_OCDM_START_BIT (3) +#define AW_PID_2049_OCDM_BITS_LEN (1) +#define AW_PID_2049_OCDM_MASK \ + (~(((1<<AW_PID_2049_OCDM_BITS_LEN)-1) << AW_PID_2049_OCDM_START_BIT)) + +#define AW_PID_2049_OCDM_DEFAULT_VALUE (1) +#define AW_PID_2049_OCDM_DEFAULT \ + (AW_PID_2049_OCDM_DEFAULT_VALUE << AW_PID_2049_OCDM_START_BIT) + +/* CLIP_PREM bit 2 (SYSINTM 0x03) */ +#define AW_PID_2049_CLIP_PREM_START_BIT (2) +#define AW_PID_2049_CLIP_PREM_BITS_LEN (1) +#define AW_PID_2049_CLIP_PREM_MASK \ + (~(((1<<AW_PID_2049_CLIP_PREM_BITS_LEN)-1) << AW_PID_2049_CLIP_PREM_START_BIT)) + +#define AW_PID_2049_CLIP_PREM_DEFAULT_VALUE (1) +#define AW_PID_2049_CLIP_PREM_DEFAULT \ + (AW_PID_2049_CLIP_PREM_DEFAULT_VALUE << AW_PID_2049_CLIP_PREM_START_BIT) + +/* OTHM bit 1 (SYSINTM 0x03) */ +#define AW_PID_2049_OTHM_START_BIT (1) +#define AW_PID_2049_OTHM_BITS_LEN (1) +#define AW_PID_2049_OTHM_MASK \ + (~(((1<<AW_PID_2049_OTHM_BITS_LEN)-1) << AW_PID_2049_OTHM_START_BIT)) + +#define AW_PID_2049_OTHM_DEFAULT_VALUE (1) +#define AW_PID_2049_OTHM_DEFAULT \ + (AW_PID_2049_OTHM_DEFAULT_VALUE << AW_PID_2049_OTHM_START_BIT) + +/* PLLM bit 0 (SYSINTM 0x03) */ +#define AW_PID_2049_PLLM_START_BIT (0) +#define AW_PID_2049_PLLM_BITS_LEN (1) +#define AW_PID_2049_PLLM_MASK \ + (~(((1<<AW_PID_2049_PLLM_BITS_LEN)-1) << AW_PID_2049_PLLM_START_BIT)) + +#define AW_PID_2049_PLLM_DEFAULT_VALUE (1) +#define AW_PID_2049_PLLM_DEFAULT \ + (AW_PID_2049_PLLM_DEFAULT_VALUE << AW_PID_2049_PLLM_START_BIT) + +/* default value of SYSINTM (0x03) */ +#define AW_PID_2049_SYSINTM_DEFAULT (0xFFFF) + +/* SYSCTRL (0x04) detail */ +/* SPK_GAIN bit 14:12 (SYSCTRL 0x04) */ +#define AW_PID_2049_SPK_GAIN_START_BIT (12) +#define AW_PID_2049_SPK_GAIN_BITS_LEN (3) +#define AW_PID_2049_SPK_GAIN_MASK \ + (~(((1<<AW_PID_2049_SPK_GAIN_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_START_BIT)) + +#define AW_PID_2049_SPK_GAIN_4_AV (0) +#define AW_PID_2049_SPK_GAIN_4_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_4_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_4P67_AV (1) +#define AW_PID_2049_SPK_GAIN_4P67_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_4P67_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_6_AV (2) +#define AW_PID_2049_SPK_GAIN_6_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_6_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_7_AV (3) +#define AW_PID_2049_SPK_GAIN_7_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_7_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_12_AV (4) +#define AW_PID_2049_SPK_GAIN_12_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_12_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_14_AV (5) +#define AW_PID_2049_SPK_GAIN_14_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_14_AV << AW_PID_2049_SPK_GAIN_START_BIT) + +#define AW_PID_2049_SPK_GAIN_DEFAULT_VALUE (0x5) +#define AW_PID_2049_SPK_GAIN_DEFAULT \ + (AW_PID_2049_SPK_GAIN_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_START_BIT) + +/* RMSE bit 11 (SYSCTRL 0x04) */ +#define AW_PID_2049_RMSE_START_BIT (11) +#define AW_PID_2049_RMSE_BITS_LEN (1) +#define AW_PID_2049_RMSE_MASK \ + (~(((1<<AW_PID_2049_RMSE_BITS_LEN)-1) << AW_PID_2049_RMSE_START_BIT)) + +#define AW_PID_2049_RMSE_PEAK_AGC (0) +#define AW_PID_2049_RMSE_PEAK_AGC_VALUE \ + (AW_PID_2049_RMSE_PEAK_AGC << AW_PID_2049_RMSE_START_BIT) + +#define AW_PID_2049_RMSE_RMS_AGC (1) +#define AW_PID_2049_RMSE_RMS_AGC_VALUE \ + (AW_PID_2049_RMSE_RMS_AGC << AW_PID_2049_RMSE_START_BIT) + +#define AW_PID_2049_RMSE_DEFAULT_VALUE (0) +#define AW_PID_2049_RMSE_DEFAULT \ + (AW_PID_2049_RMSE_DEFAULT_VALUE << AW_PID_2049_RMSE_START_BIT) + +/* HAGCE bit 10 (SYSCTRL 0x04) */ +#define AW_PID_2049_HAGCE_START_BIT (10) +#define AW_PID_2049_HAGCE_BITS_LEN (1) +#define AW_PID_2049_HAGCE_MASK \ + (~(((1<<AW_PID_2049_HAGCE_BITS_LEN)-1) << AW_PID_2049_HAGCE_START_BIT)) + +#define AW_PID_2049_HAGCE_DISABLE (0) +#define AW_PID_2049_HAGCE_DISABLE_VALUE \ + (AW_PID_2049_HAGCE_DISABLE << AW_PID_2049_HAGCE_START_BIT) + +#define AW_PID_2049_HAGCE_ENABLE (1) +#define AW_PID_2049_HAGCE_ENABLE_VALUE \ + (AW_PID_2049_HAGCE_ENABLE << AW_PID_2049_HAGCE_START_BIT) + +#define AW_PID_2049_HAGCE_DEFAULT_VALUE (0) +#define AW_PID_2049_HAGCE_DEFAULT \ + (AW_PID_2049_HAGCE_DEFAULT_VALUE << AW_PID_2049_HAGCE_START_BIT) + +/* HDCCE bit 9 (SYSCTRL 0x04) */ +#define AW_PID_2049_HDCCE_START_BIT (9) +#define AW_PID_2049_HDCCE_BITS_LEN (1) +#define AW_PID_2049_HDCCE_MASK \ + (~(((1<<AW_PID_2049_HDCCE_BITS_LEN)-1) << AW_PID_2049_HDCCE_START_BIT)) + +#define AW_PID_2049_HDCCE_DISABLE (0) +#define AW_PID_2049_HDCCE_DISABLE_VALUE \ + (AW_PID_2049_HDCCE_DISABLE << AW_PID_2049_HDCCE_START_BIT) + +#define AW_PID_2049_HDCCE_ENABLE (1) +#define AW_PID_2049_HDCCE_ENABLE_VALUE \ + (AW_PID_2049_HDCCE_ENABLE << AW_PID_2049_HDCCE_START_BIT) + +#define AW_PID_2049_HDCCE_DEFAULT_VALUE (1) +#define AW_PID_2049_HDCCE_DEFAULT \ + (AW_PID_2049_HDCCE_DEFAULT_VALUE << AW_PID_2049_HDCCE_START_BIT) + +/* HMUTE bit 8 (SYSCTRL 0x04) */ +#define AW_PID_2049_HMUTE_START_BIT (8) +#define AW_PID_2049_HMUTE_BITS_LEN (1) +#define AW_PID_2049_HMUTE_MASK \ + (~(((1<<AW_PID_2049_HMUTE_BITS_LEN)-1) << AW_PID_2049_HMUTE_START_BIT)) + +#define AW_PID_2049_HMUTE_DISABLE (0) +#define AW_PID_2049_HMUTE_DISABLE_VALUE \ + (AW_PID_2049_HMUTE_DISABLE << AW_PID_2049_HMUTE_START_BIT) + +#define AW_PID_2049_HMUTE_ENABLE (1) +#define AW_PID_2049_HMUTE_ENABLE_VALUE \ + (AW_PID_2049_HMUTE_ENABLE << AW_PID_2049_HMUTE_START_BIT) + +#define AW_PID_2049_HMUTE_DEFAULT_VALUE (1) +#define AW_PID_2049_HMUTE_DEFAULT \ + (AW_PID_2049_HMUTE_DEFAULT_VALUE << AW_PID_2049_HMUTE_START_BIT) + +/* RCV_MODE bit 7 (SYSCTRL 0x04) */ +#define AW_PID_2049_RCV_MODE_START_BIT (7) +#define AW_PID_2049_RCV_MODE_BITS_LEN (1) +#define AW_PID_2049_RCV_MODE_MASK \ + (~(((1<<AW_PID_2049_RCV_MODE_BITS_LEN)-1) << AW_PID_2049_RCV_MODE_START_BIT)) + +#define AW_PID_2049_RCV_MODE_SPEAKER (0) +#define AW_PID_2049_RCV_MODE_SPEAKER_VALUE \ + (AW_PID_2049_RCV_MODE_SPEAKER << AW_PID_2049_RCV_MODE_START_BIT) + +#define AW_PID_2049_RCV_MODE_RECEIVER (1) +#define AW_PID_2049_RCV_MODE_RECEIVER_VALUE \ + (AW_PID_2049_RCV_MODE_RECEIVER << AW_PID_2049_RCV_MODE_START_BIT) + +#define AW_PID_2049_RCV_MODE_DEFAULT_VALUE (0) +#define AW_PID_2049_RCV_MODE_DEFAULT \ + (AW_PID_2049_RCV_MODE_DEFAULT_VALUE << AW_PID_2049_RCV_MODE_START_BIT) + +/* I2SEN bit 6 (SYSCTRL 0x04) */ +#define AW_PID_2049_I2SEN_START_BIT (6) +#define AW_PID_2049_I2SEN_BITS_LEN (1) +#define AW_PID_2049_I2SEN_MASK \ + (~(((1<<AW_PID_2049_I2SEN_BITS_LEN)-1) << AW_PID_2049_I2SEN_START_BIT)) + +#define AW_PID_2049_I2SEN_DISABLE (0) +#define AW_PID_2049_I2SEN_DISABLE_VALUE \ + (AW_PID_2049_I2SEN_DISABLE << AW_PID_2049_I2SEN_START_BIT) + +#define AW_PID_2049_I2SEN_ENABLE (1) +#define AW_PID_2049_I2SEN_ENABLE_VALUE \ + (AW_PID_2049_I2SEN_ENABLE << AW_PID_2049_I2SEN_START_BIT) + +#define AW_PID_2049_I2SEN_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SEN_DEFAULT \ + (AW_PID_2049_I2SEN_DEFAULT_VALUE << AW_PID_2049_I2SEN_START_BIT) + +/* WSINV bit 5 (SYSCTRL 0x04) */ +#define AW_PID_2049_WSINV_START_BIT (5) +#define AW_PID_2049_WSINV_BITS_LEN (1) +#define AW_PID_2049_WSINV_MASK \ + (~(((1<<AW_PID_2049_WSINV_BITS_LEN)-1) << AW_PID_2049_WSINV_START_BIT)) + +#define AW_PID_2049_WSINV_NOT_SWITCH (0) +#define AW_PID_2049_WSINV_NOT_SWITCH_VALUE \ + (AW_PID_2049_WSINV_NOT_SWITCH << AW_PID_2049_WSINV_START_BIT) + +#define AW_PID_2049_WSINV_SWITCH (1) +#define AW_PID_2049_WSINV_SWITCH_VALUE \ + (AW_PID_2049_WSINV_SWITCH << AW_PID_2049_WSINV_START_BIT) + +#define AW_PID_2049_WSINV_DEFAULT_VALUE (0) +#define AW_PID_2049_WSINV_DEFAULT \ + (AW_PID_2049_WSINV_DEFAULT_VALUE << AW_PID_2049_WSINV_START_BIT) + +/* BCKINV bit 4 (SYSCTRL 0x04) */ +#define AW_PID_2049_BCKINV_START_BIT (4) +#define AW_PID_2049_BCKINV_BITS_LEN (1) +#define AW_PID_2049_BCKINV_MASK \ + (~(((1<<AW_PID_2049_BCKINV_BITS_LEN)-1) << AW_PID_2049_BCKINV_START_BIT)) + +#define AW_PID_2049_BCKINV_NOT_INVERT (0) +#define AW_PID_2049_BCKINV_NOT_INVERT_VALUE \ + (AW_PID_2049_BCKINV_NOT_INVERT << AW_PID_2049_BCKINV_START_BIT) + +#define AW_PID_2049_BCKINV_INVERTED (1) +#define AW_PID_2049_BCKINV_INVERTED_VALUE \ + (AW_PID_2049_BCKINV_INVERTED << AW_PID_2049_BCKINV_START_BIT) + +#define AW_PID_2049_BCKINV_DEFAULT_VALUE (0) +#define AW_PID_2049_BCKINV_DEFAULT \ + (AW_PID_2049_BCKINV_DEFAULT_VALUE << AW_PID_2049_BCKINV_START_BIT) + +/* IPLL bit 3 (SYSCTRL 0x04) */ +#define AW_PID_2049_IPLL_START_BIT (3) +#define AW_PID_2049_IPLL_BITS_LEN (1) +#define AW_PID_2049_IPLL_MASK \ + (~(((1<<AW_PID_2049_IPLL_BITS_LEN)-1) << AW_PID_2049_IPLL_START_BIT)) + +#define AW_PID_2049_IPLL_BCK (0) +#define AW_PID_2049_IPLL_BCK_VALUE \ + (AW_PID_2049_IPLL_BCK << AW_PID_2049_IPLL_START_BIT) + +#define AW_PID_2049_IPLL_WCK (1) +#define AW_PID_2049_IPLL_WCK_VALUE \ + (AW_PID_2049_IPLL_WCK << AW_PID_2049_IPLL_START_BIT) + +#define AW_PID_2049_IPLL_DEFAULT_VALUE (0) +#define AW_PID_2049_IPLL_DEFAULT \ + (AW_PID_2049_IPLL_DEFAULT_VALUE << AW_PID_2049_IPLL_START_BIT) + +/* DSPBY bit 2 (SYSCTRL 0x04) */ +#define AW_PID_2049_DSPBY_START_BIT (2) +#define AW_PID_2049_DSPBY_BITS_LEN (1) +#define AW_PID_2049_DSPBY_MASK \ + (~(((1<<AW_PID_2049_DSPBY_BITS_LEN)-1) << AW_PID_2049_DSPBY_START_BIT)) + +#define AW_PID_2049_DSPBY_WORKING (0) +#define AW_PID_2049_DSPBY_WORKING_VALUE \ + (AW_PID_2049_DSPBY_WORKING << AW_PID_2049_DSPBY_START_BIT) + +#define AW_PID_2049_DSPBY_BYPASS (1) +#define AW_PID_2049_DSPBY_BYPASS_VALUE \ + (AW_PID_2049_DSPBY_BYPASS << AW_PID_2049_DSPBY_START_BIT) + +#define AW_PID_2049_DSPBY_DEFAULT_VALUE (1) +#define AW_PID_2049_DSPBY_DEFAULT \ + (AW_PID_2049_DSPBY_DEFAULT_VALUE << AW_PID_2049_DSPBY_START_BIT) + +/* AMPPD bit 1 (SYSCTRL 0x04) */ +#define AW_PID_2049_AMPPD_START_BIT (1) +#define AW_PID_2049_AMPPD_BITS_LEN (1) +#define AW_PID_2049_AMPPD_MASK \ + (~(((1<<AW_PID_2049_AMPPD_BITS_LEN)-1) << AW_PID_2049_AMPPD_START_BIT)) + +#define AW_PID_2049_AMPPD_WORKING (0) +#define AW_PID_2049_AMPPD_WORKING_VALUE \ + (AW_PID_2049_AMPPD_WORKING << AW_PID_2049_AMPPD_START_BIT) + +#define AW_PID_2049_AMPPD_POWER_DOWN (1) +#define AW_PID_2049_AMPPD_POWER_DOWN_VALUE \ + (AW_PID_2049_AMPPD_POWER_DOWN << AW_PID_2049_AMPPD_START_BIT) + +#define AW_PID_2049_AMPPD_DEFAULT_VALUE (1) +#define AW_PID_2049_AMPPD_DEFAULT \ + (AW_PID_2049_AMPPD_DEFAULT_VALUE << AW_PID_2049_AMPPD_START_BIT) + +/* PWDN bit 0 (SYSCTRL 0x04) */ +#define AW_PID_2049_PWDN_START_BIT (0) +#define AW_PID_2049_PWDN_BITS_LEN (1) +#define AW_PID_2049_PWDN_MASK \ + (~(((1<<AW_PID_2049_PWDN_BITS_LEN)-1) << AW_PID_2049_PWDN_START_BIT)) + +#define AW_PID_2049_PWDN_WORKING (0) +#define AW_PID_2049_PWDN_WORKING_VALUE \ + (AW_PID_2049_PWDN_WORKING << AW_PID_2049_PWDN_START_BIT) + +#define AW_PID_2049_PWDN_POWER_DOWN (1) +#define AW_PID_2049_PWDN_POWER_DOWN_VALUE \ + (AW_PID_2049_PWDN_POWER_DOWN << AW_PID_2049_PWDN_START_BIT) + +#define AW_PID_2049_PWDN_DEFAULT_VALUE (1) +#define AW_PID_2049_PWDN_DEFAULT \ + (AW_PID_2049_PWDN_DEFAULT_VALUE << AW_PID_2049_PWDN_START_BIT) + +/* default value of SYSCTRL (0x04) */ +/* #define AW_PID_2049_SYSCTRL_DEFAULT (0x5307) */ + +/* SYSCTRL2 (0x05) detail */ +/* VOL bit 15:6 (SYSCTRL2 0x05) */ +#define AW_PID_2049_MUTE_VOL (90 * 8) +#define AW_PID_2049_VOLUME_STEP_DB (6 * 8) + +#define AW_PID_2049_VOL_6DB_START (6) +#define AW_PID_2049_VOL_START_BIT (6) +#define AW_PID_2049_VOL_BITS_LEN (10) +#define AW_PID_2049_VOL_MASK \ + (~(((1<<AW_PID_2049_VOL_BITS_LEN)-1) << AW_PID_2049_VOL_START_BIT)) + +#define AW_PID_2049_VOL_DEFAULT_VALUE (0) +#define AW_PID_2049_VOL_DEFAULT \ + (AW_PID_2049_VOL_DEFAULT_VALUE << AW_PID_2049_VOL_START_BIT) + +/* INTMODE bit 5 (SYSCTRL2 0x05) */ +#define AW_PID_2049_INTMODE_START_BIT (5) +#define AW_PID_2049_INTMODE_BITS_LEN (1) +#define AW_PID_2049_INTMODE_MASK \ + (~(((1<<AW_PID_2049_INTMODE_BITS_LEN)-1) << AW_PID_2049_INTMODE_START_BIT)) + +#define AW_PID_2049_INTMODE_OPENMINUS_DRAIN (0) +#define AW_PID_2049_INTMODE_OPENMINUS_DRAIN_VALUE \ + (AW_PID_2049_INTMODE_OPENMINUS_DRAIN << AW_PID_2049_INTMODE_START_BIT) + +#define AW_PID_2049_INTMODE_PUSHPULL (1) +#define AW_PID_2049_INTMODE_PUSHPULL_VALUE \ + (AW_PID_2049_INTMODE_PUSHPULL << AW_PID_2049_INTMODE_START_BIT) + +#define AW_PID_2049_INTMODE_DEFAULT_VALUE (0) +#define AW_PID_2049_INTMODE_DEFAULT \ + (AW_PID_2049_INTMODE_DEFAULT_VALUE << AW_PID_2049_INTMODE_START_BIT) + +/* INTN bit 4 (SYSCTRL2 0x05) */ +#define AW_PID_2049_INTN_START_BIT (4) +#define AW_PID_2049_INTN_BITS_LEN (1) +#define AW_PID_2049_INTN_MASK \ + (~(((1<<AW_PID_2049_INTN_BITS_LEN)-1) << AW_PID_2049_INTN_START_BIT)) + +#define AW_PID_2049_INTN_SYSINT (0) +#define AW_PID_2049_INTN_SYSINT_VALUE \ + (AW_PID_2049_INTN_SYSINT << AW_PID_2049_INTN_START_BIT) + +#define AW_PID_2049_INTN_SYSST (1) +#define AW_PID_2049_INTN_SYSST_VALUE \ + (AW_PID_2049_INTN_SYSST << AW_PID_2049_INTN_START_BIT) + +#define AW_PID_2049_INTN_DEFAULT_VALUE (0) +#define AW_PID_2049_INTN_DEFAULT \ + (AW_PID_2049_INTN_DEFAULT_VALUE << AW_PID_2049_INTN_START_BIT) + +/* BST_IPEAK bit 3:0 (SYSCTRL2 0x05) */ +#define AW_PID_2049_BST_IPEAK_START_BIT (0) +#define AW_PID_2049_BST_IPEAK_BITS_LEN (4) +#define AW_PID_2049_BST_IPEAK_MASK \ + (~(((1<<AW_PID_2049_BST_IPEAK_BITS_LEN)-1) << AW_PID_2049_BST_IPEAK_START_BIT)) + +#define AW_PID_2049_BST_IPEAK_1P50A (0) +#define AW_PID_2049_BST_IPEAK_1P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_1P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_1P75A (1) +#define AW_PID_2049_BST_IPEAK_1P75A_VALUE \ + (AW_PID_2049_BST_IPEAK_1P75A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P00A (2) +#define AW_PID_2049_BST_IPEAK_2P00A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P00A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P25A (3) +#define AW_PID_2049_BST_IPEAK_2P25A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P25A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P50A (4) +#define AW_PID_2049_BST_IPEAK_2P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_2P75A (5) +#define AW_PID_2049_BST_IPEAK_2P75A_VALUE \ + (AW_PID_2049_BST_IPEAK_2P75A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P00A (6) +#define AW_PID_2049_BST_IPEAK_3P00A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P00A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P25A (7) +#define AW_PID_2049_BST_IPEAK_3P25A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P25A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P50A (8) +#define AW_PID_2049_BST_IPEAK_3P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_3P75A (9) +#define AW_PID_2049_BST_IPEAK_3P75A_VALUE \ + (AW_PID_2049_BST_IPEAK_3P75A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_4P00A (10) +#define AW_PID_2049_BST_IPEAK_4P00A_VALUE \ + (AW_PID_2049_BST_IPEAK_4P00A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_4P25A (11) +#define AW_PID_2049_BST_IPEAK_4P25A_VALUE \ + (AW_PID_2049_BST_IPEAK_4P25A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_4P50A (12) +#define AW_PID_2049_BST_IPEAK_4P50A_VALUE \ + (AW_PID_2049_BST_IPEAK_4P50A << AW_PID_2049_BST_IPEAK_START_BIT) + +#define AW_PID_2049_BST_IPEAK_DEFAULT_VALUE (9) +#define AW_PID_2049_BST_IPEAK_DEFAULT \ + (AW_PID_2049_BST_IPEAK_DEFAULT_VALUE << AW_PID_2049_BST_IPEAK_START_BIT) + +/* default value of SYSCTRL2 (0x05) */ +/* #define AW_PID_2049_SYSCTRL2_DEFAULT (0x0009) */ + +/* I2SCTRL (0x06) detail */ +/* SLOT_NUM bit 14:12 (I2SCTRL 0x06) */ +#define AW_PID_2049_SLOT_NUM_START_BIT (12) +#define AW_PID_2049_SLOT_NUM_BITS_LEN (3) +#define AW_PID_2049_SLOT_NUM_MASK \ + (~(((1<<AW_PID_2049_SLOT_NUM_BITS_LEN)-1) << AW_PID_2049_SLOT_NUM_START_BIT)) + +#define AW_PID_2049_SLOT_NUM_I2S_MODE (0) +#define AW_PID_2049_SLOT_NUM_I2S_MODE_VALUE \ + (AW_PID_2049_SLOT_NUM_I2S_MODE << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM1S (1) +#define AW_PID_2049_SLOT_NUM_TDM1S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM1S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM2S (2) +#define AW_PID_2049_SLOT_NUM_TDM2S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM2S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM4S (3) +#define AW_PID_2049_SLOT_NUM_TDM4S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM4S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM6S (4) +#define AW_PID_2049_SLOT_NUM_TDM6S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM6S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM8S (5) +#define AW_PID_2049_SLOT_NUM_TDM8S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM8S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_TDM16S (6) +#define AW_PID_2049_SLOT_NUM_TDM16S_VALUE \ + (AW_PID_2049_SLOT_NUM_TDM16S << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_RESERVED (7) +#define AW_PID_2049_SLOT_NUM_RESERVED_VALUE \ + (AW_PID_2049_SLOT_NUM_RESERVED << AW_PID_2049_SLOT_NUM_START_BIT) + +#define AW_PID_2049_SLOT_NUM_DEFAULT_VALUE (0) +#define AW_PID_2049_SLOT_NUM_DEFAULT \ + (AW_PID_2049_SLOT_NUM_DEFAULT_VALUE << AW_PID_2049_SLOT_NUM_START_BIT) + +/* CHSEL bit 11:10 (I2SCTRL 0x06) */ +#define AW_PID_2049_CHSEL_START_BIT (10) +#define AW_PID_2049_CHSEL_BITS_LEN (2) +#define AW_PID_2049_CHSEL_MASK \ + (~(((1<<AW_PID_2049_CHSEL_BITS_LEN)-1) << AW_PID_2049_CHSEL_START_BIT)) + +#define AW_PID_2049_CHSEL_RESERVED (0) +#define AW_PID_2049_CHSEL_RESERVED_VALUE \ + (AW_PID_2049_CHSEL_RESERVED << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_LEFT (1) +#define AW_PID_2049_CHSEL_LEFT_VALUE \ + (AW_PID_2049_CHSEL_LEFT << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_RIGHT (2) +#define AW_PID_2049_CHSEL_RIGHT_VALUE \ + (AW_PID_2049_CHSEL_RIGHT << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_MONO (3) +#define AW_PID_2049_CHSEL_MONO_VALUE \ + (AW_PID_2049_CHSEL_MONO << AW_PID_2049_CHSEL_START_BIT) + +#define AW_PID_2049_CHSEL_DEFAULT_VALUE (1) +#define AW_PID_2049_CHSEL_DEFAULT \ + (AW_PID_2049_CHSEL_DEFAULT_VALUE << AW_PID_2049_CHSEL_START_BIT) + +/* I2SMD bit 9:8 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SMD_START_BIT (8) +#define AW_PID_2049_I2SMD_BITS_LEN (2) +#define AW_PID_2049_I2SMD_MASK \ + (~(((1<<AW_PID_2049_I2SMD_BITS_LEN)-1) << AW_PID_2049_I2SMD_START_BIT)) + +#define AW_PID_2049_I2SMD_PHILIP_STANDARD (0) +#define AW_PID_2049_I2SMD_PHILIP_STANDARD_VALUE \ + (AW_PID_2049_I2SMD_PHILIP_STANDARD << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_MSB_JUSTIFIED (1) +#define AW_PID_2049_I2SMD_MSB_JUSTIFIED_VALUE \ + (AW_PID_2049_I2SMD_MSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_LSB_JUSTIFIED (2) +#define AW_PID_2049_I2SMD_LSB_JUSTIFIED_VALUE \ + (AW_PID_2049_I2SMD_LSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_RESERVED (3) +#define AW_PID_2049_I2SMD_RESERVED_VALUE \ + (AW_PID_2049_I2SMD_RESERVED << AW_PID_2049_I2SMD_START_BIT) + +#define AW_PID_2049_I2SMD_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SMD_DEFAULT \ + (AW_PID_2049_I2SMD_DEFAULT_VALUE << AW_PID_2049_I2SMD_START_BIT) + +/* I2SFS bit 7:6 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SFS_START_BIT (6) +#define AW_PID_2049_I2SFS_BITS_LEN (2) +#define AW_PID_2049_I2SFS_MASK \ + (~(((1<<AW_PID_2049_I2SFS_BITS_LEN)-1) << AW_PID_2049_I2SFS_START_BIT)) + +#define AW_PID_2049_I2SFS_16_BITS (0) +#define AW_PID_2049_I2SFS_16_BITS_VALUE \ + (AW_PID_2049_I2SFS_16_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_20_BITS (1) +#define AW_PID_2049_I2SFS_20_BITS_VALUE \ + (AW_PID_2049_I2SFS_20_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_24_BITS (2) +#define AW_PID_2049_I2SFS_24_BITS_VALUE \ + (AW_PID_2049_I2SFS_24_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_32_BITS (3) +#define AW_PID_2049_I2SFS_32_BITS_VALUE \ + (AW_PID_2049_I2SFS_32_BITS << AW_PID_2049_I2SFS_START_BIT) + +#define AW_PID_2049_I2SFS_DEFAULT_VALUE (3) +#define AW_PID_2049_I2SFS_DEFAULT \ + (AW_PID_2049_I2SFS_DEFAULT_VALUE << AW_PID_2049_I2SFS_START_BIT) + +/* I2SBCK bit 5:4 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SBCK_START_BIT (4) +#define AW_PID_2049_I2SBCK_BITS_LEN (2) +#define AW_PID_2049_I2SBCK_MASK \ + (~(((1<<AW_PID_2049_I2SBCK_BITS_LEN)-1) << AW_PID_2049_I2SBCK_START_BIT)) + +#define AW_PID_2049_I2SBCK_32FS (0) +#define AW_PID_2049_I2SBCK_32FS_VALUE \ + (AW_PID_2049_I2SBCK_32FS << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_48FS (1) +#define AW_PID_2049_I2SBCK_48FS_VALUE \ + (AW_PID_2049_I2SBCK_48FS << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_64FS (2) +#define AW_PID_2049_I2SBCK_64FS_VALUE \ + (AW_PID_2049_I2SBCK_64FS << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_RESERVED (3) +#define AW_PID_2049_I2SBCK_RESERVED_VALUE \ + (AW_PID_2049_I2SBCK_RESERVED << AW_PID_2049_I2SBCK_START_BIT) + +#define AW_PID_2049_I2SBCK_DEFAULT_VALUE (2) +#define AW_PID_2049_I2SBCK_DEFAULT \ + (AW_PID_2049_I2SBCK_DEFAULT_VALUE << AW_PID_2049_I2SBCK_START_BIT) + +/* I2SSR bit 3:0 (I2SCTRL 0x06) */ +#define AW_PID_2049_I2SSR_START_BIT (0) +#define AW_PID_2049_I2SSR_BITS_LEN (4) +#define AW_PID_2049_I2SSR_MASK \ + (~(((1<<AW_PID_2049_I2SSR_BITS_LEN)-1) << AW_PID_2049_I2SSR_START_BIT)) + +#define AW_PID_2049_I2SSR_8_KHZ (0) +#define AW_PID_2049_I2SSR_8_KHZ_VALUE \ + (AW_PID_2049_I2SSR_8_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_11_KHZ (1) +#define AW_PID_2049_I2SSR_11_KHZ_VALUE \ + (AW_PID_2049_I2SSR_11_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_12_KHZ (2) +#define AW_PID_2049_I2SSR_12_KHZ_VALUE \ + (AW_PID_2049_I2SSR_12_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_16_KHZ (3) +#define AW_PID_2049_I2SSR_16_KHZ_VALUE \ + (AW_PID_2049_I2SSR_16_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_22_KHZ (4) +#define AW_PID_2049_I2SSR_22_KHZ_VALUE \ + (AW_PID_2049_I2SSR_22_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_24_KHZ (5) +#define AW_PID_2049_I2SSR_24_KHZ_VALUE \ + (AW_PID_2049_I2SSR_24_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_32_KHZ (6) +#define AW_PID_2049_I2SSR_32_KHZ_VALUE \ + (AW_PID_2049_I2SSR_32_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_44_KHZ (7) +#define AW_PID_2049_I2SSR_44_KHZ_VALUE \ + (AW_PID_2049_I2SSR_44_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_48_KHZ (8) +#define AW_PID_2049_I2SSR_48_KHZ_VALUE \ + (AW_PID_2049_I2SSR_48_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_96_KHZ (9) +#define AW_PID_2049_I2SSR_96_KHZ_VALUE \ + (AW_PID_2049_I2SSR_96_KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_192KHZ (10) +#define AW_PID_2049_I2SSR_192KHZ_VALUE \ + (AW_PID_2049_I2SSR_192KHZ << AW_PID_2049_I2SSR_START_BIT) + +#define AW_PID_2049_I2SSR_DEFAULT_VALUE (8) +#define AW_PID_2049_I2SSR_DEFAULT \ + (AW_PID_2049_I2SSR_DEFAULT_VALUE << AW_PID_2049_I2SSR_START_BIT) + +/* default value of I2SCTRL (0x06) */ +/* #define AW_PID_2049_I2SCTRL_DEFAULT (0x04E8) */ + +/* I2SCFG1 (0x07) detail */ +/* I2S_RXL_SLOTVLD bit 15:12 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT (12) +#define AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN (4) +#define AW_PID_2049_I2S_RXL_SLOTVLD_MASK \ + (~(((1<<AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0 (0) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1 (1) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2 (2) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3 (3) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15 (15) +#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15_VALUE \ + (AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE (0) +#define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT \ + (AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT) + +/* I2S_RXR_SLOTVLD bit 11:8 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT (8) +#define AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN (4) +#define AW_PID_2049_I2S_RXR_SLOTVLD_MASK \ + (~(((1<<AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0 (0) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1 (1) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2 (2) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3 (3) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15 (15) +#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15_VALUE \ + (AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE (1) +#define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT \ + (AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT) + +/* I2S_TX_SLOTVLD bit 7:4 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2S_TX_SLOTVLD_START_BIT (4) +#define AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN (4) +#define AW_PID_2049_I2S_TX_SLOTVLD_MASK \ + (~(((1<<AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0 (0) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1 (1) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2 (2) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3 (3) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15 (15) +#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15_VALUE \ + (AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +#define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE (0) +#define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT \ + (AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT) + +/* FSYNC_TYPE bit 3 (I2SCFG1 0x07) */ +#define AW_PID_2049_FSYNC_TYPE_START_BIT (3) +#define AW_PID_2049_FSYNC_TYPE_BITS_LEN (1) +#define AW_PID_2049_FSYNC_TYPE_MASK \ + (~(((1<<AW_PID_2049_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_2049_FSYNC_TYPE_START_BIT)) + +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT (0) +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT_VALUE \ + (AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT << AW_PID_2049_FSYNC_TYPE_START_BIT) + +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK (1) +#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK_VALUE \ + (AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK << AW_PID_2049_FSYNC_TYPE_START_BIT) + +#define AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE (0) +#define AW_PID_2049_FSYNC_TYPE_DEFAULT \ + (AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE << AW_PID_2049_FSYNC_TYPE_START_BIT) + +/* I2SCHS bit 2 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2SCHS_START_BIT (2) +#define AW_PID_2049_I2SCHS_BITS_LEN (1) +#define AW_PID_2049_I2SCHS_MASK \ + (~(((1<<AW_PID_2049_I2SCHS_BITS_LEN)-1) << AW_PID_2049_I2SCHS_START_BIT)) + +#define AW_PID_2049_I2SCHS_LEFT (0) +#define AW_PID_2049_I2SCHS_LEFT_VALUE \ + (AW_PID_2049_I2SCHS_LEFT << AW_PID_2049_I2SCHS_START_BIT) + +#define AW_PID_2049_I2SCHS_RIGHT (1) +#define AW_PID_2049_I2SCHS_RIGHT_VALUE \ + (AW_PID_2049_I2SCHS_RIGHT << AW_PID_2049_I2SCHS_START_BIT) + +#define AW_PID_2049_I2SCHS_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SCHS_DEFAULT \ + (AW_PID_2049_I2SCHS_DEFAULT_VALUE << AW_PID_2049_I2SCHS_START_BIT) + +/* I2SRXEN bit 1 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2SRXEN_START_BIT (1) +#define AW_PID_2049_I2SRXEN_BITS_LEN (1) +#define AW_PID_2049_I2SRXEN_MASK \ + (~(((1<<AW_PID_2049_I2SRXEN_BITS_LEN)-1) << AW_PID_2049_I2SRXEN_START_BIT)) + +#define AW_PID_2049_I2SRXEN_DISABLE (0) +#define AW_PID_2049_I2SRXEN_DISABLE_VALUE \ + (AW_PID_2049_I2SRXEN_DISABLE << AW_PID_2049_I2SRXEN_START_BIT) + +#define AW_PID_2049_I2SRXEN_ENABLE (1) +#define AW_PID_2049_I2SRXEN_ENABLE_VALUE \ + (AW_PID_2049_I2SRXEN_ENABLE << AW_PID_2049_I2SRXEN_START_BIT) + +#define AW_PID_2049_I2SRXEN_DEFAULT_VALUE (1) +#define AW_PID_2049_I2SRXEN_DEFAULT \ + (AW_PID_2049_I2SRXEN_DEFAULT_VALUE << AW_PID_2049_I2SRXEN_START_BIT) + +/* I2STXEN bit 0 (I2SCFG1 0x07) */ +#define AW_PID_2049_I2STXEN_START_BIT (0) +#define AW_PID_2049_I2STXEN_BITS_LEN (1) +#define AW_PID_2049_I2STXEN_MASK \ + (~(((1<<AW_PID_2049_I2STXEN_BITS_LEN)-1) << AW_PID_2049_I2STXEN_START_BIT)) + +#define AW_PID_2049_I2STXEN_DISABLE (0) +#define AW_PID_2049_I2STXEN_DISABLE_VALUE \ + (AW_PID_2049_I2STXEN_DISABLE << AW_PID_2049_I2STXEN_START_BIT) + +#define AW_PID_2049_I2STXEN_ENABLE (1) +#define AW_PID_2049_I2STXEN_ENABLE_VALUE \ + (AW_PID_2049_I2STXEN_ENABLE << AW_PID_2049_I2STXEN_START_BIT) + +#define AW_PID_2049_I2STXEN_DEFAULT_VALUE (0) +#define AW_PID_2049_I2STXEN_DEFAULT \ + (AW_PID_2049_I2STXEN_DEFAULT_VALUE << AW_PID_2049_I2STXEN_START_BIT) + +/* default value of I2SCFG1 (0x07) */ +/* #define AW_PID_2049_I2SCFG1_DEFAULT (0x0102) */ + +/* I2SCFG2 (0x08) detail */ +/* ULS_FIR_MD bit 14 (I2SCFG2 0x08) */ +#define AW_PID_2049_ULS_FIR_MD_START_BIT (14) +#define AW_PID_2049_ULS_FIR_MD_BITS_LEN (1) +#define AW_PID_2049_ULS_FIR_MD_MASK \ + (~(((1<<AW_PID_2049_ULS_FIR_MD_BITS_LEN)-1) << AW_PID_2049_ULS_FIR_MD_START_BIT)) + +#define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED (0) +#define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED_VALUE \ + (AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED << AW_PID_2049_ULS_FIR_MD_START_BIT) + +#define AW_PID_2049_ULS_FIR_MD_USED (1) +#define AW_PID_2049_ULS_FIR_MD_USED_VALUE \ + (AW_PID_2049_ULS_FIR_MD_USED << AW_PID_2049_ULS_FIR_MD_START_BIT) + +#define AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE (0) +#define AW_PID_2049_ULS_FIR_MD_DEFAULT \ + (AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE << AW_PID_2049_ULS_FIR_MD_START_BIT) + +/* ULS_MODE bit 13 (I2SCFG2 0x08) */ +#define AW_PID_2049_ULS_MODE_START_BIT (13) +#define AW_PID_2049_ULS_MODE_BITS_LEN (1) +#define AW_PID_2049_ULS_MODE_MASK \ + (~(((1<<AW_PID_2049_ULS_MODE_BITS_LEN)-1) << AW_PID_2049_ULS_MODE_START_BIT)) + +#define AW_PID_2049_ULS_MODE_LOWPASS (0) +#define AW_PID_2049_ULS_MODE_LOWPASS_VALUE \ + (AW_PID_2049_ULS_MODE_LOWPASS << AW_PID_2049_ULS_MODE_START_BIT) + +#define AW_PID_2049_ULS_MODE_TDM (1) +#define AW_PID_2049_ULS_MODE_TDM_VALUE \ + (AW_PID_2049_ULS_MODE_TDM << AW_PID_2049_ULS_MODE_START_BIT) + +#define AW_PID_2049_ULS_MODE_DEFAULT_VALUE (0) +#define AW_PID_2049_ULS_MODE_DEFAULT \ + (AW_PID_2049_ULS_MODE_DEFAULT_VALUE << AW_PID_2049_ULS_MODE_START_BIT) + +/* ULS_EN bit 12 (I2SCFG2 0x08) */ +#define AW_PID_2049_ULS_EN_START_BIT (12) +#define AW_PID_2049_ULS_EN_BITS_LEN (1) +#define AW_PID_2049_ULS_EN_MASK \ + (~(((1<<AW_PID_2049_ULS_EN_BITS_LEN)-1) << AW_PID_2049_ULS_EN_START_BIT)) + +#define AW_PID_2049_ULS_EN_DISABLE (0) +#define AW_PID_2049_ULS_EN_DISABLE_VALUE \ + (AW_PID_2049_ULS_EN_DISABLE << AW_PID_2049_ULS_EN_START_BIT) + +#define AW_PID_2049_ULS_EN_ENABLE (1) +#define AW_PID_2049_ULS_EN_ENABLE_VALUE \ + (AW_PID_2049_ULS_EN_ENABLE << AW_PID_2049_ULS_EN_START_BIT) + +#define AW_PID_2049_ULS_EN_DEFAULT_VALUE (0) +#define AW_PID_2049_ULS_EN_DEFAULT \ + (AW_PID_2049_ULS_EN_DEFAULT_VALUE << AW_PID_2049_ULS_EN_START_BIT) + +/* IV2CH bit 9 (I2SCFG2 0x08) */ +#define AW_PID_2049_IV2CH_START_BIT (9) +#define AW_PID_2049_IV2CH_BITS_LEN (1) +#define AW_PID_2049_IV2CH_MASK \ + (~(((1<<AW_PID_2049_IV2CH_BITS_LEN)-1) << AW_PID_2049_IV2CH_START_BIT)) + +#define AW_PID_2049_IV2CH_LEGACY (0) +#define AW_PID_2049_IV2CH_LEGACY_VALUE \ + (AW_PID_2049_IV2CH_LEGACY << AW_PID_2049_IV2CH_START_BIT) + +#define AW_PID_2049_IV2CH_SPECIAL (1) +#define AW_PID_2049_IV2CH_SPECIAL_VALUE \ + (AW_PID_2049_IV2CH_SPECIAL << AW_PID_2049_IV2CH_START_BIT) + +#define AW_PID_2049_IV2CH_DEFAULT_VALUE (0) +#define AW_PID_2049_IV2CH_DEFAULT \ + (AW_PID_2049_IV2CH_DEFAULT_VALUE << AW_PID_2049_IV2CH_START_BIT) + +/* I2S_TXEDGE bit 8 (I2SCFG2 0x08) */ +#define AW_PID_2049_I2S_TXEDGE_START_BIT (8) +#define AW_PID_2049_I2S_TXEDGE_BITS_LEN (1) +#define AW_PID_2049_I2S_TXEDGE_MASK \ + (~(((1<<AW_PID_2049_I2S_TXEDGE_BITS_LEN)-1) << AW_PID_2049_I2S_TXEDGE_START_BIT)) + +#define AW_PID_2049_I2S_TXEDGE_NEGEDGE (0) +#define AW_PID_2049_I2S_TXEDGE_NEGEDGE_VALUE \ + (AW_PID_2049_I2S_TXEDGE_NEGEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT) + +#define AW_PID_2049_I2S_TXEDGE_POSEDGE (1) +#define AW_PID_2049_I2S_TXEDGE_POSEDGE_VALUE \ + (AW_PID_2049_I2S_TXEDGE_POSEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT) + +#define AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE (0) +#define AW_PID_2049_I2S_TXEDGE_DEFAULT \ + (AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE << AW_PID_2049_I2S_TXEDGE_START_BIT) + +/* I2SDOSEL bit 7 (I2SCFG2 0x08) */ +#define AW_PID_2049_I2SDOSEL_START_BIT (7) +#define AW_PID_2049_I2SDOSEL_BITS_LEN (1) +#define AW_PID_2049_I2SDOSEL_MASK \ + (~(((1<<AW_PID_2049_I2SDOSEL_BITS_LEN)-1) << AW_PID_2049_I2SDOSEL_START_BIT)) + +#define AW_PID_2049_I2SDOSEL_ZEROS (0) +#define AW_PID_2049_I2SDOSEL_ZEROS_VALUE \ + (AW_PID_2049_I2SDOSEL_ZEROS << AW_PID_2049_I2SDOSEL_START_BIT) + +#define AW_PID_2049_I2SDOSEL_TXDATA (1) +#define AW_PID_2049_I2SDOSEL_TXDATA_VALUE \ + (AW_PID_2049_I2SDOSEL_TXDATA << AW_PID_2049_I2SDOSEL_START_BIT) + +#define AW_PID_2049_I2SDOSEL_DEFAULT_VALUE (0) +#define AW_PID_2049_I2SDOSEL_DEFAULT \ + (AW_PID_2049_I2SDOSEL_DEFAULT_VALUE << AW_PID_2049_I2SDOSEL_START_BIT) + +/* DOHZ bit 6 (I2SCFG2 0x08) */ +#define AW_PID_2049_DOHZ_START_BIT (6) +#define AW_PID_2049_DOHZ_BITS_LEN (1) +#define AW_PID_2049_DOHZ_MASK \ + (~(((1<<AW_PID_2049_DOHZ_BITS_LEN)-1) << AW_PID_2049_DOHZ_START_BIT)) + +#define AW_PID_2049_DOHZ_ALL (0) +#define AW_PID_2049_DOHZ_ALL_VALUE \ + (AW_PID_2049_DOHZ_ALL << AW_PID_2049_DOHZ_START_BIT) + +#define AW_PID_2049_DOHZ_HIZ (1) +#define AW_PID_2049_DOHZ_HIZ_VALUE \ + (AW_PID_2049_DOHZ_HIZ << AW_PID_2049_DOHZ_START_BIT) + +#define AW_PID_2049_DOHZ_DEFAULT_VALUE (1) +#define AW_PID_2049_DOHZ_DEFAULT \ + (AW_PID_2049_DOHZ_DEFAULT_VALUE << AW_PID_2049_DOHZ_START_BIT) + +/* DRVSTREN bit 5 (I2SCFG2 0x08) */ +#define AW_PID_2049_DRVSTREN_START_BIT (5) +#define AW_PID_2049_DRVSTREN_BITS_LEN (1) +#define AW_PID_2049_DRVSTREN_MASK \ + (~(((1<<AW_PID_2049_DRVSTREN_BITS_LEN)-1) << AW_PID_2049_DRVSTREN_START_BIT)) + +#define AW_PID_2049_DRVSTREN_4MA (0) +#define AW_PID_2049_DRVSTREN_4MA_VALUE \ + (AW_PID_2049_DRVSTREN_4MA << AW_PID_2049_DRVSTREN_START_BIT) + +#define AW_PID_2049_DRVSTREN_12MA (1) +#define AW_PID_2049_DRVSTREN_12MA_VALUE \ + (AW_PID_2049_DRVSTREN_12MA << AW_PID_2049_DRVSTREN_START_BIT) + +#define AW_PID_2049_DRVSTREN_DEFAULT_VALUE (1) +#define AW_PID_2049_DRVSTREN_DEFAULT \ + (AW_PID_2049_DRVSTREN_DEFAULT_VALUE << AW_PID_2049_DRVSTREN_START_BIT) + +/* INPLEV bit 4 (I2SCFG2 0x08) */ +#define AW_PID_2049_INPLEV_START_BIT (4) +#define AW_PID_2049_INPLEV_BITS_LEN (1) +#define AW_PID_2049_INPLEV_MASK \ + (~(((1<<AW_PID_2049_INPLEV_BITS_LEN)-1) << AW_PID_2049_INPLEV_START_BIT)) + +#define AW_PID_2049_INPLEV_NOT_ATTENUATED (0) +#define AW_PID_2049_INPLEV_NOT_ATTENUATED_VALUE \ + (AW_PID_2049_INPLEV_NOT_ATTENUATED << AW_PID_2049_INPLEV_START_BIT) + +#define AW_PID_2049_INPLEV_ATTENUATED (1) +#define AW_PID_2049_INPLEV_ATTENUATED_VALUE \ + (AW_PID_2049_INPLEV_ATTENUATED << AW_PID_2049_INPLEV_START_BIT) + +#define AW_PID_2049_INPLEV_DEFAULT_VALUE (0) +#define AW_PID_2049_INPLEV_DEFAULT \ + (AW_PID_2049_INPLEV_DEFAULT_VALUE << AW_PID_2049_INPLEV_START_BIT) + +/* CFSEL bit 2:0 (I2SCFG2 0x08) */ +#define AW_PID_2049_CFSEL_START_BIT (0) +#define AW_PID_2049_CFSEL_BITS_LEN (3) +#define AW_PID_2049_CFSEL_MASK \ + (~(((1<<AW_PID_2049_CFSEL_BITS_LEN)-1) << AW_PID_2049_CFSEL_START_BIT)) + +#define AW_PID_2049_CFSEL_HAGC (0) +#define AW_PID_2049_CFSEL_HAGC_VALUE \ + (AW_PID_2049_CFSEL_HAGC << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_DFIFO (1) +#define AW_PID_2049_CFSEL_DFIFO_VALUE \ + (AW_PID_2049_CFSEL_DFIFO << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_ULS (2) +#define AW_PID_2049_CFSEL_ULS_VALUE \ + (AW_PID_2049_CFSEL_ULS << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_IVT_FS (3) +#define AW_PID_2049_CFSEL_IVT_FS_VALUE \ + (AW_PID_2049_CFSEL_IVT_FS << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_IVT_IPVT (4) +#define AW_PID_2049_CFSEL_IVT_IPVT_VALUE \ + (AW_PID_2049_CFSEL_IVT_IPVT << AW_PID_2049_CFSEL_START_BIT) + +#define AW_PID_2049_CFSEL_DEFAULT_VALUE (0) +#define AW_PID_2049_CFSEL_DEFAULT \ + (AW_PID_2049_CFSEL_DEFAULT_VALUE << AW_PID_2049_CFSEL_START_BIT) + +/* default value of I2SCFG2 (0x08) */ +/* #define AW_PID_2049_I2SCFG2_DEFAULT (0x0060) */ + +/* HAGCCFG1 (0x09) detail */ +/* RVTH bit 15:8 (HAGCCFG1 0x09) */ +#define AW_PID_2049_RVTH_START_BIT (8) +#define AW_PID_2049_RVTH_BITS_LEN (8) +#define AW_PID_2049_RVTH_MASK \ + (~(((1<<AW_PID_2049_RVTH_BITS_LEN)-1) << AW_PID_2049_RVTH_START_BIT)) + +#define AW_PID_2049_RVTH_DEFAULT_VALUE (0x39) +#define AW_PID_2049_RVTH_DEFAULT \ + (AW_PID_2049_RVTH_DEFAULT_VALUE << AW_PID_2049_RVTH_START_BIT) + +/* AVTH bit 7:0 (HAGCCFG1 0x09) */ +#define AW_PID_2049_AVTH_START_BIT (0) +#define AW_PID_2049_AVTH_BITS_LEN (8) +#define AW_PID_2049_AVTH_MASK \ + (~(((1<<AW_PID_2049_AVTH_BITS_LEN)-1) << AW_PID_2049_AVTH_START_BIT)) + +#define AW_PID_2049_AVTH_DEFAULT_VALUE (0x40) +#define AW_PID_2049_AVTH_DEFAULT \ + (AW_PID_2049_AVTH_DEFAULT_VALUE << AW_PID_2049_AVTH_START_BIT) + +/* default value of HAGCCFG1 (0x09) */ +/* #define AW_PID_2049_HAGCCFG1_DEFAULT (0x3940) */ + +/* HAGCCFG2 (0x0A) detail */ +/* ATTH bit 15:0 (HAGCCFG2 0x0A) */ +#define AW_PID_2049_ATTH_START_BIT (0) +#define AW_PID_2049_ATTH_BITS_LEN (16) +#define AW_PID_2049_ATTH_MASK \ + (~(((1<<AW_PID_2049_ATTH_BITS_LEN)-1) << AW_PID_2049_ATTH_START_BIT)) + +#define AW_PID_2049_ATTH_RESERVED (0) +#define AW_PID_2049_ATTH_RESERVED_VALUE \ + (AW_PID_2049_ATTH_RESERVED << AW_PID_2049_ATTH_START_BIT) + +#define AW_PID_2049_ATTH_DEFAULT_VALUE (0x0030) +#define AW_PID_2049_ATTH_DEFAULT \ + (AW_PID_2049_ATTH_DEFAULT_VALUE << AW_PID_2049_ATTH_START_BIT) + +/* default value of HAGCCFG2 (0x0A) */ +/* #define AW_PID_2049_HAGCCFG2_DEFAULT (0x0030) */ + +/* HAGCCFG3 (0x0B) detail */ +/* RTTH bit 15:0 (HAGCCFG3 0x0B) */ +#define AW_PID_2049_RTTH_START_BIT (0) +#define AW_PID_2049_RTTH_BITS_LEN (16) +#define AW_PID_2049_RTTH_MASK \ + (~(((1<<AW_PID_2049_RTTH_BITS_LEN)-1) << AW_PID_2049_RTTH_START_BIT)) + +#define AW_PID_2049_RTTH_RESERVED (0) +#define AW_PID_2049_RTTH_RESERVED_VALUE \ + (AW_PID_2049_RTTH_RESERVED << AW_PID_2049_RTTH_START_BIT) + +#define AW_PID_2049_RTTH_DEFAULT_VALUE (0x01E0) +#define AW_PID_2049_RTTH_DEFAULT \ + (AW_PID_2049_RTTH_DEFAULT_VALUE << AW_PID_2049_RTTH_START_BIT) + +/* default value of HAGCCFG3 (0x0B) */ +/* #define AW_PID_2049_HAGCCFG3_DEFAULT (0x01E0) */ + +/* HAGCCFG4 (0x0C) detail */ +/* IIC_GEN_ADDR bit 15:9 (HAGCCFG4 0x0C) */ +#define AW_PID_2049_IIC_GEN_ADDR_START_BIT (9) +#define AW_PID_2049_IIC_GEN_ADDR_BITS_LEN (7) +#define AW_PID_2049_IIC_GEN_ADDR_MASK \ + (~(((1<<AW_PID_2049_IIC_GEN_ADDR_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_ADDR_START_BIT)) + +#define AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE (0x0E) +#define AW_PID_2049_IIC_GEN_ADDR_DEFAULT \ + (AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_ADDR_START_BIT) + +/* IIC_GEN_EN bit 8 (HAGCCFG4 0x0C) */ +#define AW_PID_2049_IIC_GEN_EN_START_BIT (8) +#define AW_PID_2049_IIC_GEN_EN_BITS_LEN (1) +#define AW_PID_2049_IIC_GEN_EN_MASK \ + (~(((1<<AW_PID_2049_IIC_GEN_EN_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_EN_START_BIT)) + +#define AW_PID_2049_IIC_GEN_EN_DISABLE (0) +#define AW_PID_2049_IIC_GEN_EN_DISABLE_VALUE \ + (AW_PID_2049_IIC_GEN_EN_DISABLE << AW_PID_2049_IIC_GEN_EN_START_BIT) + +#define AW_PID_2049_IIC_GEN_EN_ENABLE (1) +#define AW_PID_2049_IIC_GEN_EN_ENABLE_VALUE \ + (AW_PID_2049_IIC_GEN_EN_ENABLE << AW_PID_2049_IIC_GEN_EN_START_BIT) + +#define AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE (0) +#define AW_PID_2049_IIC_GEN_EN_DEFAULT \ + (AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_EN_START_BIT) + +/* HOLDTH bit 7:0 (HAGCCFG4 0x0C) */ +#define AW_PID_2049_HOLDTH_START_BIT (0) +#define AW_PID_2049_HOLDTH_BITS_LEN (8) +#define AW_PID_2049_HOLDTH_MASK \ + (~(((1<<AW_PID_2049_HOLDTH_BITS_LEN)-1) << AW_PID_2049_HOLDTH_START_BIT)) + +#define AW_PID_2049_HOLDTH_RESERVED (0) +#define AW_PID_2049_HOLDTH_RESERVED_VALUE \ + (AW_PID_2049_HOLDTH_RESERVED << AW_PID_2049_HOLDTH_START_BIT) + +#define AW_PID_2049_HOLDTH_DEFAULT_VALUE (0x64) +#define AW_PID_2049_HOLDTH_DEFAULT \ + (AW_PID_2049_HOLDTH_DEFAULT_VALUE << AW_PID_2049_HOLDTH_START_BIT) + +/* default value of HAGCCFG4 (0x0C) */ +/* #define AW_PID_2049_HAGCCFG4_DEFAULT (0x1C64) */ + +/* AGC_DSP_CTL bit 15 (HAGCCFG7 0x0F) */ +#define AW_PID_2049_AGC_DSP_CTL_START_BIT (15) +#define AW_PID_2049_AGC_DSP_CTL_BITS_LEN (1) +#define AW_PID_2049_AGC_DSP_CTL_MASK \ + (~(((1<<AW_PID_2049_AGC_DSP_CTL_BITS_LEN)-1) << AW_PID_2049_AGC_DSP_CTL_START_BIT)) + +#define AW_PID_2049_AGC_DSP_CTL_DISABLE (0) +#define AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE \ + (AW_PID_2049_AGC_DSP_CTL_DISABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT) + +#define AW_PID_2049_AGC_DSP_CTL_ENABLE (1) +#define AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE \ + (AW_PID_2049_AGC_DSP_CTL_ENABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT) +/* VDSEL bit 0 (I2SCFG3 0x12) */ +#define AW_PID_2049_VDSEL_START_BIT (0) +#define AW_PID_2049_VDSEL_BITS_LEN (1) +#define AW_PID_2049_VDSEL_MASK \ + (~(((1<<AW_PID_2049_VDSEL_BITS_LEN)-1) << AW_PID_2049_VDSEL_START_BIT)) + +/* MEM_CLKSEL bit 3 (DBGCTRL 0x13) */ +#define AW_PID_2049_MEM_CLKSEL_START_BIT (3) +#define AW_PID_2049_MEM_CLKSEL_BITS_LEN (1) +#define AW_PID_2049_MEM_CLKSEL_MASK \ + (~(((1<<AW_PID_2049_MEM_CLKSEL_BITS_LEN)-1) << AW_PID_2049_MEM_CLKSEL_START_BIT)) + +#define AW_PID_2049_MEM_CLKSEL_OSC_CLK (0) +#define AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE \ + (AW_PID_2049_MEM_CLKSEL_OSC_CLK << AW_PID_2049_MEM_CLKSEL_START_BIT) + +#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK (1) +#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE \ + (AW_PID_2049_MEM_CLKSEL_DAP_HCLK << AW_PID_2049_MEM_CLKSEL_START_BIT) + +/* HAGCST (0x20) detail */ +/* SPK_GAIN_ST bit 10:8 (HAGCST 0x20) */ +#define AW_PID_2049_SPK_GAIN_ST_START_BIT (8) +#define AW_PID_2049_SPK_GAIN_ST_BITS_LEN (3) +#define AW_PID_2049_SPK_GAIN_ST_MASK \ + (~(((1<<AW_PID_2049_SPK_GAIN_ST_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_ST_START_BIT)) + +#define AW_PID_2049_SPK_GAIN_ST_4_AV (0) +#define AW_PID_2049_SPK_GAIN_ST_4_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_4_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_4P67_AV (1) +#define AW_PID_2049_SPK_GAIN_ST_4P67_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_4P67_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_6_AV (2) +#define AW_PID_2049_SPK_GAIN_ST_6_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_6_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_7_AV (3) +#define AW_PID_2049_SPK_GAIN_ST_7_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_7_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_12_AV (4) +#define AW_PID_2049_SPK_GAIN_ST_12_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_12_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_14_AV (5) +#define AW_PID_2049_SPK_GAIN_ST_14_AV_VALUE \ + (AW_PID_2049_SPK_GAIN_ST_14_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +#define AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE (5) +#define AW_PID_2049_SPK_GAIN_ST_DEFAULT \ + (AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_ST_START_BIT) + +/* BSTVOUT_ST bit 5:0 (HAGCST 0x20) */ +#define AW_PID_2049_BSTVOUT_ST_START_BIT (0) +#define AW_PID_2049_BSTVOUT_ST_BITS_LEN (6) +#define AW_PID_2049_BSTVOUT_ST_MASK \ + (~(((1<<AW_PID_2049_BSTVOUT_ST_BITS_LEN)-1) << AW_PID_2049_BSTVOUT_ST_START_BIT)) + +#define AW_PID_2049_BSTVOUT_ST_3P125V (0) +#define AW_PID_2049_BSTVOUT_ST_3P125V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P125V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P250V (1) +#define AW_PID_2049_BSTVOUT_ST_3P250V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P250V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P375V (2) +#define AW_PID_2049_BSTVOUT_ST_3P375V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P375V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P500V (3) +#define AW_PID_2049_BSTVOUT_ST_3P500V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P500V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P625V (4) +#define AW_PID_2049_BSTVOUT_ST_3P625V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P625V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_3P750V (5) +#define AW_PID_2049_BSTVOUT_ST_3P750V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_3P750V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_11P000V (63) +#define AW_PID_2049_BSTVOUT_ST_11P000V_VALUE \ + (AW_PID_2049_BSTVOUT_ST_11P000V << AW_PID_2049_BSTVOUT_ST_START_BIT) + +#define AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE (0) +#define AW_PID_2049_BSTVOUT_ST_DEFAULT \ + (AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE << AW_PID_2049_BSTVOUT_ST_START_BIT) + +/* default value of HAGCST (0x20) */ +/* #define AW_PID_2049_HAGCST_DEFAULT (0x0500) */ + +/* VBAT (0x21) detail */ +/* VBAT_DET bit 9:0 (VBAT 0x21) */ +#define AW_PID_2049_VBAT_DET_START_BIT (0) +#define AW_PID_2049_VBAT_DET_BITS_LEN (10) +#define AW_PID_2049_VBAT_DET_MASK \ + (~(((1<<AW_PID_2049_VBAT_DET_BITS_LEN)-1) << AW_PID_2049_VBAT_DET_START_BIT)) + +#define AW_PID_2049_VBAT_DET_DEFAULT_VALUE (0x263) +#define AW_PID_2049_VBAT_DET_DEFAULT \ + (AW_PID_2049_VBAT_DET_DEFAULT_VALUE << AW_PID_2049_VBAT_DET_START_BIT) + +#define AW_PID_2049_VBAT_RANGE (6025) +#define AW_PID_2049_INT_10BIT (1023) +/* default value of VBAT (0x21) */ +/* #define AW_PID_2049_VBAT_DEFAULT (0x0263) */ + +/* TEMP (0x22) detail */ +/* TEMP_DET bit 9:0 (TEMP 0x22) */ +#define AW_PID_2049_TEMP_DET_START_BIT (0) +#define AW_PID_2049_TEMP_DET_BITS_LEN (10) +#define AW_PID_2049_TEMP_DET_MASK \ + (~(((1<<AW_PID_2049_TEMP_DET_BITS_LEN)-1) << AW_PID_2049_TEMP_DET_START_BIT)) + +#define AW_PID_2049_TEMP_DET_MINUS_40 (0x3D8) +#define AW_PID_2049_TEMP_DET_MINUS_40_VALUE \ + (AW_PID_2049_TEMP_DET_MINUS_40 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_0 (0x00) +#define AW_PID_2049_TEMP_DET_0_VALUE \ + (AW_PID_2049_TEMP_DET_0 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_1 (0x01) +#define AW_PID_2049_TEMP_DET_1_VALUE \ + (AW_PID_2049_TEMP_DET_1 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_25 (0x19) +#define AW_PID_2049_TEMP_DET_25_VALUE \ + (AW_PID_2049_TEMP_DET_25 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_55 (0x37) +#define AW_PID_2049_TEMP_DET_55_VALUE \ + (AW_PID_2049_TEMP_DET_55 << AW_PID_2049_TEMP_DET_START_BIT) + +#define AW_PID_2049_TEMP_DET_DEFAULT_VALUE (0x019) +#define AW_PID_2049_TEMP_DET_DEFAULT \ + (AW_PID_2049_TEMP_DET_DEFAULT_VALUE << AW_PID_2049_TEMP_DET_START_BIT) +#define AW_PID_2049_TEMP_SIGN_MASK (~(1 << 9)) +#define AW_PID_2049_TEMP_NEG_MASK (0XFC00) + +/* default value of TEMP (0x22) */ +/* #define AW_PID_2049_TEMP_DEFAULT (0x0019) */ + +/* PVDD (0x23) detail */ +/* PVDD_DET bit 9:0 (PVDD 0x23) */ +#define AW_PID_2049_PVDD_DET_START_BIT (0) +#define AW_PID_2049_PVDD_DET_BITS_LEN (10) +#define AW_PID_2049_PVDD_DET_MASK \ + (~(((1<<AW_PID_2049_PVDD_DET_BITS_LEN)-1) << AW_PID_2049_PVDD_DET_START_BIT)) + +#define AW_PID_2049_PVDD_DET_DEFAULT_VALUE (0x263) +#define AW_PID_2049_PVDD_DET_DEFAULT \ + (AW_PID_2049_PVDD_DET_DEFAULT_VALUE << AW_PID_2049_PVDD_DET_START_BIT) + +/* default value of PVDD (0x23) */ +/* #define AW_PID_2049_PVDD_DEFAULT (0x0263) */ + +/* BSTCTRL1 (0x60) detail */ +/* BST_RTH bit 13:8 (BSTCTRL1 0x60) */ +#define AW_PID_2049_BST_RTH_START_BIT (8) +#define AW_PID_2049_BST_RTH_BITS_LEN (6) +#define AW_PID_2049_BST_RTH_MASK \ + (~(((1<<AW_PID_2049_BST_RTH_BITS_LEN)-1) << AW_PID_2049_BST_RTH_START_BIT)) + +#define AW_PID_2049_BST_RTH_DEFAULT_VALUE (4) +#define AW_PID_2049_BST_RTH_DEFAULT \ + (AW_PID_2049_BST_RTH_DEFAULT_VALUE << AW_PID_2049_BST_RTH_START_BIT) + +/* BST_ATH bit 5:0 (BSTCTRL1 0x60) */ +#define AW_PID_2049_BST_ATH_START_BIT (0) +#define AW_PID_2049_BST_ATH_BITS_LEN (6) +#define AW_PID_2049_BST_ATH_MASK \ + (~(((1<<AW_PID_2049_BST_ATH_BITS_LEN)-1) << AW_PID_2049_BST_ATH_START_BIT)) + +#define AW_PID_2049_BST_ATH_DEFAULT_VALUE (2) +#define AW_PID_2049_BST_ATH_DEFAULT \ + (AW_PID_2049_BST_ATH_DEFAULT_VALUE << AW_PID_2049_BST_ATH_START_BIT) + +/* default value of BSTCTRL1 (0x60) */ +/* #define AW_PID_2049_BSTCTRL1_DEFAULT (0x0402) */ + +/* BSTCTRL2 (0x61) detail */ +/* BST_MODE bit 14:12 (BSTCTRL2 0x61) */ +#define AW_PID_2049_BST_MODE_START_BIT (12) +#define AW_PID_2049_BST_MODE_BITS_LEN (3) +#define AW_PID_2049_BST_MODE_MASK \ + (~(((1<<AW_PID_2049_BST_MODE_BITS_LEN)-1) << AW_PID_2049_BST_MODE_START_BIT)) + +#define AW_PID_2049_BST_MODE_TRANSPARENT (0) +#define AW_PID_2049_BST_MODE_TRANSPARENT_VALUE \ + (AW_PID_2049_BST_MODE_TRANSPARENT << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_FORCE_BOOST (1) +#define AW_PID_2049_BST_MODE_FORCE_BOOST_VALUE \ + (AW_PID_2049_BST_MODE_FORCE_BOOST << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_SMART_BOOST1 (5) +#define AW_PID_2049_BST_MODE_SMART_BOOST1_VALUE \ + (AW_PID_2049_BST_MODE_SMART_BOOST1 << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_SMART_BOOST2 (6) +#define AW_PID_2049_BST_MODE_SMART_BOOST2_VALUE \ + (AW_PID_2049_BST_MODE_SMART_BOOST2 << AW_PID_2049_BST_MODE_START_BIT) + +#define AW_PID_2049_BST_MODE_DEFAULT_VALUE (0x6) +#define AW_PID_2049_BST_MODE_DEFAULT \ + (AW_PID_2049_BST_MODE_DEFAULT_VALUE << AW_PID_2049_BST_MODE_START_BIT) + +/* WDT_CNT bit 7:0 (WDT 0x42) */ +#define AW_PID_2049_WDT_CNT_START_BIT (0) +#define AW_PID_2049_WDT_CNT_BITS_LEN (8) +#define AW_PID_2049_WDT_CNT_MASK \ + (~(((1<<AW_PID_2049_WDT_CNT_BITS_LEN)-1) << AW_PID_2049_WDT_CNT_START_BIT)) + +/* BST_TDEG bit 11:8 (BSTCTRL2 0x61) */ +#define AW_PID_2049_BST_TDEG_START_BIT (8) +#define AW_PID_2049_BST_TDEG_BITS_LEN (4) +#define AW_PID_2049_BST_TDEG_MASK \ + (~(((1<<AW_PID_2049_BST_TDEG_BITS_LEN)-1) << AW_PID_2049_BST_TDEG_START_BIT)) + +#define AW_PID_2049_BST_TDEG_0P50_MS (0) +#define AW_PID_2049_BST_TDEG_0P50_MS_VALUE \ + (AW_PID_2049_BST_TDEG_0P50_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_1P00_MS (1) +#define AW_PID_2049_BST_TDEG_1P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_1P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_2P00_MS (2) +#define AW_PID_2049_BST_TDEG_2P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_2P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_4P00_MS (3) +#define AW_PID_2049_BST_TDEG_4P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_4P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_8P00_MS (4) +#define AW_PID_2049_BST_TDEG_8P00_MS_VALUE \ + (AW_PID_2049_BST_TDEG_8P00_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_10P7_MS (5) +#define AW_PID_2049_BST_TDEG_10P7_MS_VALUE \ + (AW_PID_2049_BST_TDEG_10P7_MS << AW_PID_2049_BST_TDEG_START_BIT) + +/* ReAbs bit 3 (ASR1 0x45) */ +#define AW_PID_2049_ReAbs_START_BIT (3) +#define AW_PID_2049_ReAbs_BITS_LEN (1) +#define AW_PID_2049_ReAbs_MASK \ + (~(((1<<AW_PID_2049_ReAbs_BITS_LEN)-1) << AW_PID_2049_ReAbs_START_BIT)) + +#define AW_PID_2049_BST_TDEG_13P3_MS (6) +#define AW_PID_2049_BST_TDEG_13P3_MS_VALUE \ + (AW_PID_2049_BST_TDEG_13P3_MS << AW_PID_2049_BST_TDEG_START_BIT) + +/* DSP_VOL bit 15:8 (DSPCFG 0x47) */ +#define AW_PID_2049_DSP_VOL_START_BIT (8) +#define AW_PID_2049_DSP_VOL_BITS_LEN (8) +#define AW_PID_2049_DSP_VOL_MASK \ + (~(((1<<AW_PID_2049_DSP_VOL_BITS_LEN)-1) << AW_PID_2049_DSP_VOL_START_BIT)) + +#define AW_PID_2049_DSP_VOL_MUTE (0XFF00) +#define AW_PID_2049_DSP_VOL_NOISE_ST (0X1800) + +#define AW_PID_2049_BST_TDEG_16P0_MS (7) +#define AW_PID_2049_BST_TDEG_16P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_16P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_18P6_MS (8) +#define AW_PID_2049_BST_TDEG_18P6_MS_VALUE \ + (AW_PID_2049_BST_TDEG_18P6_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_21P3_MS (9) +#define AW_PID_2049_BST_TDEG_21P3_MS_VALUE \ + (AW_PID_2049_BST_TDEG_21P3_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_24P0_MS (10) +#define AW_PID_2049_BST_TDEG_24P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_24P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_32P0_MS (11) +#define AW_PID_2049_BST_TDEG_32P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_32P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_64P0_MS (12) +#define AW_PID_2049_BST_TDEG_64P0_MS_VALUE \ + (AW_PID_2049_BST_TDEG_64P0_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_128_MS (13) +#define AW_PID_2049_BST_TDEG_128_MS_VALUE \ + (AW_PID_2049_BST_TDEG_128_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_256_MS (14) +#define AW_PID_2049_BST_TDEG_256_MS_VALUE \ + (AW_PID_2049_BST_TDEG_256_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_1200_MS (15) +#define AW_PID_2049_BST_TDEG_1200_MS_VALUE \ + (AW_PID_2049_BST_TDEG_1200_MS << AW_PID_2049_BST_TDEG_START_BIT) + +#define AW_PID_2049_BST_TDEG_DEFAULT_VALUE (11) +#define AW_PID_2049_BST_TDEG_DEFAULT \ + (AW_PID_2049_BST_TDEG_DEFAULT_VALUE << AW_PID_2049_BST_TDEG_START_BIT) + +/* VOUT_VREFSET bit 5:0 (BSTCTRL2 0x61) */ +/* CCO_MUX bit 14 (PLLCTRL1 0x52) */ +#define AW_PID_2049_CCO_MUX_START_BIT (14) +#define AW_PID_2049_CCO_MUX_BITS_LEN (1) +#define AW_PID_2049_CCO_MUX_MASK \ + (~(((1<<AW_PID_2049_CCO_MUX_BITS_LEN)-1) << AW_PID_2049_CCO_MUX_START_BIT)) + +#define AW_PID_2049_CCO_MUX_DIVIDED (0) +#define AW_PID_2049_CCO_MUX_DIVIDED_VALUE \ + (AW_PID_2049_CCO_MUX_DIVIDED << AW_PID_2049_CCO_MUX_START_BIT) + +#define AW_PID_2049_CCO_MUX_BYPASS (1) +#define AW_PID_2049_CCO_MUX_BYPASS_VALUE \ + (AW_PID_2049_CCO_MUX_BYPASS << AW_PID_2049_CCO_MUX_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_START_BIT (0) +#define AW_PID_2049_VOUT_VREFSET_BITS_LEN (6) +#define AW_PID_2049_VOUT_VREFSET_MASK \ + (~(((1<<AW_PID_2049_VOUT_VREFSET_BITS_LEN)-1) << AW_PID_2049_VOUT_VREFSET_START_BIT)) + +#define AW_PID_2049_VOUT_VREFSET_3P125V (0) +#define AW_PID_2049_VOUT_VREFSET_3P125V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P125V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P250V (1) +#define AW_PID_2049_VOUT_VREFSET_3P250V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P250V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P375V (2) +#define AW_PID_2049_VOUT_VREFSET_3P375V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P375V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P500V (3) +#define AW_PID_2049_VOUT_VREFSET_3P500V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P500V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P625V (4) +#define AW_PID_2049_VOUT_VREFSET_3P625V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P625V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_3P750V (5) +#define AW_PID_2049_VOUT_VREFSET_3P750V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_3P750V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_11P000V (63) +#define AW_PID_2049_VOUT_VREFSET_11P000V_VALUE \ + (AW_PID_2049_VOUT_VREFSET_11P000V << AW_PID_2049_VOUT_VREFSET_START_BIT) + +#define AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE (0x33) +#define AW_PID_2049_VOUT_VREFSET_DEFAULT \ + (AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE << AW_PID_2049_VOUT_VREFSET_START_BIT) + +/* default value of BSTCTRL2 (0x61) */ +/* #define AW_PID_2049_BSTCTRL2_DEFAULT (0x6B33) */ + +/* detail information of registers end */ + +/* EF_VSN_GESLP bit 9:0 (EFRH 0x78) */ +#define AW_PID_2049_EF_VSN_GESLP_START_BIT (0) +#define AW_PID_2049_EF_VSN_GESLP_BITS_LEN (10) +#define AW_PID_2049_EF_VSN_GESLP_MASK \ + (~(((1<<AW_PID_2049_EF_VSN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_VSN_GESLP_START_BIT)) + +#define AW_PID_2049_EF_VSN_GESLP_SIGN_MASK (~(1 << 9)) +#define AW_PID_2049_EF_VSN_GESLP_SIGN_NEG (0xfe00) +/* EF_ISN_GESLP bit 9:0 (EFRM2 0x79) */ +#define AW_PID_2049_EF_ISN_GESLP_START_BIT (0) +#define AW_PID_2049_EF_ISN_GESLP_BITS_LEN (10) +#define AW_PID_2049_EF_ISN_GESLP_MASK \ + (~(((1<<AW_PID_2049_EF_ISN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_ISN_GESLP_START_BIT)) + +#define AW_PID_2049_EF_ISN_GESLP_SIGN_MASK (~(1 << 9)) +#define AW_PID_2049_EF_ISN_GESLP_SIGN_NEG (0xfe00) +/* + * Vcalb + */ + +#define AW_PID_2049_CABL_BASE_VALUE (1000) +#define AW_PID_2049_ICABLK_FACTOR (1) +#define AW_PID_2049_VCABLK_FACTOR (1) +#define AW_PID_2049_VCAL_FACTOR (1 << 12) +#define AW_PID_2049_VSCAL_FACTOR (16500) +#define AW_PID_2049_ISCAL_FACTOR (3667) +#define AW_PID_2049_EF_VSENSE_GAIN_SHIFT (0) + +#define AW_PID_2049_VCABLK_FACTOR_DAC (2) +#define AW_PID_2049_VSCAL_FACTOR_DAC (11790) +#define AW_PID_2049_EF_DAC_GESLP_SHIFT (10) +#define AW_PID_2049_EF_DAC_GESLP_SIGN_MASK (1 << 5) +#define AW_PID_2049_EF_DAC_GESLP_SIGN_NEG (0xffc0) + +#define AW_PID_2049_VCALB_ADJ_FACTOR (12) + +/* + * AW883XX DSP + */ +#define AW_PID_2049_DSP_CFG_ADDR (0x9C80) +#define AW_PID_2049_DSP_FW_ADDR (0x8C00) + +#define AW_PID_2049_DSP_REG_RESULT_F0 (0x9C58) +#define AW_PID_2049_DSP_F0_SHIFT (1) + +#define AW_PID_2049_DSP_REG_CALRE (0x9C5A) +#define AW_PID_2049_DSP_REG_CALRE_SHIFT (10) +#define AW_PID_2049_DSP_REG_RESULT_Q (0x9C5C) +#define AW_PID_2049_DSP_Q_SHIFT (11) + +#define AW_PID_2049_DSP_REG_VMAX (0x9C94) + + +#define AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG (0x9CE2) +/* bit 0 */ +#define AW_PID_2049_DSP_MONITOR_MASK (~(1 << 0)) +#define AW_PID_2049_DSP_MONITOR_ENABLE (1 << 0) +#define AW_PID_2049_DSP_MONITOR_DISABLE (0 << 0) +/*bit 4*/ +#define AW_PID_2049_DSP_REG_NOISE_MASK (~(1 << 4)) + +#define AW_PID_2049_DSP_TEMP_PEAK_MASK (~(1 << 4)) +#define AW_PID_2049_DSP_TEMP_SEL_FLAG (~(1 << 14)) + +#define AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH (0x9CE4)/*32bit*/ +#define AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH (0x9CE6)/*32bit*/ +#define AW_PID_2049_DSP_REG_VCALB (0x9CF7) + +#define AW_PID_2049_DSP_REG_CFG_ADPZ_RE (0x9D00)/*32bit*/ +#define AW_PID_2049_DSP_RE_SHIFT (12) + +#define AW_PID_2049_DSP_REG_CFG_ADPZ_RA (0x9D02)/*32bit*/ + +#define AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN (0x9D08) + + +#define AW_PID_2049_DSP_REG_CRC_ADDR (0x9F42)/*32bit*/ +#define AW_PID_2049_DSP_REG_CFGF0_FS (0x9F44)/*32bit*/ +#define AW_PID_2049_DSP_REG_CFG_RE_ALPHA (0x9F47) +#define AW_PID_2049_DSP_REG_TEMP_ADDR (0x9C5D) +#define AW_PID_2049_DSP_REG_TEMP_SWITCH (0x9D71)/*16bit*/ +#define AW_PID_2049_DSP_CALI_F0_DELAY (0x9CFD) +#define AW_PID_2049_DSP_CFG_ADPZ_T0 (0x9D11)/*16bit*/ +#define AW_PID_2049_DSP_CFG_ADPZ_COILALPHA (0x9D0F)/*16bit*/ +#define AW_PID_2049_DSP_ST_S1 (0x8180) +#define AW_PID_2049_DSP_ST_E1 (0x83FD) +#define AW_PID_2049_DSP_ST_S2 (0x9C00) +#define AW_PID_2049_DSP_ST_E2 (0x9C5D) + +#endif /* #ifndef __AW_PID_2049_REG_H__ */

From: Weidong Wang wangweidong.a@awinic.com

Add a DT schema for describing Awinic AW883xx audio amplifiers. They are controlled using I2C. Signed-off-by: Weidong Wang wangweidong.a@awinic.com --- .../bindings/sound/awinic,aw883xx.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml

diff --git a/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml new file mode 100644 index 000000000000..b72c9177ebb7 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/awinic,aw883xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Awinic AW883xx Smart Audio Amplifier + +maintainers: + - Stephan Gerhold stephan@gerhold.net + +description: + The Awinic AW883XX is an I2S/TDM input, high efficiency + digital Smart K audio amplifier with an integrated 10.25V + smart boost convert. + +allOf: + - $ref: name-prefix.yaml# + +properties: + compatible: + const: awinic,aw883xx_smartpa + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + sound-name-prefix: true + +required: + - compatible + - reg + - reset-gpios + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + audio-codec@34 { + compatible = "awinic,aw883xx_smartpa"; + reg = <0x34>; + reset-gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + };