[alsa-devel] [PATCH 2/2] ASoC: pcm512x: Fix clocking calculations when not using the PLL
The rationale behind the current calculation is somewhat obscure [1] and can yield slightly wrong dividers in certain cases, which the machine drivers for some boards (like the HiFiBerry DAC+ Pro) seemingly try to circumvent, by updating the rate fraction so as to suit this calculation.
The updated calculation should correctly yield the smallest bit clock rate that would fit the frame.
[1] http://mailman.alsa-project.org/pipermail/alsa-devel/2019-January/144219.htm...
Signed-off-by: Dimitris Papavasiliou dpapavas@gmail.com --- sound/soc/codecs/pcm512x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c index b63d9392bae3..87a2bff366f3 100644 --- a/sound/soc/codecs/pcm512x.c +++ b/sound/soc/codecs/pcm512x.c @@ -929,8 +929,8 @@ static int pcm512x_set_dividers(struct snd_soc_dai *dai,
if (!pcm512x->pll_out) { sck_rate = clk_get_rate(pcm512x->sclk); - bclk_div = params->rate_den * 64 / lrclk_div; - bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div); + bclk_rate = params_rate(params) * lrclk_div; + bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
mck_rate = sck_rate; } else {
The patch
ASoC: pcm512x: Fix clocking calculations when not using the PLL
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
From 51b033c2608147efe3a5368bfa64837e772d8c55 Mon Sep 17 00:00:00 2001
From: Dimitris Papavasiliou dpapavas@gmail.com Date: Sat, 26 Jan 2019 15:23:45 +0200 Subject: [PATCH] ASoC: pcm512x: Fix clocking calculations when not using the PLL
The rationale behind the current calculation is somewhat obscure [1] and can yield slightly wrong dividers in certain cases, which the machine drivers for some boards (like the HiFiBerry DAC+ Pro) seemingly try to circumvent, by updating the rate fraction so as to suit this calculation.
The updated calculation should correctly yield the smallest bit clock rate that would fit the frame.
[1] http://mailman.alsa-project.org/pipermail/alsa-devel/2019-January/144219.htm...
Signed-off-by: Dimitris Papavasiliou dpapavas@gmail.com Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/codecs/pcm512x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c index ce8c5dbd2164..ae3bd533eadb 100644 --- a/sound/soc/codecs/pcm512x.c +++ b/sound/soc/codecs/pcm512x.c @@ -929,8 +929,8 @@ static int pcm512x_set_dividers(struct snd_soc_dai *dai,
if (!pcm512x->pll_out) { sck_rate = clk_get_rate(pcm512x->sclk); - bclk_div = params->rate_den * 64 / lrclk_div; - bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div); + bclk_rate = params_rate(params) * lrclk_div; + bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
mck_rate = sck_rate; } else {
participants (2)
-
Dimitris Papavasiliou
-
Mark Brown