When we have a MCLK provided by the clock API read the rate at startup and store it so that there's something set before the machine driver has done clocking configuration (eg, if it only configures clocking based on sample rate).

Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/codecs/wm8960.c | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 366f5d769d6d..c0ce1ef75a74 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -1425,6 +1425,14 @@ static int wm8960_i2c_probe(struct i2c_client *i2c) if (IS_ERR(wm8960->mclk)) { if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER) return -EPROBE_DEFER; + } else { + ret = clk_get_rate(wm8960->mclk); + if (ret >= 0) { + wm8960->freq_in = ret; + } else { + dev_err(&i2c->dev, "Failed to read MCLK rate: %d\n", + ret); + } }

wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap);

The wm8960 driver supports an automatic clocking mode which will use the MCLK directly where possible and fall back to the PLL if there is no suitable configuration directly using the MCLK. Clock 0 will be used by the generic cards when configuring things, currently this is a MCLK only mode but using AUTO mode would be more functional. Since the driver still prefers to use MCLK directly where possible there should be no negative impact on systems which are able to use MCLK directly.

As far as I can see nothing is using the system clock as part of the ABI, the only reference I can see to a mode in a machine driver is the Freescale i.MX card which uses the automatic mode with an explicit in kernel call using the constant so will be unaffected.

Signed-off-by: Mark Brown broonie@kernel.org --- sound/soc/codecs/wm8960.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/wm8960.h b/sound/soc/codecs/wm8960.h index 63ba6c03c488..e8ff33b188e9 100644 --- a/sound/soc/codecs/wm8960.h +++ b/sound/soc/codecs/wm8960.h @@ -77,9 +77,9 @@ #define WM8960_SYSCLK_DIV_1 (0 << 1) #define WM8960_SYSCLK_DIV_2 (2 << 1)

-#define WM8960_SYSCLK_MCLK (0 << 0) +#define WM8960_SYSCLK_AUTO (0 << 0) #define WM8960_SYSCLK_PLL (1 << 0) -#define WM8960_SYSCLK_AUTO (2 << 0) +#define WM8960_SYSCLK_MCLK (2 << 0)

#define WM8960_DAC_DIV_1 (0 << 3) #define WM8960_DAC_DIV_1_5 (1 << 3)