[alsa-devel] [PATCH v2 0/7] Add support for new SAI IP version
So far SAI IPs integrated with imx6 only supported one data line. Starting with imx7 and imx8 SAI integration support up to 8 data lines.
New SAI IP version introduces two new registers (Version and Parmeter registers) which are placed at the beginning of register address space. For this reason we need to fix the register's address.
Changes since v1: - removed patches from Lucas as they were already accepted - addressed comments from Lucas and Nicolin regarding device tree property naming - removed comment saying that "datalines" must be always consecutively enabled (this is not true, checked with IP owner) - added new patch to document newly introduced compatbile strings - removed patch introducing combined mode as I will still need some time to figure out how to properly allow users to set it.
Nicolin,
Unfortunately I couldn't find any clean solution on handling registers address shifts. As mentioned in patch 5/7 Tx/Rx data registers and Tx/Rx FIFO registers keep their addresses while others are shifted by 8 bytes.
Even if I could create two regmaps as suggested I will still need to update each call of regmap_functions.
Daniel Baluta (7): ASoC: fsl_sai: Add registers definition for multiple datalines ASoC: fsl_sai: Update Tx/Rx channel enable mask ASoC: fsl_sai: Add support to enable multiple data lines ASoC: dt-bindings: Document dl-mask property ASoC: fsl_sai: Add support for SAI new version ASoC: fsl_sai: Add support for imx7ulp/imx8mq ASoC: dt-bindings: Introduce compatible strings for 7ULP and 8MQ
.../devicetree/bindings/sound/fsl-sai.txt | 10 +- sound/soc/fsl/fsl_sai.c | 331 ++++++++++++------ sound/soc/fsl/fsl_sai.h | 82 +++-- 3 files changed, 293 insertions(+), 130 deletions(-)
SAI IP supports up to 8 data lines. The configuration of supported number of data lines is decided at SoC integration time.
This patch adds definitions for all related data TX/RX registers: * TDR0..7, Transmit data register * TFR0..7, Transmit FIFO register * RDR0..7, Receive data register * RFR0..7, Receive FIFO register
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com --- sound/soc/fsl/fsl_sai.c | 76 +++++++++++++++++++++++++++++++++++------ sound/soc/fsl/fsl_sai.h | 36 ++++++++++++++++--- 2 files changed, 98 insertions(+), 14 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 6d3c6c8d50ce..17b0aff4ee8b 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -685,7 +685,14 @@ static struct reg_default fsl_sai_reg_defaults[] = { {FSL_SAI_TCR3, 0}, {FSL_SAI_TCR4, 0}, {FSL_SAI_TCR5, 0}, - {FSL_SAI_TDR, 0}, + {FSL_SAI_TDR0, 0}, + {FSL_SAI_TDR1, 0}, + {FSL_SAI_TDR2, 0}, + {FSL_SAI_TDR3, 0}, + {FSL_SAI_TDR4, 0}, + {FSL_SAI_TDR5, 0}, + {FSL_SAI_TDR6, 0}, + {FSL_SAI_TDR7, 0}, {FSL_SAI_TMR, 0}, {FSL_SAI_RCR1, 0}, {FSL_SAI_RCR2, 0}, @@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TCR3: case FSL_SAI_TCR4: case FSL_SAI_TCR5: - case FSL_SAI_TFR: + case FSL_SAI_TFR0: + case FSL_SAI_TFR1: + case FSL_SAI_TFR2: + case FSL_SAI_TFR3: + case FSL_SAI_TFR4: + case FSL_SAI_TFR5: + case FSL_SAI_TFR6: + case FSL_SAI_TFR7: case FSL_SAI_TMR: case FSL_SAI_RCSR: case FSL_SAI_RCR1: @@ -712,8 +726,22 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) case FSL_SAI_RCR3: case FSL_SAI_RCR4: case FSL_SAI_RCR5: - case FSL_SAI_RDR: - case FSL_SAI_RFR: + case FSL_SAI_RDR0: + case FSL_SAI_RDR1: + case FSL_SAI_RDR2: + case FSL_SAI_RDR3: + case FSL_SAI_RDR4: + case FSL_SAI_RDR5: + case FSL_SAI_RDR6: + case FSL_SAI_RDR7: + case FSL_SAI_RFR0: + case FSL_SAI_RFR1: + case FSL_SAI_RFR2: + case FSL_SAI_RFR3: + case FSL_SAI_RFR4: + case FSL_SAI_RFR5: + case FSL_SAI_RFR6: + case FSL_SAI_RFR7: case FSL_SAI_RMR: return true; default: @@ -726,9 +754,30 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) switch (reg) { case FSL_SAI_TCSR: case FSL_SAI_RCSR: - case FSL_SAI_TFR: - case FSL_SAI_RFR: - case FSL_SAI_RDR: + case FSL_SAI_TFR0: + case FSL_SAI_TFR1: + case FSL_SAI_TFR2: + case FSL_SAI_TFR3: + case FSL_SAI_TFR4: + case FSL_SAI_TFR5: + case FSL_SAI_TFR6: + case FSL_SAI_TFR7: + case FSL_SAI_RFR0: + case FSL_SAI_RFR1: + case FSL_SAI_RFR2: + case FSL_SAI_RFR3: + case FSL_SAI_RFR4: + case FSL_SAI_RFR5: + case FSL_SAI_RFR6: + case FSL_SAI_RFR7: + case FSL_SAI_RDR0: + case FSL_SAI_RDR1: + case FSL_SAI_RDR2: + case FSL_SAI_RDR3: + case FSL_SAI_RDR4: + case FSL_SAI_RDR5: + case FSL_SAI_RDR6: + case FSL_SAI_RDR7: return true; default: return false; @@ -744,7 +793,14 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TCR3: case FSL_SAI_TCR4: case FSL_SAI_TCR5: - case FSL_SAI_TDR: + case FSL_SAI_TDR0: + case FSL_SAI_TDR1: + case FSL_SAI_TDR2: + case FSL_SAI_TDR3: + case FSL_SAI_TDR4: + case FSL_SAI_TDR5: + case FSL_SAI_TDR6: + case FSL_SAI_TDR7: case FSL_SAI_TMR: case FSL_SAI_RCSR: case FSL_SAI_RCR1: @@ -885,8 +941,8 @@ static int fsl_sai_probe(struct platform_device *pdev) MCLK_DIR(index)); }
- sai->dma_params_rx.addr = res->start + FSL_SAI_RDR; - sai->dma_params_tx.addr = res->start + FSL_SAI_TDR; + sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0; + sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0; sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 7c1ef671da28..4bb478041d67 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -20,8 +20,22 @@ #define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */ #define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */ #define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */ -#define FSL_SAI_TDR 0x20 /* SAI Transmit Data */ -#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */ +#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */ +#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */ +#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */ +#define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */ +#define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */ +#define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */ +#define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */ +#define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */ +#define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */ +#define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */ +#define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */ +#define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */ +#define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */ +#define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */ +#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */ +#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */ #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */ #define FSL_SAI_RCSR 0x80 /* SAI Receive Control */ #define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */ @@ -29,8 +43,22 @@ #define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */ #define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */ #define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */ -#define FSL_SAI_RDR 0xa0 /* SAI Receive Data */ -#define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */ +#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */ +#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */ +#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */ +#define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */ +#define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */ +#define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */ +#define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */ +#define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */ +#define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */ +#define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */ +#define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */ +#define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */ +#define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */ +#define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */ +#define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */ +#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */ #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
On Sun, Jul 28, 2019 at 10:24:23PM +0300, Daniel Baluta wrote:
SAI IP supports up to 8 data lines. The configuration of supported number of data lines is decided at SoC integration time.
This patch adds definitions for all related data TX/RX registers:
- TDR0..7, Transmit data register
- TFR0..7, Transmit FIFO register
- RDR0..7, Receive data register
- RFR0..7, Receive FIFO register
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
sound/soc/fsl/fsl_sai.c | 76 +++++++++++++++++++++++++++++++++++------ sound/soc/fsl/fsl_sai.h | 36 ++++++++++++++++--- 2 files changed, 98 insertions(+), 14 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 6d3c6c8d50ce..17b0aff4ee8b 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c
@@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TCR3: case FSL_SAI_TCR4: case FSL_SAI_TCR5:
- case FSL_SAI_TFR:
- case FSL_SAI_TFR0:
- case FSL_SAI_TFR1:
- case FSL_SAI_TFR2:
- case FSL_SAI_TFR3:
- case FSL_SAI_TFR4:
- case FSL_SAI_TFR5:
- case FSL_SAI_TFR6:
- case FSL_SAI_TFR7: case FSL_SAI_TMR: case FSL_SAI_RCSR: case FSL_SAI_RCR1:
A tricky thing here is that those SAI instances on older SoC don't support multi data lines physically, while seemly having registers pre-defined. So your change doesn't sound doing anything wrong to them at all, I am still wondering if it is necessary to apply them to newer compatible only though, as for older compatibles of SAI, these registers would be useless and confusing if being exposed.
What do you think?
On Mon, Jul 29, 2019 at 10:42 PM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Sun, Jul 28, 2019 at 10:24:23PM +0300, Daniel Baluta wrote:
SAI IP supports up to 8 data lines. The configuration of supported number of data lines is decided at SoC integration time.
This patch adds definitions for all related data TX/RX registers: * TDR0..7, Transmit data register * TFR0..7, Transmit FIFO register * RDR0..7, Receive data register * RFR0..7, Receive FIFO register
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
sound/soc/fsl/fsl_sai.c | 76 +++++++++++++++++++++++++++++++++++------ sound/soc/fsl/fsl_sai.h | 36 ++++++++++++++++--- 2 files changed, 98 insertions(+), 14 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 6d3c6c8d50ce..17b0aff4ee8b 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c
@@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TCR3: case FSL_SAI_TCR4: case FSL_SAI_TCR5:
case FSL_SAI_TFR:
case FSL_SAI_TFR0:case FSL_SAI_TFR1:case FSL_SAI_TFR2:case FSL_SAI_TFR3:case FSL_SAI_TFR4:case FSL_SAI_TFR5:case FSL_SAI_TFR6:case FSL_SAI_TFR7: case FSL_SAI_TMR: case FSL_SAI_RCSR: case FSL_SAI_RCR1:A tricky thing here is that those SAI instances on older SoC don't support multi data lines physically, while seemly having registers pre-defined. So your change doesn't sound doing anything wrong to them at all, I am still wondering if it is necessary to apply them to newer compatible only though, as for older compatibles of SAI, these registers would be useless and confusing if being exposed.
What do you think?
Yes, I thought about this too. But, I tried to keep the code as short as possible and technically it is not wrong. When 1 data line is supported for example application will only care about TDR0, TFR0, etc.
On Mon, Jul 29, 2019 at 10:57:43PM +0300, Daniel Baluta wrote:
On Mon, Jul 29, 2019 at 10:42 PM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Sun, Jul 28, 2019 at 10:24:23PM +0300, Daniel Baluta wrote:
@@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TCR3: case FSL_SAI_TCR4: case FSL_SAI_TCR5:
case FSL_SAI_TFR:
case FSL_SAI_TFR0:
A tricky thing here is that those SAI instances on older SoC don't support multi data lines physically, while seemly having registers pre-defined. So your change doesn't sound doing anything wrong to them at all, I am still wondering if it is necessary to apply them to newer compatible only though, as for older compatibles of SAI, these registers would be useless and confusing if being exposed.
What do you think?
Yes, I thought about this too. But, I tried to keep the code as short as possible and technically it is not wrong. When 1 data line is supported for example application will only care about TDR0, TFR0, etc.
So long as it's safe to read the registers (you don't get a bus error or anything) I'd say it's more trouble than it's worth to have separate regmap configuations just for this. The main reasons for restricting readability are where there's physical problems with doing the reads or to keep the size of the debugfs files under control for usability and performance reasons.
On Mon, Jul 29, 2019 at 09:20:01PM +0100, Mark Brown wrote:
On Mon, Jul 29, 2019 at 10:57:43PM +0300, Daniel Baluta wrote:
On Mon, Jul 29, 2019 at 10:42 PM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Sun, Jul 28, 2019 at 10:24:23PM +0300, Daniel Baluta wrote:
@@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TCR3: case FSL_SAI_TCR4: case FSL_SAI_TCR5:
case FSL_SAI_TFR:
case FSL_SAI_TFR0:A tricky thing here is that those SAI instances on older SoC don't support multi data lines physically, while seemly having registers pre-defined. So your change doesn't sound doing anything wrong to them at all, I am still wondering if it is necessary to apply them to newer compatible only though, as for older compatibles of SAI, these registers would be useless and confusing if being exposed.
What do you think?
Yes, I thought about this too. But, I tried to keep the code as short as possible and technically it is not wrong. When 1 data line is supported for example application will only care about TDR0, TFR0, etc.
So long as it's safe to read the registers (you don't get a bus error or anything) I'd say it's more trouble than it's worth to have separate regmap configuations just for this. The main reasons for restricting readability are where there's physical problems with doing the reads or to keep the size of the debugfs files under control for usability and performance reasons.
Thanks for the input, Mark.
Daniel, did you get a chance to test it on older SoCs? At least nothing breaks like bus errors?
On Tue, Jul 30, 2019 at 10:59 AM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Mon, Jul 29, 2019 at 09:20:01PM +0100, Mark Brown wrote:
On Mon, Jul 29, 2019 at 10:57:43PM +0300, Daniel Baluta wrote:
On Mon, Jul 29, 2019 at 10:42 PM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Sun, Jul 28, 2019 at 10:24:23PM +0300, Daniel Baluta wrote:
@@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TCR3: case FSL_SAI_TCR4: case FSL_SAI_TCR5:
case FSL_SAI_TFR:
case FSL_SAI_TFR0:A tricky thing here is that those SAI instances on older SoC don't support multi data lines physically, while seemly having registers pre-defined. So your change doesn't sound doing anything wrong to them at all, I am still wondering if it is necessary to apply them to newer compatible only though, as for older compatibles of SAI, these registers would be useless and confusing if being exposed.
What do you think?
Yes, I thought about this too. But, I tried to keep the code as short as possible and technically it is not wrong. When 1 data line is supported for example application will only care about TDR0, TFR0, etc.
So long as it's safe to read the registers (you don't get a bus error or anything) I'd say it's more trouble than it's worth to have separate regmap configuations just for this. The main reasons for restricting readability are where there's physical problems with doing the reads or to keep the size of the debugfs files under control for usability and performance reasons.
Thanks for the input, Mark.
Daniel, did you get a chance to test it on older SoCs? At least nothing breaks like bus errors?
Tested on imx6sx-sdb, everything looks good. No bus errors.
On Tue, Aug 06, 2019 at 02:15:03PM +0300, Daniel Baluta wrote:
On Tue, Jul 30, 2019 at 10:59 AM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Mon, Jul 29, 2019 at 09:20:01PM +0100, Mark Brown wrote:
On Mon, Jul 29, 2019 at 10:57:43PM +0300, Daniel Baluta wrote:
On Mon, Jul 29, 2019 at 10:42 PM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Sun, Jul 28, 2019 at 10:24:23PM +0300, Daniel Baluta wrote:
@@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TCR3: case FSL_SAI_TCR4: case FSL_SAI_TCR5:
case FSL_SAI_TFR:
case FSL_SAI_TFR0:A tricky thing here is that those SAI instances on older SoC don't support multi data lines physically, while seemly having registers pre-defined. So your change doesn't sound doing anything wrong to them at all, I am still wondering if it is necessary to apply them to newer compatible only though, as for older compatibles of SAI, these registers would be useless and confusing if being exposed.
What do you think?
Yes, I thought about this too. But, I tried to keep the code as short as possible and technically it is not wrong. When 1 data line is supported for example application will only care about TDR0, TFR0, etc.
So long as it's safe to read the registers (you don't get a bus error or anything) I'd say it's more trouble than it's worth to have separate regmap configuations just for this. The main reasons for restricting readability are where there's physical problems with doing the reads or to keep the size of the debugfs files under control for usability and performance reasons.
Thanks for the input, Mark.
Daniel, did you get a chance to test it on older SoCs? At least nothing breaks like bus errors?
Tested on imx6sx-sdb, everything looks good. No bus errors.
Okay. Let's just stick to it then. Thanks for the reply.
Tx channel enable (TCE) / Rx channel enable (RCE) bits enable corresponding data channel for Tx/Rx operation.
Because SAI supports up the 8 channels TCE/RCE occupy up the 8 bits inside TCR3/RCR3 registers we need to extend the mask to reflect this.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com --- sound/soc/fsl/fsl_sai.c | 6 ++++-- sound/soc/fsl/fsl_sai.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 17b0aff4ee8b..637b1d12a575 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -599,7 +599,8 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream, bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; int ret;
- regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), + FSL_SAI_CR3_TRCE_MASK, FSL_SAI_CR3_TRCE);
ret = snd_pcm_hw_constraint_list(substream->runtime, 0, @@ -614,7 +615,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream, struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
- regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0); + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), + FSL_SAI_CR3_TRCE_MASK, 0); }
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 4bb478041d67..20c5b9b1e8bc 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -110,6 +110,7 @@
/* SAI Transmit and Receive Configuration 3 Register */ #define FSL_SAI_CR3_TRCE BIT(16) +#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16) #define FSL_SAI_CR3_WDFL(x) (x) #define FSL_SAI_CR3_WDFL_MASK 0x1f
SAI supports up to 8 Rx/Tx data lines which can be enabled using TCE/RCE bits of TCR3/RCR3 registers.
Data lines to be enabled are read from DT fsl,dl-mask property. By default (if no DT entry is provided) only data line 0 is enabled.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com --- sound/soc/fsl/fsl_sai.c | 11 ++++++++++- sound/soc/fsl/fsl_sai.h | 4 +++- 2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 637b1d12a575..5e7cb7fd29f5 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -601,7 +601,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE_MASK, - FSL_SAI_CR3_TRCE); + FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]);
ret = snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); @@ -888,6 +888,15 @@ static int fsl_sai_probe(struct platform_device *pdev) } }
+ /* + * active data lines mask for TX/RX, defaults to 1 (only the first + * data line is enabled + */ + sai->dl_mask[RX] = 1; + sai->dl_mask[TX] = 1; + of_property_read_u32_index(np, "fsl,dl-mask", RX, &sai->dl_mask[RX]); + of_property_read_u32_index(np, "fsl,dl-mask", TX, &sai->dl_mask[TX]); + irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 20c5b9b1e8bc..6d32f0950ec5 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -109,7 +109,7 @@ #define FSL_SAI_CR2_DIV_MASK 0xff
/* SAI Transmit and Receive Configuration 3 Register */ -#define FSL_SAI_CR3_TRCE BIT(16) +#define FSL_SAI_CR3_TRCE(x) ((x) << 16) #define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16) #define FSL_SAI_CR3_WDFL(x) (x) #define FSL_SAI_CR3_WDFL_MASK 0x1f @@ -176,6 +176,8 @@ struct fsl_sai { unsigned int slots; unsigned int slot_width;
+ unsigned int dl_mask[2]; + const struct fsl_sai_soc_data *soc_data; struct snd_dmaengine_dai_dma_data dma_params_rx; struct snd_dmaengine_dai_dma_data dma_params_tx;
On Sun, Jul 28, 2019 at 10:24:25PM +0300, Daniel Baluta wrote:
SAI supports up to 8 Rx/Tx data lines which can be enabled using TCE/RCE bits of TCR3/RCR3 registers.
Data lines to be enabled are read from DT fsl,dl-mask property. By default (if no DT entry is provided) only data line 0 is enabled.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
sound/soc/fsl/fsl_sai.c | 11 ++++++++++- sound/soc/fsl/fsl_sai.h | 4 +++- 2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 637b1d12a575..5e7cb7fd29f5 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -601,7 +601,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE_MASK,
FSL_SAI_CR3_TRCE);
FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]);ret = snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
@@ -888,6 +888,15 @@ static int fsl_sai_probe(struct platform_device *pdev) } }
- /*
* active data lines mask for TX/RX, defaults to 1 (only the first* data line is enabled*/- sai->dl_mask[RX] = 1;
- sai->dl_mask[TX] = 1;
- of_property_read_u32_index(np, "fsl,dl-mask", RX, &sai->dl_mask[RX]);
- of_property_read_u32_index(np, "fsl,dl-mask", TX, &sai->dl_mask[TX]);
Just curious what if we enable 8 data lines through DT bindings while an audio file only has 1 or 2 channels. Will TRCE bits be okay to stay with 8 data channels configurations? Btw, how does DMA work for the data registers? ESAI has one entry at a fixed address for all data channels while SAI seems to have different data registers.
On Mon, Jul 29, 2019 at 11:22 PM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Sun, Jul 28, 2019 at 10:24:25PM +0300, Daniel Baluta wrote:
SAI supports up to 8 Rx/Tx data lines which can be enabled using TCE/RCE bits of TCR3/RCR3 registers.
Data lines to be enabled are read from DT fsl,dl-mask property. By default (if no DT entry is provided) only data line 0 is enabled.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
sound/soc/fsl/fsl_sai.c | 11 ++++++++++- sound/soc/fsl/fsl_sai.h | 4 +++- 2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 637b1d12a575..5e7cb7fd29f5 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -601,7 +601,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE_MASK,
FSL_SAI_CR3_TRCE);
FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]); ret = snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);@@ -888,6 +888,15 @@ static int fsl_sai_probe(struct platform_device *pdev) } }
/** active data lines mask for TX/RX, defaults to 1 (only the first* data line is enabled*/sai->dl_mask[RX] = 1;sai->dl_mask[TX] = 1;of_property_read_u32_index(np, "fsl,dl-mask", RX, &sai->dl_mask[RX]);of_property_read_u32_index(np, "fsl,dl-mask", TX, &sai->dl_mask[TX]);Just curious what if we enable 8 data lines through DT bindings while an audio file only has 1 or 2 channels. Will TRCE bits be okay to stay with 8 data channels configurations? Btw, how does DMA work for the data registers? ESAI has one entry at a fixed address for all data channels while SAI seems to have different data registers.
Hi Nicolin,
I have sent v3 and removed this patch from the series because we need to find a better solution.
I think we should enable TCE based on the number of available datalines and the number of active channels. Will come with a RFC patch later.
Pasting here the reply of SAI Audio IP owner regarding to your question above, just for anyone to have more info of our private discussion:
If all 8 datalines are enabled using TCE then the transmit FIFO for all 8 datalines need to be serviced, otherwise a FIFO underrun will be generated. Each dataline has a separate transmit FIFO with a separate register to service the FIFO, so each dataline can be serviced separately. Note that configuring FCOMB=2 would make it look like ESAI with a common address for all FIFOs. When performing DMA transfers to multiple datalines, there are a couple of options: * Use 1 DMA channel to copy first slot for each dataline to each FIFO and then update the destination address back to the first register. * Configure separate DMA channel for each dataline and trigger the first one by the DMA request and the subsequent channels by DMA linking or scatter/gather. * Configure FCOMB=2 and treat it the same as the ESAI. This is almost the same as 1, but don’t need to update the destination address.
Thanks, Daniel.
On Tue, Aug 06, 2019 at 06:23:27PM +0300, Daniel Baluta wrote:
On Mon, Jul 29, 2019 at 11:22 PM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Sun, Jul 28, 2019 at 10:24:25PM +0300, Daniel Baluta wrote:
SAI supports up to 8 Rx/Tx data lines which can be enabled using TCE/RCE bits of TCR3/RCR3 registers.
Data lines to be enabled are read from DT fsl,dl-mask property. By default (if no DT entry is provided) only data line 0 is enabled.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
sound/soc/fsl/fsl_sai.c | 11 ++++++++++- sound/soc/fsl/fsl_sai.h | 4 +++- 2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 637b1d12a575..5e7cb7fd29f5 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -601,7 +601,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE_MASK,
FSL_SAI_CR3_TRCE);
FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]); ret = snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);@@ -888,6 +888,15 @@ static int fsl_sai_probe(struct platform_device *pdev) } }
/** active data lines mask for TX/RX, defaults to 1 (only the first* data line is enabled*/sai->dl_mask[RX] = 1;sai->dl_mask[TX] = 1;of_property_read_u32_index(np, "fsl,dl-mask", RX, &sai->dl_mask[RX]);of_property_read_u32_index(np, "fsl,dl-mask", TX, &sai->dl_mask[TX]);Just curious what if we enable 8 data lines through DT bindings while an audio file only has 1 or 2 channels. Will TRCE bits be okay to stay with 8 data channels configurations? Btw, how does DMA work for the data registers? ESAI has one entry at a fixed address for all data channels while SAI seems to have different data registers.
Hi Nicolin,
I have sent v3 and removed this patch from the series because we need to find a better solution.
Ack. I was in that private mail thread. So it's totally fine.
I think we should enable TCE based on the number of available datalines and the number of active channels. Will come with a RFC patch later.
Yea, that's exactly what I suspected during patch review and what I suggested previously too. Look forward to your patch.
Pasting here the reply of SAI Audio IP owner regarding to your question above, just for anyone to have more info of our private discussion:
If all 8 datalines are enabled using TCE then the transmit FIFO for all 8 datalines need to be serviced, otherwise a FIFO underrun will be generated. Each dataline has a separate transmit FIFO with a separate register to service the FIFO, so each dataline can be serviced separately. Note that configuring FCOMB=2 would make it look like ESAI with a common address for all FIFOs. When performing DMA transfers to multiple datalines, there are a couple of options: * Use 1 DMA channel to copy first slot for each dataline to each FIFO and then update the destination address back to the first register. * Configure separate DMA channel for each dataline and trigger the first one by the DMA request and the subsequent channels by DMA linking or scatter/gather. * Configure FCOMB=2 and treat it the same as the ESAI. This is almost the same as 1, but don’t need to update the destination address.
Thanks, Daniel.
SAI supports up to 8 data lines. This property let the user configure how many data lines should be used per transfer direction (Tx/Rx).
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 2e726b983845..2b38036a4883 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -49,6 +49,13 @@ Optional properties:
- big-endian : Boolean property, required if all the SAI registers are big-endian rather than little-endian. + - fsl,dl-mask : list of two integers (bitmask, first for RX, second + for TX) representing enabled datalines. Bit 0 + represents first data line, bit 1 represents second + data line and so on. Data line is enabled if + corresponding bit is set to 1. By default, if property + not present, only dataline 0 is enabled for both + directions.
Optional properties (for mx6ul):
On Sun, Jul 28, 2019 at 10:24:26PM +0300, Daniel Baluta wrote:
SAI supports up to 8 data lines. This property let the user configure how many data lines should be used per transfer direction (Tx/Rx).
This sounds a bit less persuasive to me as we are adding a DT property that's used to describe a hardware connections and it would be probably better to mention that the mapping between the mask and the data lines could be more flexible than consecutive active data lines as you said previously.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
Documentation/devicetree/bindings/sound/fsl-sai.txt | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 2e726b983845..2b38036a4883 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -49,6 +49,13 @@ Optional properties:
- big-endian : Boolean property, required if all the SAI registers are big-endian rather than little-endian.
- fsl,dl-mask : list of two integers (bitmask, first for RX, second
I am leaving this naming to DT maintainer.
for TX) representing enabled datalines. Bit 0represents first data line, bit 1 represents seconddata line and so on. Data line is enabled ifcorresponding bit is set to 1. By default, if propertynot present, only dataline 0 is enabled for bothdirections.
To make this patch more convincing, could we add an example as well in the Example section of this binding file? Like: /* RX data lines 0/1 and TX data lines 0/2 are connected */ fsl,dl-mask = <0x3 0x5>;
On Mon, Jul 29, 2019 at 11:15 PM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Sun, Jul 28, 2019 at 10:24:26PM +0300, Daniel Baluta wrote:
SAI supports up to 8 data lines. This property let the user configure how many data lines should be used per transfer direction (Tx/Rx).
This sounds a bit less persuasive to me as we are adding a DT property that's used to describe a hardware connections and it would be probably better to mention that the mapping between the mask and the data lines could be more flexible than consecutive active data lines as you said previously.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
Documentation/devicetree/bindings/sound/fsl-sai.txt | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 2e726b983845..2b38036a4883 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -49,6 +49,13 @@ Optional properties:
- big-endian : Boolean property, required if all the SAI registers are big-endian rather than little-endian.
- fsl,dl-mask : list of two integers (bitmask, first for RX, second
I am leaving this naming to DT maintainer.
for TX) representing enabled datalines. Bit 0represents first data line, bit 1 represents seconddata line and so on. Data line is enabled ifcorresponding bit is set to 1. By default, if propertynot present, only dataline 0 is enabled for bothdirections.To make this patch more convincing, could we add an example as well in the Example section of this binding file? Like: /* RX data lines 0/1 and TX data lines 0/2 are connected */ fsl,dl-mask = <0x3 0x5>;
Sure, will add an example.
New IP version introduces Version ID and Parameter registers and optionally added Timestamp feature.
VERID and PARAM registers are placed at the top of registers address space and some registers are shifted according to the following table:
Tx/Rx data registers and Tx/Rx FIFO registers keep their addresses, all other registers are shifted by 8.
SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map of the Reference Manual [1].
In order to make as less changes as possible we attach an offset to each register offset to each changed register definition. The offset is read from each board private data.
[1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQ...
Signed-off-by: Mihai Serban mihai.serban@nxp.com [initial coding in the NXP internal tree] Signed-off-by: Shengjiu Wang shengjiu.wang@nxp.com [bugfixing and cleanups] Signed-off-by: Daniel Baluta daniel.baluta@nxp.com [adapted to linux-next] --- sound/soc/fsl/fsl_sai.c | 230 ++++++++++++++++++++++++---------------- sound/soc/fsl/fsl_sai.h | 41 +++---- 2 files changed, 157 insertions(+), 114 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 5e7cb7fd29f5..54e5e9abae01 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -40,6 +40,7 @@ static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { static irqreturn_t fsl_sai_isr(int irq, void *devid) { struct fsl_sai *sai = (struct fsl_sai *)devid; + unsigned int ofs = sai->soc_data->reg_offset; struct device *dev = &sai->pdev->dev; u32 flags, xcsr, mask; bool irq_none = true; @@ -52,7 +53,7 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid) mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
/* Tx IRQ */ - regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr); + regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); flags = xcsr & mask;
if (flags) @@ -82,11 +83,11 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid) xcsr &= ~FSL_SAI_CSR_xF_MASK;
if (flags) - regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr); + regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
irq_rx: /* Rx IRQ */ - regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr); + regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); flags = xcsr & mask;
if (flags) @@ -116,7 +117,7 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid) xcsr &= ~FSL_SAI_CSR_xF_MASK;
if (flags) - regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr); + regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
out: if (irq_none) @@ -140,6 +141,7 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, int clk_id, unsigned int freq, int fsl_dir) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int ofs = sai->soc_data->reg_offset; bool tx = fsl_dir == FSL_FMT_TRANSMITTER; u32 val_cr2 = 0;
@@ -160,7 +162,7 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, return -EINVAL; }
- regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), FSL_SAI_CR2_MSEL_MASK, val_cr2);
return 0; @@ -193,6 +195,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, unsigned int fmt, int fsl_dir) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int ofs = sai->soc_data->reg_offset; bool tx = fsl_dir == FSL_FMT_TRANSMITTER; u32 val_cr2 = 0, val_cr4 = 0;
@@ -287,9 +290,9 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, return -EINVAL; }
- regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); - regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
@@ -316,6 +319,7 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); + unsigned int ofs = sai->soc_data->reg_offset; unsigned long clk_rate; u32 savediv = 0, ratio, savesub = freq; u32 id; @@ -378,17 +382,17 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) */ if ((sai->synchronous[TX] && !sai->synchronous[RX]) || (!tx && !sai->synchronous[RX])) { - regmap_update_bits(sai->regmap, FSL_SAI_RCR2, + regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); - regmap_update_bits(sai->regmap, FSL_SAI_RCR2, + regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_DIV_MASK, savediv - 1); } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) || (tx && !sai->synchronous[TX])) { - regmap_update_bits(sai->regmap, FSL_SAI_TCR2, + regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); - regmap_update_bits(sai->regmap, FSL_SAI_TCR2, + regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_DIV_MASK, savediv - 1); }
@@ -403,6 +407,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int ofs = sai->soc_data->reg_offset; bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; unsigned int channels = params_channels(params); u32 word_width = params_width(params); @@ -455,19 +460,19 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
if (!sai->is_slave_mode) { if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { - regmap_update_bits(sai->regmap, FSL_SAI_TCR4, + regmap_update_bits(sai->regmap, FSL_SAI_TCR4(ofs), FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, val_cr4); - regmap_update_bits(sai->regmap, FSL_SAI_TCR5, + regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs), FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | FSL_SAI_CR5_FBT_MASK, val_cr5); regmap_write(sai->regmap, FSL_SAI_TMR, ~0UL - ((1 << channels) - 1)); } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { - regmap_update_bits(sai->regmap, FSL_SAI_RCR4, + regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs), FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, val_cr4); - regmap_update_bits(sai->regmap, FSL_SAI_RCR5, + regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs), FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | FSL_SAI_CR5_FBT_MASK, val_cr5); regmap_write(sai->regmap, FSL_SAI_RMR, @@ -475,10 +480,10 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, } }
- regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, val_cr4); - regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | FSL_SAI_CR5_FBT_MASK, val_cr5); regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1)); @@ -506,6 +511,8 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *cpu_dai) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int ofs = sai->soc_data->reg_offset; + bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; u32 xcsr, count = 100;
@@ -514,9 +521,9 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. */ - regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, - sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); - regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, + regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, + sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); + regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
/* @@ -527,43 +534,44 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
- regmap_update_bits(sai->regmap, FSL_SAI_RCSR, + regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); - regmap_update_bits(sai->regmap, FSL_SAI_TCSR, + regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
- regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_FRDE, 0); - regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_xIE_MASK, 0);
/* Check if the opposite FRDE is also disabled */ - regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr); + regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); if (!(xcsr & FSL_SAI_CSR_FRDE)) { /* Disable both directions and reset their FIFOs */ - regmap_update_bits(sai->regmap, FSL_SAI_TCSR, + regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_TERE, 0); - regmap_update_bits(sai->regmap, FSL_SAI_RCSR, + regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_TERE, 0);
/* TERE will remain set till the end of current frame */ do { udelay(10); - regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr); + regmap_read(sai->regmap, + FSL_SAI_xCSR(tx, ofs), &xcsr); } while (--count && xcsr & FSL_SAI_CSR_TERE);
- regmap_update_bits(sai->regmap, FSL_SAI_TCSR, + regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); - regmap_update_bits(sai->regmap, FSL_SAI_RCSR, + regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
/* @@ -575,13 +583,13 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, */ if (!sai->is_slave_mode) { /* Software Reset for both Tx and Rx */ - regmap_write(sai->regmap, - FSL_SAI_TCSR, FSL_SAI_CSR_SR); - regmap_write(sai->regmap, - FSL_SAI_RCSR, FSL_SAI_CSR_SR); + regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), + FSL_SAI_CSR_SR); + regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), + FSL_SAI_CSR_SR); /* Clear SR bit to finish the reset */ - regmap_write(sai->regmap, FSL_SAI_TCSR, 0); - regmap_write(sai->regmap, FSL_SAI_RCSR, 0); + regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); + regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); } } break; @@ -596,12 +604,13 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int ofs = sai->soc_data->reg_offset; bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; int ret;
- regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), FSL_SAI_CR3_TRCE_MASK, - FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]); + FSL_SAI_CR3_TRCE(sai->dl_mask[tx]));
ret = snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); @@ -613,9 +622,10 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int ofs = sai->soc_data->reg_offset; bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
- regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), FSL_SAI_CR3_TRCE_MASK, 0); }
@@ -633,18 +643,20 @@ static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) { struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); + unsigned int ofs = sai->soc_data->reg_offset;
/* Software Reset for both Tx and Rx */ - regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); - regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); + regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); + regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); /* Clear SR bit to finish the reset */ - regmap_write(sai->regmap, FSL_SAI_TCSR, 0); - regmap_write(sai->regmap, FSL_SAI_RCSR, 0); + regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); + regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
- regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK, + regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), + FSL_SAI_CR1_RFW_MASK, sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); - regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK, - FSL_SAI_MAXBURST_RX - 1); + regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), + FSL_SAI_CR1_RFW_MASK, FSL_SAI_MAXBURST_RX - 1);
snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, &sai->dma_params_rx); @@ -681,12 +693,12 @@ static const struct snd_soc_component_driver fsl_component = { .name = "fsl-sai", };
-static struct reg_default fsl_sai_reg_defaults[] = { - {FSL_SAI_TCR1, 0}, - {FSL_SAI_TCR2, 0}, - {FSL_SAI_TCR3, 0}, - {FSL_SAI_TCR4, 0}, - {FSL_SAI_TCR5, 0}, +static struct reg_default fsl_sai_reg_defaults_ofs0[] = { + {FSL_SAI_TCR1(0), 0}, + {FSL_SAI_TCR2(0), 0}, + {FSL_SAI_TCR3(0), 0}, + {FSL_SAI_TCR4(0), 0}, + {FSL_SAI_TCR5(0), 0}, {FSL_SAI_TDR0, 0}, {FSL_SAI_TDR1, 0}, {FSL_SAI_TDR2, 0}, @@ -695,24 +707,50 @@ static struct reg_default fsl_sai_reg_defaults[] = { {FSL_SAI_TDR5, 0}, {FSL_SAI_TDR6, 0}, {FSL_SAI_TDR7, 0}, - {FSL_SAI_TMR, 0}, - {FSL_SAI_RCR1, 0}, - {FSL_SAI_RCR2, 0}, - {FSL_SAI_RCR3, 0}, - {FSL_SAI_RCR4, 0}, - {FSL_SAI_RCR5, 0}, - {FSL_SAI_RMR, 0}, + {FSL_SAI_TMR, 0}, + {FSL_SAI_RCR1(0), 0}, + {FSL_SAI_RCR2(0), 0}, + {FSL_SAI_RCR3(0), 0}, + {FSL_SAI_RCR4(0), 0}, + {FSL_SAI_RCR5(0), 0}, + {FSL_SAI_RMR, 0}, +}; + +static struct reg_default fsl_sai_reg_defaults_ofs8[] = { + {FSL_SAI_TCR1(8), 0}, + {FSL_SAI_TCR2(8), 0}, + {FSL_SAI_TCR3(8), 0}, + {FSL_SAI_TCR4(8), 0}, + {FSL_SAI_TCR5(8), 0}, + {FSL_SAI_TDR0, 0}, + {FSL_SAI_TDR1, 0}, + {FSL_SAI_TDR2, 0}, + {FSL_SAI_TDR3, 0}, + {FSL_SAI_TDR4, 0}, + {FSL_SAI_TDR5, 0}, + {FSL_SAI_TDR6, 0}, + {FSL_SAI_TDR7, 0}, + {FSL_SAI_TMR, 0}, + {FSL_SAI_RCR1(8), 0}, + {FSL_SAI_RCR2(8), 0}, + {FSL_SAI_RCR3(8), 0}, + {FSL_SAI_RCR4(8), 0}, + {FSL_SAI_RCR5(8), 0}, + {FSL_SAI_RMR, 0}, };
static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) { + struct fsl_sai *sai = dev_get_drvdata(dev); + unsigned int ofs = sai->soc_data->reg_offset; + + if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) + return true; + + if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) + return true; + switch (reg) { - case FSL_SAI_TCSR: - case FSL_SAI_TCR1: - case FSL_SAI_TCR2: - case FSL_SAI_TCR3: - case FSL_SAI_TCR4: - case FSL_SAI_TCR5: case FSL_SAI_TFR0: case FSL_SAI_TFR1: case FSL_SAI_TFR2: @@ -722,12 +760,6 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TFR6: case FSL_SAI_TFR7: case FSL_SAI_TMR: - case FSL_SAI_RCSR: - case FSL_SAI_RCR1: - case FSL_SAI_RCR2: - case FSL_SAI_RCR3: - case FSL_SAI_RCR4: - case FSL_SAI_RCR5: case FSL_SAI_RDR0: case FSL_SAI_RDR1: case FSL_SAI_RDR2: @@ -753,9 +785,13 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) { + struct fsl_sai *sai = dev_get_drvdata(dev); + unsigned int ofs = sai->soc_data->reg_offset; + + if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) + return true; + switch (reg) { - case FSL_SAI_TCSR: - case FSL_SAI_RCSR: case FSL_SAI_TFR0: case FSL_SAI_TFR1: case FSL_SAI_TFR2: @@ -788,13 +824,16 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) { + struct fsl_sai *sai = dev_get_drvdata(dev); + unsigned int ofs = sai->soc_data->reg_offset; + + if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) + return true; + + if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) + return true; + switch (reg) { - case FSL_SAI_TCSR: - case FSL_SAI_TCR1: - case FSL_SAI_TCR2: - case FSL_SAI_TCR3: - case FSL_SAI_TCR4: - case FSL_SAI_TCR5: case FSL_SAI_TDR0: case FSL_SAI_TDR1: case FSL_SAI_TDR2: @@ -804,12 +843,6 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) case FSL_SAI_TDR6: case FSL_SAI_TDR7: case FSL_SAI_TMR: - case FSL_SAI_RCSR: - case FSL_SAI_RCR1: - case FSL_SAI_RCR2: - case FSL_SAI_RCR3: - case FSL_SAI_RCR4: - case FSL_SAI_RCR5: case FSL_SAI_RMR: return true; default: @@ -817,15 +850,15 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) } }
-static const struct regmap_config fsl_sai_regmap_config = { +static struct regmap_config fsl_sai_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .fast_io = true,
.max_register = FSL_SAI_RMR, - .reg_defaults = fsl_sai_reg_defaults, - .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults), + .reg_defaults = fsl_sai_reg_defaults_ofs0, + .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), .readable_reg = fsl_sai_readable_reg, .volatile_reg = fsl_sai_volatile_reg, .writeable_reg = fsl_sai_writeable_reg, @@ -857,6 +890,12 @@ static int fsl_sai_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base);
+ if (sai->soc_data->reg_offset == 8) { + fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; + fsl_sai_regmap_config.num_reg_defaults = + ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); + } + sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus", base, &fsl_sai_regmap_config);
@@ -982,11 +1021,13 @@ static int fsl_sai_remove(struct platform_device *pdev) static const struct fsl_sai_soc_data fsl_sai_vf610_data = { .use_imx_pcm = false, .fifo_depth = 32, + .reg_offset = 0, };
static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { .use_imx_pcm = true, .fifo_depth = 32, + .reg_offset = 0, };
static const struct of_device_id fsl_sai_ids[] = { @@ -1019,6 +1060,7 @@ static int fsl_sai_runtime_suspend(struct device *dev) static int fsl_sai_runtime_resume(struct device *dev) { struct fsl_sai *sai = dev_get_drvdata(dev); + unsigned int ofs = sai->soc_data->reg_offset; int ret;
ret = clk_prepare_enable(sai->bus_clk); @@ -1040,11 +1082,11 @@ static int fsl_sai_runtime_resume(struct device *dev) }
regcache_cache_only(sai->regmap, false); - regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); - regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); + regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); + regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); usleep_range(1000, 2000); - regmap_write(sai->regmap, FSL_SAI_TCSR, 0); - regmap_write(sai->regmap, FSL_SAI_RCSR, 0); + regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); + regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
ret = regcache_sync(sai->regmap); if (ret) diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 6d32f0950ec5..0e61e1a01506 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -14,12 +14,12 @@ SNDRV_PCM_FMTBIT_S32_LE)
/* SAI Register Map Register */ -#define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */ -#define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */ -#define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */ -#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */ -#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */ -#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */ +#define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */ +#define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */ +#define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */ +#define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */ +#define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */ +#define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */ #define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */ #define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */ #define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */ @@ -37,12 +37,12 @@ #define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */ #define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */ #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */ -#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */ -#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */ -#define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */ -#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */ -#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */ -#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */ +#define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */ +#define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */ +#define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */ +#define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */ +#define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */ +#define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */ #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */ #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */ #define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */ @@ -61,14 +61,14 @@ #define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */ #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
-#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR) -#define FSL_SAI_xCR1(tx) (tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1) -#define FSL_SAI_xCR2(tx) (tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2) -#define FSL_SAI_xCR3(tx) (tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3) -#define FSL_SAI_xCR4(tx) (tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4) -#define FSL_SAI_xCR5(tx) (tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5) -#define FSL_SAI_xDR(tx) (tx ? FSL_SAI_TDR : FSL_SAI_RDR) -#define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR) +#define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs)) +#define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs)) +#define FSL_SAI_xCR2(tx, ofs) (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs)) +#define FSL_SAI_xCR3(tx, ofs) (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs)) +#define FSL_SAI_xCR4(tx, ofs) (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs)) +#define FSL_SAI_xCR5(tx, ofs) (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs)) +#define FSL_SAI_xDR(tx, ofs) (tx ? FSL_SAI_TDR(ofs) : FSL_SAI_RDR(ofs)) +#define FSL_SAI_xFR(tx, ofs) (tx ? FSL_SAI_TFR(ofs) : FSL_SAI_RFR(ofs)) #define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
/* SAI Transmit/Receive Control Register */ @@ -158,6 +158,7 @@ struct fsl_sai_soc_data { bool use_imx_pcm; unsigned int fifo_depth; + unsigned int reg_offset; };
struct fsl_sai {
SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM) at the beginning of register address space.
On imx7ulp FIFOs can held up to 16 x 32 bit samples. On imx8mq FIFOs can held up to 128 x 32 bit samples.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com --- sound/soc/fsl/fsl_sai.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 54e5e9abae01..0fb6750fefd5 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -1030,10 +1030,24 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { .reg_offset = 0, };
+static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { + .use_imx_pcm = true, + .fifo_depth = 16, + .reg_offset = 8, +}; + +static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { + .use_imx_pcm = true, + .fifo_depth = 128, + .reg_offset = 8, +}; + static const struct of_device_id fsl_sai_ids[] = { { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, + { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, + { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_sai_ids);
On Sun, Jul 28, 2019 at 10:24:28PM +0300, Daniel Baluta wrote:
SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM) at the beginning of register address space.
On imx7ulp FIFOs can held up to 16 x 32 bit samples. On imx8mq FIFOs can held up to 128 x 32 bit samples.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
Acked-by: Nicolin Chen nicoleotsuka@gmail.com
sound/soc/fsl/fsl_sai.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 54e5e9abae01..0fb6750fefd5 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -1030,10 +1030,24 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { .reg_offset = 0, };
+static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
- .use_imx_pcm = true,
- .fifo_depth = 16,
- .reg_offset = 8,
+};
+static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
- .use_imx_pcm = true,
- .fifo_depth = 128,
- .reg_offset = 8,
+};
static const struct of_device_id fsl_sai_ids[] = { { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
- { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
- { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, { /* sentinel */ }
}; MODULE_DEVICE_TABLE(of, fsl_sai_ids); -- 2.17.1
For i.MX7ULP and i.MX8MQ register map is changed. Add two new compatbile strings to differentiate this.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 2b38036a4883..b008e9cfedc1 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -8,7 +8,8 @@ codec/DSP interfaces. Required properties:
- compatible : Compatible list, contains "fsl,vf610-sai", - "fsl,imx6sx-sai" or "fsl,imx6ul-sai" + "fsl,imx6sx-sai", "fsl,imx6ul-sai", + "fsl,imx7ulp-sai", "fsl,imx8mq-sai".
- reg : Offset and length of the register set for the device.
On Sun, Jul 28, 2019 at 10:24:29PM +0300, Daniel Baluta wrote:
For i.MX7ULP and i.MX8MQ register map is changed. Add two new compatbile strings to differentiate this.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 2b38036a4883..b008e9cfedc1 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -8,7 +8,8 @@ codec/DSP interfaces. Required properties:
- compatible : Compatible list, contains "fsl,vf610-sai",
"fsl,imx6sx-sai" or "fsl,imx6ul-sai"
"fsl,imx6sx-sai", "fsl,imx6ul-sai","fsl,imx7ulp-sai", "fsl,imx8mq-sai".
A nit, could have that 'or' :)
- reg : Offset and length of the register set for the device.
-- 2.17.1
On Tue, Jul 30, 2019 at 11:02 AM Nicolin Chen nicoleotsuka@gmail.com wrote:
On Sun, Jul 28, 2019 at 10:24:29PM +0300, Daniel Baluta wrote:
For i.MX7ULP and i.MX8MQ register map is changed. Add two new compatbile strings to differentiate this.
Signed-off-by: Daniel Baluta daniel.baluta@nxp.com
Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 2b38036a4883..b008e9cfedc1 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -8,7 +8,8 @@ codec/DSP interfaces. Required properties:
- compatible : Compatible list, contains "fsl,vf610-sai",
"fsl,imx6sx-sai" or "fsl,imx6ul-sai"
"fsl,imx6sx-sai", "fsl,imx6ul-sai","fsl,imx7ulp-sai", "fsl,imx8mq-sai".A nit, could have that 'or' :)
I removed the 'or' on purpose because I don't want to move it around each time we add a new compatible.
Anyhow, I can put it back if this is the convention.
On Tue, Jul 30, 2019 at 03:02:30PM +0300, Daniel Baluta wrote:
I removed the 'or' on purpose because I don't want to move it around each time we add a new compatible.
Anyhow, I can put it back if this is the convention.
You could convert to the YAML binding format and sidestep the problem a different way!
On Tue, Jul 30, 2019 at 3:05 PM Mark Brown broonie@kernel.org wrote:
On Tue, Jul 30, 2019 at 03:02:30PM +0300, Daniel Baluta wrote:
I removed the 'or' on purpose because I don't want to move it around each time we add a new compatible.
Anyhow, I can put it back if this is the convention.
You could convert to the YAML binding format and sidestep the problem a different way!
Someone needs to do that in the end, so will try to change to yaml with the next version of the patch series.
participants (4)
-
Daniel Baluta -
Daniel Baluta -
Mark Brown -
Nicolin Chen