[alsa-devel] [PATCH] ASoC: Document DAI signal polarity
Currently there is no clear definition of what is FSYNC polarity. Different drivers use its own definition of what is "normal" and what is "inverted" fsync. This leads to compatibility problems between drivers.
For example TegraX1 driver assumes that DSP-A format with frames starting at rising FSYNC edge has "negative" polarity, while RT5677 assumes it is "positive" polarity.
Explicitly specify meaning of BCLK/FSYNC polarity to avoid future compatibility problems.
Signed-off-by: Anatol Pomozov anatol.pomozov@gmail.com --- include/sound/soc-dai.h | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h index 2df96b1..45198db 100644 --- a/include/sound/soc-dai.h +++ b/include/sound/soc-dai.h @@ -48,10 +48,22 @@ struct snd_compr_stream; #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
/* - * DAI hardware signal inversions. + * DAI hardware signal polarity. * - * Specifies whether the DAI can also support inverted clocks for the specified - * format. + * BCLK: + * - "normal" polarity means signal is available at rising edge of BCLK + * - "inverted" polarity means signal is available at falling edge of BCLK + * + * FSYNC "normal" polarity depends on the frame format: + * - I2S: frame consists of left then right channel data. Left channel starts + * with falling FSYNC edge, right channel starts with rising FSYNC edge. + * - I2S right/left justified: frame consists of left then right channel data. + * Left channel starts with rising FSYNC edge, right channel starts with + * falling FSYNC edge. + * - DSP A/B: Frame starts with rising FSYNC edge. + * - AC97: Frame starts with rising FSYNC edge. + * + * "Negative" FSYNC polarity is the one opposite of "normal" polarity. */ #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */ #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
Dear Anatol Pomozov,
On Thu, Oct 1, 2015 at 8:09 PM, Anatol Pomozov anatol.pomozov@gmail.com wrote:
Currently there is no clear definition of what is FSYNC polarity. Different drivers use its own definition of what is "normal" and what is "inverted" fsync. This leads to compatibility problems between drivers.
For example TegraX1 driver assumes that DSP-A format with frames starting at rising FSYNC edge has "negative" polarity, while RT5677 assumes it is "positive" polarity.
This wording is confusing. "Normal"/"inverted" are more appropriate than "positive"/"negative" here, because the latter would refer to the falling/rising edges, not to the regular polarity as the former.
Explicitly specify meaning of BCLK/FSYNC polarity to avoid future compatibility problems.
Signed-off-by: Anatol Pomozov anatol.pomozov@gmail.com
include/sound/soc-dai.h | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h index 2df96b1..45198db 100644 --- a/include/sound/soc-dai.h +++ b/include/sound/soc-dai.h @@ -48,10 +48,22 @@ struct snd_compr_stream; #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
/*
- DAI hardware signal inversions.
- DAI hardware signal polarity.
- Specifies whether the DAI can also support inverted clocks for the specified
- format.
Please keep this sentence or rephrase it, but do not remove it: it clarifies "normal" as meaning the default for the specified format (I²S, L/R-justified, DSP A/B, AC'97, PDM).
- BCLK:
- "normal" polarity means signal is available at rising edge of BCLK
- "inverted" polarity means signal is available at falling edge of BCLK
- FSYNC "normal" polarity depends on the frame format:
- I2S: frame consists of left then right channel data. Left channel starts
with falling FSYNC edge, right channel starts with rising FSYNC edge.
- I2S right/left justified: frame consists of left then right channel data.
The L/R-justified formats are independent of I²S, so "I2S" should be removed from this line.
Left channel starts with rising FSYNC edge, right channel starts with
falling FSYNC edge.
- DSP A/B: Frame starts with rising FSYNC edge.
- AC97: Frame starts with rising FSYNC edge.
*/
- "Negative" FSYNC polarity is the one opposite of "normal" polarity.
#define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */
#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
2.6.0.rc2.230.g3dd15c0
Best regards, Benoît
On Thu, Oct 01, 2015 at 11:09:19AM -0700, Anatol Pomozov wrote:
- I2S right/left justified: frame consists of left then right channel data.
Left channel starts with rising FSYNC edge, right channel starts with
falling FSYNC edge.
These are just called left and right justified - they do look a lot like I2S but I2S isn't part of the name in normal usage so it's a little confusing.
Also it's more normal when talking about both left and right to list left first, it scans better.
Dear Mark Brown,
On Mon, Oct 5, 2015 at 5:12 PM, Mark Brown broonie@kernel.org wrote:
On Thu, Oct 01, 2015 at 11:09:19AM -0700, Anatol Pomozov wrote:
- I2S right/left justified: frame consists of left then right channel data.
Left channel starts with rising FSYNC edge, right channel starts with
falling FSYNC edge.These are just called left and right justified - they do look a lot like I2S but I2S isn't part of the name in normal usage so it's a little confusing.
Also it's more normal when talking about both left and right to list left first, it scans better.
This has already been addressed in the v2 here (you were Cc'ed): http://mailman.alsa-project.org/pipermail/alsa-devel/2015-October/098307.htm...
Best regards, Benoît
On Mon, Oct 05, 2015 at 09:20:05PM +0200, Benoît Thébaudeau wrote:
Also it's more normal when talking about both left and right to list left first, it scans better.
This has already been addressed in the v2 here (you were Cc'ed): http://mailman.alsa-project.org/pipermail/alsa-devel/2015-October/098307.htm...
That's the only version I had in my inbox.
participants (3)
-
Anatol Pomozov -
Benoît Thébaudeau -
Mark Brown