[PATCH v2 0/7] soundwire: qcom: add support for SM8550 (Soundwire v2.0.0)
Hi,
Changes since v1: 1. Patch 1: Increase maxItems to 16 for port-related properties. 2. Re-order patch 1 and 2. 3. Patch 3: Drop unneeded semicolon. 4. Patch 5: Fix lang typo in subject.
Best regards, Krzysztof
Krzysztof Kozlowski (7): dt-bindings: soundwire: qcom: add Qualcomm Soundwire v2.0.0 dt-bindings: soundwire: qcom: add 16-bit sample interval soundwire: qcom: allow 16-bit sample interval for ports soundwire: qcom: use consistently 'ctrl' as state variable name soundwire: qcom: prepare for handling different register layouts soundwire: qcom: add support for v2.0.0 controller soundwire: qcom: use tabs for indentation in defines
.../bindings/soundwire/qcom,soundwire.yaml | 41 +- drivers/soundwire/qcom.c | 387 ++++++++++++------ 2 files changed, 289 insertions(+), 139 deletions(-)
Add compatible for Qualcomm Soundwire v2.0.0 controller, which comes with several differences against v1.7.0 in register layout and more ports (thus increase maxItems of each port-related property to 16).
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
---
Changes since v1: 1. Increase maxItems to 16 for port-related properties. --- .../bindings/soundwire/qcom,soundwire.yaml | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index 3efdc192ab01..c283c594fb5c 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -21,6 +21,7 @@ properties: - qcom,soundwire-v1.5.1 - qcom,soundwire-v1.6.0 - qcom,soundwire-v1.7.0 + - qcom,soundwire-v2.0.0
reg: maxItems: 1 @@ -80,7 +81,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 8 + maxItems: 16
qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -91,7 +92,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 8 + maxItems: 16
qcom,ports-offset1: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -102,7 +103,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 8 + maxItems: 16
qcom,ports-offset2: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -113,7 +114,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 8 + maxItems: 16
qcom,ports-lane-control: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -124,7 +125,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 8 + maxItems: 16
qcom,ports-block-pack-mode: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -137,7 +138,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 8 + maxItems: 16 items: oneOf: - minimum: 0 @@ -154,7 +155,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 8 + maxItems: 16 items: oneOf: - minimum: 0 @@ -171,7 +172,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 8 + maxItems: 16 items: oneOf: - minimum: 0 @@ -187,7 +188,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 8 + maxItems: 16 items: oneOf: - minimum: 0
On Mon, 03 Apr 2023 15:24:57 +0200, Krzysztof Kozlowski wrote:
Add compatible for Qualcomm Soundwire v2.0.0 controller, which comes with several differences against v1.7.0 in register layout and more ports (thus increase maxItems of each port-related property to 16).
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Changes since v1:
- Increase maxItems to 16 for port-related properties.
.../bindings/soundwire/qcom,soundwire.yaml | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)
Reviewed-by: Rob Herring robh@kernel.org
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- .../bindings/soundwire/qcom,soundwire.yaml | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index c283c594fb5c..883b8be9be1b 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -86,7 +86,7 @@ properties: qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array description: - Sample interval low of each data port. + Sample interval (only lowest byte) of each data port. Out ports followed by In ports. Used for Sample Interval calculation. Value of 0xff indicates that this option is not implemented or applicable for the respective data port. @@ -94,6 +94,19 @@ properties: minItems: 3 maxItems: 16
+ qcom,ports-sinterval: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Sample interval of each data port. + Out ports followed by In ports. Used for Sample Interval calculation. + Value of 0xffff indicates that this option is not implemented + or applicable for the respective data port. + More info in MIPI Alliance SoundWire 1.0 Specifications. + minItems: 3 + maxItems: 16 + items: + maximum: 0xffff + qcom,ports-offset1: $ref: /schemas/types.yaml#/definitions/uint8-array description: @@ -219,10 +232,15 @@ required: - '#size-cells' - qcom,dout-ports - qcom,din-ports - - qcom,ports-sinterval-low - qcom,ports-offset1 - qcom,ports-offset2
+oneOf: + - required: + - qcom,ports-sinterval-low + - required: + - qcom,ports-sinterval + additionalProperties: false
examples:
On Mon, Apr 03, 2023 at 03:24:58PM +0200, Krzysztof Kozlowski wrote:
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
.../bindings/soundwire/qcom,soundwire.yaml | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index c283c594fb5c..883b8be9be1b 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -86,7 +86,7 @@ properties: qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array description:
Sample interval low of each data port.
Sample interval (only lowest byte) of each data port. Out ports followed by In ports. Used for Sample Interval calculation. Value of 0xff indicates that this option is not implemented or applicable for the respective data port.@@ -94,6 +94,19 @@ properties: minItems: 3 maxItems: 16
- qcom,ports-sinterval:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- description:
Sample interval of each data port.Out ports followed by In ports. Used for Sample Interval calculation.Value of 0xffff indicates that this option is not implementedor applicable for the respective data port.More info in MIPI Alliance SoundWire 1.0 Specifications.- minItems: 3
- maxItems: 16
- items:
maximum: 0xffff
Why not use uint16-array?
- qcom,ports-offset1: $ref: /schemas/types.yaml#/definitions/uint8-array description:
@@ -219,10 +232,15 @@ required:
- '#size-cells'
- qcom,dout-ports
- qcom,din-ports
- qcom,ports-sinterval-low
- qcom,ports-offset1
- qcom,ports-offset2
+oneOf:
- required:
- qcom,ports-sinterval-low
- required:
- qcom,ports-sintervaladditionalProperties: false
examples:
2.34.1
On 04/04/2023 16:21, Rob Herring wrote:
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index c283c594fb5c..883b8be9be1b 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -86,7 +86,7 @@ properties: qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array description:
Sample interval low of each data port.
Sample interval (only lowest byte) of each data port. Out ports followed by In ports. Used for Sample Interval calculation. Value of 0xff indicates that this option is not implemented or applicable for the respective data port.@@ -94,6 +94,19 @@ properties: minItems: 3 maxItems: 16
- qcom,ports-sinterval:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- description:
Sample interval of each data port.Out ports followed by In ports. Used for Sample Interval calculation.Value of 0xffff indicates that this option is not implementedor applicable for the respective data port.More info in MIPI Alliance SoundWire 1.0 Specifications.- minItems: 3
- maxItems: 16
- items:
maximum: 0xffffWhy not use uint16-array?
Because I am afraid it will grow in next version to 24 or 32 bits. I can change easily maximum, but if I put here uint16-array, all DTS will have /bytes 16/ annotation.
Best regards, Krzysztof
On Mon, 03 Apr 2023 15:24:58 +0200, Krzysztof Kozlowski wrote:
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
.../bindings/soundwire/qcom,soundwire.yaml | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)
Reviewed-by: Rob Herring robh@kernel.org
On 03/04/2023 14:24, Krzysztof Kozlowski wrote:
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
.../bindings/soundwire/qcom,soundwire.yaml | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index c283c594fb5c..883b8be9be1b 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -86,7 +86,7 @@ properties: qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array description:
Sample interval low of each data port.
Sample interval (only lowest byte) of each data port. Out ports followed by In ports. Used for Sample Interval calculation. Value of 0xff indicates that this option is not implemented or applicable for the respective data port.@@ -94,6 +94,19 @@ properties: minItems: 3 maxItems: 16
- qcom,ports-sinterval:
- $ref: /schemas/types.yaml#/definitions/uint32-array
Should this not be ref: /schemas/types.yaml#/definitions/uint16-array ?
--srini
- description:
Sample interval of each data port.Out ports followed by In ports. Used for Sample Interval calculation.Value of 0xffff indicates that this option is not implementedor applicable for the respective data port.More info in MIPI Alliance SoundWire 1.0 Specifications.- minItems: 3
- maxItems: 16
- items:
maximum: 0xffff- qcom,ports-offset1: $ref: /schemas/types.yaml#/definitions/uint8-array description:
@@ -219,10 +232,15 @@ required: - '#size-cells' - qcom,dout-ports - qcom,din-ports
- qcom,ports-sinterval-low
- qcom,ports-offset1
- qcom,ports-offset2
+oneOf:
- required:
- qcom,ports-sinterval-low
- required:
- qcom,ports-sintervaladditionalProperties: false
examples:
On 12/04/2023 17:28, Srinivas Kandagatla wrote:
On 03/04/2023 14:24, Krzysztof Kozlowski wrote:
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
.../bindings/soundwire/qcom,soundwire.yaml | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index c283c594fb5c..883b8be9be1b 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -86,7 +86,7 @@ properties: qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array description:
Sample interval low of each data port.
Sample interval (only lowest byte) of each data port. Out ports followed by In ports. Used for Sample Interval calculation. Value of 0xff indicates that this option is not implemented or applicable for the respective data port.@@ -94,6 +94,19 @@ properties: minItems: 3 maxItems: 16
- qcom,ports-sinterval:
- $ref: /schemas/types.yaml#/definitions/uint32-array
Should this not be ref: /schemas/types.yaml#/definitions/uint16-array ?
Same answer as for Rob:
Because I am afraid it will grow in next version to 24 or 32 bits. I can change easily maximum, but if I put here uint16-array, all DTS will have /bytes 16/ annotation.
Best regards, Krzysztof
On 12/04/2023 17:16, Krzysztof Kozlowski wrote:
On 12/04/2023 17:28, Srinivas Kandagatla wrote:
On 03/04/2023 14:24, Krzysztof Kozlowski wrote:
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
.../bindings/soundwire/qcom,soundwire.yaml | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index c283c594fb5c..883b8be9be1b 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -86,7 +86,7 @@ properties: qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array description:
Sample interval low of each data port.
Sample interval (only lowest byte) of each data port. Out ports followed by In ports. Used for Sample Interval calculation. Value of 0xff indicates that this option is not implemented or applicable for the respective data port.@@ -94,6 +94,19 @@ properties: minItems: 3 maxItems: 16
- qcom,ports-sinterval:
- $ref: /schemas/types.yaml#/definitions/uint32-array
Should this not be ref: /schemas/types.yaml#/definitions/uint16-array ?
Same answer as for Rob:
Because I am afraid it will grow in next version to 24 or 32 bits. I can change easily maximum, but if I put here uint16-array, all DTS will have /bytes 16/ annotation.
As per MiPi Specs the sample Interval is an integer in the range 2 to 65535. I don't see a value in making this u32, other than adding some confusion by deviating from specs.
--srini
Best regards, Krzysztof
On 13/04/2023 13:12, Srinivas Kandagatla wrote:
- qcom,ports-sinterval:
- $ref: /schemas/types.yaml#/definitions/uint32-array
Should this not be ref: /schemas/types.yaml#/definitions/uint16-array ?
Same answer as for Rob:
Because I am afraid it will grow in next version to 24 or 32 bits. I can change easily maximum, but if I put here uint16-array, all DTS will have /bytes 16/ annotation.
As per MiPi Specs the sample Interval is an integer in the range 2 to 65535. I don't see a value in making this u32, other than adding some confusion by deviating from specs.
Hm, in such case I'll make it uint16.
Best regards, Krzysztof
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
---
Changes since v1: 1. Drop unneeded semicolon. --- drivers/soundwire/qcom.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index c296e0bf897b..faa091e7472a 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -95,6 +95,7 @@ #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) +#define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) #define SWR_MSTR_MAX_REG_ADDR (0x1740)
@@ -131,7 +132,7 @@ enum { };
struct qcom_swrm_port_config { - u8 si; + u32 si; u8 off1; u8 off2; u8 bp_mode; @@ -806,12 +807,20 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus,
value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; - value |= pcfg->si; + value |= pcfg->si & 0xff;
ret = ctrl->reg_write(ctrl, reg, value); if (ret) goto err;
+ if (pcfg->si > 0xff) { + value = (pcfg->si >> 8) & 0xff; + reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank); + ret = ctrl->reg_write(ctrl, reg, value); + if (ret) + goto err; + } + if (pcfg->lane_control != SWR_INVALID_PARAM) { reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); value = pcfg->lane_control; @@ -1185,7 +1194,7 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) struct device_node *np = ctrl->dev->of_node; u8 off1[QCOM_SDW_MAX_PORTS]; u8 off2[QCOM_SDW_MAX_PORTS]; - u8 si[QCOM_SDW_MAX_PORTS]; + u32 si[QCOM_SDW_MAX_PORTS]; u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; u8 hstart[QCOM_SDW_MAX_PORTS]; u8 hstop[QCOM_SDW_MAX_PORTS]; @@ -1193,6 +1202,7 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) u8 blk_group_count[QCOM_SDW_MAX_PORTS]; u8 lane_control[QCOM_SDW_MAX_PORTS]; int i, ret, nports, val; + bool si_32 = false;
ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
@@ -1236,9 +1246,14 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) return ret;
ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", - si, nports); - if (ret) - return ret; + (u8 *)si, nports); + if (ret) { + ret = of_property_read_u32_array(np, "qcom,ports-sinterval", + si, nports); + if (ret) + return ret; + si_32 = true; + }
ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", bp_mode, nports); @@ -1266,7 +1281,10 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
for (i = 0; i < nports; i++) { /* Valid port number range is from 1-14 */ - ctrl->pconfig[i + 1].si = si[i]; + if (si_32) + ctrl->pconfig[i + 1].si = si[i]; + else + ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; ctrl->pconfig[i + 1].off1 = off1[i]; ctrl->pconfig[i + 1].off2 = off2[i]; ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
On 3.04.2023 15:24, Krzysztof Kozlowski wrote:
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
I have little insight in this code, but the changes look logical, so..
Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org
Konrad
Changes since v1:
- Drop unneeded semicolon.
drivers/soundwire/qcom.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index c296e0bf897b..faa091e7472a 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -95,6 +95,7 @@ #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) +#define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) #define SWR_MSTR_MAX_REG_ADDR (0x1740)
@@ -131,7 +132,7 @@ enum { };
struct qcom_swrm_port_config {
- u8 si;
- u32 si; u8 off1; u8 off2; u8 bp_mode;
@@ -806,12 +807,20 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus,
value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
- value |= pcfg->si;
value |= pcfg->si & 0xff;
ret = ctrl->reg_write(ctrl, reg, value); if (ret) goto err;
if (pcfg->si > 0xff) {
value = (pcfg->si >> 8) & 0xff;reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank);ret = ctrl->reg_write(ctrl, reg, value);if (ret)goto err;}
if (pcfg->lane_control != SWR_INVALID_PARAM) { reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); value = pcfg->lane_control;
@@ -1185,7 +1194,7 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) struct device_node *np = ctrl->dev->of_node; u8 off1[QCOM_SDW_MAX_PORTS]; u8 off2[QCOM_SDW_MAX_PORTS];
- u8 si[QCOM_SDW_MAX_PORTS];
- u32 si[QCOM_SDW_MAX_PORTS]; u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; u8 hstart[QCOM_SDW_MAX_PORTS]; u8 hstop[QCOM_SDW_MAX_PORTS];
@@ -1193,6 +1202,7 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) u8 blk_group_count[QCOM_SDW_MAX_PORTS]; u8 lane_control[QCOM_SDW_MAX_PORTS]; int i, ret, nports, val;
bool si_32 = false;
ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
@@ -1236,9 +1246,14 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) return ret;
ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
si, nports);- if (ret)
return ret;
(u8 *)si, nports);if (ret) {
ret = of_property_read_u32_array(np, "qcom,ports-sinterval",si, nports);if (ret)return ret;si_32 = true;}
ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", bp_mode, nports);
@@ -1266,7 +1281,10 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
for (i = 0; i < nports; i++) { /* Valid port number range is from 1-14 */
ctrl->pconfig[i + 1].si = si[i];
if (si_32)ctrl->pconfig[i + 1].si = si[i];elsectrl->pconfig[i + 1].si = ((u8 *)si)[i];
The pointer to 'struct qcom_swrm_ctrl' was called sometimes 'swrm' and sometimes 'ctrl' variable. Choose one - 'ctrl' - so the code will be consistent and easier to read.
No functional change.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- drivers/soundwire/qcom.c | 168 +++++++++++++++++++-------------------- 1 file changed, 84 insertions(+), 84 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index faa091e7472a..00522de47b6f 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -279,14 +279,14 @@ static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, return val; }
-static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) +static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) { u32 fifo_outstanding_data, value; int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
do { /* Check for fifo underflow during read */ - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); + ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
/* Check if read data is available in read fifo */ @@ -297,39 +297,39 @@ static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) } while (fifo_retry_count--);
if (fifo_outstanding_data == 0) { - dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__); + dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); return -EIO; }
return 0; }
-static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm) +static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) { u32 fifo_outstanding_cmds, value; int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
do { /* Check for fifo overflow during write */ - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); + ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
/* Check for space in write fifo before writing */ - if (fifo_outstanding_cmds < swrm->wr_fifo_depth) + if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) return 0;
usleep_range(500, 510); } while (fifo_retry_count--);
- if (fifo_outstanding_cmds == swrm->wr_fifo_depth) { - dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__); + if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { + dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); return -EIO; }
return 0; }
-static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, +static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, u8 dev_addr, u16 reg_addr) {
@@ -342,20 +342,20 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, val = swrm_get_packed_reg_val(&cmd_id, cmd_data, dev_addr, reg_addr); } else { - val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, + val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, dev_addr, reg_addr); }
- if (swrm_wait_for_wr_fifo_avail(swrm)) + if (swrm_wait_for_wr_fifo_avail(ctrl)) return SDW_CMD_FAIL_OTHER;
if (cmd_id == SWR_BROADCAST_CMD_ID) - reinit_completion(&swrm->broadcast); + reinit_completion(&ctrl->broadcast);
/* Its assumed that write is okay as we do not get any status back */ - swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val); + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
- if (swrm->version <= SWRM_VERSION_1_3_0) + if (ctrl->version <= SWRM_VERSION_1_3_0) usleep_range(150, 155);
if (cmd_id == SWR_BROADCAST_CMD_ID) { @@ -363,7 +363,7 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, * sleep for 10ms for MSM soundwire variant to allow broadcast * command to complete. */ - ret = wait_for_completion_timeout(&swrm->broadcast, + ret = wait_for_completion_timeout(&ctrl->broadcast, msecs_to_jiffies(TIMEOUT_MS)); if (!ret) ret = SDW_CMD_IGNORED; @@ -376,41 +376,41 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, return ret; }
-static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm, +static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, u8 dev_addr, u16 reg_addr, u32 len, u8 *rval) { u32 cmd_data, cmd_id, val, retry_attempt = 0;
- val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); + val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
/* * Check for outstanding cmd wrt. write fifo depth to avoid * overflow as read will also increase write fifo cnt. */ - swrm_wait_for_wr_fifo_avail(swrm); + swrm_wait_for_wr_fifo_avail(ctrl);
/* wait for FIFO RD to complete to avoid overflow */ usleep_range(100, 105); - swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val); /* wait for FIFO RD CMD complete to avoid overflow */ usleep_range(250, 255);
- if (swrm_wait_for_rd_fifo_avail(swrm)) + if (swrm_wait_for_rd_fifo_avail(ctrl)) return SDW_CMD_FAIL_OTHER;
do { - swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); + ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); rval[0] = cmd_data & 0xFF; cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
- if (cmd_id != swrm->rcmd_id) { + if (cmd_id != ctrl->rcmd_id) { if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { /* wait 500 us before retry on fifo read failure */ usleep_range(500, 505); - swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, SWRM_CMD_FIFO_FLUSH); - swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val); } retry_attempt++; } else { @@ -419,9 +419,9 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
} while (retry_attempt < MAX_FIFO_RD_RETRY);
- dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ + dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ dev_num: 0x%x, cmd_data: 0x%x\n", - reg_addr, swrm->rcmd_id, dev_addr, cmd_data); + reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
return SDW_CMD_IGNORED; } @@ -533,39 +533,39 @@ static int qcom_swrm_enumerate(struct sdw_bus *bus)
static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) { - struct qcom_swrm_ctrl *swrm = dev_id; + struct qcom_swrm_ctrl *ctrl = dev_id; int ret;
- ret = pm_runtime_resume_and_get(swrm->dev); + ret = pm_runtime_resume_and_get(ctrl->dev); if (ret < 0 && ret != -EACCES) { - dev_err_ratelimited(swrm->dev, + dev_err_ratelimited(ctrl->dev, "pm_runtime_resume_and_get failed in %s, ret %d\n", __func__, ret); return ret; }
- if (swrm->wake_irq > 0) { - if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq))) - disable_irq_nosync(swrm->wake_irq); + if (ctrl->wake_irq > 0) { + if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) + disable_irq_nosync(ctrl->wake_irq); }
- pm_runtime_mark_last_busy(swrm->dev); - pm_runtime_put_autosuspend(swrm->dev); + pm_runtime_mark_last_busy(ctrl->dev); + pm_runtime_put_autosuspend(ctrl->dev);
return IRQ_HANDLED; }
static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) { - struct qcom_swrm_ctrl *swrm = dev_id; + struct qcom_swrm_ctrl *ctrl = dev_id; u32 value, intr_sts, intr_sts_masked, slave_status; u32 i; int devnum; int ret = IRQ_HANDLED; - clk_prepare_enable(swrm->hclk); + clk_prepare_enable(ctrl->hclk);
- swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); - intr_sts_masked = intr_sts & swrm->intr_mask; + ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts); + intr_sts_masked = intr_sts & ctrl->intr_mask;
do { for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { @@ -575,80 +575,80 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
switch (value) { case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: - devnum = qcom_swrm_get_alert_slave_dev_num(swrm); + devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); if (devnum < 0) { - dev_err_ratelimited(swrm->dev, + dev_err_ratelimited(ctrl->dev, "no slave alert found.spurious interrupt\n"); } else { - sdw_handle_slave_status(&swrm->bus, swrm->status); + sdw_handle_slave_status(&ctrl->bus, ctrl->status); }
break; case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: - dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n"); - swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status); - if (swrm->slave_status == slave_status) { - dev_dbg(swrm->dev, "Slave status not changed %x\n", + dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); + ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); + if (ctrl->slave_status == slave_status) { + dev_dbg(ctrl->dev, "Slave status not changed %x\n", slave_status); } else { - qcom_swrm_get_device_status(swrm); - qcom_swrm_enumerate(&swrm->bus); - sdw_handle_slave_status(&swrm->bus, swrm->status); + qcom_swrm_get_device_status(ctrl); + qcom_swrm_enumerate(&ctrl->bus); + sdw_handle_slave_status(&ctrl->bus, ctrl->status); } break; case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: - dev_err_ratelimited(swrm->dev, + dev_err_ratelimited(ctrl->dev, "%s: SWR bus clsh detected\n", __func__); - swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; - swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); + ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; + ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); - dev_err_ratelimited(swrm->dev, + ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO overflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); - dev_err_ratelimited(swrm->dev, + ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO underflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); - dev_err(swrm->dev, + ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + dev_err(ctrl->dev, "%s: SWR write FIFO overflow fifo status %x\n", __func__, value); - swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR: - swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); - dev_err_ratelimited(swrm->dev, + ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + dev_err_ratelimited(ctrl->dev, "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", __func__, value); - swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: - dev_err_ratelimited(swrm->dev, + dev_err_ratelimited(ctrl->dev, "%s: SWR Port collision detected\n", __func__); - swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; - swrm->reg_write(swrm, - SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); + ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; + ctrl->reg_write(ctrl, + SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: - dev_err_ratelimited(swrm->dev, + dev_err_ratelimited(ctrl->dev, "%s: SWR read enable valid mismatch\n", __func__); - swrm->intr_mask &= + ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; - swrm->reg_write(swrm, - SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); + ctrl->reg_write(ctrl, + SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: - complete(&swrm->broadcast); + complete(&ctrl->broadcast); break; case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: break; @@ -657,19 +657,19 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: break; default: - dev_err_ratelimited(swrm->dev, + dev_err_ratelimited(ctrl->dev, "%s: SWR unknown interrupt value: %d\n", __func__, value); ret = IRQ_NONE; break; } } - swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); - swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); - intr_sts_masked = intr_sts & swrm->intr_mask; + ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, intr_sts); + ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts); + intr_sts_masked = intr_sts & ctrl->intr_mask; } while (intr_sts_masked);
- clk_disable_unprepare(swrm->hclk); + clk_disable_unprepare(ctrl->hclk); return ret; }
@@ -1301,23 +1301,23 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) #ifdef CONFIG_DEBUG_FS static int swrm_reg_show(struct seq_file *s_file, void *data) { - struct qcom_swrm_ctrl *swrm = s_file->private; + struct qcom_swrm_ctrl *ctrl = s_file->private; int reg, reg_val, ret;
- ret = pm_runtime_resume_and_get(swrm->dev); + ret = pm_runtime_resume_and_get(ctrl->dev); if (ret < 0 && ret != -EACCES) { - dev_err_ratelimited(swrm->dev, + dev_err_ratelimited(ctrl->dev, "pm_runtime_resume_and_get failed in %s, ret %d\n", __func__, ret); return ret; }
for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) { - swrm->reg_read(swrm, reg, ®_val); + ctrl->reg_read(ctrl, reg, ®_val); seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); } - pm_runtime_mark_last_busy(swrm->dev); - pm_runtime_put_autosuspend(swrm->dev); + pm_runtime_mark_last_busy(ctrl->dev); + pm_runtime_put_autosuspend(ctrl->dev);
return 0; @@ -1498,13 +1498,13 @@ static int qcom_swrm_remove(struct platform_device *pdev) return 0; }
-static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) +static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) { int retry = SWRM_LINK_STATUS_RETRY_CNT; int comp_sts;
do { - swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts); + ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts);
if (comp_sts & SWRM_FRM_GEN_ENABLED) return true; @@ -1512,7 +1512,7 @@ static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) usleep_range(500, 510); } while (retry--);
- dev_err(swrm->dev, "%s: link status not %s\n", __func__, + dev_err(ctrl->dev, "%s: link status not %s\n", __func__, comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
return false;
On 3.04.2023 15:25, Krzysztof Kozlowski wrote:
The pointer to 'struct qcom_swrm_ctrl' was called sometimes 'swrm' and sometimes 'ctrl' variable. Choose one - 'ctrl' - so the code will be consistent and easier to read.
No functional change.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org
Konrad
drivers/soundwire/qcom.c | 168 +++++++++++++++++++-------------------- 1 file changed, 84 insertions(+), 84 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index faa091e7472a..00522de47b6f 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -279,14 +279,14 @@ static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, return val; }
-static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) +static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) { u32 fifo_outstanding_data, value; int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
do { /* Check for fifo underflow during read */
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
/* Check if read data is available in read fifo */
@@ -297,39 +297,39 @@ static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) } while (fifo_retry_count--);
if (fifo_outstanding_data == 0) {
dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);return -EIO; }
return 0;
}
-static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm) +static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) { u32 fifo_outstanding_cmds, value; int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
do { /* Check for fifo overflow during write */
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
/* Check for space in write fifo before writing */
if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) return 0;usleep_range(500, 510); } while (fifo_retry_count--);
- if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);return -EIO; }
return 0;
}
-static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, +static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, u8 dev_addr, u16 reg_addr) {
@@ -342,20 +342,20 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, val = swrm_get_packed_reg_val(&cmd_id, cmd_data, dev_addr, reg_addr); } else {
val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, dev_addr, reg_addr);
- if (swrm_wait_for_wr_fifo_avail(swrm))
if (swrm_wait_for_wr_fifo_avail(ctrl)) return SDW_CMD_FAIL_OTHER;
if (cmd_id == SWR_BROADCAST_CMD_ID)
reinit_completion(&swrm->broadcast);
reinit_completion(&ctrl->broadcast);/* Its assumed that write is okay as we do not get any status back */
- swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
- ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
- if (swrm->version <= SWRM_VERSION_1_3_0)
if (ctrl->version <= SWRM_VERSION_1_3_0) usleep_range(150, 155);
if (cmd_id == SWR_BROADCAST_CMD_ID) {
@@ -363,7 +363,7 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, * sleep for 10ms for MSM soundwire variant to allow broadcast * command to complete. */
ret = wait_for_completion_timeout(&swrm->broadcast,
ret = wait_for_completion_timeout(&ctrl->broadcast, msecs_to_jiffies(TIMEOUT_MS));@@ -376,41 +376,41 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, return ret; }
-static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm, +static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, u8 dev_addr, u16 reg_addr, u32 len, u8 *rval) { u32 cmd_data, cmd_id, val, retry_attempt = 0;
- val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
/*
- Check for outstanding cmd wrt. write fifo depth to avoid
- overflow as read will also increase write fifo cnt.
*/
- swrm_wait_for_wr_fifo_avail(swrm);
swrm_wait_for_wr_fifo_avail(ctrl);
/* wait for FIFO RD to complete to avoid overflow */ usleep_range(100, 105);
- swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
- ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val); /* wait for FIFO RD CMD complete to avoid overflow */ usleep_range(250, 255);
- if (swrm_wait_for_rd_fifo_avail(swrm))
if (swrm_wait_for_rd_fifo_avail(ctrl)) return SDW_CMD_FAIL_OTHER;
do {
swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
if (cmd_id != swrm->rcmd_id) {
if (cmd_id != ctrl->rcmd_id) { if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { /* wait 500 us before retry on fifo read failure */ usleep_range(500, 505);
swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, SWRM_CMD_FIFO_FLUSH);
swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val); } retry_attempt++;@@ -419,9 +419,9 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
} while (retry_attempt < MAX_FIFO_RD_RETRY);
- dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
- dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ dev_num: 0x%x, cmd_data: 0x%x\n",
reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);return SDW_CMD_IGNORED;
} @@ -533,39 +533,39 @@ static int qcom_swrm_enumerate(struct sdw_bus *bus)
static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) {
- struct qcom_swrm_ctrl *swrm = dev_id;
- struct qcom_swrm_ctrl *ctrl = dev_id; int ret;
- ret = pm_runtime_resume_and_get(swrm->dev);
- ret = pm_runtime_resume_and_get(ctrl->dev); if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "pm_runtime_resume_and_get failed in %s, ret %d\n", __func__, ret);
- if (swrm->wake_irq > 0) {
if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq)))disable_irq_nosync(swrm->wake_irq);
- if (ctrl->wake_irq > 0) {
if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))disable_irq_nosync(ctrl->wake_irq);
- pm_runtime_mark_last_busy(swrm->dev);
- pm_runtime_put_autosuspend(swrm->dev);
pm_runtime_mark_last_busy(ctrl->dev);
pm_runtime_put_autosuspend(ctrl->dev);
return IRQ_HANDLED;
}
static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) {
- struct qcom_swrm_ctrl *swrm = dev_id;
- struct qcom_swrm_ctrl *ctrl = dev_id; u32 value, intr_sts, intr_sts_masked, slave_status; u32 i; int devnum; int ret = IRQ_HANDLED;
- clk_prepare_enable(swrm->hclk);
- clk_prepare_enable(ctrl->hclk);
- swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
- intr_sts_masked = intr_sts & swrm->intr_mask;
ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts);
intr_sts_masked = intr_sts & ctrl->intr_mask;
do { for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
@@ -575,80 +575,80 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
switch (value) { case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); if (devnum < 0) {
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "no slave alert found.spurious interrupt\n"); } else {
sdw_handle_slave_status(&swrm->bus, swrm->status);
sdw_handle_slave_status(&ctrl->bus, ctrl->status); } break; case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n");swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);if (swrm->slave_status == slave_status) {dev_dbg(swrm->dev, "Slave status not changed %x\n",
dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);if (ctrl->slave_status == slave_status) {dev_dbg(ctrl->dev, "Slave status not changed %x\n", slave_status); } else {
qcom_swrm_get_device_status(swrm);qcom_swrm_enumerate(&swrm->bus);sdw_handle_slave_status(&swrm->bus, swrm->status);
qcom_swrm_get_device_status(ctrl);qcom_swrm_enumerate(&ctrl->bus);sdw_handle_slave_status(&ctrl->bus, ctrl->status); } break; case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "%s: SWR bus clsh detected\n", __func__);
swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(swrm->dev,
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO overflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(swrm->dev,
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO underflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);dev_err(swrm->dev,
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);dev_err(ctrl->dev, "%s: SWR write FIFO overflow fifo status %x\n", __func__, value);
swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR:
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(swrm->dev,
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(ctrl->dev, "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", __func__, value);
swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "%s: SWR Port collision detected\n", __func__);
swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;swrm->reg_write(swrm,SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;ctrl->reg_write(ctrl,SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "%s: SWR read enable valid mismatch\n", __func__);
swrm->intr_mask &=
ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
swrm->reg_write(swrm,SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
ctrl->reg_write(ctrl,SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
complete(&swrm->broadcast);
complete(&ctrl->broadcast); break; case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: break;@@ -657,19 +657,19 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: break; default:
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "%s: SWR unknown interrupt value: %d\n", __func__, value); ret = IRQ_NONE; break; }
swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);intr_sts_masked = intr_sts & swrm->intr_mask;
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, intr_sts);ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts);intr_sts_masked = intr_sts & ctrl->intr_mask;
- clk_disable_unprepare(swrm->hclk);
- clk_disable_unprepare(ctrl->hclk); return ret;
}
@@ -1301,23 +1301,23 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) #ifdef CONFIG_DEBUG_FS static int swrm_reg_show(struct seq_file *s_file, void *data) {
- struct qcom_swrm_ctrl *swrm = s_file->private;
- struct qcom_swrm_ctrl *ctrl = s_file->private; int reg, reg_val, ret;
- ret = pm_runtime_resume_and_get(swrm->dev);
- ret = pm_runtime_resume_and_get(ctrl->dev); if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "pm_runtime_resume_and_get failed in %s, ret %d\n", __func__, ret);return ret; }
for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
swrm->reg_read(swrm, reg, ®_val);
ctrl->reg_read(ctrl, reg, ®_val);
- pm_runtime_mark_last_busy(swrm->dev);
- pm_runtime_put_autosuspend(swrm->dev);
pm_runtime_mark_last_busy(ctrl->dev);
pm_runtime_put_autosuspend(ctrl->dev);
return 0;
@@ -1498,13 +1498,13 @@ static int qcom_swrm_remove(struct platform_device *pdev) return 0; }
-static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) +static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) { int retry = SWRM_LINK_STATUS_RETRY_CNT; int comp_sts;
do {
swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts);if (comp_sts & SWRM_FRM_GEN_ENABLED) return true;
@@ -1512,7 +1512,7 @@ static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) usleep_range(500, 510); } while (retry--);
- dev_err(swrm->dev, "%s: link status not %s\n", __func__,
dev_err(ctrl->dev, "%s: link status not %s\n", __func__, comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
return false;
On 03/04/2023 14:25, Krzysztof Kozlowski wrote:
The pointer to 'struct qcom_swrm_ctrl' was called sometimes 'swrm' and sometimes 'ctrl' variable. Choose one - 'ctrl' - so the code will be consistent and easier to read.
No functional change.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Reviewed-by: Srinivas Kandagagatla srinivas.kandagatla@linaro.org Tested-by: Srinivas Kandagagatla srinivas.kandagatla@linaro.org
--srini
drivers/soundwire/qcom.c | 168 +++++++++++++++++++-------------------- 1 file changed, 84 insertions(+), 84 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index faa091e7472a..00522de47b6f 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -279,14 +279,14 @@ static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, return val; }
-static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) +static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) { u32 fifo_outstanding_data, value; int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
do { /* Check for fifo underflow during read */
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
/* Check if read data is available in read fifo */
@@ -297,39 +297,39 @@ static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) } while (fifo_retry_count--);
if (fifo_outstanding_data == 0) {
dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);return -EIO; }
return 0; }
-static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm) +static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) { u32 fifo_outstanding_cmds, value; int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
do { /* Check for fifo overflow during write */
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
/* Check for space in write fifo before writing */
if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) return 0;usleep_range(500, 510); } while (fifo_retry_count--);
- if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);return -EIO; }
return 0; }
-static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, +static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, u8 dev_addr, u16 reg_addr) {
@@ -342,20 +342,20 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, val = swrm_get_packed_reg_val(&cmd_id, cmd_data, dev_addr, reg_addr); } else {
val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, dev_addr, reg_addr);
- if (swrm_wait_for_wr_fifo_avail(swrm))
if (swrm_wait_for_wr_fifo_avail(ctrl)) return SDW_CMD_FAIL_OTHER;
if (cmd_id == SWR_BROADCAST_CMD_ID)
reinit_completion(&swrm->broadcast);
reinit_completion(&ctrl->broadcast);/* Its assumed that write is okay as we do not get any status back */
- swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
- ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
- if (swrm->version <= SWRM_VERSION_1_3_0)
if (ctrl->version <= SWRM_VERSION_1_3_0) usleep_range(150, 155);
if (cmd_id == SWR_BROADCAST_CMD_ID) {
@@ -363,7 +363,7 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, * sleep for 10ms for MSM soundwire variant to allow broadcast * command to complete. */
ret = wait_for_completion_timeout(&swrm->broadcast,
ret = wait_for_completion_timeout(&ctrl->broadcast, msecs_to_jiffies(TIMEOUT_MS));@@ -376,41 +376,41 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, return ret; }
-static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm, +static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, u8 dev_addr, u16 reg_addr, u32 len, u8 *rval) { u32 cmd_data, cmd_id, val, retry_attempt = 0;
- val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
/*
- Check for outstanding cmd wrt. write fifo depth to avoid
- overflow as read will also increase write fifo cnt.
*/
- swrm_wait_for_wr_fifo_avail(swrm);
swrm_wait_for_wr_fifo_avail(ctrl);
/* wait for FIFO RD to complete to avoid overflow */ usleep_range(100, 105);
- swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
- ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val); /* wait for FIFO RD CMD complete to avoid overflow */ usleep_range(250, 255);
- if (swrm_wait_for_rd_fifo_avail(swrm))
if (swrm_wait_for_rd_fifo_avail(ctrl)) return SDW_CMD_FAIL_OTHER;
do {
swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
if (cmd_id != swrm->rcmd_id) {
if (cmd_id != ctrl->rcmd_id) { if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { /* wait 500 us before retry on fifo read failure */ usleep_range(500, 505);
swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, SWRM_CMD_FIFO_FLUSH);
swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val); } retry_attempt++;@@ -419,9 +419,9 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
} while (retry_attempt < MAX_FIFO_RD_RETRY);
- dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
- dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ dev_num: 0x%x, cmd_data: 0x%x\n",
reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);return SDW_CMD_IGNORED; }
@@ -533,39 +533,39 @@ static int qcom_swrm_enumerate(struct sdw_bus *bus)
static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) {
- struct qcom_swrm_ctrl *swrm = dev_id;
- struct qcom_swrm_ctrl *ctrl = dev_id; int ret;
- ret = pm_runtime_resume_and_get(swrm->dev);
- ret = pm_runtime_resume_and_get(ctrl->dev); if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "pm_runtime_resume_and_get failed in %s, ret %d\n", __func__, ret);
- if (swrm->wake_irq > 0) {
if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq)))disable_irq_nosync(swrm->wake_irq);
- if (ctrl->wake_irq > 0) {
if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))disable_irq_nosync(ctrl->wake_irq);
- pm_runtime_mark_last_busy(swrm->dev);
- pm_runtime_put_autosuspend(swrm->dev);
pm_runtime_mark_last_busy(ctrl->dev);
pm_runtime_put_autosuspend(ctrl->dev);
return IRQ_HANDLED; }
static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) {
- struct qcom_swrm_ctrl *swrm = dev_id;
- struct qcom_swrm_ctrl *ctrl = dev_id; u32 value, intr_sts, intr_sts_masked, slave_status; u32 i; int devnum; int ret = IRQ_HANDLED;
- clk_prepare_enable(swrm->hclk);
- clk_prepare_enable(ctrl->hclk);
- swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
- intr_sts_masked = intr_sts & swrm->intr_mask;
ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts);
intr_sts_masked = intr_sts & ctrl->intr_mask;
do { for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
@@ -575,80 +575,80 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
switch (value) { case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); if (devnum < 0) {
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "no slave alert found.spurious interrupt\n"); } else {
sdw_handle_slave_status(&swrm->bus, swrm->status);
sdw_handle_slave_status(&ctrl->bus, ctrl->status); } break; case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n");swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);if (swrm->slave_status == slave_status) {dev_dbg(swrm->dev, "Slave status not changed %x\n",
dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);if (ctrl->slave_status == slave_status) {dev_dbg(ctrl->dev, "Slave status not changed %x\n", slave_status); } else {
qcom_swrm_get_device_status(swrm);qcom_swrm_enumerate(&swrm->bus);sdw_handle_slave_status(&swrm->bus, swrm->status);
qcom_swrm_get_device_status(ctrl);qcom_swrm_enumerate(&ctrl->bus);sdw_handle_slave_status(&ctrl->bus, ctrl->status); } break; case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "%s: SWR bus clsh detected\n", __func__);
swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(swrm->dev,
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO overflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(swrm->dev,
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO underflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);dev_err(swrm->dev,
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);dev_err(ctrl->dev, "%s: SWR write FIFO overflow fifo status %x\n", __func__, value);
swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR:
swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(swrm->dev,
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);dev_err_ratelimited(ctrl->dev, "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", __func__, value);
swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "%s: SWR Port collision detected\n", __func__);
swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;swrm->reg_write(swrm,SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;ctrl->reg_write(ctrl,SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "%s: SWR read enable valid mismatch\n", __func__);
swrm->intr_mask &=
ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
swrm->reg_write(swrm,SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
ctrl->reg_write(ctrl,SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
complete(&swrm->broadcast);
complete(&ctrl->broadcast); break; case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: break;@@ -657,19 +657,19 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: break; default:
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "%s: SWR unknown interrupt value: %d\n", __func__, value); ret = IRQ_NONE; break; }
swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);intr_sts_masked = intr_sts & swrm->intr_mask;
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, intr_sts);ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts);intr_sts_masked = intr_sts & ctrl->intr_mask;
- clk_disable_unprepare(swrm->hclk);
- clk_disable_unprepare(ctrl->hclk); return ret; }
@@ -1301,23 +1301,23 @@ static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) #ifdef CONFIG_DEBUG_FS static int swrm_reg_show(struct seq_file *s_file, void *data) {
- struct qcom_swrm_ctrl *swrm = s_file->private;
- struct qcom_swrm_ctrl *ctrl = s_file->private; int reg, reg_val, ret;
- ret = pm_runtime_resume_and_get(swrm->dev);
- ret = pm_runtime_resume_and_get(ctrl->dev); if (ret < 0 && ret != -EACCES) {
dev_err_ratelimited(swrm->dev,
dev_err_ratelimited(ctrl->dev, "pm_runtime_resume_and_get failed in %s, ret %d\n", __func__, ret);return ret; }
for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
swrm->reg_read(swrm, reg, ®_val);
ctrl->reg_read(ctrl, reg, ®_val);
- pm_runtime_mark_last_busy(swrm->dev);
- pm_runtime_put_autosuspend(swrm->dev);
pm_runtime_mark_last_busy(ctrl->dev);
pm_runtime_put_autosuspend(ctrl->dev);
return 0;
@@ -1498,13 +1498,13 @@ static int qcom_swrm_remove(struct platform_device *pdev) return 0; }
-static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) +static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) { int retry = SWRM_LINK_STATUS_RETRY_CNT; int comp_sts;
do {
swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts);if (comp_sts & SWRM_FRM_GEN_ENABLED) return true;
@@ -1512,7 +1512,7 @@ static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) usleep_range(500, 510); } while (retry--);
- dev_err(swrm->dev, "%s: link status not %s\n", __func__,
dev_err(ctrl->dev, "%s: link status not %s\n", __func__, comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
return false;
Currently the driver supports Qualcomm Soundwire controller versions from v1.3 till v1.7 which mostly have same register layout. With coming Qualcomm Soundwire v2.0, several registers were moved and changed, thus a different register layout will have to be supported.
Prepare for this by: 1. Renaming few register defines to indicate v1.3 (earliest supported) version, 2. Add a simple table for mapping register to its offset, 3. Change the code to use the mapping table.
Since only few registers differ, this solution seems easier then switching to regmap fields.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
---
Changes since v1: 1. Fix lang typo in subject. --- drivers/soundwire/qcom.c | 130 +++++++++++++++++++++++++++++---------- 1 file changed, 97 insertions(+), 33 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 00522de47b6f..b6666ffe37ae 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -41,7 +41,7 @@ #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) #define SWRM_COMP_MASTER_ID 0x104 -#define SWRM_INTERRUPT_STATUS 0x200 +#define SWRM_V1_3_INTERRUPT_STATUS 0x200 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) @@ -58,20 +58,20 @@ #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) #define SWRM_INTERRUPT_MAX 17 -#define SWRM_INTERRUPT_MASK_ADDR 0x204 -#define SWRM_INTERRUPT_CLEAR 0x208 -#define SWRM_INTERRUPT_CPU_EN 0x210 -#define SWRM_CMD_FIFO_WR_CMD 0x300 -#define SWRM_CMD_FIFO_RD_CMD 0x304 +#define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 +#define SWRM_V1_3_INTERRUPT_CLEAR 0x208 +#define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 +#define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 +#define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 #define SWRM_CMD_FIFO_CMD 0x308 #define SWRM_CMD_FIFO_FLUSH 0x1 -#define SWRM_CMD_FIFO_STATUS 0x30C +#define SWRM_V1_3_CMD_FIFO_STATUS 0x30C #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) #define SWRM_CMD_FIFO_CFG_ADDR 0x314 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) #define SWRM_RD_WR_CMD_RETRIES 0x7 -#define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318 +#define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) #define SWRM_ENUMERATOR_CFG_ADDR 0x500 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) @@ -97,7 +97,7 @@ #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) -#define SWR_MSTR_MAX_REG_ADDR (0x1740) +#define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 @@ -143,10 +143,28 @@ struct qcom_swrm_port_config { u8 lane_control; };
+/* + * Internal IDs for different register layouts. Only few registers differ per + * each variant, so the list of IDs below does not include all of registers. + */ +enum { + SWRM_REG_FRAME_GEN_ENABLED, + SWRM_REG_INTERRUPT_STATUS, + SWRM_REG_INTERRUPT_MASK_ADDR, + SWRM_REG_INTERRUPT_CLEAR, + SWRM_REG_INTERRUPT_CPU_EN, + SWRM_REG_CMD_FIFO_WR_CMD, + SWRM_REG_CMD_FIFO_RD_CMD, + SWRM_REG_CMD_FIFO_STATUS, + SWRM_REG_CMD_FIFO_RD_FIFO_ADDR, +}; + struct qcom_swrm_ctrl { struct sdw_bus bus; struct device *dev; struct regmap *regmap; + u32 max_reg; + const unsigned int *reg_layout; void __iomem *mmio; struct reset_control *audio_cgcr; #ifdef CONFIG_DEBUG_FS @@ -187,22 +205,42 @@ struct qcom_swrm_data { u32 default_cols; u32 default_rows; bool sw_clk_gate_required; + u32 max_reg; + const unsigned int *reg_layout; +}; + +static const unsigned int swrm_v1_3_reg_layout[] = { + [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS, + [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS, + [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR, + [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR, + [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN, + [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD, + [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD, + [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS, + [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR, };
static const struct qcom_swrm_data swrm_v1_3_data = { .default_rows = 48, .default_cols = 16, + .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, + .reg_layout = swrm_v1_3_reg_layout, };
static const struct qcom_swrm_data swrm_v1_5_data = { .default_rows = 50, .default_cols = 16, + .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, + .reg_layout = swrm_v1_3_reg_layout, };
static const struct qcom_swrm_data swrm_v1_6_data = { .default_rows = 50, .default_cols = 16, .sw_clk_gate_required = true, + .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, + .reg_layout = swrm_v1_3_reg_layout, };
#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) @@ -286,7 +324,8 @@ static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
do { /* Check for fifo underflow during read */ - ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], + &value); fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
/* Check if read data is available in read fifo */ @@ -311,7 +350,8 @@ static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
do { /* Check for fifo overflow during write */ - ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], + &value); fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
/* Check for space in write fifo before writing */ @@ -353,7 +393,7 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, reinit_completion(&ctrl->broadcast);
/* Its assumed that write is okay as we do not get any status back */ - ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val); + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
if (ctrl->version <= SWRM_VERSION_1_3_0) usleep_range(150, 155); @@ -392,7 +432,7 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
/* wait for FIFO RD to complete to avoid overflow */ usleep_range(100, 105); - ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val); + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); /* wait for FIFO RD CMD complete to avoid overflow */ usleep_range(250, 255);
@@ -400,7 +440,8 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, return SDW_CMD_FAIL_OTHER;
do { - ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], + &cmd_data); rval[0] = cmd_data & 0xFF; cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
@@ -410,7 +451,9 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, usleep_range(500, 505); ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, SWRM_CMD_FIFO_FLUSH); - ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val); + ctrl->reg_write(ctrl, + ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], + val); } retry_attempt++; } else { @@ -564,7 +607,8 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) int ret = IRQ_HANDLED; clk_prepare_enable(ctrl->hclk);
- ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts); + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], + &intr_sts); intr_sts_masked = intr_sts & ctrl->intr_mask;
do { @@ -602,29 +646,39 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) "%s: SWR bus clsh detected\n", __func__); ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); + ctrl->reg_write(ctrl, + ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], + ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: - ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + ctrl->reg_read(ctrl, + ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], + &value); dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO overflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: - ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + ctrl->reg_read(ctrl, + ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], + &value); dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO underflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: - ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + ctrl->reg_read(ctrl, + ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], + &value); dev_err(ctrl->dev, "%s: SWR write FIFO overflow fifo status %x\n", __func__, value); ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR: - ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + ctrl->reg_read(ctrl, + ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], + &value); dev_err_ratelimited(ctrl->dev, "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", __func__, value); @@ -636,7 +690,8 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) __func__); ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; ctrl->reg_write(ctrl, - SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); + ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], + ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: dev_err_ratelimited(ctrl->dev, @@ -645,7 +700,8 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; ctrl->reg_write(ctrl, - SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); + ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], + ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: complete(&ctrl->broadcast); @@ -664,8 +720,10 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) break; } } - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, intr_sts); - ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts); + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], + intr_sts); + ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], + &intr_sts); intr_sts_masked = intr_sts & ctrl->intr_mask; } while (intr_sts_masked);
@@ -690,7 +748,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; /* Mask soundwire interrupts */ - ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], SWRM_INTERRUPT_STATUS_RMSK);
/* Configure No pings */ @@ -723,7 +781,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
/* enable CPU IRQs */ if (ctrl->mmio) { - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], SWRM_INTERRUPT_STATUS_RMSK); } ctrl->slave_status = 0; @@ -1312,7 +1370,7 @@ static int swrm_reg_show(struct seq_file *s_file, void *data) return ret; }
- for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) { + for (reg = 0; reg <= ctrl->max_reg; reg += 4) { ctrl->reg_read(ctrl, reg, ®_val); seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); } @@ -1340,6 +1398,8 @@ static int qcom_swrm_probe(struct platform_device *pdev) return -ENOMEM;
data = of_device_get_match_data(dev); + ctrl->max_reg = data->max_reg; + ctrl->reg_layout = data->reg_layout; ctrl->rows_index = sdw_find_row_index(data->default_rows); ctrl->cols_index = sdw_find_col_index(data->default_cols); #if IS_REACHABLE(CONFIG_SLIMBUS) @@ -1556,12 +1616,14 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) } else { ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); } - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; - ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], + ctrl->intr_mask); + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], + ctrl->intr_mask);
usleep_range(100, 105); if (!swrm_wait_for_frame_gen_enabled(ctrl)) @@ -1583,8 +1645,10 @@ static int __maybe_unused swrm_runtime_suspend(struct device *dev) if (!ctrl->clock_stop_not_supported) { /* Mask bus clash interrupt */ ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; - ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); - ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], + ctrl->intr_mask); + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], + ctrl->intr_mask); /* Prepare slaves for clock stop */ ret = sdw_bus_prep_clk_stop(&ctrl->bus); if (ret < 0 && ret != -ENODATA) {
On 3.04.2023 15:25, Krzysztof Kozlowski wrote:
Currently the driver supports Qualcomm Soundwire controller versions from v1.3 till v1.7 which mostly have same register layout. With coming Qualcomm Soundwire v2.0, several registers were moved and changed, thus a different register layout will have to be supported.
Prepare for this by:
- Renaming few register defines to indicate v1.3 (earliest supported) version,
- Add a simple table for mapping register to its offset,
- Change the code to use the mapping table.
Since only few registers differ, this solution seems easier then switching to regmap fields.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org
Konrad
Changes since v1:
- Fix lang typo in subject.
drivers/soundwire/qcom.c | 130 +++++++++++++++++++++++++++++---------- 1 file changed, 97 insertions(+), 33 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 00522de47b6f..b6666ffe37ae 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -41,7 +41,7 @@ #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) #define SWRM_COMP_MASTER_ID 0x104 -#define SWRM_INTERRUPT_STATUS 0x200 +#define SWRM_V1_3_INTERRUPT_STATUS 0x200 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) @@ -58,20 +58,20 @@ #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) #define SWRM_INTERRUPT_MAX 17 -#define SWRM_INTERRUPT_MASK_ADDR 0x204 -#define SWRM_INTERRUPT_CLEAR 0x208 -#define SWRM_INTERRUPT_CPU_EN 0x210 -#define SWRM_CMD_FIFO_WR_CMD 0x300 -#define SWRM_CMD_FIFO_RD_CMD 0x304 +#define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 +#define SWRM_V1_3_INTERRUPT_CLEAR 0x208 +#define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 +#define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 +#define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 #define SWRM_CMD_FIFO_CMD 0x308 #define SWRM_CMD_FIFO_FLUSH 0x1 -#define SWRM_CMD_FIFO_STATUS 0x30C +#define SWRM_V1_3_CMD_FIFO_STATUS 0x30C #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) #define SWRM_CMD_FIFO_CFG_ADDR 0x314 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) #define SWRM_RD_WR_CMD_RETRIES 0x7 -#define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318 +#define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) #define SWRM_ENUMERATOR_CFG_ADDR 0x500 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) @@ -97,7 +97,7 @@ #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) -#define SWR_MSTR_MAX_REG_ADDR (0x1740) +#define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 @@ -143,10 +143,28 @@ struct qcom_swrm_port_config { u8 lane_control; };
+/*
- Internal IDs for different register layouts. Only few registers differ per
- each variant, so the list of IDs below does not include all of registers.
- */
+enum {
- SWRM_REG_FRAME_GEN_ENABLED,
- SWRM_REG_INTERRUPT_STATUS,
- SWRM_REG_INTERRUPT_MASK_ADDR,
- SWRM_REG_INTERRUPT_CLEAR,
- SWRM_REG_INTERRUPT_CPU_EN,
- SWRM_REG_CMD_FIFO_WR_CMD,
- SWRM_REG_CMD_FIFO_RD_CMD,
- SWRM_REG_CMD_FIFO_STATUS,
- SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
+};
struct qcom_swrm_ctrl { struct sdw_bus bus; struct device *dev; struct regmap *regmap;
- u32 max_reg;
- const unsigned int *reg_layout; void __iomem *mmio; struct reset_control *audio_cgcr;
#ifdef CONFIG_DEBUG_FS @@ -187,22 +205,42 @@ struct qcom_swrm_data { u32 default_cols; u32 default_rows; bool sw_clk_gate_required;
- u32 max_reg;
- const unsigned int *reg_layout;
+};
+static const unsigned int swrm_v1_3_reg_layout[] = {
- [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
- [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
- [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
- [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
- [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
- [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
- [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
- [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
- [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
};
static const struct qcom_swrm_data swrm_v1_3_data = { .default_rows = 48, .default_cols = 16,
- .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
- .reg_layout = swrm_v1_3_reg_layout,
};
static const struct qcom_swrm_data swrm_v1_5_data = { .default_rows = 50, .default_cols = 16,
- .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
- .reg_layout = swrm_v1_3_reg_layout,
};
static const struct qcom_swrm_data swrm_v1_6_data = { .default_rows = 50, .default_cols = 16, .sw_clk_gate_required = true,
- .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
- .reg_layout = swrm_v1_3_reg_layout,
};
#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) @@ -286,7 +324,8 @@ static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
do { /* Check for fifo underflow during read */
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value);fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
/* Check if read data is available in read fifo */
@@ -311,7 +350,8 @@ static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
do { /* Check for fifo overflow during write */
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value);fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
/* Check for space in write fifo before writing */
@@ -353,7 +393,7 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, reinit_completion(&ctrl->broadcast);
/* Its assumed that write is okay as we do not get any status back */
- ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
if (ctrl->version <= SWRM_VERSION_1_3_0) usleep_range(150, 155);
@@ -392,7 +432,7 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
/* wait for FIFO RD to complete to avoid overflow */ usleep_range(100, 105);
- ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
- ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); /* wait for FIFO RD CMD complete to avoid overflow */ usleep_range(250, 255);
@@ -400,7 +440,8 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, return SDW_CMD_FAIL_OTHER;
do {
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],&cmd_data);@@ -410,7 +451,9 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, usleep_range(500, 505); ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, SWRM_CMD_FIFO_FLUSH);
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
ctrl->reg_write(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],val); } retry_attempt++;@@ -564,7 +607,8 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) int ret = IRQ_HANDLED; clk_prepare_enable(ctrl->hclk);
- ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts);
ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
&intr_sts);intr_sts_masked = intr_sts & ctrl->intr_mask;
do {
@@ -602,29 +646,39 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) "%s: SWR bus clsh detected\n", __func__); ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_write(ctrl,ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value); dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO overflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value); dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO underflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value); dev_err(ctrl->dev, "%s: SWR write FIFO overflow fifo status %x\n", __func__, value); ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR:
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value); dev_err_ratelimited(ctrl->dev, "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", __func__, value);@@ -636,7 +690,8 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) __func__); ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; ctrl->reg_write(ctrl,
SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: dev_err_ratelimited(ctrl->dev,@@ -645,7 +700,8 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; ctrl->reg_write(ctrl,
SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: complete(&ctrl->broadcast);@@ -664,8 +720,10 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) break; } }
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, intr_sts);ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts);
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],intr_sts);ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],&intr_sts);@@ -690,7 +748,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; /* Mask soundwire interrupts */
- ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], SWRM_INTERRUPT_STATUS_RMSK);
/* Configure No pings */
@@ -723,7 +781,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
/* enable CPU IRQs */ if (ctrl->mmio) {
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], SWRM_INTERRUPT_STATUS_RMSK);@@ -1312,7 +1370,7 @@ static int swrm_reg_show(struct seq_file *s_file, void *data) return ret; }
- for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
- for (reg = 0; reg <= ctrl->max_reg; reg += 4) { ctrl->reg_read(ctrl, reg, ®_val); seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); }
@@ -1340,6 +1398,8 @@ static int qcom_swrm_probe(struct platform_device *pdev) return -ENOMEM;
data = of_device_get_match_data(dev);
- ctrl->max_reg = data->max_reg;
- ctrl->reg_layout = data->reg_layout; ctrl->rows_index = sdw_find_row_index(data->default_rows); ctrl->cols_index = sdw_find_col_index(data->default_cols);
#if IS_REACHABLE(CONFIG_SLIMBUS) @@ -1556,12 +1616,14 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) } else { ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); }
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask);usleep_range(100, 105); if (!swrm_wait_for_frame_gen_enabled(ctrl))
@@ -1583,8 +1645,10 @@ static int __maybe_unused swrm_runtime_suspend(struct device *dev) if (!ctrl->clock_stop_not_supported) { /* Mask bus clash interrupt */ ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask);
On 03/04/2023 14:25, Krzysztof Kozlowski wrote:
Currently the driver supports Qualcomm Soundwire controller versions from v1.3 till v1.7 which mostly have same register layout. With coming Qualcomm Soundwire v2.0, several registers were moved and changed, thus a different register layout will have to be supported.
Prepare for this by:
- Renaming few register defines to indicate v1.3 (earliest supported) version,
- Add a simple table for mapping register to its offset,
- Change the code to use the mapping table.
Since only few registers differ, this solution seems easier then switching to regmap fields.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Reviewed-by: Srinivas Kandagagatla srinivas.kandagatla@linaro.org Tested-by: Srinivas Kandagagatla srinivas.kandagatla@linaro.org
tested on RB5 and SM8450 HDK.
--srini
Changes since v1:
- Fix lang typo in subject.
drivers/soundwire/qcom.c | 130 +++++++++++++++++++++++++++++---------- 1 file changed, 97 insertions(+), 33 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 00522de47b6f..b6666ffe37ae 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -41,7 +41,7 @@ #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) #define SWRM_COMP_MASTER_ID 0x104 -#define SWRM_INTERRUPT_STATUS 0x200 +#define SWRM_V1_3_INTERRUPT_STATUS 0x200 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) @@ -58,20 +58,20 @@ #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) #define SWRM_INTERRUPT_MAX 17 -#define SWRM_INTERRUPT_MASK_ADDR 0x204 -#define SWRM_INTERRUPT_CLEAR 0x208 -#define SWRM_INTERRUPT_CPU_EN 0x210 -#define SWRM_CMD_FIFO_WR_CMD 0x300 -#define SWRM_CMD_FIFO_RD_CMD 0x304 +#define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 +#define SWRM_V1_3_INTERRUPT_CLEAR 0x208 +#define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 +#define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 +#define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 #define SWRM_CMD_FIFO_CMD 0x308 #define SWRM_CMD_FIFO_FLUSH 0x1 -#define SWRM_CMD_FIFO_STATUS 0x30C +#define SWRM_V1_3_CMD_FIFO_STATUS 0x30C #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) #define SWRM_CMD_FIFO_CFG_ADDR 0x314 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) #define SWRM_RD_WR_CMD_RETRIES 0x7 -#define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318 +#define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) #define SWRM_ENUMERATOR_CFG_ADDR 0x500 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) @@ -97,7 +97,7 @@ #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) -#define SWR_MSTR_MAX_REG_ADDR (0x1740) +#define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 @@ -143,10 +143,28 @@ struct qcom_swrm_port_config { u8 lane_control; };
+/*
- Internal IDs for different register layouts. Only few registers differ per
- each variant, so the list of IDs below does not include all of registers.
- */
+enum {
- SWRM_REG_FRAME_GEN_ENABLED,
- SWRM_REG_INTERRUPT_STATUS,
- SWRM_REG_INTERRUPT_MASK_ADDR,
- SWRM_REG_INTERRUPT_CLEAR,
- SWRM_REG_INTERRUPT_CPU_EN,
- SWRM_REG_CMD_FIFO_WR_CMD,
- SWRM_REG_CMD_FIFO_RD_CMD,
- SWRM_REG_CMD_FIFO_STATUS,
- SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
+};
- struct qcom_swrm_ctrl { struct sdw_bus bus; struct device *dev; struct regmap *regmap;
- u32 max_reg;
- const unsigned int *reg_layout; void __iomem *mmio; struct reset_control *audio_cgcr; #ifdef CONFIG_DEBUG_FS
@@ -187,22 +205,42 @@ struct qcom_swrm_data { u32 default_cols; u32 default_rows; bool sw_clk_gate_required;
- u32 max_reg;
- const unsigned int *reg_layout;
+};
+static const unsigned int swrm_v1_3_reg_layout[] = {
[SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
[SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
[SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
[SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
[SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
[SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR, };
static const struct qcom_swrm_data swrm_v1_3_data = { .default_rows = 48, .default_cols = 16,
.max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
.reg_layout = swrm_v1_3_reg_layout, };
static const struct qcom_swrm_data swrm_v1_5_data = { .default_rows = 50, .default_cols = 16,
.max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
.reg_layout = swrm_v1_3_reg_layout, };
static const struct qcom_swrm_data swrm_v1_6_data = { .default_rows = 50, .default_cols = 16, .sw_clk_gate_required = true,
.max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
.reg_layout = swrm_v1_3_reg_layout, };
#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
@@ -286,7 +324,8 @@ static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
do { /* Check for fifo underflow during read */
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value);fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
/* Check if read data is available in read fifo */
@@ -311,7 +350,8 @@ static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
do { /* Check for fifo overflow during write */
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value);fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
/* Check for space in write fifo before writing */
@@ -353,7 +393,7 @@ static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, reinit_completion(&ctrl->broadcast);
/* Its assumed that write is okay as we do not get any status back */
- ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
if (ctrl->version <= SWRM_VERSION_1_3_0) usleep_range(150, 155);
@@ -392,7 +432,7 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
/* wait for FIFO RD to complete to avoid overflow */ usleep_range(100, 105);
- ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
- ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); /* wait for FIFO RD CMD complete to avoid overflow */ usleep_range(250, 255);
@@ -400,7 +440,8 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, return SDW_CMD_FAIL_OTHER;
do {
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],&cmd_data);@@ -410,7 +451,9 @@ static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, usleep_range(500, 505); ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, SWRM_CMD_FIFO_FLUSH);
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
ctrl->reg_write(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],val); } retry_attempt++;@@ -564,7 +607,8 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) int ret = IRQ_HANDLED; clk_prepare_enable(ctrl->hclk);
- ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts);
ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
&intr_sts);intr_sts_masked = intr_sts & ctrl->intr_mask;
do {
@@ -602,29 +646,39 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) "%s: SWR bus clsh detected\n", __func__); ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_write(ctrl,ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value); dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO overflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value); dev_err_ratelimited(ctrl->dev, "%s: SWR read FIFO underflow fifo status 0x%x\n", __func__, value); break; case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value); dev_err(ctrl->dev, "%s: SWR write FIFO overflow fifo status %x\n", __func__, value); ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR:
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
ctrl->reg_read(ctrl,ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],&value); dev_err_ratelimited(ctrl->dev, "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", __func__, value);@@ -636,7 +690,8 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) __func__); ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; ctrl->reg_write(ctrl,
SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: dev_err_ratelimited(ctrl->dev,@@ -645,7 +700,8 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; ctrl->reg_write(ctrl,
SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask); break; case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: complete(&ctrl->broadcast);@@ -664,8 +720,10 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) break; } }
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, intr_sts);ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &intr_sts);
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],intr_sts);ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],&intr_sts);@@ -690,7 +748,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; /* Mask soundwire interrupts */
- ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], SWRM_INTERRUPT_STATUS_RMSK);
/* Configure No pings */
@@ -723,7 +781,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
/* enable CPU IRQs */ if (ctrl->mmio) {
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], SWRM_INTERRUPT_STATUS_RMSK);@@ -1312,7 +1370,7 @@ static int swrm_reg_show(struct seq_file *s_file, void *data) return ret; }
- for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
- for (reg = 0; reg <= ctrl->max_reg; reg += 4) { ctrl->reg_read(ctrl, reg, ®_val); seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); }
@@ -1340,6 +1398,8 @@ static int qcom_swrm_probe(struct platform_device *pdev) return -ENOMEM;
data = of_device_get_match_data(dev);
- ctrl->max_reg = data->max_reg;
- ctrl->reg_layout = data->reg_layout; ctrl->rows_index = sdw_find_row_index(data->default_rows); ctrl->cols_index = sdw_find_col_index(data->default_cols); #if IS_REACHABLE(CONFIG_SLIMBUS)
@@ -1556,12 +1616,14 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) } else { ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); }
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask);usleep_range(100, 105); if (!swrm_wait_for_frame_gen_enabled(ctrl))
@@ -1583,8 +1645,10 @@ static int __maybe_unused swrm_runtime_suspend(struct device *dev) if (!ctrl->clock_stop_not_supported) { /* Mask bus clash interrupt */ ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],ctrl->intr_mask);
Add support for Qualcomm Soundwire Controller with a bit different register layout.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- drivers/soundwire/qcom.c | 65 +++++++++++++++++++++++++++++++++++----- 1 file changed, 57 insertions(+), 8 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index b6666ffe37ae..f2e1135ef113 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -31,6 +31,7 @@ #define SWRM_VERSION_1_3_0 0x01030000 #define SWRM_VERSION_1_5_1 0x01050001 #define SWRM_VERSION_1_7_0 0x01070000 +#define SWRM_VERSION_2_0_0 0x02000000 #define SWRM_COMP_HW_VERSION 0x00 #define SWRM_COMP_CFG_ADDR 0x04 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) @@ -42,6 +43,7 @@ #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) #define SWRM_COMP_MASTER_ID 0x104 #define SWRM_V1_3_INTERRUPT_STATUS 0x200 +#define SWRM_V2_0_INTERRUPT_STATUS 0x5000 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) @@ -54,24 +56,32 @@ #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) +#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) +#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) #define SWRM_INTERRUPT_MAX 17 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 +#define SWRM_V2_0_INTERRUPT_CLEAR 0x5008 #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 +#define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004 #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 +#define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020 #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 +#define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024 #define SWRM_CMD_FIFO_CMD 0x308 #define SWRM_CMD_FIFO_FLUSH 0x1 #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C +#define SWRM_V2_0_CMD_FIFO_STATUS 0x5050 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) #define SWRM_CMD_FIFO_CFG_ADDR 0x314 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) #define SWRM_RD_WR_CMD_RETRIES 0x7 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 +#define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) #define SWRM_ENUMERATOR_CFG_ADDR 0x500 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) @@ -98,6 +108,11 @@ #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740 +#define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac + +#define SWRM_V2_0_CLK_CTRL 0x5060 +#define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0) +#define SWRM_V2_0_LINK_STATUS 0x5064
#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 @@ -243,6 +258,26 @@ static const struct qcom_swrm_data swrm_v1_6_data = { .reg_layout = swrm_v1_3_reg_layout, };
+static const unsigned int swrm_v2_0_reg_layout[] = { + [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS, + [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS, + [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */ + [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR, + [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN, + [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD, + [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD, + [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS, + [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR, +}; + +static const struct qcom_swrm_data swrm_v2_0_data = { + .default_rows = 50, + .default_cols = 16, + .sw_clk_gate_required = true, + .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR, + .reg_layout = swrm_v2_0_reg_layout, +}; + #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, @@ -748,18 +783,23 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; /* Mask soundwire interrupts */ - ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], - SWRM_INTERRUPT_STATUS_RMSK); + if (ctrl->version < SWRM_VERSION_2_0_0) + ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], + SWRM_INTERRUPT_STATUS_RMSK);
/* Configure No pings */ ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
- if (ctrl->version >= SWRM_VERSION_1_7_0) { + if (ctrl->version == SWRM_VERSION_1_7_0) { ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); + } else if (ctrl->version >= SWRM_VERSION_2_0_0) { + ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); + ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, + SWRM_V2_0_CLK_CTRL_CLK_START); } else { ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); } @@ -1609,10 +1649,14 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) } else { reset_control_reset(ctrl->audio_cgcr);
- if (ctrl->version >= SWRM_VERSION_1_7_0) { + if (ctrl->version == SWRM_VERSION_1_7_0) { ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); + } else if (ctrl->version >= SWRM_VERSION_2_0_0) { + ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); + ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, + SWRM_V2_0_CLK_CTRL_CLK_START); } else { ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); } @@ -1620,8 +1664,10 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; - ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], - ctrl->intr_mask); + if (ctrl->version < SWRM_VERSION_2_0_0) + ctrl->reg_write(ctrl, + ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], + ctrl->intr_mask); ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], ctrl->intr_mask);
@@ -1645,8 +1691,10 @@ static int __maybe_unused swrm_runtime_suspend(struct device *dev) if (!ctrl->clock_stop_not_supported) { /* Mask bus clash interrupt */ ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; - ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], - ctrl->intr_mask); + if (ctrl->version < SWRM_VERSION_2_0_0) + ctrl->reg_write(ctrl, + ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], + ctrl->intr_mask); ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], ctrl->intr_mask); /* Prepare slaves for clock stop */ @@ -1684,6 +1732,7 @@ static const struct of_device_id qcom_swrm_of_match[] = { { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data }, + { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data }, {/* sentinel */}, };
On 3.04.2023 15:25, Krzysztof Kozlowski wrote:
Add support for Qualcomm Soundwire Controller with a bit different register layout.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org
Konrad
drivers/soundwire/qcom.c | 65 +++++++++++++++++++++++++++++++++++----- 1 file changed, 57 insertions(+), 8 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index b6666ffe37ae..f2e1135ef113 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -31,6 +31,7 @@ #define SWRM_VERSION_1_3_0 0x01030000 #define SWRM_VERSION_1_5_1 0x01050001 #define SWRM_VERSION_1_7_0 0x01070000 +#define SWRM_VERSION_2_0_0 0x02000000 #define SWRM_COMP_HW_VERSION 0x00 #define SWRM_COMP_CFG_ADDR 0x04 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) @@ -42,6 +43,7 @@ #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) #define SWRM_COMP_MASTER_ID 0x104 #define SWRM_V1_3_INTERRUPT_STATUS 0x200 +#define SWRM_V2_0_INTERRUPT_STATUS 0x5000 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) @@ -54,24 +56,32 @@ #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) +#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) +#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) #define SWRM_INTERRUPT_MAX 17 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 +#define SWRM_V2_0_INTERRUPT_CLEAR 0x5008 #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 +#define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004 #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 +#define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020 #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 +#define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024 #define SWRM_CMD_FIFO_CMD 0x308 #define SWRM_CMD_FIFO_FLUSH 0x1 #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C +#define SWRM_V2_0_CMD_FIFO_STATUS 0x5050 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) #define SWRM_CMD_FIFO_CFG_ADDR 0x314 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) #define SWRM_RD_WR_CMD_RETRIES 0x7 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 +#define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) #define SWRM_ENUMERATOR_CFG_ADDR 0x500 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) @@ -98,6 +108,11 @@ #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740 +#define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
+#define SWRM_V2_0_CLK_CTRL 0x5060 +#define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0) +#define SWRM_V2_0_LINK_STATUS 0x5064
#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 @@ -243,6 +258,26 @@ static const struct qcom_swrm_data swrm_v1_6_data = { .reg_layout = swrm_v1_3_reg_layout, };
+static const unsigned int swrm_v2_0_reg_layout[] = {
- [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
- [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
- [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
- [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
- [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
- [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
- [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
- [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
- [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
+};
+static const struct qcom_swrm_data swrm_v2_0_data = {
- .default_rows = 50,
- .default_cols = 16,
- .sw_clk_gate_required = true,
- .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
- .reg_layout = swrm_v2_0_reg_layout,
+};
#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, @@ -748,18 +783,23 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; /* Mask soundwire interrupts */
- ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
SWRM_INTERRUPT_STATUS_RMSK);
if (ctrl->version < SWRM_VERSION_2_0_0)
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],SWRM_INTERRUPT_STATUS_RMSK);/* Configure No pings */ ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
- if (ctrl->version >= SWRM_VERSION_1_7_0) {
- if (ctrl->version == SWRM_VERSION_1_7_0) { ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
- } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,SWRM_V2_0_CLK_CTRL_CLK_START);@@ -1609,10 +1649,14 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) } else { reset_control_reset(ctrl->audio_cgcr);
if (ctrl->version >= SWRM_VERSION_1_7_0) {
if (ctrl->version == SWRM_VERSION_1_7_0) { ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);} else if (ctrl->version >= SWRM_VERSION_2_0_0) {ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,SWRM_V2_0_CLK_CTRL_CLK_START);@@ -1620,8 +1664,10 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);
if (ctrl->version < SWRM_VERSION_2_0_0)ctrl->reg_write(ctrl,ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);@@ -1645,8 +1691,10 @@ static int __maybe_unused swrm_runtime_suspend(struct device *dev) if (!ctrl->clock_stop_not_supported) { /* Mask bus clash interrupt */ ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);
if (ctrl->version < SWRM_VERSION_2_0_0)ctrl->reg_write(ctrl,ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);@@ -1684,6 +1732,7 @@ static const struct of_device_id qcom_swrm_of_match[] = { { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
- { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data }, {/* sentinel */},
};
On 03/04/2023 14:25, Krzysztof Kozlowski wrote:
Add support for Qualcomm Soundwire Controller with a bit different register layout.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
drivers/soundwire/qcom.c | 65 +++++++++++++++++++++++++++++++++++----- 1 file changed, 57 insertions(+), 8 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index b6666ffe37ae..f2e1135ef113 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -31,6 +31,7 @@ #define SWRM_VERSION_1_3_0 0x01030000 #define SWRM_VERSION_1_5_1 0x01050001 #define SWRM_VERSION_1_7_0 0x01070000 +#define SWRM_VERSION_2_0_0 0x02000000 #define SWRM_COMP_HW_VERSION 0x00 #define SWRM_COMP_CFG_ADDR 0x04 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) @@ -42,6 +43,7 @@ #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) #define SWRM_COMP_MASTER_ID 0x104 #define SWRM_V1_3_INTERRUPT_STATUS 0x200 +#define SWRM_V2_0_INTERRUPT_STATUS 0x5000 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) @@ -54,24 +56,32 @@ #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) +#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) +#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) #define SWRM_INTERRUPT_MAX 17 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 +#define SWRM_V2_0_INTERRUPT_CLEAR 0x5008 #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 +#define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004 #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 +#define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020 #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 +#define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024 #define SWRM_CMD_FIFO_CMD 0x308 #define SWRM_CMD_FIFO_FLUSH 0x1 #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C +#define SWRM_V2_0_CMD_FIFO_STATUS 0x5050 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) #define SWRM_CMD_FIFO_CFG_ADDR 0x314 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) #define SWRM_RD_WR_CMD_RETRIES 0x7 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 +#define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) #define SWRM_ENUMERATOR_CFG_ADDR 0x500 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) @@ -98,6 +108,11 @@ #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740 +#define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
+#define SWRM_V2_0_CLK_CTRL 0x5060 +#define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0) +#define SWRM_V2_0_LINK_STATUS 0x5064
#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 @@ -243,6 +258,26 @@ static const struct qcom_swrm_data swrm_v1_6_data = { .reg_layout = swrm_v1_3_reg_layout, };
+static const unsigned int swrm_v2_0_reg_layout[] = {
- [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
- [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
- [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
- [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
- [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
- [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
- [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
- [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
- [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
+};
+static const struct qcom_swrm_data swrm_v2_0_data = {
- .default_rows = 50,
- .default_cols = 16,
- .sw_clk_gate_required = true,
- .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
- .reg_layout = swrm_v2_0_reg_layout,
+};
#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
@@ -748,18 +783,23 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; /* Mask soundwire interrupts */
- ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
SWRM_INTERRUPT_STATUS_RMSK);
if (ctrl->version < SWRM_VERSION_2_0_0)
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],SWRM_INTERRUPT_STATUS_RMSK);/* Configure No pings */ ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
- if (ctrl->version >= SWRM_VERSION_1_7_0) {
- if (ctrl->version == SWRM_VERSION_1_7_0) { ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
- } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
we can move this to a proper switch case rather than if else's
--srini
ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,SWRM_V2_0_CLK_CTRL_CLK_START);@@ -1609,10 +1649,14 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) } else { reset_control_reset(ctrl->audio_cgcr);
if (ctrl->version >= SWRM_VERSION_1_7_0) {
if (ctrl->version == SWRM_VERSION_1_7_0) { ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);} else if (ctrl->version >= SWRM_VERSION_2_0_0) {ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,SWRM_V2_0_CLK_CTRL_CLK_START);@@ -1620,8 +1664,10 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev) SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);
if (ctrl->version < SWRM_VERSION_2_0_0)ctrl->reg_write(ctrl,ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);@@ -1645,8 +1691,10 @@ static int __maybe_unused swrm_runtime_suspend(struct device *dev) if (!ctrl->clock_stop_not_supported) { /* Mask bus clash interrupt */ ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);
if (ctrl->version < SWRM_VERSION_2_0_0)ctrl->reg_write(ctrl,ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],ctrl->intr_mask);@@ -1684,6 +1732,7 @@ static const struct of_device_id qcom_swrm_of_match[] = { { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
- { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data }, {/* sentinel */}, };
On 13/04/2023 13:27, Srinivas Kandagatla wrote: RM_INTERRUPT_STATUS_RMSK);
/* Configure No pings */ ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
- if (ctrl->version >= SWRM_VERSION_1_7_0) {
- if (ctrl->version == SWRM_VERSION_1_7_0) { ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
- } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
we can move this to a proper switch case rather than if else's
OK
Best regards, Krzysztof
Use consistently only tabs to indent the value in defines.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org --- drivers/soundwire/qcom.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index f2e1135ef113..77a5e4cbbe9b 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -58,9 +58,9 @@ #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) -#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) -#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) -#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) +#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) +#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) +#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) #define SWRM_INTERRUPT_MAX 17 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 @@ -125,20 +125,20 @@ #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
-#define MAX_FREQ_NUM 1 -#define TIMEOUT_MS 100 -#define QCOM_SWRM_MAX_RD_LEN 0x1 -#define QCOM_SDW_MAX_PORTS 14 -#define DEFAULT_CLK_FREQ 9600000 -#define SWRM_MAX_DAIS 0xF -#define SWR_INVALID_PARAM 0xFF -#define SWR_HSTOP_MAX_VAL 0xF -#define SWR_HSTART_MIN_VAL 0x0 -#define SWR_BROADCAST_CMD_ID 0x0F -#define SWR_MAX_CMD_ID 14 -#define MAX_FIFO_RD_RETRY 3 -#define SWR_OVERFLOW_RETRY_COUNT 30 -#define SWRM_LINK_STATUS_RETRY_CNT 100 +#define MAX_FREQ_NUM 1 +#define TIMEOUT_MS 100 +#define QCOM_SWRM_MAX_RD_LEN 0x1 +#define QCOM_SDW_MAX_PORTS 14 +#define DEFAULT_CLK_FREQ 9600000 +#define SWRM_MAX_DAIS 0xF +#define SWR_INVALID_PARAM 0xFF +#define SWR_HSTOP_MAX_VAL 0xF +#define SWR_HSTART_MIN_VAL 0x0 +#define SWR_BROADCAST_CMD_ID 0x0F +#define SWR_MAX_CMD_ID 14 +#define MAX_FIFO_RD_RETRY 3 +#define SWR_OVERFLOW_RETRY_COUNT 30 +#define SWRM_LINK_STATUS_RETRY_CNT 100
enum { MASTER_ID_WSA = 1,
On 3.04.2023 15:25, Krzysztof Kozlowski wrote:
Use consistently only tabs to indent the value in defines.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Reviewed-by: Konrad Dybcio konrad.dybcio@linaro.org
Konrad
drivers/soundwire/qcom.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index f2e1135ef113..77a5e4cbbe9b 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -58,9 +58,9 @@ #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) -#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) -#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) -#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) +#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) +#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) +#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) #define SWRM_INTERRUPT_MAX 17 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 @@ -125,20 +125,20 @@ #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
-#define MAX_FREQ_NUM 1 -#define TIMEOUT_MS 100 -#define QCOM_SWRM_MAX_RD_LEN 0x1 -#define QCOM_SDW_MAX_PORTS 14 -#define DEFAULT_CLK_FREQ 9600000 -#define SWRM_MAX_DAIS 0xF -#define SWR_INVALID_PARAM 0xFF -#define SWR_HSTOP_MAX_VAL 0xF -#define SWR_HSTART_MIN_VAL 0x0 -#define SWR_BROADCAST_CMD_ID 0x0F -#define SWR_MAX_CMD_ID 14 -#define MAX_FIFO_RD_RETRY 3 -#define SWR_OVERFLOW_RETRY_COUNT 30 -#define SWRM_LINK_STATUS_RETRY_CNT 100 +#define MAX_FREQ_NUM 1 +#define TIMEOUT_MS 100 +#define QCOM_SWRM_MAX_RD_LEN 0x1 +#define QCOM_SDW_MAX_PORTS 14 +#define DEFAULT_CLK_FREQ 9600000 +#define SWRM_MAX_DAIS 0xF +#define SWR_INVALID_PARAM 0xFF +#define SWR_HSTOP_MAX_VAL 0xF +#define SWR_HSTART_MIN_VAL 0x0 +#define SWR_BROADCAST_CMD_ID 0x0F +#define SWR_MAX_CMD_ID 14 +#define MAX_FIFO_RD_RETRY 3 +#define SWR_OVERFLOW_RETRY_COUNT 30 +#define SWRM_LINK_STATUS_RETRY_CNT 100
enum { MASTER_ID_WSA = 1,
On 03/04/2023 14:25, Krzysztof Kozlowski wrote:
Use consistently only tabs to indent the value in defines.
Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Reviewed-by: Srinivas Kandagatla srinivas.kandagatla@linaro.org
--srini
drivers/soundwire/qcom.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index f2e1135ef113..77a5e4cbbe9b 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -58,9 +58,9 @@ #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) -#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) -#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) -#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) +#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) +#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) +#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) #define SWRM_INTERRUPT_MAX 17 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 @@ -125,20 +125,20 @@ #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
-#define MAX_FREQ_NUM 1 -#define TIMEOUT_MS 100 -#define QCOM_SWRM_MAX_RD_LEN 0x1 -#define QCOM_SDW_MAX_PORTS 14 -#define DEFAULT_CLK_FREQ 9600000 -#define SWRM_MAX_DAIS 0xF -#define SWR_INVALID_PARAM 0xFF -#define SWR_HSTOP_MAX_VAL 0xF -#define SWR_HSTART_MIN_VAL 0x0 -#define SWR_BROADCAST_CMD_ID 0x0F -#define SWR_MAX_CMD_ID 14 -#define MAX_FIFO_RD_RETRY 3 -#define SWR_OVERFLOW_RETRY_COUNT 30 -#define SWRM_LINK_STATUS_RETRY_CNT 100 +#define MAX_FREQ_NUM 1 +#define TIMEOUT_MS 100 +#define QCOM_SWRM_MAX_RD_LEN 0x1 +#define QCOM_SDW_MAX_PORTS 14 +#define DEFAULT_CLK_FREQ 9600000 +#define SWRM_MAX_DAIS 0xF +#define SWR_INVALID_PARAM 0xFF +#define SWR_HSTOP_MAX_VAL 0xF +#define SWR_HSTART_MIN_VAL 0x0 +#define SWR_BROADCAST_CMD_ID 0x0F +#define SWR_MAX_CMD_ID 14 +#define MAX_FIFO_RD_RETRY 3 +#define SWR_OVERFLOW_RETRY_COUNT 30 +#define SWRM_LINK_STATUS_RETRY_CNT 100
enum { MASTER_ID_WSA = 1,
participants (4)
-
Konrad Dybcio -
Krzysztof Kozlowski -
Rob Herring -
Srinivas Kandagatla