[PATCH v2 0/2] ASoC: fsl_esai: Add support for imx8qm
Add support for imx8qm.
Shengjiu Wang (2): ASoC: fsl_esai: introduce SoC specific data ASoC: fsl_esai: Add new compatible string for imx8qm
Changes in v2 - drop the 0002 patch in v1, the dma relate limitation should be done in dma driver, or define a new DMA API for it.
.../devicetree/bindings/sound/fsl,esai.txt | 1 + sound/soc/fsl/fsl_esai.c | 46 +++++++++++++++---- 2 files changed, 38 insertions(+), 9 deletions(-)
Introduce a SoC specific data structure which contains the differences between the different SoCs. This makes it easier to support more differences without having to introduce a new if/else each time.
Signed-off-by: Shengjiu Wang shengjiu.wang@nxp.com Acked-by: Nicolin Chen nicoleotsuka@gmail.com --- sound/soc/fsl/fsl_esai.c | 46 ++++++++++++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 9 deletions(-)
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c index 84290be778f0..bac65ba7fbad 100644 --- a/sound/soc/fsl/fsl_esai.c +++ b/sound/soc/fsl/fsl_esai.c @@ -21,6 +21,17 @@ SNDRV_PCM_FMTBIT_S20_3LE | \ SNDRV_PCM_FMTBIT_S24_LE)
+/** + * fsl_esai_soc_data: soc specific data + * + * @imx: for imx platform + * @reset_at_xrun: flags for enable reset operaton + */ +struct fsl_esai_soc_data { + bool imx; + bool reset_at_xrun; +}; + /** * fsl_esai: ESAI private data * @@ -33,6 +44,7 @@ * @fsysclk: system clock source to derive HCK, SCK and FS * @spbaclk: SPBA clock (optional, depending on SoC design) * @task: tasklet to handle the reset operation + * @soc: soc specific data * @lock: spin lock between hw_reset() and trigger() * @fifo_depth: depth of tx/rx FIFO * @slot_width: width of each DAI slot @@ -44,7 +56,6 @@ * @sck_div: if using PSR/PM dividers for SCKx clock * @slave_mode: if fully using DAI slave mode * @synchronous: if using tx/rx synchronous mode - * @reset_at_xrun: flags for enable reset operaton * @name: driver name */ struct fsl_esai { @@ -57,6 +68,7 @@ struct fsl_esai { struct clk *fsysclk; struct clk *spbaclk; struct tasklet_struct task; + const struct fsl_esai_soc_data *soc; spinlock_t lock; /* Protect hw_reset and trigger */ u32 fifo_depth; u32 slot_width; @@ -70,10 +82,24 @@ struct fsl_esai { bool sck_div[2]; bool slave_mode; bool synchronous; - bool reset_at_xrun; char name[32]; };
+static struct fsl_esai_soc_data fsl_esai_vf610 = { + .imx = false, + .reset_at_xrun = true, +}; + +static struct fsl_esai_soc_data fsl_esai_imx35 = { + .imx = true, + .reset_at_xrun = true, +}; + +static struct fsl_esai_soc_data fsl_esai_imx6ull = { + .imx = true, + .reset_at_xrun = false, +}; + static irqreturn_t esai_isr(int irq, void *devid) { struct fsl_esai *esai_priv = (struct fsl_esai *)devid; @@ -85,7 +111,7 @@ static irqreturn_t esai_isr(int irq, void *devid) regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
if ((saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE)) && - esai_priv->reset_at_xrun) { + esai_priv->soc->reset_at_xrun) { dev_dbg(&pdev->dev, "reset module for xrun\n"); regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, ESAI_xCR_xEIE_MASK, 0); @@ -936,9 +962,11 @@ static int fsl_esai_probe(struct platform_device *pdev) esai_priv->pdev = pdev; snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np);
- if (of_device_is_compatible(np, "fsl,vf610-esai") || - of_device_is_compatible(np, "fsl,imx35-esai")) - esai_priv->reset_at_xrun = true; + esai_priv->soc = of_device_get_match_data(&pdev->dev); + if (!esai_priv->soc) { + dev_err(&pdev->dev, "failed to get soc data\n"); + return -ENODEV; + }
/* Get the addresses and IRQ */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1063,9 +1091,9 @@ static int fsl_esai_remove(struct platform_device *pdev) }
static const struct of_device_id fsl_esai_dt_ids[] = { - { .compatible = "fsl,imx35-esai", }, - { .compatible = "fsl,vf610-esai", }, - { .compatible = "fsl,imx6ull-esai", }, + { .compatible = "fsl,imx35-esai", .data = &fsl_esai_imx35 }, + { .compatible = "fsl,vf610-esai", .data = &fsl_esai_vf610 }, + { .compatible = "fsl,imx6ull-esai", .data = &fsl_esai_imx6ull }, {} }; MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
Add new compatible string "fsl,imx8qm-esai" in the binding document.
Signed-off-by: Shengjiu Wang shengjiu.wang@nxp.com Acked-by: Rob Herring robh@kernel.org --- Documentation/devicetree/bindings/sound/fsl,esai.txt | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt index 0e6e2166f76c..0a2480aeecf0 100644 --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt @@ -12,6 +12,7 @@ Required properties: "fsl,imx35-esai", "fsl,vf610-esai", "fsl,imx6ull-esai", + "fsl,imx8qm-esai",
- reg : Offset and length of the register set for the device.
On Fri, 15 May 2020 18:10:49 +0800, Shengjiu Wang wrote:
Add support for imx8qm.
Shengjiu Wang (2): ASoC: fsl_esai: introduce SoC specific data ASoC: fsl_esai: Add new compatible string for imx8qm
Changes in v2
- drop the 0002 patch in v1, the dma relate limitation should be done in dma driver, or define a new DMA API for it.
[...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.8
Thanks!
[1/2] ASoC: fsl_esai: introduce SoC specific data commit: 6878e75204e1d0420fd8130bad33f88053ba44de [2/2] ASoC: fsl_esai: Add new compatible string for imx8qm commit: d59628b310a77e616ce2e5857e6ede5bf96c6784
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks, Mark
participants (2)
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Mark Brown
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Shengjiu Wang