Declare base structures, registers and device routines for the catpt solution. Catpt deprecates and is a direct replacement for sound/soc/intel/haswell. Supports Lynxpoint and Wildcat Point both.

Signed-off-by: Cezary Rojewski cezary.rojewski@intel.com --- sound/soc/intel/catpt/core.h | 187 +++++++++++++++ sound/soc/intel/catpt/device.c | 376 ++++++++++++++++++++++++++++++ sound/soc/intel/catpt/registers.h | 191 +++++++++++++++ 3 files changed, 754 insertions(+) create mode 100644 sound/soc/intel/catpt/core.h create mode 100644 sound/soc/intel/catpt/device.c create mode 100644 sound/soc/intel/catpt/registers.h

diff --git a/sound/soc/intel/catpt/core.h b/sound/soc/intel/catpt/core.h new file mode 100644 index 000000000000..aa231ba9eaa9 --- /dev/null +++ b/sound/soc/intel/catpt/core.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2020 Intel Corporation. All rights reserved. + * + * Author: Cezary Rojewski cezary.rojewski@intel.com + */ + +#ifndef __SND_SOC_INTEL_CATPT_CORE_H +#define __SND_SOC_INTEL_CATPT_CORE_H + +#include <linux/dma/dw.h> +#include <linux/irqreturn.h> +#include "messages.h" +#include "registers.h" + +void catpt_sram_init(struct resource *sram, u32 start, u32 size); +void catpt_sram_free(struct resource *sram); +struct resource * +catpt_request_region(struct resource *root, resource_size_t size); + +static inline bool catpt_resource_overlapping(struct resource *r1, + struct resource *r2, + struct resource *ret) +{ + if (!resource_overlaps(r1, r2)) + return false; + ret->start = max(r1->start, r2->start); + ret->end = min(r1->end, r2->end); + return true; +} + +struct catpt_ipc_msg { + union { + u32 header; + union catpt_global_msg rsp; + }; + void *data; + size_t size; +}; + +struct catpt_ipc { + struct device *dev; + + struct catpt_ipc_msg rx; + struct catpt_fw_ready config; + u32 default_timeout; + bool ready; + + spinlock_t lock; + struct mutex mutex; + struct completion done_completion; + struct completion busy_completion; +}; + +void catpt_ipc_init(struct catpt_ipc *ipc, struct device *dev); + +struct catpt_module_type { + bool loaded; + u32 entry_point; + u32 persistent_size; + u32 scratch_size; + /* DRAM, initial module state */ + u32 state_offset; + u32 state_size; + + struct list_head node; +}; + +struct catpt_spec { + struct snd_soc_acpi_mach *machines; + u8 core_id; + u32 host_dram_offset; + u32 host_iram_offset; + u32 host_shim_offset; + u32 host_dma_offset[CATPT_DMA_COUNT]; + u32 host_ssp_offset[CATPT_SSP_COUNT]; + u32 dram_mask; + u32 iram_mask; + void (*pll_shutdown)(struct catpt_dev *cdev, bool enable); + int (*power_up)(struct catpt_dev *cdev); + int (*power_down)(struct catpt_dev *cdev); +}; + +struct catpt_dev { + struct device *dev; + struct dw_dma_chip *dmac; + struct catpt_ipc ipc; + + void __iomem *pci_ba; + void __iomem *lpe_ba; + u32 lpe_base; + int irq; + + const struct catpt_spec *spec; + struct completion fw_ready; + + struct resource dram; + struct resource iram; + struct resource *scratch; + + struct catpt_mixer_stream_info mixer; + struct catpt_module_type modules[CATPT_MODULE_COUNT]; + struct catpt_ssp_device_format devfmt[CATPT_SSP_COUNT]; + struct list_head stream_list; + spinlock_t list_lock; + struct mutex clk_mutex; + + struct catpt_dx_context dx_ctx; + void *dxbuf_vaddr; + dma_addr_t dxbuf_paddr; +}; + +int catpt_dmac_probe(struct catpt_dev *cdev); +void catpt_dmac_remove(struct catpt_dev *cdev); +struct dma_chan *catpt_dma_request_config_chan(struct catpt_dev *cdev); +int catpt_dma_memcpy_todsp(struct catpt_dev *cdev, struct dma_chan *chan, + dma_addr_t dst_addr, dma_addr_t src_addr, + size_t size); +int catpt_dma_memcpy_fromdsp(struct catpt_dev *cdev, struct dma_chan *chan, + dma_addr_t dst_addr, dma_addr_t src_addr, + size_t size); + +void lpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable); +void wpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable); +int lpt_dsp_power_up(struct catpt_dev *cdev); +int lpt_dsp_power_down(struct catpt_dev *cdev); +int wpt_dsp_power_up(struct catpt_dev *cdev); +int wpt_dsp_power_down(struct catpt_dev *cdev); +int catpt_dsp_stall(struct catpt_dev *cdev, bool stall); +void catpt_dsp_update_srampge(struct catpt_dev *cdev, struct resource *sram, + unsigned long mask); +int catpt_dsp_update_lpclock(struct catpt_dev *cdev); +irqreturn_t catpt_dsp_irq_handler(int irq, void *dev_id); +irqreturn_t catpt_dsp_irq_thread(int irq, void *dev_id); + +/* + * IPC handlers may return positive values which denote successful + * HOST <-> DSP communication yet failure to process specific request. + * Use below macro to convert returned non-zero values appropriately + */ +#define CATPT_IPC_ERROR(err) ((err < 0) ? err : -EREMOTEIO) + +int catpt_dsp_send_msg_timeout(struct catpt_dev *cdev, + struct catpt_ipc_msg request, + struct catpt_ipc_msg *reply, int timeout); +int catpt_dsp_send_msg(struct catpt_dev *cdev, struct catpt_ipc_msg request, + struct catpt_ipc_msg *reply); + +int catpt_first_boot_firmware(struct catpt_dev *cdev); +int catpt_boot_firmware(struct catpt_dev *cdev, bool restore); +int catpt_store_streams_context(struct catpt_dev *cdev, struct dma_chan *chan); +int catpt_store_module_states(struct catpt_dev *cdev, struct dma_chan *chan); +int catpt_store_memdumps(struct catpt_dev *cdev, struct dma_chan *chan); +int catpt_coredump(struct catpt_dev *cdev); + +int catpt_sysfs_create(struct catpt_dev *cdev); +void catpt_sysfs_remove(struct catpt_dev *cdev); + +#include <sound/memalloc.h> +#include <uapi/sound/asound.h> + +struct snd_pcm_substream; +struct catpt_stream_template; + +struct catpt_stream_runtime { + struct snd_pcm_substream *substream; + + struct catpt_stream_template *template; + struct catpt_stream_info info; + struct resource *persistent; + struct snd_dma_buffer pgtbl; + + bool allocated:1; + bool prepared:1; + + struct list_head node; +}; + +int catpt_register_plat_component(struct catpt_dev *cdev); +void catpt_stream_update_position(struct catpt_dev *cdev, + struct catpt_stream_runtime *stream, + struct catpt_notify_position *pos); +struct catpt_stream_runtime * +catpt_stream_find(struct catpt_dev *cdev, u8 stream_hw_id); +int catpt_arm_stream_templates(struct catpt_dev *cdev); + +#endif diff --git a/sound/soc/intel/catpt/device.c b/sound/soc/intel/catpt/device.c new file mode 100644 index 000000000000..a4a498ba3456 --- /dev/null +++ b/sound/soc/intel/catpt/device.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright(c) 2020 Intel Corporation. All rights reserved. +// +// Author: Cezary Rojewski cezary.rojewski@intel.com +// +// Special thanks to: +// Marcin Barlik marcin.barlik@intel.com +// Piotr Papierkowski piotr.papierkowski@intel.com +// +// for sharing LPT-LP and WTP-LP AudioDSP architecture expertise and +// helping backtrack its historical background +// + +#include <linux/acpi.h> +#include <linux/dma-mapping.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <sound/soc.h> +#include <sound/soc-acpi.h> +#include <sound/soc-acpi-intel-match.h> +#include "core.h" +#include "registers.h" + +#define CREATE_TRACE_POINTS +#include "trace.h" + +#ifdef CONFIG_PM +static int catpt_suspend(struct device *dev) +{ + struct catpt_dev *cdev = dev_get_drvdata(dev); + struct dma_chan *chan; + int ret; + + chan = catpt_dma_request_config_chan(cdev); + if (IS_ERR(chan)) + return PTR_ERR(chan); + + memset(&cdev->dx_ctx, 0, sizeof(cdev->dx_ctx)); + ret = catpt_ipc_enter_dxstate(cdev, CATPT_DX_STATE_D3, &cdev->dx_ctx); + if (ret) { + ret = CATPT_IPC_ERROR(ret); + goto exit; + } + + ret = catpt_dsp_stall(cdev, true); + if (ret < 0) + goto exit; + + ret = catpt_store_memdumps(cdev, chan); + if (ret < 0) { + dev_err(cdev->dev, "store memdumps failed: %d\n", ret); + goto exit; + } + + ret = catpt_store_module_states(cdev, chan); + if (ret < 0) { + dev_err(cdev->dev, "store module states failed: %d\n", ret); + goto exit; + } + + ret = catpt_store_streams_context(cdev, chan); + if (ret < 0) { + dev_err(cdev->dev, "store streams ctx failed: %d\n", ret); + goto exit; + } +exit: + dma_release_channel(chan); + if (ret < 0) + return ret; + return cdev->spec->power_down(cdev); +} + +static int catpt_resume(struct device *dev) +{ + struct catpt_dev *cdev = dev_get_drvdata(dev); + int ret, i; + + ret = cdev->spec->power_up(cdev); + if (ret < 0) + return ret; + + if (!module_is_live(dev->driver->owner)) { + dev_info(dev, "module unloading, skipping fw boot\n"); + return 0; + } + + ret = catpt_boot_firmware(cdev, true); + if (ret < 0) { + dev_err(cdev->dev, "boot firmware failed: %d\n", ret); + return ret; + } + + /* reconfigure SSP devices after dx transition */ + for (i = 0; i < CATPT_SSP_COUNT; i++) { + if (cdev->devfmt[i].iface == UINT_MAX) + continue; + + ret = catpt_ipc_set_device_format(cdev, &cdev->devfmt[i]); + if (ret) + return CATPT_IPC_ERROR(ret); + } + + return 0; +} +#endif + +#ifdef CONFIG_PM_SLEEP +static int catpt_runtime_suspend(struct device *dev) +{ + return catpt_suspend(dev); +} + +static int catpt_runtime_resume(struct device *dev) +{ + return catpt_resume(dev); +} +#endif + +static const struct dev_pm_ops catpt_dev_pm = { + SET_SYSTEM_SLEEP_PM_OPS(catpt_suspend, catpt_resume) + SET_RUNTIME_PM_OPS(catpt_runtime_suspend, catpt_runtime_resume, NULL) +}; + +/* machine board owned by CATPT is removed with this hook */ +static void board_pdev_unregister(void *data) +{ + platform_device_unregister(data); +} + +static int catpt_register_board(struct catpt_dev *cdev) +{ + const struct catpt_spec *spec = cdev->spec; + struct snd_soc_acpi_mach *mach; + struct platform_device *board; + int ret; + + mach = snd_soc_acpi_find_machine(spec->machines); + if (!mach) { + dev_info(cdev->dev, "no machines present\n"); + return 0; + } + + mach->mach_params.platform = "catpt-platform"; + board = platform_device_register_data(NULL, mach->drv_name, + PLATFORM_DEVID_NONE, + (const void *)mach, sizeof(*mach)); + if (!board) { + dev_err(cdev->dev, "board register failed\n"); + return PTR_ERR(board); + } + + ret = devm_add_action(cdev->dev, board_pdev_unregister, board); + if (ret < 0) { + platform_device_unregister(board); + return ret; + } + + return 0; +} + +static int catpt_probe_components(struct catpt_dev *cdev) +{ + int ret; + + ret = cdev->spec->power_up(cdev); + if (ret < 0) + return ret; + + ret = catpt_dmac_probe(cdev); + if (ret < 0) { + dev_err(cdev->dev, "DMAC probe failed: %d\n", ret); + goto dmac_err; + } + + ret = catpt_first_boot_firmware(cdev); + if (ret < 0) { + dev_err(cdev->dev, "first fw boot failed: %d\n", ret); + goto boot_fw_err; + } + + ret = catpt_register_plat_component(cdev); + if (ret < 0) { + dev_err(cdev->dev, "register plat comp failed: %d\n", ret); + goto boot_fw_err; + } + + ret = catpt_register_board(cdev); + if (ret < 0) { + dev_err(cdev->dev, "register board failed: %d\n", ret); + goto board_err; + } + + ret = catpt_sysfs_create(cdev); + if (ret < 0) + goto board_err; + + /* reflect actual ADSP state in pm_runtime */ + pm_runtime_set_active(cdev->dev); + + pm_runtime_set_autosuspend_delay(cdev->dev, 2000); + pm_runtime_use_autosuspend(cdev->dev); + pm_runtime_mark_last_busy(cdev->dev); + pm_runtime_enable(cdev->dev); + return 0; + +board_err: + snd_soc_unregister_component(cdev->dev); +boot_fw_err: + catpt_dmac_remove(cdev); +dmac_err: + cdev->spec->power_down(cdev); + + return ret; +} + +static void catpt_dev_init(struct catpt_dev *cdev, struct device *dev) +{ + cdev->dev = dev; + init_completion(&cdev->fw_ready); + INIT_LIST_HEAD(&cdev->stream_list); + spin_lock_init(&cdev->list_lock); + mutex_init(&cdev->clk_mutex); + /* + * Mark both device formats as uninitialized. Once corresponding + * cpu_dai's pcm is created, proper values are assigned + */ + cdev->devfmt[CATPT_SSP_IFACE_0].iface = UINT_MAX; + cdev->devfmt[CATPT_SSP_IFACE_1].iface = UINT_MAX; + + catpt_ipc_init(&cdev->ipc, dev); + + catpt_sram_init(&cdev->dram, cdev->spec->host_dram_offset, + catpt_dram_size(cdev)); + catpt_sram_init(&cdev->iram, cdev->spec->host_iram_offset, + catpt_iram_size(cdev)); +} + +static int catpt_acpi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct catpt_dev *cdev; + struct resource *res; + int ret; + + cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); + if (!cdev) + return -ENOMEM; + + cdev->spec = device_get_match_data(dev); + if (!cdev->spec) + return -ENODEV; + + catpt_dev_init(cdev, dev); + + /* map DSP bar address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + cdev->lpe_ba = devm_ioremap(dev, res->start, resource_size(res)); + if (!cdev->lpe_ba) + return -EIO; + cdev->lpe_base = res->start; + + /* map PCI bar address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return -ENODEV; + cdev->pci_ba = devm_ioremap(dev, res->start, resource_size(res)); + if (!cdev->pci_ba) + return -EIO; + + /* alloc buffer for storing DRAM context during dx transitions */ + cdev->dxbuf_vaddr = dma_alloc_coherent(dev, catpt_dram_size(cdev), + &cdev->dxbuf_paddr, GFP_KERNEL); + if (!cdev->dxbuf_vaddr) + return -ENOMEM; + + ret = platform_get_irq(pdev, 0); + if (ret < 0) + goto irq_err; + cdev->irq = ret; + + platform_set_drvdata(pdev, cdev); + + ret = devm_request_threaded_irq(dev, cdev->irq, catpt_dsp_irq_handler, + catpt_dsp_irq_thread, + IRQF_SHARED, "AudioDSP", cdev); + if (ret < 0) + goto irq_err; + + ret = catpt_probe_components(cdev); + if (ret < 0) + goto irq_err; + return 0; + +irq_err: + dma_free_coherent(cdev->dev, catpt_dram_size(cdev), + cdev->dxbuf_vaddr, cdev->dxbuf_paddr); + + return ret; +} + +static int catpt_acpi_remove(struct platform_device *pdev) +{ + struct catpt_dev *cdev = platform_get_drvdata(pdev); + + pm_runtime_disable(cdev->dev); + + snd_soc_unregister_component(cdev->dev); + catpt_dmac_remove(cdev); + cdev->spec->power_down(cdev); + + dma_free_coherent(cdev->dev, catpt_dram_size(cdev), + cdev->dxbuf_vaddr, cdev->dxbuf_paddr); + catpt_sram_free(&cdev->iram); + catpt_sram_free(&cdev->dram); + + catpt_sysfs_remove(cdev); + + return 0; +} + +static struct catpt_spec lpt_desc = { + .machines = snd_soc_acpi_intel_haswell_machines, + .core_id = 0x01, + .host_dram_offset = 0x000000, + .host_iram_offset = 0x080000, + .host_shim_offset = 0x0E7000, + .host_dma_offset = { 0x0F0000, 0x0F8000 }, + .host_ssp_offset = { 0x0E8000, 0x0E9000 }, + .dram_mask = LPT_VDRTCTL0_DSRAMPGE_MASK, + .iram_mask = LPT_VDRTCTL0_ISRAMPGE_MASK, + .pll_shutdown = lpt_dsp_pll_shutdown, + .power_up = lpt_dsp_power_up, + .power_down = lpt_dsp_power_down, +}; + +static struct catpt_spec wpt_desc = { + .machines = snd_soc_acpi_intel_broadwell_machines, + .core_id = 0x02, + .host_dram_offset = 0x000000, + .host_iram_offset = 0x0A0000, + .host_shim_offset = 0x0FB000, + .host_dma_offset = { 0x0FE000, 0x0FF000 }, + .host_ssp_offset = { 0x0FC000, 0x0FD000 }, + .dram_mask = WPT_VDRTCTL0_DSRAMPGE_MASK, + .iram_mask = WPT_VDRTCTL0_ISRAMPGE_MASK, + .pll_shutdown = wpt_dsp_pll_shutdown, + .power_up = wpt_dsp_power_up, + .power_down = wpt_dsp_power_down, +}; + +static const struct acpi_device_id catpt_ids[] = { + { "INT33C8", (unsigned long)&lpt_desc }, + { "INT3438", (unsigned long)&wpt_desc }, + { }, +}; +MODULE_DEVICE_TABLE(acpi, catpt_ids); + +static struct platform_driver catpt_acpi_driver = { + .probe = catpt_acpi_probe, + .remove = catpt_acpi_remove, + .driver = { + .name = "catpt_adsp", + .acpi_match_table = ACPI_PTR(catpt_ids), + .pm = &catpt_dev_pm, + }, +}; +module_platform_driver(catpt_acpi_driver); + +MODULE_AUTHOR("Cezary Rojewski cezary.rojewski@intel.com"); +MODULE_DESCRIPTION("Intel LPT/WPT AudioDSP driver"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/intel/catpt/registers.h b/sound/soc/intel/catpt/registers.h new file mode 100644 index 000000000000..93de761479e1 --- /dev/null +++ b/sound/soc/intel/catpt/registers.h @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2020 Intel Corporation. All rights reserved. + * + * Author: Cezary Rojewski cezary.rojewski@intel.com + */ + +#ifndef __SND_SOC_INTEL_CATPT_REGS_H +#define __SND_SOC_INTEL_CATPT_REGS_H + +#include <linux/iopoll.h> + +#define CATPT_SHIM_REGS_SIZE 4096 +#define CATPT_DMA_REGS_SIZE 1024 +#define CATPT_DMA_COUNT 2 +#define CATPT_SSP_REGS_SIZE 512 + +/* DSP Shim registers */ + +#define CATPT_SHIM_REG_CS 0x0 +#define CATPT_SHIM_REG_ISC 0x18 +#define CATPT_SHIM_REG_ISD 0x20 +#define CATPT_SHIM_REG_IMC 0x28 +#define CATPT_SHIM_REG_IMD 0x30 +#define CATPT_SHIM_REG_IPCC 0x38 +#define CATPT_SHIM_REG_IPCD 0x40 +#define CATPT_SHIM_REG_CLKCTL 0x78 +#define CATPT_SHIM_REG_CS2 0x80 +#define CATPT_SHIM_REG_LTRC 0xE0 +#define CATPT_SHIM_REG_HMDC 0xE8 + +#define CATPT_CS_LPCS BIT(31) +#define CATPT_CS_SFCR(ssp) BIT(27 + ssp) +#define CATPT_CS_S1IOCS BIT(23) +#define CATPT_CS_S0IOCS BIT(21) +#define CATPT_CS_PCE BIT(15) +#define CATPT_CS_SDPM(ssp) BIT(11 + ssp) +#define CATPT_CS_STALL BIT(10) +#define CATPT_CS_DCS GENMASK(6, 4) +/* b100 DSP core & audio fabric high clock */ +#define CATPT_CS_DCS_HIGH (0x4 << 4) +#define CATPT_CS_SBCS(ssp) BIT(2 + ssp) +#define CATPT_CS_RST BIT(1) + +#define CATPT_ISC_IPCDB BIT(1) +#define CATPT_ISC_IPCCD BIT(0) +#define CATPT_ISD_DCPWM BIT(31) +#define CATPT_ISD_IPCCB BIT(1) +#define CATPT_ISD_IPCDD BIT(0) + +#define CATPT_IMC_IPCDB BIT(1) +#define CATPT_IMC_IPCCD BIT(0) +#define CATPT_IMD_IPCCB BIT(1) +#define CATPT_IMD_IPCDD BIT(0) + +#define CATPT_IPCC_BUSY BIT(31) +#define CATPT_IPCC_DONE BIT(30) +#define CATPT_IPCD_BUSY BIT(31) +#define CATPT_IPCD_DONE BIT(30) + +#define CATPT_CLKCTL_CFCIP BIT(31) +#define CATPT_CLKCTL_SMOS GENMASK(25, 24) + +#define CATPT_HMDC_HDDA(e, ch) BIT(8 * e + ch) + +#define CATPT_CS_DEFAULT 0x8480040E +#define CATPT_ISC_DEFAULT 0x0 +#define CATPT_ISD_DEFAULT 0x0 +#define CATPT_IMC_DEFAULT 0x7FFF0003 +#define CATPT_IMD_DEFAULT 0x7FFF0003 +#define CATPT_IPCC_DEFAULT 0x0 +#define CATPT_IPCD_DEFAULT 0x0 +#define CATPT_CLKCTL_DEFAULT 0x7FF +#define CATPT_CS2_DEFAULT 0x0 +#define CATPT_LTRC_DEFAULT 0x0 +#define CATPT_HMDC_DEFAULT 0x0 + +/* PCI Configuration registers */ + +#define CATPT_PCI_REG_PMCS 0x84 +#define CATPT_PCI_REG_VDRTCTL0 0xA0 +#define CATPT_PCI_REG_VDRTCTL2 0xA8 + +#define CATPT_PMCS_PS GENMASK(1, 0) +#define CATPT_PMCS_PS_D3HOT (0x3 << 0) + +#define CATPT_VDRTCTL2_DTCGE BIT(10) +#define CATPT_VDRTCTL2_DCLCGE BIT(1) +#define CATPT_VDRTCTL2_CGEALL 0xF7F + +/* LPT PCI Configuration bits */ + +#define LPT_VDRTCTL0_DSRAMPGE(b) BIT(16 + b) +#define LPT_VDRTCTL0_DSRAMPGE_MASK GENMASK(31, 16) +#define LPT_VDRTCTL0_ISRAMPGE(b) BIT(6 + b) +#define LPT_VDRTCTL0_ISRAMPGE_MASK GENMASK(15, 6) +#define LPT_VDRTCTL0_D3SRAMPGD BIT(2) +#define LPT_VDRTCTL0_D3PGD BIT(1) +#define LPT_VDRTCTL0_APLLSE BIT(0) + +/* WPT PCI Configuration bits */ + +#define WPT_VDRTCTL0_DSRAMPGE(b) BIT(12 + b) +#define WPT_VDRTCTL0_DSRAMPGE_MASK GENMASK(31, 12) +#define WPT_VDRTCTL0_ISRAMPGE(b) BIT(2 + b) +#define WPT_VDRTCTL0_ISRAMPGE_MASK GENMASK(11, 2) +#define WPT_VDRTCTL0_D3SRAMPGD BIT(1) +#define WPT_VDRTCTL0_D3PGD BIT(0) + +#define WPT_VDRTCTL2_APLLSE BIT(31) + +/* SSP Interface registers */ + +#define CATPT_SSP_SSC0 0x0 +#define CATPT_SSP_SSC1 0x4 +#define CATPT_SSP_SSS 0x8 +#define CATPT_SSP_SSIT 0xC +#define CATPT_SSP_SSD 0x10 +#define CATPT_SSP_SSTO 0x28 +#define CATPT_SSP_SSPSP 0x2C +#define CATPT_SSP_SSTSA 0x30 +#define CATPT_SSP_SSRSA 0x34 +#define CATPT_SSP_SSTSS 0x38 +#define CATPT_SSP_SSC2 0x40 +#define CATPT_SSP_SSPSP2 0x44 + +#define CATPT_SSP_SSC0_DEFAULT 0x0 +#define CATPT_SSP_SSC1_DEFAULT 0x0 +#define CATPT_SSP_SSS_DEFAULT 0xF004 +#define CATPT_SSP_SSIT_DEFAULT 0x0 +#define CATPT_SSP_SSD_DEFAULT 0xC43893A3 +#define CATPT_SSP_SSTO_DEFAULT 0x0 +#define CATPT_SSP_SSPSP_DEFAULT 0x0 +#define CATPT_SSP_SSTSA_DEFAULT 0x0 +#define CATPT_SSP_SSRSA_DEFAULT 0x0 +#define CATPT_SSP_SSTSS_DEFAULT 0x0 +#define CATPT_SSP_SSC2_DEFAULT 0x0 +#define CATPT_SSP_SSPSP2_DEFAULT 0x0 + +/* Physically the same block, access address differs between host and dsp */ +#define CATPT_DSP_DRAM_OFFSET 0x400000 +#define catpt_to_host_offset(offset) (offset & ~(CATPT_DSP_DRAM_OFFSET)) +#define catpt_to_dsp_offset(offset) (offset | CATPT_DSP_DRAM_OFFSET) + +#define CATPT_MEMBLOCK_SIZE 0x8000 +#define catpt_num_dram(cdev) (hweight_long((cdev)->spec->dram_mask)) +#define catpt_num_iram(cdev) (hweight_long((cdev)->spec->iram_mask)) +#define catpt_dram_size(cdev) (catpt_num_dram(cdev) * CATPT_MEMBLOCK_SIZE) +#define catpt_iram_size(cdev) (catpt_num_iram(cdev) * CATPT_MEMBLOCK_SIZE) + +/* registry I/O helpers */ + +#define catpt_shim_addr(cdev) \ + ((cdev)->lpe_ba + (cdev)->spec->host_shim_offset) +#define catpt_dma_addr(cdev, dma) \ + ((cdev)->lpe_ba + (cdev)->spec->host_dma_offset[dma]) +#define catpt_ssp_addr(cdev, ssp) \ + ((cdev)->lpe_ba + (cdev)->spec->host_ssp_offset[ssp]) +#define catpt_inbox_addr(cdev) \ + ((cdev)->lpe_ba + (cdev)->ipc.config.inbox_offset) +#define catpt_outbox_addr(cdev) \ + ((cdev)->lpe_ba + (cdev)->ipc.config.outbox_offset) + +#define catpt_writel_ssp(cdev, ssp, reg, val) \ + writel(val, catpt_ssp_addr(cdev, ssp) + CATPT_SSP_##reg) + +#define catpt_readl_shim(cdev, reg) \ + readl(catpt_shim_addr(cdev) + CATPT_SHIM_REG_##reg) +#define catpt_writel_shim(cdev, reg, val) \ + writel(val, catpt_shim_addr(cdev) + CATPT_SHIM_REG_##reg) +#define catpt_updatel_shim(cdev, reg, mask, val) \ + catpt_writel_shim(cdev, reg, \ + (catpt_readl_shim(cdev, reg) & ~(mask)) | val) + +#define catpt_readl_poll_shim(cdev, reg, val, cond, delay_us, timeout_us) \ + readl_poll_timeout(catpt_shim_addr(cdev) + CATPT_SHIM_REG_##reg, \ + val, cond, delay_us, timeout_us) + +#define catpt_readl_pci(cdev, reg) \ + readl(cdev->pci_ba + CATPT_PCI_REG_##reg) +#define catpt_writel_pci(cdev, reg, val) \ + writel(val, cdev->pci_ba + CATPT_PCI_REG_##reg) +#define catpt_updatel_pci(cdev, reg, mask, val) \ + catpt_writel_pci(cdev, reg, \ + (catpt_readl_pci(cdev, reg) & ~(mask)) | val) + +#define catpt_readl_poll_pci(cdev, reg, val, cond, delay_us, timeout_us) \ + readl_poll_timeout((cdev)->pci_ba + CATPT_PCI_REG_##reg, \ + val, cond, delay_us, timeout_us) + +#endif

For Lynxpoint and Wildcat Point solution, is it host's responsibility to allocate SRAM regions and ensure those already taken are not overwritten with other data until released. Blocks are transferred to SRAM - either IRAM or DRAM - via DW DMA controller. Once basefw is booted, ownership of DMA transfer is lost in favour of DSP.

Hosts reponsibilities don't end on initial block allocation and binary transfer. During Dx transitions host must store FW runtime context from DRAM before putting AudioDSP subsystem into lower power state. Said context gets flashed after D0 entry to bring DSP right where it was just before suspending.

Load and restore procedures are finalized with SRAM power gating and adequate clock level selection. This power gates unused EBBs and clock speed effectively reducing power consumption.

Signed-off-by: Cezary Rojewski cezary.rojewski@intel.com --- sound/soc/intel/catpt/loader.c | 673 +++++++++++++++++++++++++++++++++ 1 file changed, 673 insertions(+) create mode 100644 sound/soc/intel/catpt/loader.c

diff --git a/sound/soc/intel/catpt/loader.c b/sound/soc/intel/catpt/loader.c new file mode 100644 index 000000000000..21559ba9f30b --- /dev/null +++ b/sound/soc/intel/catpt/loader.c @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright(c) 2020 Intel Corporation. All rights reserved. +// +// Author: Cezary Rojewski cezary.rojewski@intel.com +// + +#include <linux/dma-mapping.h> +#include <linux/firmware.h> +#include "core.h" +#include "registers.h" +#include "trace.h" + +/* FW load (200ms) plus operational delays */ +#define FW_READY_TIMEOUT_MSECS 250 + +#define FW_SIGNATURE "$SST" +#define FW_SIGNATURE_SIZE 4 + +/* some nice binary layout picture here */ + +struct catpt_fw_hdr { + char signature[FW_SIGNATURE_SIZE]; + u32 file_size; + u32 modules; + u32 file_format; + u32 reserved[4]; +} __packed; + +struct catpt_fw_mod_hdr { + char signature[FW_SIGNATURE_SIZE]; + u32 mod_size; + u32 blocks; + u16 slot; + enum catpt_module_id id:16; + u32 entry_point; + u32 persistent_size; + u32 scratch_size; +} __packed; + +enum catpt_ram_type { + CATPT_RAM_TYPE_IRAM = 1, + CATPT_RAM_TYPE_DRAM = 2, + /* DRAM with module's initial state */ + CATPT_RAM_TYPE_INSTANCE = 3, +}; + +struct catpt_fw_block_hdr { + enum catpt_ram_type type __aligned(4); + u32 size; + u32 ram_offset; + u32 rsvd; +} __packed; + +void catpt_sram_init(struct resource *sram, u32 start, u32 size) +{ + sram->start = start; + sram->end = start + size - 1; +} + +void catpt_sram_free(struct resource *sram) +{ + struct resource *res, *save; + + for (res = sram->child; res;) { + save = res->sibling; + release_resource(res); + kfree(res); + res = save; + } +} + +struct resource * +catpt_request_region(struct resource *root, resource_size_t size) +{ + struct resource *res = root->child; + resource_size_t addr = root->start; + + for (;;) { + if (res->start - addr >= size) + break; + addr = res->end + 1; + res = res->sibling; + if (!res) + return NULL; + } + + return __request_region(root, addr, size, NULL, 0); +} + +int catpt_store_streams_context(struct catpt_dev *cdev, struct dma_chan *chan) +{ + struct catpt_stream_runtime *stream; + + list_for_each_entry(stream, &cdev->stream_list, node) { + u32 off, size; + int ret; + + off = stream->persistent->start; + size = resource_size(stream->persistent); + dev_dbg(cdev->dev, "storing stream %d ctx: off 0x%08x size %d\n", + stream->info.stream_hw_id, off, size); + + ret = catpt_dma_memcpy_fromdsp(cdev, chan, + cdev->dxbuf_paddr + off, + cdev->lpe_base + off, + ALIGN(size, 4)); + if (ret < 0) { + dev_err(cdev->dev, "memcpy fromdsp failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +int catpt_store_module_states(struct catpt_dev *cdev, struct dma_chan *chan) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cdev->modules); i++) { + struct catpt_module_type *type; + u32 off; + int ret; + + type = &cdev->modules[i]; + if (!type->loaded || !type->state_size) + continue; + + off = type->state_offset; + dev_dbg(cdev->dev, "storing mod %d state: off 0x%08x size %d\n", + i, off, type->state_size); + + ret = catpt_dma_memcpy_fromdsp(cdev, chan, + cdev->dxbuf_paddr + off, + cdev->lpe_base + off, + ALIGN(type->state_size, 4)); + if (ret < 0) { + dev_err(cdev->dev, "memcpy fromdsp failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +int catpt_store_memdumps(struct catpt_dev *cdev, struct dma_chan *chan) +{ + int i; + + for (i = 0; i < cdev->dx_ctx.num_meminfo; i++) { + struct catpt_save_meminfo *info; + u32 off; + int ret; + + info = &cdev->dx_ctx.meminfo[i]; + if (info->source != CATPT_DX_TYPE_MEMORY_DUMP) + continue; + + off = catpt_to_host_offset(info->offset); + if (off < cdev->dram.start || off > cdev->dram.end) + continue; + + dev_dbg(cdev->dev, "storing memdump: off 0x%08x size %d\n", + off, info->size); + + ret = catpt_dma_memcpy_fromdsp(cdev, chan, + cdev->dxbuf_paddr + off, + cdev->lpe_base + off, + ALIGN(info->size, 4)); + if (ret < 0) { + dev_err(cdev->dev, "memcpy fromdsp failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int +catpt_restore_streams_context(struct catpt_dev *cdev, struct dma_chan *chan) +{ + struct catpt_stream_runtime *stream; + + list_for_each_entry(stream, &cdev->stream_list, node) { + u32 off, size; + int ret; + + off = stream->persistent->start; + size = resource_size(stream->persistent); + dev_dbg(cdev->dev, "restoring stream %d ctx: off 0x%08x size %d\n", + stream->info.stream_hw_id, off, size); + + ret = catpt_dma_memcpy_todsp(cdev, chan, + cdev->lpe_base + off, + cdev->dxbuf_paddr + off, + ALIGN(size, 4)); + if (ret < 0) { + dev_err(cdev->dev, "memcpy fromdsp failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int catpt_restore_memdumps(struct catpt_dev *cdev, struct dma_chan *chan) +{ + int i; + + for (i = 0; i < cdev->dx_ctx.num_meminfo; i++) { + struct catpt_save_meminfo *info; + u32 off; + int ret; + + info = &cdev->dx_ctx.meminfo[i]; + if (info->source != CATPT_DX_TYPE_MEMORY_DUMP) + continue; + + off = catpt_to_host_offset(info->offset); + if (off < cdev->dram.start || off > cdev->dram.end) + continue; + + dev_dbg(cdev->dev, "restoring memdump: off 0x%08x size %d\n", + off, info->size); + + ret = catpt_dma_memcpy_todsp(cdev, chan, + cdev->lpe_base + off, + cdev->dxbuf_paddr + off, + ALIGN(info->size, 4)); + if (ret < 0) { + dev_err(cdev->dev, "restore block failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int catpt_restore_fwimage(struct catpt_dev *cdev, + struct dma_chan *chan, dma_addr_t paddr, + struct catpt_fw_block_hdr *blk) +{ + struct resource r1, r2, common; + int i; + + print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4, + blk, sizeof(*blk), false); + + r1.start = cdev->dram.start + blk->ram_offset; + r1.end = r1.start + blk->size - 1; + /* advance to data area */ + paddr += sizeof(*blk); + + for (i = 0; i < cdev->dx_ctx.num_meminfo; i++) { + struct catpt_save_meminfo *info; + u32 off; + int ret; + + info = &cdev->dx_ctx.meminfo[i]; + + if (info->source != CATPT_DX_TYPE_FW_IMAGE) + continue; + + off = catpt_to_host_offset(info->offset); + if (off < cdev->dram.start || off > cdev->dram.end) + continue; + + r2.start = off; + r2.end = r2.start + info->size - 1; + + if (!catpt_resource_overlapping(&r2, &r1, &common)) + continue; + /* calculate start offset of common data area */ + off = common.start - r1.start; + + dev_dbg(cdev->dev, "restoring fwimage: %pr\n", &common); + + ret = catpt_dma_memcpy_todsp(cdev, chan, common.start, + paddr + off, + resource_size(&common)); + if (ret < 0) { + dev_err(cdev->dev, "memcpy todsp failed: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int catpt_load_block(struct catpt_dev *cdev, + struct dma_chan *chan, dma_addr_t paddr, + struct catpt_fw_block_hdr *blk, bool alloc) +{ + struct resource *sram, *res; + dma_addr_t dst_addr; + int ret; + + print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4, + blk, sizeof(*blk), false); + + switch (blk->type) { + case CATPT_RAM_TYPE_IRAM: + sram = &cdev->iram; + break; + default: + sram = &cdev->dram; + break; + }; + + dst_addr = sram->start + blk->ram_offset; + if (alloc) { + res = __request_region(sram, dst_addr, blk->size, NULL, 0); + if (!res) + return -EBUSY; + } + + /* advance to data area */ + paddr += sizeof(*blk); + + ret = catpt_dma_memcpy_todsp(cdev, chan, dst_addr, paddr, blk->size); + if (ret < 0) { + dev_err(cdev->dev, "memcpy error: %d\n", ret); + __release_region(sram, dst_addr, blk->size); + } + + return ret; +} + +static int catpt_restore_basefw(struct catpt_dev *cdev, + struct dma_chan *chan, dma_addr_t paddr, + struct catpt_fw_mod_hdr *basefw) +{ + u32 offset = sizeof(*basefw); + int ret, i; + + print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4, + basefw, sizeof(*basefw), false); + + /* restore basefw image */ + for (i = 0; i < basefw->blocks; i++) { + struct catpt_fw_block_hdr *blk; + + blk = (struct catpt_fw_block_hdr *)((u8 *)basefw + offset); + + switch (blk->type) { + case CATPT_RAM_TYPE_IRAM: + ret = catpt_load_block(cdev, chan, paddr + offset, + blk, false); + break; + default: + ret = catpt_restore_fwimage(cdev, chan, paddr + offset, + blk); + break; + } + + if (ret < 0) { + dev_err(cdev->dev, "restore block failed: %d\n", ret); + return ret; + } + + offset += sizeof(*blk) + blk->size; + } + + /* then proceed with memory dumps */ + ret = catpt_restore_memdumps(cdev, chan); + if (ret < 0) + dev_err(cdev->dev, "restore memdumps failed: %d\n", ret); + + return ret; +} + +static int catpt_restore_module(struct catpt_dev *cdev, + struct dma_chan *chan, dma_addr_t paddr, + struct catpt_fw_mod_hdr *mod) +{ + u32 offset = sizeof(*mod); + int i; + + print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4, + mod, sizeof(*mod), false); + + for (i = 0; i < mod->blocks; i++) { + struct catpt_fw_block_hdr *blk; + int ret; + + blk = (struct catpt_fw_block_hdr *)((u8 *)mod + offset); + + switch (blk->type) { + case CATPT_RAM_TYPE_INSTANCE: + /* restore module state */ + ret = catpt_dma_memcpy_todsp(cdev, chan, + cdev->lpe_base + blk->ram_offset, + cdev->dxbuf_paddr + blk->ram_offset, + ALIGN(blk->size, 4)); + break; + default: + ret = catpt_load_block(cdev, chan, paddr + offset, + blk, false); + break; + } + + if (ret < 0) { + dev_err(cdev->dev, "restore block failed: %d\n", ret); + return ret; + } + + offset += sizeof(*blk) + blk->size; + } + + return 0; +} + +static int catpt_load_module(struct catpt_dev *cdev, + struct dma_chan *chan, dma_addr_t paddr, + struct catpt_fw_mod_hdr *mod) +{ + struct catpt_module_type *type; + u32 offset = sizeof(*mod); + int i; + + print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4, + mod, sizeof(*mod), false); + + type = &cdev->modules[mod->id]; + + for (i = 0; i < mod->blocks; i++) { + struct catpt_fw_block_hdr *blk; + int ret; + + blk = (struct catpt_fw_block_hdr *)((u8 *)mod + offset); + + ret = catpt_load_block(cdev, chan, paddr + offset, blk, true); + if (ret < 0) { + dev_err(cdev->dev, "load block failed: %d\n", ret); + return ret; + } + + /* + * Save state window coordinates - these will be + * used to capture module state on D0 exit + */ + if (blk->type == CATPT_RAM_TYPE_INSTANCE) { + type->state_offset = blk->ram_offset; + type->state_size = blk->size; + } + + offset += sizeof(*blk) + blk->size; + } + + /* init module type static info */ + type->loaded = true; + /* DSP expects address from module header substracted by 4 */ + type->entry_point = mod->entry_point - 4; + type->persistent_size = mod->persistent_size; + type->scratch_size = mod->scratch_size; + + return 0; +} + +static int catpt_restore_firmware(struct catpt_dev *cdev, + struct dma_chan *chan, dma_addr_t paddr, + struct catpt_fw_hdr *fw) +{ + u32 offset = sizeof(*fw); + int i; + + print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4, + fw, sizeof(*fw), false); + + for (i = 0; i < fw->modules; i++) { + struct catpt_fw_mod_hdr *mod; + int ret; + + mod = (struct catpt_fw_mod_hdr *)((u8 *)fw + offset); + if (strncmp(fw->signature, mod->signature, + FW_SIGNATURE_SIZE)) { + dev_err(cdev->dev, "module signature mismatch\n"); + return -EINVAL; + } + + if (mod->id > CATPT_MODID_LAST) + return -EINVAL; + + switch (mod->id) { + case CATPT_MODID_BASE_FW: + ret = catpt_restore_basefw(cdev, chan, paddr + offset, + mod); + break; + default: + ret = catpt_restore_module(cdev, chan, paddr + offset, + mod); + break; + } + + if (ret < 0) { + dev_err(cdev->dev, "restore module failed: %d\n", ret); + return ret; + } + + offset += sizeof(*mod) + mod->mod_size; + } + + return 0; +} + +static int catpt_load_firmware(struct catpt_dev *cdev, + struct dma_chan *chan, dma_addr_t paddr, + struct catpt_fw_hdr *fw) +{ + u32 offset = sizeof(*fw); + int i; + + print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4, + fw, sizeof(*fw), false); + + for (i = 0; i < fw->modules; i++) { + struct catpt_fw_mod_hdr *mod; + int ret; + + mod = (struct catpt_fw_mod_hdr *)((u8 *)fw + offset); + if (strncmp(fw->signature, mod->signature, + FW_SIGNATURE_SIZE)) { + dev_err(cdev->dev, "module signature mismatch\n"); + return -EINVAL; + } + + if (mod->id > CATPT_MODID_LAST) + return -EINVAL; + + ret = catpt_load_module(cdev, chan, paddr + offset, mod); + if (ret < 0) { + dev_err(cdev->dev, "load module failed: %d\n", ret); + return ret; + } + + offset += sizeof(*mod) + mod->mod_size; + } + + return 0; +} + +static int catpt_load_image(struct catpt_dev *cdev, struct dma_chan *chan, + const char *name, const char *signature, + bool restore) +{ + struct catpt_fw_hdr *fw; + struct firmware *img; + dma_addr_t paddr; + void *vaddr; + int ret; + + ret = request_firmware((const struct firmware **)&img, name, cdev->dev); + if (ret < 0) + return ret; + + fw = (struct catpt_fw_hdr *)img->data; + if (strncmp(fw->signature, signature, FW_SIGNATURE_SIZE)) { + dev_err(cdev->dev, "firmware signature mismatch\n"); + ret = -EINVAL; + goto release_fw; + } + + vaddr = dma_alloc_coherent(cdev->dev, img->size, &paddr, GFP_KERNEL); + if (!vaddr) { + ret = -ENOMEM; + goto release_fw; + } + + memcpy(vaddr, img->data, img->size); + fw = (struct catpt_fw_hdr *)vaddr; + if (restore) + ret = catpt_restore_firmware(cdev, chan, paddr, fw); + else + ret = catpt_load_firmware(cdev, chan, paddr, fw); + + dma_free_coherent(cdev->dev, img->size, vaddr, paddr); +release_fw: + release_firmware(img); + return ret; +} + +static int catpt_load_images(struct catpt_dev *cdev, bool restore) +{ + static const char *const names[] = { + "intel/IntcSST1.bin", + "intel/IntcSST2.bin", + }; + struct dma_chan *chan; + int ret; + + chan = catpt_dma_request_config_chan(cdev); + if (IS_ERR(chan)) + return PTR_ERR(chan); + + ret = catpt_load_image(cdev, chan, names[cdev->spec->core_id - 1], + FW_SIGNATURE, restore); + if (ret < 0) + goto exit; + + if (!restore) + goto exit; + ret = catpt_restore_streams_context(cdev, chan); + if (ret < 0) + dev_err(cdev->dev, "restore streams ctx failed: %d\n", ret); +exit: + dma_release_channel(chan); + return ret; +} + +int catpt_boot_firmware(struct catpt_dev *cdev, bool restore) +{ + int ret; + + catpt_dsp_stall(cdev, true); + + ret = catpt_load_images(cdev, restore); + if (ret < 0) { + dev_err(cdev->dev, "load binaries failed: %d\n", ret); + return ret; + } + + reinit_completion(&cdev->fw_ready); + catpt_dsp_stall(cdev, false); + + ret = wait_for_completion_timeout(&cdev->fw_ready, + msecs_to_jiffies(FW_READY_TIMEOUT_MSECS)); + if (!ret) { + dev_err(cdev->dev, "firmware ready timeout\n"); + return -ETIMEDOUT; + } + + /* update sram pg & clock once done booting */ + catpt_dsp_update_srampge(cdev, &cdev->dram, cdev->spec->dram_mask); + catpt_dsp_update_srampge(cdev, &cdev->iram, cdev->spec->iram_mask); + + return catpt_dsp_update_lpclock(cdev); +} + +int catpt_first_boot_firmware(struct catpt_dev *cdev) +{ + struct resource *res; + int ret; + + ret = catpt_boot_firmware(cdev, false); + if (ret < 0) { + dev_err(cdev->dev, "basefw boot failed: %d\n", ret); + return ret; + } + + /* restrict FW Core dump area */ + __request_region(&cdev->dram, 0, 0x200, NULL, 0); + /* restrict entire area following BASE_FW - highest offset in DRAM */ + for (res = cdev->dram.child; res->sibling; res = res->sibling) + ; + __request_region(&cdev->dram, res->end + 1, + cdev->dram.end - res->end, NULL, 0); + + ret = catpt_ipc_get_mixer_stream_info(cdev, &cdev->mixer); + if (ret) + return CATPT_IPC_ERROR(ret); + + ret = catpt_arm_stream_templates(cdev); + if (ret < 0) { + dev_err(cdev->dev, "arm templates failed: %d\n", ret); + return ret; + } + + /* update dram pg for scratch and restricted regions */ + catpt_dsp_update_srampge(cdev, &cdev->dram, cdev->spec->dram_mask); + + return 0; +}

Declare global and stream IPC message types and define appropriate message handlers.

Signed-off-by: Cezary Rojewski cezary.rojewski@intel.com --- sound/soc/intel/catpt/messages.c | 312 ++++++++++++++++++++++++ sound/soc/intel/catpt/messages.h | 401 +++++++++++++++++++++++++++++++ 2 files changed, 713 insertions(+) create mode 100644 sound/soc/intel/catpt/messages.c create mode 100644 sound/soc/intel/catpt/messages.h

diff --git a/sound/soc/intel/catpt/messages.c b/sound/soc/intel/catpt/messages.c new file mode 100644 index 000000000000..e8583b40830d --- /dev/null +++ b/sound/soc/intel/catpt/messages.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright(c) 2020 Intel Corporation. All rights reserved. +// +// Author: Cezary Rojewski cezary.rojewski@intel.com +// + +#include "core.h" +#include "messages.h" +#include "registers.h" + +int catpt_ipc_get_fw_version(struct catpt_dev *cdev, + struct catpt_fw_version *version) +{ + union catpt_global_msg msg = CATPT_GLOBAL_MSG(GET_FW_VERSION); + struct catpt_ipc_msg request = {{0}}, reply; + int ret; + + request.header = msg.val; + reply.size = sizeof(*version); + reply.data = version; + + ret = catpt_dsp_send_msg(cdev, request, &reply); + if (ret) + dev_err(cdev->dev, "get fw version failed: %d\n", ret); + + return ret; +} + +struct catpt_alloc_stream_input { + enum catpt_path_id path_id:8; + enum catpt_stream_type stream_type:8; + enum catpt_format_id format_id:8; + u8 reserved; + struct catpt_audio_format input_format; + struct catpt_ring_info ring_info; + u8 num_entries; + /* flex array with entries here */ + struct catpt_memory_info persistent_mem; + struct catpt_memory_info scratch_mem; + u32 num_notifications; /* obsolete */ +} __packed; + +int catpt_ipc_alloc_stream(struct catpt_dev *cdev, + enum catpt_path_id path_id, + enum catpt_stream_type type, + struct catpt_audio_format *afmt, + struct catpt_ring_info *rinfo, + u8 num_modules, + struct catpt_module_entry *modules, + struct resource *persistent, + struct resource *scratch, + struct catpt_stream_info *sinfo) +{ + union catpt_global_msg msg = CATPT_GLOBAL_MSG(ALLOCATE_STREAM); + struct catpt_alloc_stream_input input; + struct catpt_ipc_msg request, reply; + size_t size, arrsz; + u8 *payload; + off_t off; + int ret; + + off = offsetof(struct catpt_alloc_stream_input, persistent_mem); + arrsz = sizeof(*modules) * num_modules; + size = sizeof(input) + arrsz; + + payload = kzalloc(size, GFP_KERNEL); + if (!payload) + return -ENOMEM; + + memset(&input, 0, sizeof(input)); + input.path_id = path_id; + input.stream_type = type; + input.format_id = CATPT_FORMAT_PCM; + input.input_format = *afmt; + input.ring_info = *rinfo; + input.num_entries = num_modules; + input.persistent_mem.offset = catpt_to_dsp_offset(persistent->start); + input.persistent_mem.size = resource_size(persistent); + if (scratch) { + input.scratch_mem.offset = catpt_to_dsp_offset(scratch->start); + input.scratch_mem.size = resource_size(scratch); + } + + /* re-arrange the input: account for flex array 'entries' */ + memcpy(payload, &input, sizeof(input)); + memmove(payload + off + arrsz, payload + off, sizeof(input) - off); + memcpy(payload + off, modules, arrsz); + + request.header = msg.val; + request.size = size; + request.data = payload; + reply.size = sizeof(*sinfo); + reply.data = sinfo; + + ret = catpt_dsp_send_msg(cdev, request, &reply); + if (ret) + dev_err(cdev->dev, "alloc stream type %d failed: %d\n", + type, ret); + + kfree(payload); + return ret; +} + +int catpt_ipc_free_stream(struct catpt_dev *cdev, u8 stream_hw_id) +{ + union catpt_global_msg msg = CATPT_GLOBAL_MSG(FREE_STREAM); + struct catpt_ipc_msg request; + int ret; + + request.header = msg.val; + request.size = sizeof(stream_hw_id); + request.data = &stream_hw_id; + + ret = catpt_dsp_send_msg(cdev, request, NULL); + if (ret) + dev_err(cdev->dev, "free stream %d failed: %d\n", + stream_hw_id, ret); + + return ret; +} + +int catpt_ipc_set_device_format(struct catpt_dev *cdev, + struct catpt_ssp_device_format *devfmt) +{ + union catpt_global_msg msg = CATPT_GLOBAL_MSG(SET_DEVICE_FORMATS); + struct catpt_ipc_msg request; + int ret; + + request.header = msg.val; + request.size = sizeof(*devfmt); + request.data = devfmt; + + ret = catpt_dsp_send_msg(cdev, request, NULL); + if (ret) + dev_err(cdev->dev, "set device format failed: %d\n", ret); + + return ret; +} + +int catpt_ipc_enter_dxstate(struct catpt_dev *cdev, enum catpt_dx_state state, + struct catpt_dx_context *dx_ctx) +{ + union catpt_global_msg msg = CATPT_GLOBAL_MSG(ENTER_DX_STATE); + struct catpt_ipc_msg request, reply; + int ret; + + request.header = msg.val; + request.size = sizeof(state); + request.data = &state; + reply.size = sizeof(*dx_ctx); + reply.data = dx_ctx; + + ret = catpt_dsp_send_msg(cdev, request, &reply); + if (ret) + dev_err(cdev->dev, "enter dx state failed: %d\n", ret); + + return ret; +} + +int catpt_ipc_get_mixer_stream_info(struct catpt_dev *cdev, + struct catpt_mixer_stream_info *info) +{ + union catpt_global_msg msg = CATPT_GLOBAL_MSG(GET_MIXER_STREAM_INFO); + struct catpt_ipc_msg request = {{0}}, reply; + int ret; + + request.header = msg.val; + reply.size = sizeof(*info); + reply.data = info; + + ret = catpt_dsp_send_msg(cdev, request, &reply); + if (ret) + dev_err(cdev->dev, "get mixer info failed: %d\n", ret); + + return ret; +} + +int catpt_ipc_reset_stream(struct catpt_dev *cdev, u8 stream_hw_id) +{ + union catpt_stream_msg msg = CATPT_STREAM_MSG(RESET_STREAM); + struct catpt_ipc_msg request = {{0}}; + int ret; + + msg.stream_hw_id = stream_hw_id; + request.header = msg.val; + + ret = catpt_dsp_send_msg(cdev, request, NULL); + if (ret) + dev_err(cdev->dev, "reset stream %d failed: %d\n", + stream_hw_id, ret); + + return ret; +} + +int catpt_ipc_pause_stream(struct catpt_dev *cdev, u8 stream_hw_id) +{ + union catpt_stream_msg msg = CATPT_STREAM_MSG(PAUSE_STREAM); + struct catpt_ipc_msg request = {{0}}; + int ret; + + msg.stream_hw_id = stream_hw_id; + request.header = msg.val; + + ret = catpt_dsp_send_msg(cdev, request, NULL); + if (ret) + dev_err(cdev->dev, "pause stream %d failed: %d\n", + stream_hw_id, ret); + + return ret; +} + +int catpt_ipc_resume_stream(struct catpt_dev *cdev, u8 stream_hw_id) +{ + union catpt_stream_msg msg = CATPT_STREAM_MSG(RESUME_STREAM); + struct catpt_ipc_msg request = {{0}}; + int ret; + + msg.stream_hw_id = stream_hw_id; + request.header = msg.val; + + ret = catpt_dsp_send_msg(cdev, request, NULL); + if (ret) + dev_err(cdev->dev, "resume stream %d failed: %d\n", + stream_hw_id, ret); + + return ret; +} + +struct catpt_set_volume_input { + u32 channel; + u32 target_volume; + u64 curve_duration; + enum catpt_audio_curve_type curve_type __aligned(4); +} __packed; + +int catpt_ipc_set_volume(struct catpt_dev *cdev, u8 stream_hw_id, + u32 channel, u32 volume, + u32 curve_duration, + enum catpt_audio_curve_type curve_type) +{ + union catpt_stream_msg msg = CATPT_STAGE_MSG(SET_VOLUME); + struct catpt_ipc_msg request; + struct catpt_set_volume_input input; + int ret; + + msg.stream_hw_id = stream_hw_id; + input.channel = channel; + input.target_volume = volume; + input.curve_duration = curve_duration; + input.curve_type = curve_type; + + request.header = msg.val; + request.size = sizeof(input); + request.data = &input; + + ret = catpt_dsp_send_msg(cdev, request, NULL); + if (ret) + dev_err(cdev->dev, "set stream %d volume failed: %d\n", + stream_hw_id, ret); + + return ret; +} + +struct catpt_set_write_pos_input { + u32 new_write_pos; + bool end_of_buffer; + bool low_latency; +} __packed; + +int catpt_ipc_set_write_pos(struct catpt_dev *cdev, u8 stream_hw_id, + u32 pos, bool eob, bool ll) +{ + union catpt_stream_msg msg = CATPT_STAGE_MSG(SET_WRITE_POSITION); + struct catpt_ipc_msg request; + struct catpt_set_write_pos_input input; + int ret; + + msg.stream_hw_id = stream_hw_id; + input.new_write_pos = pos; + input.end_of_buffer = eob; + input.low_latency = ll; + + request.header = msg.val; + request.size = sizeof(input); + request.data = &input; + + ret = catpt_dsp_send_msg(cdev, request, NULL); + if (ret) + dev_err(cdev->dev, "set stream %d write pos failed: %d\n", + stream_hw_id, ret); + + return ret; +} + +int catpt_ipc_mute_loopback(struct catpt_dev *cdev, u8 stream_hw_id, bool mute) +{ + union catpt_stream_msg msg = CATPT_STAGE_MSG(MUTE_LOOPBACK); + struct catpt_ipc_msg request; + int ret; + + msg.stream_hw_id = stream_hw_id; + request.header = msg.val; + request.size = sizeof(mute); + request.data = &mute; + + ret = catpt_dsp_send_msg(cdev, request, NULL); + if (ret) + dev_err(cdev->dev, "mute loopback failed: %d\n", ret); + + return ret; +} diff --git a/sound/soc/intel/catpt/messages.h b/sound/soc/intel/catpt/messages.h new file mode 100644 index 000000000000..214c0ce3c7af --- /dev/null +++ b/sound/soc/intel/catpt/messages.h @@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2020 Intel Corporation. All rights reserved. + * + * Author: Cezary Rojewski cezary.rojewski@intel.com + */ + +#ifndef __SND_SOC_INTEL_CATPT_MSG_H +#define __SND_SOC_INTEL_CATPT_MSG_H + +struct catpt_dev; + +/* IPC messages base types */ + +enum catpt_reply_status { + CATPT_REPLY_SUCCESS = 0, + CATPT_REPLY_ERROR_INVALID_PARAM = 1, + CATPT_REPLY_UNKNOWN_MESSAGE_TYPE = 2, + CATPT_REPLY_OUT_OF_RESOURCES = 3, + CATPT_REPLY_BUSY = 4, + CATPT_REPLY_PENDING = 5, + CATPT_REPLY_FAILURE = 6, + CATPT_REPLY_INVALID_REQUEST = 7, + CATPT_REPLY_UNINITIALIZED = 8, + CATPT_REPLY_NOT_FOUND = 9, + CATPT_REPLY_SOURCE_NOT_STARTED = 10, +}; + +/* GLOBAL messages */ + +enum catpt_global_msg_type { + CATPT_GLB_GET_FW_VERSION = 0, + CATPT_GLB_ALLOCATE_STREAM = 3, + CATPT_GLB_FREE_STREAM = 4, + CATPT_GLB_STREAM_MESSAGE = 6, + CATPT_GLB_REQUEST_CORE_DUMP = 7, + CATPT_GLB_SET_DEVICE_FORMATS = 10, + CATPT_GLB_ENTER_DX_STATE = 12, + CATPT_GLB_GET_MIXER_STREAM_INFO = 13, +}; + +union catpt_global_msg { + u32 val; + struct { + enum catpt_reply_status status:5; + u32 context:19; /* stream or module specific */ + enum catpt_global_msg_type type:5; + u32 fw_ready:1; + u32 done:1; + u32 busy:1; + }; +} __packed; + +#define CATPT_MSG(hdr) { .val = hdr } +#define CATPT_GLOBAL_MSG(msg_type) \ + { .type = CATPT_GLB_##msg_type } + +#define BUILD_HASH_SIZE 40 + +struct catpt_fw_version { + u8 build; + u8 minor; + u8 major; + u8 type; + u8 build_hash[BUILD_HASH_SIZE]; + u32 log_providers_hash; +} __packed; + +int catpt_ipc_get_fw_version(struct catpt_dev *cdev, + struct catpt_fw_version *version); + +enum catpt_pin_id { + CATPT_PIN_ID_SYSTEM = 0, + CATPT_PIN_ID_REFERENCE = 1, + CATPT_PIN_ID_CAPTURE1 = 2, + CATPT_PIN_ID_CAPTURE2 = 3, + CATPT_PIN_ID_OFFLOAD1 = 4, + CATPT_PIN_ID_OFFLOAD2 = 5, + CATPT_PIN_ID_MIXER = 7, + CATPT_PIN_ID_BLUETOOTH_CAPTURE = 8, + CATPT_PIN_ID_BLUETOOTH_RENDER = 9, +}; + +enum catpt_path_id { + CATPT_PATH_SSP0_OUT = 0, + CATPT_PATH_SSP0_IN = 1, + CATPT_PATH_SSP1_OUT = 2, + CATPT_PATH_SSP1_IN = 3, + /* duplicated audio in capture path */ + CATPT_PATH_SSP0_IN_DUP = 4, +}; + +enum catpt_stream_type { + CATPT_STRM_TYPE_RENDER = 0, /* offload */ + CATPT_STRM_TYPE_SYSTEM = 1, + CATPT_STRM_TYPE_CAPTURE = 2, + CATPT_STRM_TYPE_LOOPBACK = 3, + CATPT_STRM_TYPE_BLUETOOTH_RENDER = 4, + CATPT_STRM_TYPE_BLUETOOTH_CAPTURE = 5, +}; + +enum catpt_format_id { + CATPT_FORMAT_PCM = 0, + CATPT_FORMAT_MP3 = 1, + CATPT_FORMAT_AAC = 2, + CATPT_FORMAT_WMA = 3, +}; + +enum catpt_channel_index { + CATPT_CHANNEL_LEFT = 0x0, + CATPT_CHANNEL_CENTER = 0x1, + CATPT_CHANNEL_RIGHT = 0x2, + CATPT_CHANNEL_LEFT_SURROUND = 0x3, + CATPT_CHANNEL_CENTER_SURROUND = 0x3, + CATPT_CHANNEL_RIGHT_SURROUND = 0x4, + CATPT_CHANNEL_LFE = 0x7, + CATPT_CHANNEL_INVALID = 0xF, +}; + +enum catpt_channel_config { + CATPT_CHANNEL_CONFIG_MONO = 0, /* One channel only */ + CATPT_CHANNEL_CONFIG_STEREO = 1, /* L & R */ + CATPT_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only */ + CATPT_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only */ + CATPT_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only */ + CATPT_CHANNEL_CONFIG_QUATRO = 5, /* L, R, Ls & Rs; PCM only */ + CATPT_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only */ + CATPT_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs */ + CATPT_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE */ + CATPT_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two */ + CATPT_CHANNEL_CONFIG_INVALID = 10, +}; + +enum catpt_interleaving_style { + CATPT_INTERLEAVING_PER_CHANNEL = 0, + CATPT_INTERLEAVING_PER_SAMPLE = 1, +}; + +struct catpt_audio_format { + u32 sample_rate; + u32 bit_depth; + u32 channel_map; + enum catpt_channel_config channel_config __aligned(4); + enum catpt_interleaving_style interleaving __aligned(4); + u8 num_channels; + u8 valid_bit_depth; + u8 reserved[2]; +} __packed; + +struct catpt_ring_info { + u32 page_table_addr; + u32 num_pages; + u32 size; + u32 offset; + u32 ring_first_page_pfn; +} __packed; + +#define CATPT_MODULE_COUNT (CATPT_MODID_LAST + 1) + +enum catpt_module_id { + CATPT_MODID_BASE_FW = 0x0, + CATPT_MODID_MP3 = 0x1, + CATPT_MODID_AAC_5_1 = 0x2, + CATPT_MODID_AAC_2_0 = 0x3, + CATPT_MODID_SRC = 0x4, + CATPT_MODID_WAVES = 0x5, + CATPT_MODID_DOLBY = 0x6, + CATPT_MODID_BOOST = 0x7, + CATPT_MODID_LPAL = 0x8, + CATPT_MODID_DTS = 0x9, + CATPT_MODID_PCM_CAPTURE = 0xA, + CATPT_MODID_PCM_SYSTEM = 0xB, + CATPT_MODID_PCM_REFERENCE = 0xC, + CATPT_MODID_PCM = 0xD, /* offload */ + CATPT_MODID_BLUETOOTH_RENDER = 0xE, + CATPT_MODID_BLUETOOTH_CAPTURE = 0xF, + CATPT_MODID_LAST = CATPT_MODID_BLUETOOTH_CAPTURE, +}; + +struct catpt_module_entry { + enum catpt_module_id module_id __aligned(4); + u32 entry_point; +} __packed; + +struct catpt_module_map { + u8 num_entries; + struct catpt_module_entry entries[]; +} __packed; + +struct catpt_memory_info { + u32 offset; + u32 size; +} __packed; + +#define CATPT_CHANNELS_MAX 4 +#define CATPT_ALL_CHANNELS_MASK UINT_MAX + +struct catpt_stream_info { + u32 stream_hw_id; + u32 reserved; + u32 read_pos_regaddr; + u32 pres_pos_regaddr; + u32 peak_meter_regaddr[CATPT_CHANNELS_MAX]; + u32 volume_regaddr[CATPT_CHANNELS_MAX]; +} __packed; + +int catpt_ipc_alloc_stream(struct catpt_dev *cdev, + enum catpt_path_id path_id, + enum catpt_stream_type type, + struct catpt_audio_format *afmt, + struct catpt_ring_info *rinfo, + u8 num_modules, + struct catpt_module_entry *modules, + struct resource *persistent, + struct resource *scratch, + struct catpt_stream_info *sinfo); +int catpt_ipc_free_stream(struct catpt_dev *cdev, u8 stream_hw_id); + +#define CATPT_SSP_COUNT (CATPT_SSP_IFACE_LAST + 1) + +enum catpt_ssp_iface { + CATPT_SSP_IFACE_0 = 0, + CATPT_SSP_IFACE_1 = 1, + CATPT_SSP_IFACE_LAST = CATPT_SSP_IFACE_1, +}; + +enum catpt_mclk_frequency { + CATPT_MCLK_OFF = 0, + CATPT_MCLK_FREQ_6_MHZ = 1, + CATPT_MCLK_FREQ_21_MHZ = 2, + CATPT_MCLK_FREQ_24_MHZ = 3, +}; + +enum catpt_ssp_mode { + CATPT_SSP_MODE_I2S_SLAVE = 0, + CATPT_SSP_MODE_I2S_MASTER = 1, + CATPT_SSP_MODE_TDM_MASTER = 2, +}; + +struct catpt_ssp_device_format { + enum catpt_ssp_iface iface; + enum catpt_mclk_frequency mclk; + enum catpt_ssp_mode mode; + u16 clock_divider; + u8 channels; +} __packed; + +int catpt_ipc_set_device_format(struct catpt_dev *cdev, + struct catpt_ssp_device_format *devfmt); + +enum catpt_dx_state { + CATPT_DX_STATE_D3 = 3, +}; + +enum catpt_dx_type { + CATPT_DX_TYPE_FW_IMAGE = 0, + CATPT_DX_TYPE_MEMORY_DUMP = 1, +}; + +struct catpt_save_meminfo { + u32 offset; + u32 size; + enum catpt_dx_type source __aligned(4); +} __packed; + +#define SAVE_MEMINFO_MAX 14 + +struct catpt_dx_context { + u32 num_meminfo; + struct catpt_save_meminfo meminfo[SAVE_MEMINFO_MAX]; +} __packed; + +int catpt_ipc_enter_dxstate(struct catpt_dev *cdev, enum catpt_dx_state state, + struct catpt_dx_context *context); + +struct catpt_mixer_stream_info { + u32 mixer_hw_id; + u32 peak_meter_regaddr[CATPT_CHANNELS_MAX]; + u32 volume_regaddr[CATPT_CHANNELS_MAX]; +} __packed; + +int catpt_ipc_get_mixer_stream_info(struct catpt_dev *cdev, + struct catpt_mixer_stream_info *info); + +/* STREAM messages */ + +enum catpt_stream_msg_type { + CATPT_STRM_RESET_STREAM = 0, + CATPT_STRM_PAUSE_STREAM = 1, + CATPT_STRM_RESUME_STREAM = 2, + CATPT_STRM_STAGE_MESSAGE = 3, + CATPT_STRM_NOTIFICATION = 4, +}; + +enum catpt_stage_action { + CATPT_STG_SET_VOLUME = 1, + CATPT_STG_SET_WRITE_POSITION = 2, + CATPT_STG_MUTE_LOOPBACK = 3, +}; + +union catpt_stream_msg { + u32 val; + struct { + enum catpt_reply_status status:5; + u32 reserved:7; + enum catpt_stage_action stage_action:4; + u32 stream_hw_id:4; + enum catpt_stream_msg_type subtype:4; + enum catpt_global_msg_type type:5; + u32 fw_ready:1; + u32 done:1; + u32 busy:1; + }; +} __packed; + +#define CATPT_STREAM_MSG(msg_type) \ +{ \ + .subtype = CATPT_STRM_##msg_type, \ + .type = CATPT_GLB_STREAM_MESSAGE } +#define CATPT_STAGE_MSG(msg_type) \ +{ \ + .stage_action = CATPT_STG_##msg_type, \ + .subtype = CATPT_STRM_STAGE_MESSAGE, \ + .type = CATPT_GLB_STREAM_MESSAGE } + +int catpt_ipc_reset_stream(struct catpt_dev *cdev, u8 stream_hw_id); +int catpt_ipc_pause_stream(struct catpt_dev *cdev, u8 stream_hw_id); +int catpt_ipc_resume_stream(struct catpt_dev *cdev, u8 stream_hw_id); + +/* STREAM messages - STAGE subtype */ + +enum catpt_audio_curve_type { + CATPT_AUDIO_CURVE_NONE = 0, + CATPT_AUDIO_CURVE_WINDOWS_FADE = 1, +}; + +int catpt_ipc_set_volume(struct catpt_dev *cdev, u8 stream_hw_id, + u32 channel, u32 volume, + u32 curve_duration, + enum catpt_audio_curve_type curve_type); + +int catpt_ipc_set_write_pos(struct catpt_dev *cdev, u8 stream_hw_id, + u32 pos, bool eob, bool ll); + +int catpt_ipc_mute_loopback(struct catpt_dev *cdev, u8 stream_hw_id, bool mute); + +/* NOTIFICATION messages */ + +enum catpt_notify_reason { + CATPT_NOTIFY_POSITION_CHANGED = 0, + CATPT_NOTIFY_GLITCH_OCCURRED = 1, +}; + +union catpt_notify_msg { + u32 val; + struct { + u32 mailbox_address:29; + u32 fw_ready:1; + u32 done:1; + u32 busy:1; + }; + struct { + enum catpt_reply_status status:5; + u32 reserved:7; + enum catpt_notify_reason notify_reason:4; + u32 stream_hw_id:4; + enum catpt_stream_msg_type subtype:4; + enum catpt_global_msg_type type:5; + u32 hdr:3; /* fw_ready, done, busy */ + }; +} __packed; + +#define FW_INFO_SIZE_MAX 100 + +struct catpt_fw_ready { + u32 inbox_offset; + u32 outbox_offset; + u32 inbox_size; + u32 outbox_size; + u32 fw_info_size; + char fw_info[FW_INFO_SIZE_MAX]; +} __packed; + +struct catpt_notify_position { + u32 stream_position; + u32 fw_cycle_count; +} __packed; + +enum catpt_glitch_type { + CATPT_GLITCH_UNDERRUN = 1, + CATPT_GLITCH_DECODER_ERROR = 2, + CATPT_GLITCH_DOUBLED_WRITE_POS = 3, +}; + +struct catpt_notify_glitch { + enum catpt_glitch_type type __aligned(4); + u64 presentation_pos; + u32 write_pos; +} __packed; + +#endif

Define tracing macros for easy catpt debug. These cover all IPC message types: requests, replies and notifications.

Signed-off-by: Cezary Rojewski cezary.rojewski@intel.com --- sound/soc/intel/catpt/trace.h | 83 +++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 sound/soc/intel/catpt/trace.h

diff --git a/sound/soc/intel/catpt/trace.h b/sound/soc/intel/catpt/trace.h new file mode 100644 index 000000000000..bb3d627dbeaf --- /dev/null +++ b/sound/soc/intel/catpt/trace.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2020 Intel Corporation. All rights reserved. + * + * Author: Cezary Rojewski cezary.rojewski@intel.com + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM intel_catpt + +#if !defined(__SND_SOC_INTEL_CATPT_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define __SND_SOC_INTEL_CATPT_TRACE_H + +#include <linux/types.h> +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(catpt_ipc_msg, + + TP_PROTO(u32 header), + + TP_ARGS(header), + + TP_STRUCT__entry( + __field(u32, header) + ), + + TP_fast_assign( + __entry->header = header; + ), + + TP_printk("0x%08x", __entry->header) +); + +DEFINE_EVENT(catpt_ipc_msg, catpt_irq, + TP_PROTO(u32 header), + TP_ARGS(header) +); + +DEFINE_EVENT(catpt_ipc_msg, catpt_ipc_request, + TP_PROTO(u32 header), + TP_ARGS(header) +); + +DEFINE_EVENT(catpt_ipc_msg, catpt_ipc_reply, + TP_PROTO(u32 header), + TP_ARGS(header) +); + +DEFINE_EVENT(catpt_ipc_msg, catpt_ipc_notify, + TP_PROTO(u32 header), + TP_ARGS(header) +); + +TRACE_EVENT_CONDITION(catpt_ipc_payload, + + TP_PROTO(const u8 *data, size_t size), + + TP_ARGS(data, size), + + TP_CONDITION(data && size), + + TP_STRUCT__entry( + __dynamic_array(u8, buf, size) + ), + + TP_fast_assign( + memcpy(__get_dynamic_array(buf), data, size); + ), + + TP_printk("%u byte(s)%s", + __get_dynamic_array_len(buf), + __print_hex_dump("", DUMP_PREFIX_NONE, 16, 4, + __get_dynamic_array(buf), + __get_dynamic_array_len(buf), false)) +); + +#endif /* __SND_SOC_INTEL_CATPT_TRACE_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE trace +#include <trace/define_trace.h>

Prevent sound/soc/intel/haswell code compile and select catpt instead as a recommended solution. Userspace-exposed members are compatible with what is exposed by deprecated solution thus no harm is done. The only visible difference is the newly added 'Loopback Mute' kcontrol.

Signed-off-by: Cezary Rojewski cezary.rojewski@intel.com --- sound/soc/intel/Kconfig | 22 +++++++++++----------- sound/soc/intel/Makefile | 2 +- sound/soc/intel/boards/Kconfig | 8 ++++---- sound/soc/intel/catpt/Makefile | 6 ++++++ 4 files changed, 22 insertions(+), 16 deletions(-) create mode 100644 sound/soc/intel/catpt/Makefile

diff --git a/sound/soc/intel/Kconfig b/sound/soc/intel/Kconfig index 82805a8681e5..4a18e8f83eeb 100644 --- a/sound/soc/intel/Kconfig +++ b/sound/soc/intel/Kconfig @@ -47,21 +47,21 @@ config SND_SOC_INTEL_SST_FIRMWARE # Haswell/Broadwell/Baytrail legacy and will be set # when these platforms are enabled

-config SND_SOC_INTEL_HASWELL - tristate "Haswell/Broadwell Platforms" +config SND_SOC_INTEL_CATPT + tristate "Haswell and Broadwell" depends on SND_DMA_SGBUF depends on DMADEVICES && ACPI - select SND_SOC_INTEL_SST - select SND_SOC_INTEL_SST_ACPI - select SND_SOC_INTEL_SST_FIRMWARE + select DW_DMAC_CORE select SND_SOC_ACPI_INTEL_MATCH help - If you have a Intel Haswell or Broadwell platform connected to - an I2S codec, then enable this option by saying Y or m. This is - typically used for Chromebooks. This is a recommended option. - This option is mutually exclusive with the SOF support on - Broadwell. If you want to enable SOF on Broadwell, you need to - deselect this option first. + Enable support for Intel(R) Haswell and Broadwell platforms + with I2S codec present. This is a recommended option. + Say Y or m if you have such device. + If unsure, say N. + +config SND_SOC_INTEL_HASWELL + tristate + select SND_SOC_INTEL_CATPT

config SND_SOC_INTEL_BAYTRAIL tristate "Baytrail (legacy) Platforms" diff --git a/sound/soc/intel/Makefile b/sound/soc/intel/Makefile index 04ee48204fc9..c88c615f85f7 100644 --- a/sound/soc/intel/Makefile +++ b/sound/soc/intel/Makefile @@ -3,9 +3,9 @@ obj-$(CONFIG_SND_SOC) += common/

# Platform Support -obj-$(CONFIG_SND_SOC_INTEL_HASWELL) += haswell/ obj-$(CONFIG_SND_SOC_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_SND_SST_ATOM_HIFI2_PLATFORM) += atom/ +obj-$(CONFIG_SND_SOC_INTEL_CATPT) += catpt/ obj-$(CONFIG_SND_SOC_INTEL_SKYLAKE) += skylake/ obj-$(CONFIG_SND_SOC_INTEL_KEEMBAY) += keembay/

diff --git a/sound/soc/intel/boards/Kconfig b/sound/soc/intel/boards/Kconfig index d96fc1313434..f4358c33059b 100644 --- a/sound/soc/intel/boards/Kconfig +++ b/sound/soc/intel/boards/Kconfig @@ -26,7 +26,7 @@ config SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES interface. If unsure select N.

-if SND_SOC_INTEL_HASWELL +if SND_SOC_INTEL_CATPT

config SND_SOC_INTEL_HASWELL_MACH tristate "Haswell Lynxpoint" @@ -40,9 +40,9 @@ config SND_SOC_INTEL_HASWELL_MACH Say Y or m if you have such a device. If unsure select "N".

-endif ## SND_SOC_INTEL_HASWELL +endif ## SND_SOC_INTEL_CATPT

-if SND_SOC_INTEL_HASWELL || SND_SOC_SOF_BROADWELL +if SND_SOC_INTEL_CATPT || SND_SOC_SOF_BROADWELL

config SND_SOC_INTEL_BDW_RT5650_MACH tristate "Broadwell with RT5650 codec" @@ -83,7 +83,7 @@ config SND_SOC_INTEL_BROADWELL_MACH Ultrabook platforms. Say Y or m if you have such a device. This is a recommended option. If unsure select "N". -endif ## SND_SOC_INTEL_HASWELL || SND_SOC_SOF_BROADWELL +endif ## SND_SOC_INTEL_CATPT || SND_SOC_SOF_BROADWELL

if SND_SOC_INTEL_BAYTRAIL

diff --git a/sound/soc/intel/catpt/Makefile b/sound/soc/intel/catpt/Makefile new file mode 100644 index 000000000000..0717190106d9 --- /dev/null +++ b/sound/soc/intel/catpt/Makefile @@ -0,0 +1,6 @@ +snd-soc-catpt-objs := device.o dsp.o loader.o ipc.o messages.o pcm.o fs.o + +# tell define_trace.h where to find the trace header +CFLAGS_device.o := -I$(src) + +obj-$(CONFIG_SND_SOC_INTEL_CATPT) += snd-soc-catpt.o

Remove code specific to sound/soc/intel/haswell. Update BE dai_link definition to provide seamless transition to catpt solution.

Signed-off-by: Cezary Rojewski cezary.rojewski@intel.com --- sound/soc/intel/boards/haswell.c | 28 ++++------------------------ 1 file changed, 4 insertions(+), 24 deletions(-)

diff --git a/sound/soc/intel/boards/haswell.c b/sound/soc/intel/boards/haswell.c index 744b7b5b8106..c268405e5594 100644 --- a/sound/soc/intel/boards/haswell.c +++ b/sound/soc/intel/boards/haswell.c @@ -13,9 +13,6 @@ #include <sound/soc-acpi.h> #include <sound/pcm_params.h>

-#include "../common/sst-dsp.h" -#include "../haswell/sst-haswell-ipc.h" - #include "../../codecs/rt5640.h"

/* Haswell ULT platforms have a Headphone and Mic jack */ @@ -77,25 +74,6 @@ static const struct snd_soc_ops haswell_rt5640_ops = { .hw_params = haswell_rt5640_hw_params, };

-static int haswell_rtd_init(struct snd_soc_pcm_runtime *rtd) -{ - struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); - struct sst_pdata *pdata = dev_get_platdata(component->dev); - struct sst_hsw *haswell = pdata->dsp; - int ret; - - /* Set ADSP SSP port settings */ - ret = sst_hsw_device_set_config(haswell, SST_HSW_DEVICE_SSP_0, - SST_HSW_DEVICE_MCLK_FREQ_24_MHZ, - SST_HSW_DEVICE_CLOCK_MASTER, 9); - if (ret < 0) { - dev_err(rtd->dev, "failed to set device config\n"); - return ret; - } - - return 0; -} - SND_SOC_DAILINK_DEF(dummy, DAILINK_COMP_ARRAY(COMP_DUMMY()));

@@ -117,13 +95,15 @@ SND_SOC_DAILINK_DEF(codec, SND_SOC_DAILINK_DEF(platform, DAILINK_COMP_ARRAY(COMP_PLATFORM("haswell-pcm-audio")));

+SND_SOC_DAILINK_DEF(ssp0_port, + DAILINK_COMP_ARRAY(COMP_CPU("ssp0-port"))); + static struct snd_soc_dai_link haswell_rt5640_dais[] = { /* Front End DAI links */ { .name = "System", .stream_name = "System Playback/Capture", .dynamic = 1, - .init = haswell_rtd_init, .trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST}, .dpcm_playback = 1, .dpcm_capture = 1, @@ -167,7 +147,7 @@ static struct snd_soc_dai_link haswell_rt5640_dais[] = { .ops = &haswell_rt5640_ops, .dpcm_playback = 1, .dpcm_capture = 1, - SND_SOC_DAILINK_REG(dummy, codec, dummy), + SND_SOC_DAILINK_REG(ssp0_port, codec, platform), }, };

Remove code specific to sound/soc/intel/haswell. Update BE dai_link definition to provide seamless transition to catpt solution.

Signed-off-by: Cezary Rojewski cezary.rojewski@intel.com --- sound/soc/intel/boards/bdw-rt5650.c | 36 ----------------------------- 1 file changed, 36 deletions(-)

diff --git a/sound/soc/intel/boards/bdw-rt5650.c b/sound/soc/intel/boards/bdw-rt5650.c index ce7320916b22..c5820787c53e 100644 --- a/sound/soc/intel/boards/bdw-rt5650.c +++ b/sound/soc/intel/boards/bdw-rt5650.c @@ -16,9 +16,6 @@ #include <sound/soc.h> #include <sound/soc-acpi.h>

-#include "../common/sst-dsp.h" -#include "../haswell/sst-haswell-ipc.h" - #include "../../codecs/rt5645.h"

struct bdw_rt5650_priv { @@ -138,30 +135,6 @@ static struct snd_soc_ops bdw_rt5650_ops = { .hw_params = bdw_rt5650_hw_params, };

-#if !IS_ENABLED(CONFIG_SND_SOC_SOF_BROADWELL) -static int bdw_rt5650_rtd_init(struct snd_soc_pcm_runtime *rtd) -{ - struct snd_soc_component *component = - snd_soc_rtdcom_lookup(rtd, DRV_NAME); - struct sst_pdata *pdata = dev_get_platdata(component->dev); - struct sst_hsw *broadwell = pdata->dsp; - int ret; - - /* Set ADSP SSP port settings - * clock_divider = 4 means BCLK = MCLK/5 = 24MHz/5 = 4.8MHz - */ - ret = sst_hsw_device_set_config(broadwell, SST_HSW_DEVICE_SSP_0, - SST_HSW_DEVICE_MCLK_FREQ_24_MHZ, - SST_HSW_DEVICE_TDM_CLOCK_MASTER, 4); - if (ret < 0) { - dev_err(rtd->dev, "error: failed to set device config\n"); - return ret; - } - - return 0; -} -#endif - static const unsigned int channels[] = { 2, 4, }; @@ -251,10 +224,8 @@ SND_SOC_DAILINK_DEF(platform, SND_SOC_DAILINK_DEF(be, DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5650:00", "rt5645-aif1")));

-#if IS_ENABLED(CONFIG_SND_SOC_SOF_BROADWELL) SND_SOC_DAILINK_DEF(ssp0_port, DAILINK_COMP_ARRAY(COMP_CPU("ssp0-port"))); -#endif

static struct snd_soc_dai_link bdw_rt5650_dais[] = { /* Front End DAI links */ @@ -263,9 +234,6 @@ static struct snd_soc_dai_link bdw_rt5650_dais[] = { .stream_name = "System Playback", .dynamic = 1, .ops = &bdw_rt5650_fe_ops, -#if !IS_ENABLED(CONFIG_SND_SOC_SOF_BROADWELL) - .init = bdw_rt5650_rtd_init, -#endif .trigger = { SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST @@ -289,11 +257,7 @@ static struct snd_soc_dai_link bdw_rt5650_dais[] = { .dpcm_playback = 1, .dpcm_capture = 1, .init = bdw_rt5650_init, -#if !IS_ENABLED(CONFIG_SND_SOC_SOF_BROADWELL) - SND_SOC_DAILINK_REG(dummy, be, dummy), -#else SND_SOC_DAILINK_REG(ssp0_port, be, platform), -#endif }, };