From: Marek Vasut marek.vasut+renesas@gmail.com

25165f79adc76b812bfb4d8f2ab120aafb28d0e6 ("ASoC: rsnd: enable clock-frequency for both 44.1kHz/48kHz") supports both 44.1kHz/48kHz clock-frequency settings for ADG which will be used for AUDIO_OLKOUTn. But some board doesn't need it, thus, it is not mandatory.

But, above patch didn't care about the case of "clock-frequency" DT property was not present. This patch ignores ADG settings if AUDIO_OLKOUTn was not used.

Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com [Kuninori: tidyup not to break non AUDIO_OLKOUTn case] Signed-off-by: Kuninori Morimoto kuninori.morimoto.gx@renesas.com ---

Marek

I think this patch solves your issue

sound/soc/sh/rcar/adg.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c index 96fef91..277774c 100644 --- a/sound/soc/sh/rcar/adg.c +++ b/sound/soc/sh/rcar/adg.c @@ -453,13 +453,18 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, [CLKI] = 0x2, };

- of_property_read_u32(np, "#clock-cells", &count); + ckr = 0; + rbga = 2; /* default 1/6 */ + rbgb = 2; /* default 1/6 */

/* * ADG supports BRRA/BRRB output only * this means all clkout0/1/2/3 will be same rate */ prop = of_find_property(np, "clock-frequency", NULL);; + if (!prop) + goto rsnd_adg_get_clkout_end; + req_size = prop->length / sizeof(u32);

of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); @@ -472,6 +477,9 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, req_48kHz_rate = req_rate[i]; }

+ if (req_rate[0] % 48000 == 0) + adg->flags = AUDIO_OUT_48; + /* * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC * have 44.1kHz or 48kHz base clocks for now. @@ -481,9 +489,6 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, * rsnd_adg_ssi_clk_try_start() * rsnd_ssi_master_clk_start() */ - ckr = 0; - rbga = 2; /* default 1/6 */ - rbgb = 2; /* default 1/6 */ adg->rbga_rate_for_441khz = 0; adg->rbgb_rate_for_48khz = 0; for_each_rsnd_clk(clk, adg, i) { @@ -528,6 +533,7 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, * this means all clkout0/1/2/3 will be * same rate */

+ of_property_read_u32(np, "#clock-cells", &count); /* * for clkout */ @@ -557,13 +563,11 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, &adg->onecell); }

+rsnd_adg_get_clkout_end: adg->ckr = ckr; adg->rbga = rbga; adg->rbgb = rbgb;

- if (req_rate[0] % 48000 == 0) - adg->flags = AUDIO_OUT_48; - for_each_rsnd_clkout(clk, adg, i) dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk)); dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",