Hi Robert
So the next issue I'm now facing is that the MCLK to SCLK divider is not being set properly in either the Audio Formatter (MM2S Fs Multiplier register) or in the I2S Transmitter (I2S Timing Control register). The xlnx_i2s driver has a set_clkdiv function defined in its snd_soc_dai_ops structure, however that doesn't appear to be getting called. And the xlnx_formatter_pcm driver doesn't seem to have any code to set XLNX_AUD_FS_MULTIPLIER at all.
In this case I have a sample rate to MCLK divider of 256, so it looks like I should add mclk-fs = <256> into the dai-link nodes in the device tree, but there will need to be some code added to the xlnx_formatter_pcm to do something with that information? And then should that driver have code to trigger the call to set_clkdiv on the CPU DAI as well?
These drivers originated in the Xilinx kernel tree ( https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com...) and in that tree they've got a top-level xlnx_pl_snd_card.c driver which is defining the MCLK divider and instantiating the other components, however that driver is not in mainline and seems like it is kind of a hack. It seems like this SCLK divider setting is the main thing that is still needed to getting the Xilinx audio cores working in mainline using simple-sound-card..
Hmm... clock is one of difficult point to be generic, I guess. audio-graph / audio-graph2 has customize feature in such case, but simple-card doesn't.
- create generic clock handling way on simple-card ? - add customize feature to simple-card ? - switch to audio-graph / audio-graph2, and use customize feature ?
Thank you for your help !!
Best regards --- Kuninori Morimoto