18 Dec
2023
18 Dec
'23
11:10 p.m.
----- Ursprüngliche Mail -----
Von: "Amit Kumar Mahapatra" amit.kumar-mahapatra@amd.com
This patch series updated the spi-nor, spi core and the AMD-Xilinx GQSPI driver to add stacked and parallel memories support.
I wish the series had a real cover letter which explains the big picture in more detail.
What I didn't really get so far, is it really necessary to support multiple chip selects within a single mtd? You changes introduce hard to maintain changes into the spi-nor/mtd core code which alert me. Why can't we have one mtd for each cs and, if needed, combine them later? We have drivers such as mtdconcat for reasons.
Thanks, //richard