On Wed, Nov 11, 2009 at 10:42 PM, Mark Brown broonie@opensource.wolfsonmicro.com wrote:
On Wed, Nov 11, 2009 at 10:34:00PM +0800, Barry Song wrote:
The only difference should be whether clock/sync is fired from codec before or after TDM interfaces are resumed to be ready for the different resume order of CPU and Codec DAI, as I guess. That's difficult to explain why.
It'd really like to understand what's going wrong with the controller here - it should just sync up off the frame sync signal.
Don't know what happens exactly in hardware controllers . But I "fixed" this porblem by isolating interfaces's sync/clock pins from Codec(config them to GPIOs), then the whole system gets normal. Since you have a plan for pm-link, I will use this way to keep the fix in blackfin locally.